K6R4004C1C-I20 [SAMSUNG]
1Mx4 Bit High Speed Static RAM(5V Operating).; 1Mx4位高速静态RAM （ 5V工作） 。
| 型号： | K6R4004C1C-I20 |
| 厂家： | 
SAMSUNG |
| 描述： | 1Mx4 Bit High Speed Static RAM(5V Operating). |
| 文件： | 总8页 (文件大小：158K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
CMOS SRAM
K6R4004C1C-C, K6R4004C1C-I, K6R4004C1C-E
Document Title
1Mx4 Bit High Speed Static RAM(5V Operating).
Operated at Extended and Industrial Temperature Ranges.
Revision History
RevNo.
Rev. 0.0
Rev. 1.0
History
Remark
Draft Data
Initial release with Preliminary.
Preliminary
Preliminary
Feb. 12. 1999
Mar. 29. 1999
1.1 Removed Low power Version.
1.2 Removed Data Retention Characteristics
1.3 Changed ISB1 to 20mA
Rev. 2.0
2.1 Relax D.C parameters.
Preliminary
Aug. 19. 1999
Item
Previous
Current
190mA
185mA
180mA
12ns
15ns
20ns
160mA
155mA
150mA
ICC
2.2 Relax Absolute Maximum Rating.
Item
Previous
Current
Voltage on Any Pin Relative to Vss
-0.5 to 7.0
-0.5 to Vcc+0.5
Rev. 3.0
3.1 Delete Preliminary
Final
Mar. 27. 2000
3.2 Update D.C parameters and 10ns part.
Previous
Current
ICC
-
190mA
185mA
180mA
Isb
Isb1
ICC
Isb
Isb1
10ns
12ns
15ns
20ns
160mA
150mA
140mA
130mA
70mA
20mA
60mA
10mA
3.3 Added Extended temperature range
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
Rev 3.0
March 2000
- 1 -
PRELIMINARY
CMOS SRAM
K6R4004C1C-C, K6R4004C1C-I, K6R4004C1C-E
1M x 4 Bit (with OE)High-Speed CMOS Static RAM
FEATURES
• Fast Access Time 10,12,15,20ns(Max.)
• Low Power Dissipation
Standby (TTL)
(CMOS) : 10mA(Max.)
Operating K6R4004C1C-10 : 160mA(Max.)
K6R4004C1C-12 : 150mA(Max.)
K6R4004C1C-15 : 140mA(Max.)
K6R4004C1C-20 : 130mA(Max.)
• Single 5.0V ±10% Power Supply
• TTL Compatible Inputs and Outputs
• I/O Compatible with 3.3V Device
• Fully Static Operation
GENERAL DESCRIPTION
The K6R4004C1C is a 4,194,304-bit high-speed Static Random
Access Memory organized as 1,048,576 words by 4 bits. The
K6R4004C1C uses 4 common input and output lines and has
an output enable pin which operates faster than address
access time at read cycle. The device is fabricated using SAM-
SUNG¢s advanced CMOS process and designed for high-
speed circuit technology. It is particularly well suited for use in
: 60mA(Max.)
high-density
high-speed
system
applications.
The
K6R4004C1C is packaged in a 400 mil 32-pin plastic SOJ.
- No Clock or Refresh required
• Three State Outputs
• Center Power/Ground Pin Configuration
• Standard Pin Configuration
PIN CONFIGURATION(Top View)
K6R4004C1C-J : 32-SOJ-400
A19
A18
A17
A16
A15
OE
A0
A1
1
2
3
4
5
6
7
8
9
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
ORDERING INFORMATION
A2
K6R4004C1C-C10/C12/C15/C20
K6R4004C1C-E10/E12/E15/E20
K6R4004C1C-I10/I12/I15/I20
Commercial Temp.
A3
Extended Temp.
Industrial Temp.
A4
CS
I/O1
Vcc
Vss
I/O4
Vss
Vcc
I/O3
A14
A13
A12
A11
A10
N.C
SOJ
FUNCTIONAL BLOCK DIAGRAM
I/O2 10
WE 11
Clk Gen.
Pre-Charge Circuit
A5
A6
A7
A8
A9
12
13
14
15
16
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
Memory Array
1024 Rows
1024 x 4 Columns
PIN FUNCTION
Data
Cont.
I/O Circuit
Column Select
I/O1~I/O4
Pin Name
A0 - A19
WE
Pin Function
Address Inputs
Write Enable
Chip Select
CLK
Gen.
CS
A10
A11
A12
A13
A14
A15
A16
A18
A17
A19
OE
Output Enable
Data Inputs/Outputs
Power(+5.0V)
Ground
I/O1 ~ I/O4
VCC
CS
WE
OE
VSS
N.C
No Connection
Rev 3.0
March 2000
- 2 -
PRELIMINARY
CMOS SRAM
K6R4004C1C-C, K6R4004C1C-I, K6R4004C1C-E
ABSOLUTE MAXIMUM RATINGS*
Parameter
Voltage on Any Pin Relative to VSS
Voltage on VCC Supply Relative to VSS
Power Dissipation
Symbol
VIN, VOUT
VCC
Rating
-0.5 to VCC+0.5
-0.5 to 7.0
1.0
Unit
V
V
PD
W
Storage Temperature
TSTG
-65 to 150
0 to 70
°C
°C
°C
°C
Operating Temperature
Commercial
TA
Extended
Industrial
-25 to 85
-40 to 85
TA
TA
* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS*(TA=0 to 70°C)
Parameter
Symbol
Min
4.5
Typ
Max
Unit
V
Supply Voltage
Ground
VCC
5.0
5.5
VSS
0
0
-
0
V
Input High Voltage
Input Low Voltage
VIH
2.2
VCC+0.5***
0.8
V
VIL
-0.5**
-
V
*
The above parameters are also guaranteed at extended and industrial temperature range.
** VIL(Min) = -2.0V a.c(Pulse Width £ 8ns) for I £ 20mA.
*** VIH(Max) = VCC + 2.0V a.c (Pulse Width £ 8ns) for I £ 20mA.
DC AND OPERATING CHARACTERISTICS*(TA=0 to 70°C, Vcc=5.0V±10%, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
-2
Max
2
Unit
mA
Input Leakage Current
Output Leakage Current
ILI
VIN=VSS to VCC
ILO
CS=VIH or OE=VIH or WE=VIL
VOUT=VSS to VCC
-2
2
mA
Operating Current
ICC
Min. Cycle, 100% Duty
CS=VIL, VIN=VIH or VIL, IOUT=0mA
Com.
10ns
12ns
15ns
20ns
10ns
12ns
15ns
20ns
-
-
-
-
-
-
-
-
-
-
160
150
140
130
175
165
155
145
60
mA
Ext.
Ind.
Standby Current
ISB
Min. Cycle, CS=VIH
mA
ISB1
f=0MHz, CS³ VCC-0.2V,
10
VIN³ VCC-0.2V or VIN£0.2V
Output Low Voltage Level
Output High Voltage Level
VOL
VOH
IOL=8mA
-
2.4
-
0.4
-
V
V
V
IOH=-4mA
IOH1=-0.1mA
VOH1**
3.95
* The above parameters are also guaranteed at extended and industrial temperature range.
** VCC=5.0V±5%, Temp.=25°C.
CAPACITANCE*(TA=25°C, f=1.0MHz)
Item
Input/Output Capacitance
Input Capacitance
Symbol
CI/O
Test Conditions
MIN
Max
Unit
VI/O=0V
VIN=0V
-
-
8
7
pF
pF
CIN
* Capacitance is sampled and not 100% tested.
Rev 3.0
March 2000
- 3 -
PRELIMINARY
CMOS SRAM
K6R4004C1C-C, K6R4004C1C-I, K6R4004C1C-E
AC CHARACTERISTICS(TA=0 to 70°C, VCC=5.0V±10%, unless otherwise noted.)
TEST CONDITIONS*
Parameter
Value
Input Pulse Levels
0V to 3V
3ns
Input Rise and Fall Times
Input and Output timing Reference Levels
Output Loads
1.5V
See below
* The above test conditions are also applied at extended and industrial temperature range.
Output Loads(B)
for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ
Output Loads(A)
DOUT
+5.0V
RL = 50W
480W
VL = 1.5V
30pF*
DOUT
ZO = 50W
255W
5pF*
* Capacitive Load consists of all components of the
test environment.
* Including Scope and Jig Capacitance
READ CYCLE*
K6R4004C1C-20
K6R4004C1C-10
K6R4004C1C-12
K6R4004C1C-15
Parameter
Symbol
Unit
Min
10
-
Max
Min
12
-
Max
Min
15
-
Max
Min
20
-
Max
Read Cycle Time
tRC
tAA
-
10
10
5
-
12
12
6
-
15
15
7
-
20
20
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
Chip Select to Output
tCO
tOE
tLZ
-
-
-
-
Output Enable to Valid Output
Chip Enable to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
Output Hold from Address Change
Chip Selection to Power Up Time
Chip Selection to Power DownTime
-
-
-
-
3
-
3
-
3
-
3
-
tOLZ
tHZ
0
-
0
-
0
-
0
-
0
5
0
6
0
7
0
9
tOHZ
tOH
tPU
tPD
0
5
0
6
0
7
0
9
3
-
3
-
3
-
3
-
0
-
0
-
0
-
0
-
-
10
-
12
-
15
-
20
* The above parameters are also guaranteed at extended and industrial temperature range.
Rev 3.0
March 2000
- 4 -
PRELIMINARY
CMOS SRAM
K6R4004C1C-C, K6R4004C1C-I, K6R4004C1C-E
WRITE CYCLE*
K6R4004C1C-10
K6R4004C1C-12
K6R4004C1C-15
K6R4004C1C-20
Unit
Parameter
Symbol
Min
10
7
Max
Min
12
8
Max
Min
15
10
0
Max
Min
20
12
0
Max
Write Cycle Time
tWC
tCW
tAS
-
-
-
-
-
-
-
5
-
-
-
-
-
-
-
-
-
-
6
-
-
-
-
-
-
-
-
-
-
7
-
-
-
-
-
-
-
-
-
-
9
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Select to End of Write
Address Set-up Time
0
0
Address Valid to End of Write
Write Pulse Width(OE High)
Write Pulse Width(OE Low)
Write Recovery Time
tAW
tWP
tWP1
tWR
tWHZ
tDW
tDH
7
8
10
10
15
0
12
12
20
0
7
8
10
0
12
0
Write to Output High-Z
0
0
0
0
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
5
6
7
9
0
0
0
0
tOW
3
3
3
3
* The above parameters are also guaranteed at extended and industrial temperature range.
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)
tRC
Address
tAA
tOH
Valid Data
Data Out
Previous Valid Data
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC
Address
tAA
tHZ(3,4,5)
tCO
CS
tOHZ
tOH
tOE
OE
tOLZ
tLZ(4,5)
Data out
Valid Data
tPU
tPD
ICC
ISB
VCC
50%
50%
Current
NOTES(READ CYCLE)
1. WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or VOL
levels.
4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to
device.
5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.
6. Device is continuously selected with CS=VIL.
7. Address valid prior to coincident with CS transition low.
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
Rev 3.0
March 2000
- 5 -
PRELIMINARY
CMOS SRAM
K6R4004C1C-C, K6R4004C1C-I, K6R4004C1C-E
TIMING WAVEFORM OF WRITE CYCLE(1) (OE= Clock)
tWC
Address
tWR(5)
tAW
OE
tCW(3)
CS
tWP(2)
tAS(4)
WE
tDW
tDH
High-Z
Data in
Data out
Valid Data
tOHZ(6)
High-Z(8)
TIMING WAVEFORM OF WRITE CYCLE(2) (OE=Low Fixed)
tWC
Address
tAW
tWR(5)
tCW(3)
CS
tAS(4)
tWP1(2)
WE
tDW
tDH
High-Z
Data in
Valid Data
tWHZ(6)
tOW
(9)
(10)
High-Z(8)
Data out
TIMING WAVEFORM OF WRITE CYCLE(3) (CS=Controlled)
tWC
Address
tAW
tWR(5)
tCW(3)
CS
tWP(2)
tAS(4)
WE
tDH
tDW
High-Z
High-Z
Data in
Valid Data
tLZ
tWHZ(6)
High-Z(8)
High-Z
Data out
Rev 3.0
March 2000
- 6 -
PRELIMINARY
CMOS SRAM
K6R4004C1C-C, K6R4004C1C-I, K6R4004C1C-E
NOTES(WRITE CYCLE)
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ; A write
ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write to the end of write.
3. tCW is measured from the later of CS going low to end of write.
4. tAS is measured from the address valid to the beginning of write.
5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.
6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the
output must not be applied because bus contention can occur.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.
9. Dout is the read data of the new address.
10. When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied.
FUNCTIONAL DESCRIPTION
CS
WE
X
OE
X*
H
Mode
Not Select
Output Disable
Read
I/O Pin
High-Z
High-Z
DOUT
Supply Current
H
ISB, ISB1
ICC
L
H
L
H
L
ICC
L
L
X
Write
DIN
ICC
* X means Don¢t Care.
Rev 3.0
March 2000
- 7 -
PRELIMINARY
CMOS SRAM
K6R4004C1C-C, K6R4004C1C-I, K6R4004C1C-E
PACKAGE DIMENSIONS
Units:millimeters/Inches
32-SOJ-400
#32
#17
9.40 ±0.25
0.370 ±0.010
11.18 ±0.12
0.440 ±0.005
+0.10
-0.05
0.20
0.008 +0.004
#1
#16
-0.002
0.69
MIN
21.36
0.841
MAX
0.027
20.95 ±0.12
0.825 ±0.005
1.30
0.051
1.30
0.051
(
(
)
)
0.10
0.004
3.76
0.148
MAX
MAX
+0.10
-0.05
+0.10
-0.05
+0.004
-0.002
0.71
0.43
1.27
0.050
0.95
(
)
0.028 +0.004
0.017
0.0375
-0.002
Rev 3.0
March 2000
- 8 -
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