K6X4016T3F-UQ70T [SAMSUNG]
Standard SRAM, 256KX16, 70ns, CMOS, PDSO44;
| 型号： | K6X4016T3F-UQ70T |
| 厂家： | 
SAMSUNG |
| 描述： | Standard SRAM, 256KX16, 70ns, CMOS, PDSO44 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总9页 (文件大小：203K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
K6X4016T3F Family
CMOS SRAM
Document Title
256Kx16 bit Low Power and Low Voltage CMOS Static RAM
Revision History
Revision No History
Draft Date
Remark
0.0
Initial draft
July 29, 2002
Preliminary
0.1
Revised
December 2, 2002
Preliminary
- Added Commercial product
- Deleted 44-TSOP2-400R Package Type.
- Added 55ns product(@ 3.0V~3.6V)
1.0
Finalized
August 8, 2003
Final
- Changed ICC(Operating power supply current) from 4mA to 2mA
- Changed ICC1(Average operating current) from 4mA to 3mA
- Changed ICC2(Average operating current) from 40mA to 25mA
- Changed ISB1(Standby Current(CMOS), Commercial)
from 15µA to 10µA
- Changed ISB1(Standby Current(CMOS), Industrial)
from 20µA to 10µA
- Changed ISB1(Standby Current(CMOS), Automotive)
from 30µA to 20µA
- Changed IDR(Data retention current, Commercial)
from 15µA to 10µA
- Changed IDR(Data retention current, Industrial)
from 20µA to 10µA
- Changed IDR(Data retention current, Automotive)
from 30µA to 20µA
2.0
Revised
March 27, 2005
Final
- Changed ISB1 of Automotive product from 20µA to 30µA
- Changed IDR of Automotive product from 20µA to 30µA
- Added Lead Free Products
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
1
Revision 2.0
March 2005
K6X4016T3F Family
CMOS SRAM
256Kx16 bit Low Power and Low Voltage CMOS Static RAM
FEATURES
GENERAL DESCRIPTION
• Process Technology: Full CMOS
• Organization: 256K x16
The K6X4016T3F families are fabricated by SAMSUNG′s
advanced CMOS process technology. The families support var-
ious operating temperature range and have 44-TSOP2 pack-
age type for user flexibility of system design. The families also
support low data retention voltage for battery back-up operation
with low data retention current.
• Power Supply Voltage: 2.7~3.6V
• Low Data Retention Voltage: 2V(Min)
• Three State Outputs
• Package Type: 44-TSOP2-400F
PRODUCT FAMILY
Power Dissipation
Product Family
Operating Temperature Vcc Range
Speed(ns)
PKG Type
Standby
Operating
(ICC2, Max)
(ISB1, Max)
K6X4016T3F-B
K6X4016T3F-F
K6X4016T3F-Q
Commercial(0~70°C)
Industrial(-40~85°C)
Automotive(-40~125°C)
10µA
10µA
30µA
551)/702)/85ns
702)/85ns
2.7~3.6V
25mA
44-TSOP2-400F
1. This parameter is measured with 30pF test load (Vcc=3.0~3.6V).
2. The parameter is measured with 30pF test load.
PIN DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
A4
A3
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
A5
Clk gen.
Precharge circuit.
2
A6
A2
3
A7
A1
4
OE
A0
5
Vcc
Vss
UB
CS
6
LB
I/OI
I/O2
I/O3
I/O4
Vcc
Vss
I/O5
I/O6
I/O7
I/O8
WE
A17
A16
A15
A14
A13
7
I/O16
I/O15
I/O14
I/O13
Vss
Vcc
I/O12
I/O11
I/O10
I/O9
NC
8
9
Row
Row
10
11
12
13
14
15
16
17
18
19
20
21
22
Memory array
Addresses
select
44-TSOP2
Forward
A8
A9
A10
A11
A12
I/O Circuit
Column select
Data
cont
I/O1~I/O8
Data
cont
I/O9~I/O16
Data
cont
Name
CS
Function
Name Function
Column Addresses
Chip Select Input
Vcc Power
OE
Output Enable Input Vss Ground
WE
Write Enable Input
Address Inputs
LB
UB
NC
Lower Byte (I/O1~8)
Upper Byte (I/O9~16)
No Connection
WE
OE
UB
LB
A0~A17
Control
logic
I/O1~I/O16 Data Input/Output
CS
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
2
Revision 2.0
March 2005
K6X4016T3F Family
CMOS SRAM
PRODUCT LIST
Commercial Products(0~70°C)
Industrial Products(-40~85°C)
Automotive Products(-40~125°C)
Part Name
Function
Part Name
Function
Part Name
Function
K6X4016T3F-TB551)
K6X4016T3F-TB70
K6X4016T3F-TB85
K6X4016T3F-UB551)
K6X4016T3F-UB70
K6X4016T3F-UB85
K6X4016T3F-TF551)
K6X4016T3F-TF70
K6X4016T3F-TF85
K6X4016T3F-UF551)
K6X4016T3F-UF70
K6X4016T3F-UF85
44-TSOP2-F, 55ns, LL
44-TSOP2-F, 70ns, LL
44-TSOP2-F, 85ns, LL
44-TSOP2-F, 55ns, LL, LF
44-TSOP2-F, 70ns, LL, LF
44-TSOP2-F, 85ns, LL, LF
44-TSOP2-F, 55ns, LL
44-TSOP2-F, 70ns, LL
44-TSOP2-F, 85ns, LL
K6X4016T3F-TQ70 44-TSOP2-F, 70ns, L
K6X4016T3F-TQ85 44-TSOP2-F, 85ns, L
K6X4016T3F-UQ70 44-TSOP2-F, 70ns, L, LF
44-TSOP2-F, 55ns, LL, LF K6X4016T3F-UQ85 44-TSOP2-F, 85ns, L, LF
44-TSOP2-F, 70ns, LL, LF
44-TSOP2-F, 85ns, LL, LF
1. Operating voltage range is 3.0~3.6V
2. LF : Lead Free Product
FUNCTIONAL DESCRIPTION
CS
H
L
OE
X1)
H
WE
X1)
H
LB
X1)
X1)
H
UB
X1)
X1)
H
I/O1~8
High-Z
High-Z
High-Z
Dout
I/O9~16
High-Z
High-Z
High-Z
High-Z
Dout
Mode
Power
Standby
Active
Active
Active
Active
Active
Active
Active
Active
Deselected
Output Disabled
Output Disabled
Lower Byte Read
Upper Byte Read
Word Read
X1)
X1)
L
L
L
H
L
H
L
L
H
H
L
High-Z
Dout
L
L
H
L
L
Dout
X1)
X1)
X1)
L
L
L
H
Din
High-Z
Din
Lower Byte Write
Upper Byte Write
Word Write
L
L
H
L
High-Z
Din
L
L
L
L
Din
1. X means don′t care. (Must be in low or high state)
1)
ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Ratings
Unit
Remark
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
VIN,VOUT
VCC
-0.2 to VCC+0.3(max. 3.9V)
-0.2 to 3.9
1.0
V
V
-
-
-
-
PD
W
°C
Storage temperature
TSTG
-65 to 150
0 to 70
K6X4016T3F-B
K6X4016T3F-F
K6X4016T3F-Q
Operating Temperature
TA
°C
-40 to 85
-40 to 125
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
3
Revision 2.0
March 2005
K6X4016T3F Family
RECOMMENDED DC OPERATING CONDITIONS
CMOS SRAM
1)
Item
Symbol
Min
Typ
Max
Unit
2.7
3.6
Supply voltage
Vcc
V
3.0/3.3
Ground
Vss
VIH
VIL
0
0
-
0
V
V
V
Vcc+0.22)
0.6
Input high voltage
Input low voltage
Note:
2.2
-0.23)
-
1. Commercial Product: TA=0 to 70°C, otherwise specified.
Industrial Product: TA=-40 to 85°C, otherwise specified.
Automotive Product: TA=-40 to 125°C, otherwise specified.
2. Overshoot: VCC+2.0V in case of pulse width ≤ 30ns.
3. Undershoot: -2.0V in case of pulse width ≤ 30ns.
4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE1) (f=1MHz, TA=25°C)
Item
Input capacitance
Symbol
CIN
Test Condition
VIN=0V
Min
Max
8
Unit
pF
-
-
Input/Output capacitance
CIO
VIO=0V
10
pF
1. Capacitance is sampled, not 100% tested
DC AND OPERATING CHARACTERISTICS
Item
Symbol
ILI
Test Conditions
Min Typ Max Unit
Input leakage current
VIL=Vss to Vcc
-1
-1
-
-
-
-
1
1
2
µA
µA
Output leakage current
Operating power supply current
ILO
CS=VIH or OE=VIH or WE=VIL VIO=Vss to Vcc
IIO=0mA, CS=VIL, VIN=VIL or VIH, Read
ICC
mA
Cycle time=1µs, 100% duty, IIO=0mA CS≤0.2V,
VIN≤0.2V or VIN≥Vcc-0.2V
Cycle time=Min2), 100% duty, IIO=0mA, CS=VIL,
VIN=VIH or VIL
ICC1
-
-
3
mA
Average operating current
ICC2
-
-
25
mA
Output low voltage
Output high voltage
Standby Current(TTL)
VOL
VOH
ISB
IOL=2.1mA
-
2.4
-
-
-
-
-
-
-
0.4
-
V
V
IOH=-1.0mA
CS=VIH, Other inputs=VIL or VIH
0.3
10
10
30
mA
µA
µA
µA
K6X4016T3F-B
-
-
-
CS≥Vcc-0.2V, Other
inputs=0~Vcc
Standby Current(CMOS)
ISB1
K6X4016T3F-F
K6X4016T3F-Q
4
Revision 2.0
March 2005
K6X4016T3F Family
CMOS SRAM
AC OPERATING CONDITIONS
TEST CONDITIONS( Test Load and Input/Output Reference)
Input pulse level: 0.4 to 2.2V
Input rising and falling time: 5ns
)
1
Input and output reference voltage: 1.5V
Output load(see right): CL=100pF+1TTL
CL=30pF+1TTL
CL
1.Including scope and jig capacitance
AC CHARACTERISTICS
( VCC=2.7~3.6V, Commercial product: TA=0 to 70°C, Industrial product: TA=-40 to 85°C, Automotive product: TA=-40 to 125°C )
Speed Bins
Parameter List
Symbol
Units
)
1
70ns
85ns
55ns
Min
Max
Min
70
-
Max
Min
85
-
Max
Read cycle time
tRC
tAA
55
-
-
55
55
25
25
-
-
70
70
35
35
-
-
85
85
40
40
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
Chip select to output
tCO
tOE
-
-
-
Output enable to valid output
LB, UB valid to data output
Chip select to low-Z output
Output enable to low-Z output
LB, UB enable to low-Z output
Output hold from address change
Chip disable to high-Z output
OE disable to high-Z output
LB, UB disable to high-Z output
Write cycle time
-
-
-
tBA
-
-
-
tLZ
10
5
10
5
10
5
Read
tOLZ
tBLZ
tOH
tHZ
-
-
-
5
-
5
-
5
-
10
0
-
10
0
-
10
0
-
20
20
20
-
25
25
25
-
25
25
25
-
tOHZ
tBHZ
tWC
tCW
tAS
0
0
0
0
0
0
55
45
0
70
60
0
85
70
0
Chip select to end of write
Address set-up time
-
-
-
-
-
-
Address valid to end of write
Write pulse width
tAW
tWP
tWR
tWHZ
tDW
tDH
45
40
0
-
60
55
0
-
70
60
0
-
-
-
-
Write
Write recovery time
-
-
-
Write to output high-Z
0
20
-
0
25
-
0
25
-
Data to write time overlap
Data hold from write time
End write to output low-Z
LB, UB valid to end of write
25
0
30
0
35
0
-
-
-
tOW
5
-
5
-
5
-
tBW
45
-
60
-
70
-
1. Voltage range is 3.0V~3.6V for commercial and industrial product.
DATA RETENTION CHARACTERISTICS
Item
Symbol
Test Condition
Min
Max
Unit
V
Typ
-
Vcc for data retention
VDR
CS≥Vcc-0.2V
2.0
3.6
10
10
30
-
K6X4016T3F-B
K6X4016T3F-F
K6X4016T3F-Q
µA
µA
µA
Data retention current
IDR
Vcc=3.0V, CS≥Vcc-0.2V
-
-
Data retention set-up time
Recovery time
tSDR
tRDR
0
5
-
-
See data retention waveform
ms
-
5
Revision 2.0
March 2005
K6X4016T3F Family
CMOS SRAM
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH, UB or/and LB=VIL)
tRC
Address
tAA
tOH
Data Valid
Data Out
Previous Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC
Address
tOH
tAA
tCO
CS
tHZ
tBA
UB, LB
OE
tBHZ
tOHZ
tOE
tOLZ
tBLZ
tLZ
Data out
High-Z
Data Valid
NOTES (READ CYCLE)
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
6
Revision 2.0
March 2005
K6X4016T3F Family
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
tWC
Address
CS
tWR(4)
tCW(2)
tAWtBW
UB, LB
tWP(1)
WE
tAS(3)
tDW
tDH
High-Z
High-Z
Data in
Data Valid
tWHZ
tOW
Data Undefined
Data out
TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled)
tWC
Address
tAS(3)
tCW(2)
tWR(4)
CS
tAW
tBW
tWP(1)
UB, LB
WE
tDW
tDH
Data Valid
Data in
Data out
High-Z
High-Z
7
Revision 2.0
March 2005
K6X4016T3F Family
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB Controlled)
tWC
Address
CS
tCW(2)
tWR(4)
tAW
tBW
UB, LB
WE
tAS(3)
tWP(1)
tDH
tDW
Data in
Data Valid
High-Z
Data out
High-Z
NOTES (WRITE CYCLE)
1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB
or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition
when CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write.
2. tCW is measured from the CS going low to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS or WE going high.
DATA RETENTION WAVE FORM
CS controlled
Data Retention Mode
tSDR
tRDR
VCC
2.7V
2.2V
VDR
CS≥VCC - 0.2V
CS
GND
8
Revision 2.0
March 2005
K6X4016T3F Family
CMOS SRAM
Unit: millimeter(inch)
PACKAGE DIMENSIONS
44 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400F)
0~8°
0.25
(
)
0.010
#44
#23
0.45 ~0.75
0.018 ~ 0.030
11.76±0.20
0.463±0.008
0.50
(
)
0.020
#1
#22
1.00±0.10
0.039±0.004
18.81
0.741
1.20
MAX.
MAX.
0.047
18.41±0.10
0.725±0.004
0.10
MAX
0.004
0.35± 0.10
0.014±0.004
0.80
0.805
0.032
(
)
0.0315
9
Revision 2.0
March 2005
相关型号：
K6X4016T3F-UQ850
Standard SRAM, 256KX16, 85ns, CMOS, PDSO44, 0.400 INCH, LEAD FREE, TSOP2-44
SAMSUNG
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