KS0118C [SAMSUNG]
GENLOCK ADC; 同步锁相ADC
| 型号： | KS0118C |
| 厂家： | 
SAMSUNG |
| 描述： | GENLOCK ADC |
| 文件： | 总10页 (文件大小：74K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
KS0118C
GENLOCK ADC
INTRODUCTION
The KS0118C is a CMOS integrated circuit designed for the GEN
LOCK and ND Conversion.
80-QFP-1420C
It is a Monolithic IC that enabled an analog NTSC composite video
signal to digitize at a clock rate that is synchronized and locked to
the incoming video horizontal line frequency.
It includes clamping function, 8-bit digitizing and creation of a line
locked sampling clock.
It is possible to correspond to the video signal system of LDP by
the use of KA9413, KA 9414-D ICS together, which is designed for
the Digital Video Signal Processor.
ORDERING IN FORMATION
Device
Package
Operating Temperature
KS0118C
80-QFP-1420C
-20 ~+75
FEATURES
• NTSC Video Signal Input
• Line-locked Sync and Clock Generation
• Line to Line Jitter < 20 nsec
• Differential Gain 2% Differential Phase 2O
• Programmable Sample Clock Frequency from 25 to 30 MHz
• Built-in 8 Bit CMOS Analog to Digital Converter
• Programmable Gain Control and Automatic DC Offset Control for Video Signal Input
• Programmable PLL Time Constants for Tracking Different Input Types
• Correctly Tracks Line Drop-outs
• Provides a Microprocessor 3 Wire Serial Interface
• Built-in Decimation Filter
Single Power Supply: +5V
KS0118C
GENLOCK ADC
BLOCK DIAGRAM
48
8 BIT
ADC
DECIMATION
FILTER
CVBS<0:7>
55
70
CLAMP
VIN
LPF
LOCK
VS
35
39
40
DIGITAL
OFFSET
CONTROL
SYNC
DETECTOR
OUTPUT
TIMING
SLICE
4
5
XTL1
XTL2
CRYSTAL
DRIVER
JITTER
REDUCTION
PIXEL
COUNTER
PHASE DET/
PLL FILTER
DTO
SERIAL MICOM INTERFACE
19 25 27
FSMP
16
Fig. 1
KS0118C
GENLOCK ADC
PIN CONFIGURATION
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
SLICE
VS
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
VRB
VRT
NC
CREF1
VDD(A)
CAGC
VIN
NC
NC
LOCK
NC
GND
NC
NC
KS0118
NC
RREF
GND
VDD(A)
RVCO
CREF2
GND
NC
NC
NC
NC
NC
SDAT
NC
SCLK
NC
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Fig. 2
KS0118C
GENLOCK ADC
PIN DESCRIPTION
Pin No
Symbol
RCPLL
I/O
Description
1
I/O External Filter Pin for Analog PLL
2
RSTB
NC
I
-
System Reset Signal Input (Active Low)
3
No Connection
4
XTL1
XTL2
VDD(A)
VDD(A)
GND
NC
I
Pin1 for External Crystal Oscillator
Pin2 for External Crystal Oscillator
+ 5V Supply Voltage for Analog Domain
+ 5V Supply Voltage for Analog Domain
Ground
5
O
-
6
7
-
8
-
9
-
No Connection
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
NC
-
No Connection
SYG
NC
O
-
Line Locked Horizontal Sync Signal
No Connection
FRZ
VDD
I
Connect this Pin to + 5V for proper Operation
+ 5V Supply Voltage for Digital Domain
Ground
-
GND
FSMP
LDP
NC
-
O
I
Freq. & Phase compensated Sample Clock used for ADC
Connect this Pin to + 5V for proper Operation
No Connection
-
SFRS
NC
I
Frame Signal for Serial Data Interface
No Connection
-
NC
-
No Connection
NC
-
No Connection
NC
-
No Connection
NC
-
No Connection
SCLK
NC
I
Clock Signal Input for Serial Data Interface
No Connection
-
SDAT
NC
I/O Serial Data in Serial Interface
-
-
No Connection
NC
No Connection
NC
-
No Connection
NC
-
No Connection
NC
-
No Connection
NC
-
No Connection
NC
-
No Connection
LOCK
NC
O
-
High when the GENLOCK is locked & in Tracking State
No Connection
NC
-
No Connection
NC
-
No Connection
Vertical Sync Signal Output
VS
O
O
Sync level. Low when CVBS < 32. This Signal is not Line locked
SLICE
KS0118C
GENLOCK ADC
PIN DESCRIPTION (Continued)
Pin No
Symbol
I/O
Description
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
NC
NC
NC
NC
NC
-
-
No Connection
No Connection
No Connection
No Connection
No Connection
-
-
-
VDD
-
+ 5V Supply Voltage for Digital Domain
Ground
GND
CVBS0
CVBS1
CVBS2
CVBS3
CVBS4
CVBS5
CVBS6
CVBS7
GND
VDD
-
O
O
O
O
O
O
O
O
-
8 Bit Composite Video Baseband Signal
8 Bit Composite Video Baseband Signal
8 Bit Composite Video Baseband Signal
8 Bit Composite Video Baseband Signal
8 Bit Composite Video Baseband Signal
8 Bit Composite Video Baseband Signal
8 Bit Composite Video Baseband Signal
8 Bit Composite Video Baseband Signal
Ground
-
+ 5V Supply Voltage for Digital Domain
+ 5V Supply Voltage for Digital Domain
+ 5V Supply Voltage for Digital Domain
Ground
VDD
-
VDD(A)
GND
NC
-
-
-
No Connection
NC
-
No Connection
NC
-
No Connection
NC
-
No Connection
VRB
I/O Bottom Voltage Reference for ADC
I/O Top Voltage Reference for ADC
I/O Decoupling Pin for Reference Voltage
VRT
CREF1
VDD(A)
CAGC
VIN
-
I
+5V Supply Voltage for Analog Domain
Capacitor for Offset Control
Analog NTSC Video Signal Input (1Vpp)
Ground
I
GND
NC
-
-
No Connection
RREF
GND
VDD(A)
RVCO
CREF2
GND
NC
I/O Current Setting Pin for Internal Analog Circuitry
-
-
Ground
+ 5V Supply Voltage for Analog Domain
I/O Current Setting Pin for Analog VCO
I/O Decoupling Pin for Reference Voltage
-
-
-
Ground
No Connection
No Connection
NC
KS0118C
GENLOCK ADC
ABSOLUTE MAXIMUM RATINGS
Characteristic
Symbol
Value
Unit
Supply Voltage
VDD
VPIN
TOPR
TSTG
-0.5 ~+7.0
GND ~ VDD
- 20 ~ + 75
-55 ~ +125
V
V
Voltage on any Digital Pin
Operating Temperature
Storage Temperature
ELECTRICAL CHARACTERISTICS
(Ta = 25 , unless otherwise specified)
Characteristic
Symbol
Test Conditions
Min
Typ
Max
Unit
Digital Input High Voltage
Digital Input Low Voltage
Digital Output High Voltage
Digital Output Low Voltage
Static Power Current
VIH
VIL
VDD = 4.75V
VDD = 5.25V
VDD = 4.75V
VDD = 5.25V
VDD = 5.25V
VDD = 5.25V
XTL = 24.576MHz
XTL = 24.576MHz
-
4.0
-
-
1.0
-
V
V
-
-
VOH
VOL
lCCS
ICCD
tUS
4.0
-
V
-
-
1.0
94
200
10
10
-
mA
mA
mA
ns
34
74
Dynamic Power Current
Serial uP I/O Set-up Time
Serial uP I/O Hold Time
Differential Phase
140
-
-
-
tUH
-
-
-
2.0
2.0
-
ns
DP
deg
%
Differential Gain
DG
SNR
fMPU
FLT
-
-
-
Signal to Noise Ratio
uP Maximum Data Rate
Frequency Lock Range
-
35
5.0
28.60
-
dB
MHz
MHz
VDD = 4.75V
XTL = 24.576MHz
-
-
-
28.66
KS0118C
GENLOCK ADC
TEST CIRCUIT
VDD(A)
VDD
VDD
0.1
GND
GND
GND
0.1
22
+
22
+
0.1
22
VDD(A)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
0.1
200
65
66
67
68
69
70
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
0.1
0.1
0.1
V25
V
DD(A)
22
VIN
15
10
+
71
72
73
74
75
120
KS0118
2.4K
0.1
VDD(A)
76
77
22
8K
V11
78
79
80
0.1
3nF
30K
82
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 23
33pF
1K
33pF
10K
0.1uF
0.1uF
22uF
+
RTSB
22uF
GND
+
X-TAL
24.576MHz
FSMP
GND
VDD
GND
GND
VDD(A)
VDD
Fig. 3.
KS0118C
GENLOCK ADC
APPLICATION INFORMATION
FUNCTION DESCRIPTION
1. GENERAL DESCRIPTION
The KS0118C implements the funtions of an 8 Bit ADC, Analog Clamp, Analog PLL Clock Generator and Digital Timing
Generation. Throuth the use of VLSl technology, the KS0118C combines analog circuits with digital signal processing to
obtain locking characteristics not achievable by ordinary methods.
The KS0118C uses 1 external frequency reference to create many different programmable line lock sampling clocks.
2. ANALOG TO DIGITAL CONVERTER
The KS0118C uses a two step, 8 bit and auto zero ADC to digitize the analog video input.
The VRT and VRB pins are the top and bottom reference voltage for the ADC.
These references are generated internally but required 0.1
decoupling capacitors to ground.
3. EXTERNAL FREQUENCY REFERENCE
The KS0118C requires an external stable frequency reference to generate the sampling clock. Although a wide range of
frequency will work with the GENLOCK, it is recommended that 24.576MHz be used as the reference.
This can be derived from a standard crystal or an external clock.
4. ANALOG PHASE LOCK LOOP
The KS0118C has an internal PLL used for producing the sampling clock. This PLL requires an external loop filter at pin
1 (RCPLL) as shown in the application circuit.
The ground connections for this filter should be placed close to pin 78, while the inputs should be located close to pin 1.
The PLL also requires an external resistor to converter the voltage of the RCPLL node to a current for use by the internal
VCO.
The voltage of the pin 76 (RVCO) will track RCPLL Although the absolute voltage of these pins depends on many factors,
it will be between 0.75 and 4.50 voltalge.
The voltage will exhibit the standard characteristics of an analog PLL.
KS0118C
GENLOCK ADC
VIN
FSMP
CVBS
ADC CODE = 32
tDSYS
tDD
SLICE
VS
tDSLICE
tDSVS
Fig. 4 Data Path Propagation Delay and Key Timing Signals
WHITE LEVEL
CODE = 224.234
100IRE
160 ( 170 ) CODES
BLANK LEVEL
CODE = 84
40 IRE
Fig. 5 Digitized Code Levels
KS0118C
GENLOCK ADC
APPLICATION CIRCUIT
KA9413
VDD(A)
VDD
VDD
0.1
GND
GND
GND
0.1
22
+
22
+
0.1
22
V
DD(A)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
0.1
200
V25
65
66
67
68
69
70
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
0.1
0.1
KA9413
0.1
Composit
Video
Signal
input ( 1Vpp )
from KA9411
VDD(A)
15
10
22
+
71
72
73
74
75
120
KS0118
2.4K
0.1
VDD(A)
76
77
22
8K
V11
78
79
80
0.1
3nF
30K
82
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 23
33pF
1K
33pF
10K
0.1uF
0.1uF
22uF
+
22uF
GND
+
X-TAL
24.576MHz
GND
GND
VDD
GND
VDD(A)
VDD
KA9413
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