KS57C5404S-XX_技术文档

Product Overview

Address Spaces

Addressing Modes

Memory Map

SAM47 Instruction Set

KS57C5404/P5404

PRODUCT OVERVIEW

1

PRODUCT OVERVIEW

OVERVIEW

The KS57C5404 single-chip CMOS microcontroller is designed for high-performance using Samsung’s newest

4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers).

With a versatile 8-bit timer/counter and a D/A converter, the KS57C5404 offers an excellent design solution for a

wide variety of telecommunication applications.

Up to 17 pins of the 24-pin SDIP package can be dedicated to I/O. Four vectored interrupts provide fast response

to internal and external events. In addition, the KS57C5404’s advanced CMOS technology has realized

substantially lower power consumption with a wide operating voltage range — all at a substantially lower cost.

OTP

The KS57C5404 microcontroller is also available in OTP (One Time Programmable) version, KS57P5404.

KS57P5404 microcontroller has an on-chip 4-Kbyte one-time-programmable EPROM instead of masked ROM.

The KS57P5404 is comparable to KS57C5404, both in function and in pin configuration.

1-1

PRODUCT OVERVIEW

KS57C5404/P5404

FEATURES SUMMARY

Memory

Bit Sequential Carrier

·

512 ´ 4-bit RAM

4096 ´ 8-bit ROM

·

Supports 16-bit serial data transfer in arbitrary

format

Power-Down Modes

I/O Pins

·

Idle mode (only CPU clock stops)

Stop mode (system clock stops)

·

17 pins I/O

N-channel open-drain I/O: 8 pins

Oscillation Sources

8-Bit Basic Timer

·

Crystal, or ceramic for system clock

Crystal, ceramic: 0.4–6.0 MHz

·

Programmable interval timer

Watchdog timer

CPU clock divider circuit (by 4, 8, or 64)

Interval 8-Bit Timer/Counter

Instruction Execution Times

·

Programmable interval timer

·

0.95, 1.91, and 15.3 ms at 4.19 MHz

0.67, 1.33, 10.7 ms at 6.0 MHz

External event counter function

Timer/counter clock output to TCLO0 pin

Operating Temperature

Buzzer Output

°

·

– 40 C to 85 °C

·

Four frequency output to BUZ pin

Operating Voltage Range

D/A Converter

·

1.8 V to 5.5 V (at 3 MHz)

2.7 V to 5.5 V (at 6 MHz)

·

8-bit D/A converter

Interrupts

Package Types

·

Two external interrupt vectors

·

24-pin SOP-375

24-pin SDIP-300

Two internal interrupt vectors

One quasi-interrupt

Memory-Mapped I/O Structure

·

Data memory bank 15

1-2

KS57C5404/P5404

PRODUCT OVERVIEW

BLOCK DIAGRAM

Watchdog

Timer

INT0, INT1

RESET

X

OUT

IN

Basic

Timer

8-bit

Timer/

Counter

Interrupt

Stack

Control

Block

Clock

Pointer

Buzzer

I/O Port 0

I/O Port 1

I/O Port 2

D/A

Converter

DAO

Program

Counter

P0.0/INT0

P0.1/INT1

P0.2/KS0

P0.3/KS1

Internal

Interrupts

Program

Status

Word

P4.0–P4.3

P5.0–P5.3

I/O Port 4

I/O Port 5

Instruction Decoder

Arithmetic Logic Unit

P1.0/TCL0

P1.1/TCLO0

P1.2/CLO

P1.3/BUZ

Flags

P2.0

512 x 4-bit

Data

Memory

4 K byte

Program

Memory

Figure 1-1. KS57C5404 Simplified Block Diagram

1-3

PRODUCT OVERVIEW

KS57C5404/P5404

PIN ASSIGNMENTS

V

X

OUT

X

V

DD

P5.3

P5.2

P5.1

P5.0

P4.3

P4.2

P4.1

P4.0

P2.0

P1.3/BUZ

P1.2/CLO

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

16

15

14

13

SS

IN

TEST

P0.0/INT0

DAO

P0.1/INT1

RESET

P0.2/KS0

P0.3/KS1

9

10

11

12

P1.0/TCL0

P1.1/TCLO0

Figure 1-2. KS57C5404 Pin Assignment Diagrams

1-4

KS57C5404/P5404

PRODUCT OVERVIEW

PIN DESCRIPTIONS

Table 1-1. KS57C5404 Pin Descriptions

Description

Pin Name

Pin Type

Share Pin

P0.0

P0.1

P0.2

P0.3

I

4-bit I/O port. 1- or 4-bit read/write and test is possible.

Pull-up resistors are assignable to input pins by software and are

automatically disabled for output pins. Pins are individually configurable

as input or output.

INT0

INT1

KS0

KS1

P1.0

P1.1

P1.2

P1.3

I/O

4-bit I/O port. 1- or 4-bit read/write and test is possible.

Pull-up resistors are assignable to input pins by software and are

automatically disabled for output pins. Pins are individually configurable

as input or output.

TCL0

TCLO0

CLO

BUZ

P2.0

I/O

1-bit I/O port. 1- or 4-bit read/write and test is possible.

Pull-up resistors are assignable to input pins by software and are

automatically disabled for output pins.

–

P4.0–P4.3

P5.0–P5.3

4-bit I/O port. 1- or 4-bit read/write and test is possible.

Pins are individually configurable as input or output.

Pull-up resistors are assignable to input pins by software and are

automatically disabled for output pins.

–

The N-channel open drain or push-pull output can be selected by

software (1-bit unit).

INT0

INT1

I/O

External interrupts with rising/falling edge detection

Quasi-interrupt input with falling edge detection

P0.0

P0.1

KS0

KS1

P0.2

P0.3

TCL0

TCLO0

CLO

I/O

O

–

External clock input for timer/counter

Timer/counter clock output

P1.0

P1.1

P1.2

P1.3

–

CPU clock output

BUZ

0.5, 1, 2, or 4 kHz frequency output at 4.19 MHz for buzzer sound

8-bit D/A converter output

DAO

VDD

Main power supply

–

VSS

–

Ground

–

RESET

TEST

X_IN, X_OUT

I

Reset signal

–

I

Chip test input pin. Hold GND when the device is operating.

Crystal, ceramic oscillator signal for system clock

–

1-5

PRODUCT OVERVIEW

KS57C5404/P5404

Table 1-2. Overview of KS57C5404 Pin Data

SDIP Pin Numbers

Share Pins

I/O Type

Reset Value

Circuit Type

V_SS

–

X_OUT, X_IN

–

TEST

–

I

–

P0.0, P0.1

RESET

INT0, INT1

–

I/O

I

Input

–

D-4

B

P0.2

P0.3

KS0

KS1

I/O

Input

D-4

P1.0

P1.1

P1.2

P1.3

TCL0

TCLO0

CLO

I/O

Input

D-2

BUZ

P2.0

–

I/O

O

Input

Output

Input

–

D-2

–

DAO

P4.0–P4.3

P5.0–P5.3

V_DD

I/O

–

E-2

–

1-6

KS57C5404/P5404

PRODUCT OVERVIEW

PIN CIRCUIT DIAGRAMS

V

DD

V

DD

-

P Channel

-

P Channel

Data

IN

Out

-

N Channel

-

N Channel

Output

Disable

Figure 1-3. Pin Circuit Type A

Figure 1-5. Pin Circuit Type C

V

DD

V

DD

Pull-up

Resistor

Pull-up

Enable

P-Channel

In/Out

Data

Circuit

Type C

IN

Output

Disable

Schmitt Trigger

Figure 1-6. Pin Circuit Type D-2

Figure 1-4. Pin Circuit Type B

1-7

PRODUCT OVERVIEW

KS57C5404/P5404 (Preliminary Spec)

V

DD

V

DD

Pull-Up

Resistor

PNE

V

DD

Resistor

Enable

Pull-up

Enable

P-Channel

In/Out

Data

Circuit

Type C

Output

Disable

Output

Disable

Figure 1-7. Pin Circuit Type D-4

Figure 1-8. Pin Circuit Type E-2

1-8

KS57C5404/P5404

ADDRESS SPACES

2

ADDRESS SPACES

PROGRAM MEMORY (ROM)

OVERVIEW

ROM maps for the KS57C5404 device are mask programmable at the factory. In its standard configuration, the

device's 4096 ´ 8-bit program memory has three areas that are directly addressable by the program counter (PC):

— 16-byte area for vector addresses

— 16-byte general-purpose area

— 96-byte instruction reference area

— 3968-byte general-purpose area

General-Purpose Memory

Two program memory areas are allocated for general-purpose use: One area is 16 bytes in size and the other is

3968 bytes.

Vector Addresses

You use the 16-byte vector address area to store the vector addresses required to execute

RESET

interrupts. Start addresses for interrupt service routines are stored in this area, along with the values of the enable

memory bank (EMB) and enable register bank (ERB) flags that are used to set their initial value for the corre-

sponding service routines. The 16-byte area can be used alternately as general-purpose ROM.

REF Instructions

Locations 0020H–007FH are used as a reference area (look-up table) for 1-byte REF instructions. Using REF

instructions, you can reduce the byte size of instruction operands. REF can reference one 2-byte instruction, two

1-byte instructions, and three-byte instruction which are stored in the look-up table. Unused look-up table

addresses can be used as general-purpose ROM.

Table 2-1. Program Memory Address Ranges

ROM Area Function

Vector address area

Address Ranges

0000H–000FH

0010H–001FH

0020H–007FH

0080H–0FFFH

Area Size (in Bytes)

16

General-purpose program memory

REF instruction look-up table area

General-purpose program memory

96

3968

2-1

ADDRESS SPACES

KS57C5404/P5404

GENERAL-PURPOSE MEMORY AREAS

The 16-byte area at the ROM locations 0010H–001FH and the 3968-byte area at the ROM locations 0080H–

0FFFH are used as general-purpose program memory.

You can also use vacant locations in the vector address area and REF instruction look-up table areas as general-

purpose program memory. But please be careful not to overwrite live data when writing programs that use

special-purpose areas of the ROM.

VECTOR ADDRESS AREA

Use the 16-byte vector address area of the ROM to store the vector addresses for executing

interrupts. The starting addresses of interrupt service routines are stored in this area, along with the enable mem-

ory bank (EMB) and enable register bank (ERB) flag values that are needed to set EMB and ERB's initial values

for the service routines. A 16-byte vector address is organized as follows:

PC13 ^(note)PC12 ^(note)

PC5 PC4

EMB

PC7

ERB

PC6

PC11

PC3

PC10

PC2

PC9

PC1

PC8

PC0

NOTE: PC13, 12 are always logic 0.

To set up the vector address area for specific programs, you should use the instruction VENTn. The programming

tips on the next page explain how to do this.

0000H

7

6

5

4

3

2

1

0

Vector

RESET

Address Area

(16 Bytes)

0000H

0002H

0004H

0006H

0008H

000AH

000CH

000EH

000FH

0010H

General-Purpose

Area

INTB

INT0

INT1

(16 Bytes)

001FH

0020H

Instruction

Reference Area

(96 Bytes)

007FH

0080H

Not implemented

(Reserved for future use)

INTT0

General-Purpose

Area

(3968 Bytes)

Not implemented

(Reserved for future use)

Not implemented

(Reserved for future use)

0FFFH

Figure 2-1. ROM Structure

Figure 2-2. Vector Address Map

2-2

KS57C5404/P5404

ADDRESS SPACES

+

PROGRAMMING TIP — Defining Vectored Interrupt Areas

The following examples show you several ways you can define the vectored interrupt area in program memory:

1. When all vector interrupts are used:

ORG

0000H

;

VENT0

VENT1

VENT2

VENT3

NOP

1,0,RESET

0,0,INTB

0,0,INT0

0,0,INT1

;

EMB ¬ 1, ERB ¬ 0; Jump to RESET address

EMB ¬ 0, ERB ¬ 0; Jump to INTB address

EMB ¬ 0, ERB ¬ 0; Jump to INT0 address

EMB ¬ 0, ERB ¬ 0; Jump to INT1 address

NOP

VENT5

0,0,INTT0

;

EMB ¬ 0, ERB ¬ 0; Jump to INTT0 address

2. When a specific vectored interrupt such as INT0, and INTT0 is not used, the unused vector interrupt locations

must be skipped with the assembly instruction ORG so that jumps will address the correct locations:

ORG

0000H

;

VENT0

VENT1

ORG

1,0,RESET

0,0,INTB

0006H

;

EMB ¬ 1, ERB ¬ 0; Jump to RESET address

EMB ¬ 0, ERB ¬ 0; Jump to INTB address

INT0 interrupt not used

VENT3

0,0,INT1

EMB ¬ 0, ERB ¬ 0; Jump to INT1 address

;

ORG

0010H

;

INTT0 interrupt not used

3. If an INT0 interrupt is not used and its corresponding vector interrupt area is not fully utilized, or if it is not

written by an ORG instruction as in Example 2, a CPU malfunction will occur:

ORG

0000H

;

VENT0

VENT1

VENT3

VENT5

1,0,RESET

0,0,INTB

0,0,INT1

;

EMB ¬ 1, ERB ¬ 0; Jump to RESET address

EMB ¬ 0, ERB ¬ 0; Jump to INTB address

EMB ¬ 0, ERB ¬ 0; Jump to INT1 address by INT0

EMB ¬ 0, ERB ¬ 0; Jump to INTT0 address by INT1

0,0,INTT0

;

ORG

0010H

General-purpose ROM area

In this example, when an INT0 interrupt is generated, the corresponding vector area is not VENT2 INT0, but

VENT3 INT1. This causes an INT0 interrupt to jump incorrectly to the INT1 address, causing a CPU malfunction.

2-3

ADDRESS SPACES

KS57C5404/P5404

INSTRUCTION REFERENCE AREA

Using 1-byte REF instructions, you can easily reference instructions with larger byte sizes that are stored in the

addresses 0020H–007FH of program memory. This 96-byte area is called the REF instruction reference area, or

look-up table. Locations in the REF look-up table may contain two one-byte instructions, a single two-byte

instruction, or three-byte instructions such as a JP or CALL. The starting address of the instruction you are

referencing must always be an even number. To reference a JP or CALL instruction, it must be written to the

reference area in a two-byte format: for JP, this format is TJP; for CALL, it is TCALL. In summary, there are three

ways to the REF instruction:

— Using the 1-byte REF instruction to execute one 2-byte or two 1-byte instructions,

— Branching to any location by referencing a branch instruction stored in the look-up table,

— Calling subroutines at any location by referencing a call instruction stored in the look-up table.

+

PROGRAMMING TIP — Using the REF Look-Up Table

Here is one example of how to use the REF instruction look-up table:

ORG

0020H

;

JMAIN

KEYCK

WATCH

INCHL

TJP

BTSF

TCALL

LD

INCS

•

MAIN

;

0, MAIN

1, KEYFG CHECK

2, CALL CLOCK

KEYFG

CLOCK

@HL,A

HL

3, (HL) ¬

A

•

ABC

LD

ORG

EA,#00H

0080

;

47, EA ¬ #00H

;

MAIN

NOP

•

REF

KEYCK

JMAIN

WATCH

INCHL

;

BTSF KEYFG (1-byte instruction)

KEYFG = 1, jump to MAIN (1-byte instruction)

KEYFG = 0, CALL CLOCK (1-byte instruction)

LD @HL,A

INCS HL

LD EA,#00H (1-byte instruction)

REF

ABC

•

2-4

KS57C5404/P5404

ADDRESS SPACES

DATA MEMORY (RAM)

OVERVIEW

In its standard configuration, the 512 ´ 4-bit data memory has five areas:

— 32 ´ 4-bit working register area

— 224 ´ 4-bit general-purpose area in bank 0 (also used as stack area)

— 256 ´ 4-bit general-purpose area in bank 1

— 128 ´ 4-bit area for memory-mapped I/O addresses

To simplify referencing, the data memory area has three memory banks — bank 0, bank 1 and bank 15. You

should use the select memory bank instruction (SMB) to select the bank you want to use as working data

memory. Data stored in RAM locations are 1-, 4-, and 8-bit addressable. Initialization values for the data memory

area are not defined by hardware and must therefore be initialized by program software following a

signal is generated in power-down mode, the data memory contents are maintained.

. When a

000H

Working Registers

(32 x 4 Bits)

01FH

020H

General-Purpose

Bank 0

Registers

And Stack Area

(224 x 4 Bits)

0FFH

100H

General-Purpose

Bank 1

(256 x 4 Bits)

1FFH

~

F80H

FFFH

Periphral Hardware

Registers

Bank 15

Figure 2-3. Data Memory (RAM) Map

2-5

ADDRESS SPACES

KS57C5404/P5404

Memory Banks 0, 1 and 15

Bank 0

(000H–0FFH)

The lowest 32 nibbles of bank 0 (000H–01FH) are used as working registers;

the next 224 nibbles (020H–0FFH) can be used both as stack area and as

general-purpose data memory. Use the stack area for implementing subroutine

calls and returns, and for interrupt processing.

Bank 1

(100H–1FFH)

(F80H–FFFH)

This area is used as general-purpose data memory.

Bank 15

The microcontroller uses bank 15 for memory-mapped peripheral I/O. Fixed

RAM locations for each peripheral hardware address are mapped into this

area.

Data Memory Addressing Modes

The enable memory bank (EMB) flag controls the addressing mode for data memory bank 0 or 15. When the

EMB flag is logic zero, the addressable area is restricted to specific locations, depending on whether direct or

indirect addressing is used. With direct addressing, you can access the locations 000H–07FH of bank 0, bank 1

and bank 15. With indirect addressing, only bank 0 (000H–0FFH) can be accessed. When the EMB flag is set to

logic one, three data memory banks can be accessed according to the current SMB value.

For 8-bit addressing, two 4-bit registers are addressed as a register pair. When using 8-bit instructions to address

RAM locations, remember to use the even-numbered register address as the instruction operand.

Working Registers

The RAM working register area in data memory bank 0 is further divided into four register banks (bank 0, 1, 2,

and 3). Each register bank has eight 4-bit registers and paired 4-bit registers are 8-bit addressable.

Register A is used as a 4-bit accumulator and the register pair EA is an 8-bit extended accumulator. The carry

flag bit can also be used as a 1-bit accumulator. The register pairs WX, WL, and HL are used as address pointers

for indirect addressing. To limit the possibility of data corruption caused by incorrect register addressing, it is

advisable to use register bank 0 for the main program and banks 1, 2, and 3 for interrupt service routines.

Bit Sequential Carrier (BSC)

The bit sequential carrier (BSC) is a 16-bit general register mapped to the RAM addresses FC0H–FC3H that can

be manipulated by 1-, 4-, and 8-bit RAM control instructions. A

clears all bit values to logic zero.

You can specify addresses and bit locations sequentially using a 1-bit indirect addressing instruction. In this way,

a program can process 16-bit data by moving the bit location sequentially, incrementing or decrementing the

value of the L register. BSC data can also be manipulated by direct addressing. For 8-bit manipulations, you must

address the upper and lower 8 bits separately.

2-6

KS57C5404/P5404

ADDRESS SPACES

Table 2-2. Data Memory Organization and Addressing

Addresses

000H–01FH

020H–0FFH

100H–1FFH

F80H–FFFH

Register Areas

Working registers

Bank

EMB Value

SMB Value

0

0, 1

0

Stack and general-purpose registers

General-purpose registers

1

I/O-mapped hardware registers

15

0, 1

15

+

PROGRAMMING TIP — Clearing Data Memory Banks 0 and 1

Clear bank 0 of the data memory area:

RAMCLR

BITS

SMB

LD

EMB

0

HL,#10H

A,#0H

@HL,A

HL

RMCL0

;

; RAM (010H–0FFH) clear

INCS

JR

RMCL0

2-7

ADDRESS SPACES

KS57C5404/P5404

WORKING REGISTERS

Working registers, mapped to the RAM address 000H-01FH in data memory bank 0 are used to temporarily store

intermediate results during program execution, as well as pointer values used for indirect addressing. Unused

registers may be used as general-purpose memory. Working register data can be manipulated as 1-bit units,

4-bit units or, using paired registers, as 8-bit units.

000H

0001

002H

A

E

L

003H

H

X

Working

Register

Bank 0

004H

005H

006H

007H

008H

W

Z

Data

Memory

Bank 0

Y

Register

Bank 1

A ... Y

00FH

010H

Register

Bank 2

017H

018H

Register

Bank 3

01FH

Figure 2-4. Working Register Map

2-8

KS57C5404/P5404

ADDRESS SPACES

Working Register Banks

For addressing purposes, the working register area is divided into four register banks — bank 0, bank 1, bank 2,

and bank 3. Any one of these banks can be selected as the working register bank by the register bank selection

instruction (SRBn) and by setting the status of the register bank enable flag (ERB).

Generally, working register bank 0 is used for the main program, and banks 1, 2, and 3 for interrupt service rou-

tines. Following this convention helps to prevent possible data corruption during program execution due to con-

tention in register bank addressing.

Table 2-3. Working Register Organization and Addressing

ERB Setting

SRB Settings

Selected Register Bank

3

2

1

x

0

1

0

x

0

1

0

1

0

1

0

Always set to bank 0

Bank 0

0

Bank 1

Bank 2

Bank 3

NOTE: 'x' means “don't care”.

Paired Working Registers

Each of the register banks is subdivided into eight 4-bit registers. These registers are named Y, Z, W, X, H, L, E

and A. You can manipulate them individually using 4-bit instructions, or as register pairs for 8-bit data

manipulation.

The names of the 8-bit register pairs in each register bank are EA, HL, WX, YZ and WL. Registers A, L, X and Z

always become the lower nibble when registers are addressed as 8-bit pairs. This makes a total of eight 4-bit

registers or four 8-bit double registers in each of the four working register banks.

(MSB)

(LSB)

(MSB)

(LSB)

Y

W

H

E

Z

X

L

A

Figure 2-5. Register Pair Configuration

2-9

ADDRESS SPACES

KS57C5404/P5404

Special-Purpose Working Registers

You use register A as a 4-bit accumulator and double register EA as an 8-bit accumulator. You can use the carry

flag as a 1-bit accumulator.

8-bit double registers WX, WL and HL are used as data pointers for indirect addressing. When the HL register

serves as a data pointer, the instructions LDI, LDD, XCHI, and XCHD can make very efficient use of working reg-

isters as program loop counters by letting you transfer a value and increment or decrement the L register value

using a single instruction.

1-Bit

C

Accumulator

4-Bit

Accumulator

A

8-Bit

Accumulator

EA

Figure 2-6. 1-Bit, 4-Bit, and 8-Bit Accumulator

Recommendation for Multiple Interrupt Processing

If more than four interrupts are being processed at one time, you can avoid possible loss of working register data

by using the PUSH RR instruction to save register contents to the stack before the service routines are executed

in the same register bank. When the routines have executed successfully, you can restore the register contents

from the stack to working memory using the POP instruction.

2-10

KS57C5404/P5404

ADDRESS SPACES

+

PROGRAMMING TIP — Selecting Your Working Register Area

The following examples show the correct programming method for selecting working register area:

1. When ERB = "0":

VENT2

;

1,0,INT0

;

EMB ¬ 1, ERB ¬ 0, Jump to INT0 address

INT0

PUSH

SRB

PUSH

SMB

LD

INCS

LD

POP

IRET

SB

2

HL

WX

YZ

EA

0

EA,#00H

80H,EA

HL,#40H

HL

WX,EA

YZ,EA

EA

YZ

WX

HL

SB

;

PUSH current SMB, SRB

Non-essential instruction, since ERB = "0"

PUSH HL register to stack

PUSH WX register to stack

PUSH YZ register to stack

PUSH EA register to stack

;

POP EA register from stack

POP YZ register from stack

POP WX register from stack

POP HL register from stack

POP current SMB, SRB

;

The POP instructions execute alternately with the PUSH instructions. If an SMB instruction is used in an interrupt

service routine, a PUSH and POP SB instruction must be used to store and restore the current SMB and SRB

values, as shown in Example 2 below.

2. When ERB = "1":

VENT2

;

1,1,INT0

;

EMB ¬ 1, ERB ¬ 1, Jump to INT0 address

INT0

PUSH

SRB

SMB

LD

INCS

LD

POP

IRET

SB

2

0

EA,#00H

80H,EA

HL,#40H

HL

WX,EA

YZ,EA

SB

;

Store current SMB, SRB

Select register bank 2

;

Restore SMB, SRB

;

2-11

ADDRESS SPACES

KS57C5404/P5404

STACK OPERATIONS

STACK POINTER (SP)

The stack pointer (SP) is an 8-bit register that stores the address used to access the stack, an area of data

memory set aside for temporary storage of data and addresses. The SP is mapped to the RAM addresses

F80H-F81H, and can be read or written by 8-bit control instructions. When addressing the SP, bit 0 must always

remain cleared to logic zero.

F80H

F81H

SP3

SP7

SP2

SP6

SP1

SP5

"0"

SP4

There are two basic stack operations: writing to the top of the stack (push), and reading from the top of the stack

(pop). A push decrements the SP and a pop increments it so that the SP always points to the top address of the

last data to be written to the stack.

The program counter contents and program status word are stored in the stack area prior to the execution of a

CALL or PUSH instruction, or during interrupt service routines. Stack operation is in a LIFO (Last-In First-Out)

type. The stack area is located in general-purpose data memory bank 0.

During an interrupt or subroutine, the PC value and the PSW are saved to the stack area. When the routine has

completed, the stack pointer is referenced to restore the PC and PSW, and the next instruction is executed.

The SP can address stack registers in bank 0 (addresses 000H-0FFH) regardless of the current value of the en-

able memory bank (EMB) flag and the select memory bank (SMB) flag.

Since the reset value of the stack pointer is not defined in firmware, we recommend that you initialize the stack

pointer by program code to location 00H. This sets the first register of the stack area to 0FFH.

NOTE

A subroutine call occupies six nibbles in the stack; an interrupt requires six. When subroutine nesting or

interrupt routines are used continuously, the stack area should be set in accordance with the maximum

number of subroutine levels. To do this, estimate the number of nibbles that will be used for the

subroutines or interrupts and set the stack area correspondingly.

Although you may use general-purpose register areas for stack operations, be careful to avoid data loss caused

by simultaneous use of the same register(s).

+

PROGRAMMING TIP — Initializing the Stack Pointer

To initialize the stack pointer (SP):

1. When EMB = "1":

SMB

LD

15

EA,#00H

SP,EA

;

Select memory bank 15

Bit 0 of accumulator A is always cleared to "0"

Stack area initial address (0FFH) ¬ (SP) – 1

2.

When EMB = "0":

LD

EA,#00H

SP,EA

;

Memory addressing area (00H–7FH, F80H–FFFH)

2-12

KS57C5404/P5404

ADDRESS SPACES

PUSH OPERATIONS

Three kinds of push operations reference the stack pointer (SP) to write data from the source register to the stack:

PUSH instructions, CALL instructions, and interrupts. In each case, the SP is decremented by a number de-

termined by the type of push operation, pointing to the next stack location available.

PUSH Instructions

A PUSH instruction references the SP to write two 4-bit data nibbles from the PC to the stack. Two 4-bit stack

addresses are referenced by the stack pointer: one for the upper register value and the other for the lower

register. After the PUSH has executed, the SP is decremented by two, pointing to the next stack location

available.

CALL Instructions

When a subroutine call is issued, the CALL instruction references the SP to write the PC's contents to four 4-bit

stack locations. Current values for the enable memory bank (EMB) flag and the enable register bank (ERB) flag

are also pushed to the stack. After the CALL has executed, the SP is decremented by six, pointing to the next

stack location available. Since six 4-bit stack locations are used per CALL, you may nest subroutine calls up to

the number of levels permitted in the stack.

Interrupt Routines

An interrupt routine references the SP to push the contents of the PC, as well as current values for the program

status word (PSW) to the stack. Six 4-bit stack locations are used to store this data. After the interrupt has

executed, the SP is decremented by six, pointing to the next stack location available. During an interrupt

sequence, subroutines may be nested up to the number of levels which are permitted in the stack area.

INTERRUPT

PUSH

(After PUSH, SP

CALL

(After CALL, SP

(When INT is acknowledged,

SP - 2)

SP - 6)

SP

SP - 6)

SP - 6

SP - 5

SP - 4

SP - 3

SP - 2

SP - 1

SP

PC 11-PC 8

SP - 6

SP - 5

SP - 4

SP - 3

SP - 2

SP - 1

SP

0

PC3 - PC0

PC7 - PC4

PC3 - PC0

PC7 - PC4

IS1

C

IS0 EMB ERB

0

EMB ERB

LOWER REGISTER

UPPER REGISTER

SP - 2

SP - 1

SP

PSW

SC2 SC1 SC0

0

Figure 2-7. Push-Type Stack Operations

2-13

ADDRESS SPACES

POP OPERATIONS

KS57C5404/P5404

For each push operation there is a corresponding pop operation to write data from the stack back to the source

register or registers: for the PUSH instruction it is the POP instruction; for CALL, the instruction RET or SRET; for

interrupts, the instruction IRET. When a pop operation occurs, the SP is incremented by a number determined by

the type of operation, pointing to the next stack location free.

POP Instructions

A POP instruction references the SP to write data stored in two 4-bit stack locations back to the register pairs and

SB register. The value for the lower 4-bit register is popped first, followed by the value for the upper 4-bit register.

After the POP has executed, the SP is incremented by two, pointing to the next stack location free.

RET and SRET Instructions

The end of a subroutine call is signaled by the return instruction, RET or SRET. The RET or SRET uses the SP to

reference the four 4-bit stack locations used for the CALL and to write this data back to the PC, the EMB, and

ERB. After the RET or SRET has executed, the SP is incremented by six, and pointing to the next stack location

free.

IRET Instructions

The end of an interrupt sequence is signaled by the instruction IRET. IRET references the SP to locate the six 4-

bit stack addresses used for the interrupt and to write this data back to the PC and the PSW. After the IRET has

executed, the SP is incremented by six, pointing to the next stack location free.

POP

SP + 2)

RET

(SP

SRET

IRET

SP + 6)

OR

(SP

SP + 6)

(SP

PC11-PC8

SP

LOWER REGISTER

UPPER REGISTER

SP

0

SP + 1

SP + 2

SP + 1

SP + 2

SP + 3

SP + 4

SP + 5

SP + 6

SP + 1

SP + 2

SP + 3

SP + 4

SP + 5

SP + 6

PC3 - PC0

PC7 - PC4

PC3 - PC0

PC7 - PC4

0

EMB ERB

IS1

C

IS0 EMB ERB

PSW

SC2 SC1 SC0

0

Figure 2-8. Pop-Type Stack Operations

2-14

KS57C5404/P5404

ADDRESS SPACES

BIT SEQUENTIAL CARRIER (BSC)

The bit sequential carrier (BSC) is a 16-bit register that is mapped to the RAM addresses FC0H–FC3H. You can

manipulate the BSC register using 1-, 4-, and 8-bit RAM control instructions. A

logic zero.

clears all BSC bit values to

Using the BSC, you can specify addresses and bit locations sequentially using 1-bit indirect addressing

(memb.@L). Bit addressing is independent of the current EMB value. In this way, programs can process 16-bit

data by moving the bit location sequentially and then incrementing or decrementing the value of the L register.

BSC data can also be manipulated using direct addressing. For 8-bit manipulations, specify the 4-bit register

names BSC0 and BSC2 and manipulate the upper and lower 8 bits separately.

If the value of the L register is 0H at BSC0.@L, the address and bit location assignment is FC0H.0. If the L

register content is FH at BSC0.@L, the address and bit location assignment is FC3H.3.

Table 2-4. BSC Register Organization

Name

BSC0

BSC1

BSC2

BSC3

Address

FC0H

Bit 3

Bit 2

Bit 1

Bit 0

BSC0.3

BSC1.3

BSC2.3

BSC3.3

BSC0.2

BSC1.2

BSC2.2

BSC3.2

BSC0.1

BSC1.1

BSC2.1

BSC3.1

BSC0.0

BSC1.0

BSC2.0

BSC3.0

FC1H

FC2H

FC3H

+

PROGRAMMING TIP — Using the BSC Register to Output 16-Bit Data

To use the bit sequential carrier (BSC) register to output 16-bit data (5937H) to the P3.0 pin:

BITS

SMB

LD

EMB

15

EA,#37H

BSC0,EA

EA,#59H

BSC2,EA

0

;

BSC0 ¬ A, BSC1 ¬

BSC2 ¬ A, BSC3 ¬

E

LD

SMB

LD

L,#0H

C,BSC0.@L

P3.0,C

L

;

AGN

LDB

INCS

JR

P3.0 ¬

C

AGN

RET

2-15

ADDRESS SPACES

KS57C5404/P5404

PROGRAM COUNTER (PC)

A 12-bit program counter (PC) stores addresses for instruction fetches during program execution. Whenever a

reset operation or an interrupt occurs, the bits PC11 through PC0 are set to the vector address. The bits bit

PC12–PC13 are reserved to support future expansion of the device's ROM size.

Usually, the PC is incremented by the number of bytes of the instruction being fetched. One exception is the 1-

byte REF instruction which is used to reference instructions stored in the ROM.

PROGRAM STATUS WORD (PSW)

The program status word (PSW) is an 8-bit word, mapped to the RAM locations FB0H–FB1H, which defines

system status and program execution status and permits an interrupted process to resume operation after an

interrupt request has been serviced. PSW values are mapped as follows:

FB0H

FB1H

IS1

C

IS0

EMB

SC1

ERB

SC0

SC2

The PSW can be manipulated by 1-bit or 4-bit read/write and by 8-bit read instructions, depending on the specific

bit or bits being addressed. The PSW can be addressed during program execution regardless of the current value

of the enable memory bank (EMB) flag.

Part or all of the PSW is saved to the stack prior to the execution of a subroutine call or hardware interrupt. After

the interrupt has been processed, the PSW values are popped from the stack back to the PSW address.

When a

is generated, the EMB and ERB values are set according to the

vector address, and the carry

flag is left undefined (or the current value is retained). PSW bits IS0, IS1, SC0, SC1, and SC2 are all cleared to

logic zero.

Table 2-5. Program Status Word Bit Descriptions

PSW Bit Identifier

IS1, IS0

Description

Interrupt status flags

Enable memory bank flag

Enable register bank flag

Carry flag

Bit Addressing

Read/Write

R/W

1, 4

1

EMB

R/W

ERB

1

R/W

C

1

R/W

SC2, SC1, SC0

Program skip flags

8

R

2-16

KS57C5404/P5404

ADDRESS SPACES

INTERRUPT STATUS FLAGS (IS0, IS1)

PSW bits IS0 and IS1 contain the current interrupt execution status values. They are mapped to the RAM bit loca-

tions FB0H.2 and FB0H.3, respectively. You can manipulate IS0 and IS1 flags directly using 1-bit RAM control in-

structions

By manipulating interrupt status flags in conjunction with the interrupt priority register (IPR), you can process

multiple interrupts by anticipating the next interrupt in an execution sequence. The interrupt priority control circuit

determines the IS0 and IS1 settings in order to control multiple interrupt processing. When both interrupt status

flags are set to "0", all interrupts are allowed. The priority with which interrupts are processed is then determined

by the IPR.

When an interrupt occurs, IS0 and IS1 are pushed to the stack as part of the PSW and are automatically

incremented to the next higher priority level. Then, when the interrupt service routine ends with an IRET instruc-

tion, IS0 and IS1 values are restored to the PSW. Table 2-6 shows the effects of IS0 and IS1 flag settings.

Table 2-6. Interrupt Status Flag Bit Settings

IS1

Value

IS0

Value

Status of Currently

Executing Process

Effect of IS0 and IS1 Settings

on Interrupt Request Control

0

1

0

1

All interrupt requests are serviced

Only high-priority interrupt(s) as determined in the

interrupt priority register (IPR) is serviced

1

0

1

2

–

No more interrupt requests are serviced

Not applicable; these bit settings are undefined

Since interrupt status flags can be addressed by write instructions, programs can exert direct control over

interrupt processing status. Before interrupt status flags can be addressed, however, you must first execute a DI

instruction to inhibit additional interrupt routines. When the bit manipulation has been completed, execute an EI in-

struction to re-enable interrupt processing.

+

PROGRAMMING TIP — Setting ISx Flags for Interrupt Processing

The following instruction sequence shows how to use the IS0 and IS1 flags to control interrupt processing:

INTB

DI

;

Disable interrupt

IS1 ¬ 0

Allow interrupts according to IPR priority level

Enable interrupt

BITR

BITS

EI

IS1

IS0

2-17

ADDRESS SPACES

EMB FLAG (EMB)

KS57C5404/P5404

The enable memory bank flag EMB is mapped to the registers FB0H–FB1H in bank 15 of the RAM. The EMB flag

occupies the bit location 1 in the register FB0H.

The EMB flag is used to allocate specific address locations in the RAM by modifying the upper 4 bits of 12-bit

data memory addresses. In this way, it controls the addressing mode for data memory banks 0, bank 1 or 15.

When the EMB flag is "0", the data memory address space is restricted to bank 15 and the addresses 000H–

07FH of memory bank 0, regardless of the SMB register contents. When the EMB flag is set to "1", you can

access general-purpose areas of bank 0, bank 1, and bank 15 by using the appropriate SMB value.

+

PROGRAMMING TIP — Using the EMB Flag to Select Memory Banks

EMB flag settings for memory bank selection:

1. When EMB = "0":

SMB

LD

SMB

LD

0

;

Non-essential instruction, since EMB = "0"

(F90H) ¬ A, bank 15 is selected

(034H) ¬ A, bank 0 is selected

Non-essential instruction, since EMB = "0"

(020H) ¬ A, bank 0 is selected

90H,A

34H,A

15

20H,A

90H,A

LD

(F90H) ¬ A, bank 15 is selected

;

2. When EMB = "1":

SMB

LD

SMB

LD

0

;

Select memory bank 0

90H,A

34H,A

15

20H,A

90H,A

(090H) ¬ A, bank 0 is selected

(034H) ¬ A, bank 0 is selected

Select memory bank 15

Program error, but assembler does not detect it

(F90H) ¬ A, bank 15 is selected

;

2-18

KS57C5404/P5404

ERB FLAG (ERB)

ADDRESS SPACES

The 1-bit register bank enable flag (ERB) determines the range of addressable working register area. When the

ERB flag is "1", you should select the working register area from the register banks 0 to 3 according to the register

bank selection register (SRB). When the ERB flag is "0", you should select register bank 0 as the working register

area, regardless of the current value of the register bank selection register (SRB).

When an internal

is generated, bit 6 of the program memory address 0000H is written to the ERB flag. This

automatically initializes the flag. When a vectored interrupt is generated, bit 6 of the respective vector address

table in the program memory is written to the ERB flag, setting the correct flag status before the interrupt service

routine is executed.

During the interrupt routine, the ERB value is automatically pushed to the stack area along with the other PSW

bits. Afterwards, it is popped back to the FB0H.0 bit location. The initial ERB flag settings for each vectored inter-

rupt are defined using VENTn instructions.

+

PROGRAMMING TIP — Using the ERB Flag to Select Register Banks

ERB flag settings for register bank selection:

1. When ERB = "0":

SRB

1

;

Register bank 0 is selected (since ERB = "0", the

SRB is configured to bank 0)

Bank 0 EA ¬ #34H

Bank 0 HL ¬ EA

Register bank 0 is selected

Bank 0 YZ ¬ EA

LD

SRB

LD

SRB

LD

EA,#34H

HL,EA

2

YZ,EA

3

Register bank 0 is selected

Bank 0 WX ¬ EA

WX,EA

;

2. When ERB = "1":

SRB

LD

SRB

LD

SRB

LD

1

;

Register bank 1 is selected

Bank 1 EA ¬ #34H

EA,#34H

HL,EA

2

YZ,EA

3

Bank 1 HL ¬ Bank 1 EA

Register bank 2 is selected

Bank 2 YZ ¬ BANK 2 EA

Register bank 3 is selected

Bank 3 WX ¬ Bank 3 EA

WX,EA

;

2-19

ADDRESS SPACES

KS57C5404/P5404

SKIP CONDITION FLAGS (SC2, SC1, SC0)

The skip condition flags SC2, SC1, and SC0 indicate the current program skip conditions and they are set and

reset automatically during program execution. These flags are mapped to the RAM bit locations FB1H.0, FB1H.1,

and FB1H.2 of the PSW.

Skip condition flags can only be addressed by 8-bit read instructions. Direct manipulation of the SC2, SC1, and

SC0 bits is not allowed.

CARRY FLAG (C)

The carry flag is mapped to the bit location FB1H.3 in the PSW. It is used to save the result of an overflow or

borrow when executing arithmetic instructions involving a carry (ADC, SBC). The carry flag can also be used as a

1-bit accumulator performing Boolean operations involving bit-addressed data memory.

If an overflow or borrow condition occurs when executing arithmetic instructions with carry (ADC, SBC), the carry

flag is set to "1". Otherwise, its value is "0". When a

occurs, the current value of the carry flag is retained

during power-down mode, but when normal operating mode resumes, its value is undefined.

The carry flag can be directly manipulated by predefined set of 1-bit read/write instructions, independent of other

bits in the PSW. Only the ADC and SBC instructions, and the instructions listed in Table 2-7 affect the carry flag.

Table 2-7. Valid Carry Flag Manipulation Instructions

Operation Type

Instructions

Carry Flag Manipulation

Set carry flag to "1"

Direct manipulation

SCF

RCF

CCF

Clear carry flag to "0" (reset carry flag)

Invert carry flag value (complement carry flag)

Test carry and skip if C = "1"

BTST C

LDB (operand) ⁽¹⁾,C

LDB C,(operand) ⁽¹⁾

RRC A

Bit transfer

Load carry flag value to the specified bit

Load contents of the specified bit to carry flag

Rotate right with carry flag

Data transfer

BAND C,(operand) ⁽¹⁾

Boolean manipulation

AND the specified bit with contents of carry flag and save

the result to the carry flag

BOR C,(operand) ⁽¹⁾

BXOR C,(operand) ⁽¹⁾

OR the specified bit with contents of carry flag and save

the result to the carry flag

XOR the specified bit with contents of carry flag and save

the result to the carry flag

INTn ⁽²⁾

IRET

Interrupt routine

Save carry flag to stack with other PSW bits

Return from interrupt

Restore carry flag from stack with other PSW bits

NOTES:

1. The operand has three bit addressing formats: mema.a, memb.@L, and @H + DA.b.

2. INTn refers to the specific interrupt being executed, it is not an instruction.

2-20

KS57C5404/P5404

ADDRESS SPACES

+

PROGRAMMING TIP — Using the Carry Flag as a 1-Bit Accumulator

1. Set the carry flag to logic one:

SCF

LD

ADC

;

C ¬ 1

EA ¬ #0C3H

HL ¬ #0AAH

EA ¬ #0C3H + #0AAH + #1H, C ¬ 1

EA,#0C3H

HL,#0AAH

EA,HL

2. Logical-AND bit 3 of address 3FH with P3.3 and output the result to P5.0:

LD

H,#3H

C,@H+0FH.3

C,P3.3

;

Set the upper four bits of the address to the H register value

C ¬ bit 3 of 3FH

C ¬ C AND P3.3

LDB

BAND

LDB

P5.0,C

Output the result from carry flag to P5.0

2-21

ADDRESS SPACES

KS57C5404/P5404

NOTES

2-22

KS57C5404/P5404

ADDRESSING MODES

3

ADDRESSING MODES

OVERVIEW

The enable memory bank flag, EMB, controls the two addressing modes for data memory. When you enable the

EMB flag, you can address the entire RAM area. When you clear the EMB flag to logic zero, the addressable

RAM is restricted to specific areas.

The EMB flag works in connection with the select memory bank instruction, SMB n. Recall that the SMB n

instruction is used to select RAM bank 0, bank 1 or 15. The SMB setting is always contained in the upper four

bits of a 12-bit RAM address. For this reason, both addressing modes (EMB = "0" and EMB = "1") apply

specifically to the memory bank indicated by the SMB instruction, and any restrictions to the addressable area

within bank 0, 1 or 15. Direct and indirect 1-, 4-, and 8-bit addressing methods can be used.

In addition, there are several RAM locations that can always be addressed using specific addressing methods,

regardless of the current EMB flag setting.

Here are a few things to remember about addressing data memory areas:

— When you address peripheral hardware locations in bank 15, you can use the mnemonic for the memory-

mapped hardware component as the operand in place of the actual address location.

— Always use an even-numbered RAM address as the operand in 8-bit direct and indirect addressing.

— With direct addressing, use the RAM address as the instruction operand; with indirect addressing, the

instruction specifies a register which contains the operand's address.

3-1

ADDRESSING MODES

KS57C5404/P5404

DA

DA.b

@HL

@H + DA.b

@WX

@WL

Addressing

Mode

memb.@L

X

mema.b

X

RAM

Areas

EMB = 0 EMB = 1

EMB = 0

EMB = 1

X

000H

Working

Registers

01FH

020H

07FH

080H

SMB = 0

Bank 0

(General

Registers

And Stack)

0FFH

100H

Bank 1:

(General

Registers)

SMB = 1

1FFH

F80H

FB0H

FBFH

FC0H

Bank 15

(Peripheral

Hardware

Registers)

SMB = 15

FF0H

FFFH

NOTES:

1. 'X' means “don't care”.

2. Blank columns indicate the RAM areas that are not addressable, given the addressing

method and enable memory bank (EMB) flag setting shown in the column headers.

Figure 3-1. RAM Address Structure

3-2

KS57C5404/P5404

ADDRESSING MODES

EMB AND ERB INITIALIZATION VALUES

The EMB and ERB flag bits are set automatically by the values of the

vector address.

vector address and the interrupt

When a

is generated internally, bit 7 of the program memory address 0000H is written to the EMB flag, ini-

tializing it automatically. When a vectored interrupt is generated, bit 7 of the respective vector address table is

written to the EMB. This automatically sets the EMB flag status for the interrupt service routine. When the

interrupt is serviced, the EMB value is automatically saved to the stack and then restored when the interrupt

routine is completed.

At the beginning of a program, the initial EMB flag value for each vectored interrupt must be set by using VENT

instruction. The EMB can be set or reset by bit manipulation instructions (BITS, BITR) regardless of the current

SMB setting.

+

PROGRAMMING TIP — Initializing the EMB and ERB Flags

The following assembly instructions show how to initialize the EMB and ERB flag settings:

ORG

VENT0

VENT1

VENT2

VENT3

NOP

VENT5

•

0000H

; ROM address assignment

1,0,RESET

0,1,INTB

0,1,INT0

0,1,INT1

; EMB ¬ 1, ERB ¬ 0, branch RESET

; EMB ¬ 0, ERB ¬ 1, branch INTB

; EMB ¬ 0, ERB ¬ 1, branch INT0

; EMB ¬ 0, ERB ¬ 1, branch INT1

0,1,INTT0

EMB

; EMB ¬ 0, ERB ¬ 1, branch INTT0

•

RESET

BITR

3-3

ADDRESSING MODES

KS57C5404/P5404

ENABLE MEMORY BANK SETTINGS

EMB = "1"

When you set the enable memory bank flag, EMB, to logic one, you can address the data memory bank specified

by the select memory bank (SMB) value (0,1 or 15) using 1-, 4-, or 8-bit instructions. You can use both direct and

indirect addressing modes. The addressable RAM areas when the EMB flag is set to logic one are as follows:

If SMB = 0,

If SMB = 1

If SMB = 15,

000H–0FFH

100H–1FFH

F80H–FFFH

EMB = "0"

When the enable memory bank flag, EMB, is set to logic zero, the addressable area is defined independently of

the SMB value, and restricted to specific locations depending on whether direct or indirect address mode is used.

If EMB = "0", the addressable area is restricted to the locations 000H–07FH in bank 0 and to the locations F80H–

FFFH in bank 15 in direct addressing. In indirect addressing, only the locations 000H–0FFH in bank 0 are

addressable, regardless of the SMB value.

To address the peripheral hardware register (bank 15) using indirect addressing, the EMB flag must first be set to

"1" and the SMB value to "15". When a RESET occurs, the EMB flag is set to the value contained in bit 7 of the

ROM address 0000H.

EMB-Independent Addressing

You can address several areas of the data memory at any time, regardless of the status of the EMB flag. These

exceptions are described in Table 3-1.

Table 3-1. RAM Addressing Not Affected by the EMB Value

Address

Addressing Method

Affected Hardware

Program Examples

000H–0FFH

Not applicable

4-bit indirect addressing using WX

and WL register pairs;

LD

A,@WX

8-bit indirect addressing using SP

PUSH

POP

FB0H–FBFH

FF0H–FFFH

1-bit direct addressing

PSW,

IEx, IRQx, I/O

BITS

BITR

EMB

IE1

FC0H–FFFH

1-bit indirect addressing using the

L register

BSC,

I/O

BTST

BAND

FC3H.@L

C,P3.@L

3-4

KS57C5404/P5404

ADDRESSING MODES

SELECT BANK REGISTER (SB)

The select bank register (SB) is used to assign the memory bank and register bank. The 8-bit SB register

consists of the 4-bit select register bank register (SRB) and the 4-bit select memory bank register (SMB), as

shown in Figure 3-2.

SMB

SMB 1

SRB

SRB 1

SB

Register

0

SMB 0

0

SRB 0

Figure 3-2. 4-Bit SMB and SRB Values in the SB Register

During interrupts and subroutine calls, the contents of the SB register can be saved to the stack in 8-bit units by

the PUSH SB instruction. You can later restore the value to the SB using the POP SB instruction.

Select Register Bank (SRB) Instruction

The select register bank (SRB) value specifies which register bank is to be used as a working register bank. The

SRB value is set by the 'SRB n' instruction, where n = 0, 1, 2, 3. One of the four register banks is selected by the

combination of ERB flag status and the SRB value that you set using the 'SRB n' instruction. The current SRB

value is retained until another register is requested by program software.

PUSH SB and POP SB instructions are used to save and restore the contents of SRB during interrupts and

subroutine calls. A

clears the 4-bit SRB value to logic zero.

Select Memory Bank (SMB) Instruction

To select one of the two data memory banks available, you must execute an SMB n instruction specifying the

number of the memory bank you want (0, 1 or 15). For example, the instruction 'SMB 1' selects bank 1 and

'SMB 15' selects bank 15. You must also remember to enable the memory bank you select by setting the enable

memory bank flag (EMB) appropriately.

The upper four bits of the 12-bit data memory address are stored in the SMB register. If the SMB value is not

specified by software (or if a

value to logic zero.

does not occur) the current value is retained. A

clears the 4-bit SMB

PUSH SB and POP SB instructions save and restore the contents of the SMB register to and from the stack area

during interrupts and subroutine calls.

3-5

ADDRESSING MODES

KS57C5404/P5404

DIRECT AND INDIRECT ADDRESSING

You can directly address 1-bit, 4-bit, and 8-bit data stored in data memory locations using a specific register or bit

address as the instruction operand.

In indirect addressing, the instruction specifies a specific register pair containing the address of the operand. The

KS57 instruction set supports 1-bit, 4-bit, and 8-bit indirect addressing. In 8-bit indirect addressing, an even-

numbered RAM address must always be used as the instruction operand, and the address register can be HL,

WX, or WL of the selected register bank.

1-BIT ADDRESSING

Table 3-2. 1-Bit Direct and Indirect RAM Addressing

Instruction

Notation

Addressing Mode

Description

EMB Flag

Setting

Addressable

Area

Memory

Bank

Hardware I/O

Mapping

DA.b

Direct: bit is indicated by the

0

000H–07FH

F80H–FFFH

Bank 0

Bank15

–

RAM address (DA), memory

bank selection, and specified

bit number (b).

All 1-bit

addressable

peripherals

(SMB = 15)

1

x

000H–FFFH

SMB = 0, 1, 15

Bank 15

mema.b

Direct: bit is indicated by

addressable area (mema) and

bit number (b).

FB0H–FBFH

FF0H–FFFH

IS0, IS1, EMB,

ERB, IEx,

IRQx, Pn.m

memb.@L

x

FC0H–FFFH

Bank 15

Indirect: the lower two bits of

register L are indicated by the

upper 10 bits of RAM area

(memb) and the upper two bits

of register L.

BSCn.x

Pn.m

@H + DA.b Indirect: bit is indicated by the

lower four bits of the address

0

1

000H–0FFH

000H–FFFH

Bank 0

–

(DA), memory bank selection,

and the H register identifier.

SMB = 0, 1, 15

All 1-bit

addressable

peripherals

(SMB = 15)

NOTE: 'x' means “don't care”.

3-6

KS57C5404/P5404

ADDRESSING MODES

+

PROGRAMMING TIP — 1-Bit Addressing Modes

1-Bit Direct Addressing

1. If EMB = "0":

AFLAG

BFLAG

CFLAG

EQU

SMB

BITS

BTST

BITS

34H.3

85H.3

0BAH.0

0

AFLAG

BFLAG

CFLAG

BFLAG

P3.0

;

Non-essential instruction, since EMB = "0"

34H.3 ¬

F85H.3 (BMOD.3) ¬

If FBAH.0 (IRQW) = 1, skip

Else if FBAH.0 (IRQW) = 0, F85H.3 (BMOD.3) ¬

FF3H.0 (P3.0) ¬

1

;

2. If EMB = "1":

AFLAG

BFLAG

CFLAG

EQU

34H.3

85H.3

0BAH.0

0

AFLAG

BFLAG

CFLAG

BFLAG

P3.0

EQU

SMB

BITS

BTST

BITS

;

Select memory bank 0

34H.3 ¬

85H.3 ¬

1

If 0BAH.0 = 1, skip

Else if 0BAH.0 = 0, 085H.3 ¬

1

FF3H.0 (P3.0) ¬

1

;

3-7

ADDRESSING MODES

KS57C5404/P5404

+

PROGRAMMING TIP — 1-Bit Addressing Modes (Continued)

1-Bit Indirect Addressing

1. If EMB = "0":

AFLAG

BFLAG

CFLAG

EQU

SMB

LD

34H.3

85H.3

0BAH.0

0

H,#0BH

@H+CFLAG

CFLAG

;

Non-essential instruction, since EMB = "0"

H ¬ #0BH

BTSTZ

BITS

If 0BAH.0 = 1, 0BAH.0 ¬ 0 and skip

Else if 0BAH.0 = 0, FBAH.0 (IRQW)

¬

1

;

2. If EMB = "1":

AFLAG

BFLAG

CFLAG

EQU

34H.3

85H.3

EQU

SMB

LD

BTSTZ

BITS

0BAH.0

0

H,#0BH

@H+CFLAG

CFLAG

;

Select memory bank 0

H ¬ #0BH

If 0BAH.0 = 1, 0BAH.0 ¬ 0 and skip

Else if 0BAH.0 = 0, 0BAH.0 ¬

1

;

3-8

KS57C5404/P5404

ADDRESSING MODES

4-BIT ADDRESSING

Table 3-3. 4-Bit Direct and Indirect RAM Addressing

Instruction

Notation

Addressing Mode

Description

EMB Flag

Setting

Addressable

Area

Memory

Bank

Hardware I/O

Mapping

DA

Direct: 4-bit address indicated

0

000H–07FH

F80H–FFFH

Bank 0

Bank15

–

by the RAM address (DA) and

the memory bank selection

All 4-bit

addressable

peripherals

1

0

000H–FFFH

000H–0FFH

SMB = 0, 1,15

Bank 0

(SMB = 15)

–

@HL

Direct: 4-bit address indicated

by the memory bank selection

and register HL

1

000H–FFFH

SMB = 0, 1, 15

All 4-bit

addressable

peripherals

(SMB = 15)

@WX

@WL

Indirect: 4-bit address

indicated by register WX

x

000H–0FFH

Bank 0

–

Indirect: 4-bit address

indicated by register WL

NOTE: 'x' means “don't care”.

PROGRAMMING TIP — 4-Bit Addressing Modes

+

4-Bit Direct Addressing

1. If EMB = "0":

ADATA

BDATA

EQU

SMB

LD

46H

8EH

15

A,P3

0

;

Non-essential instruction, since EMB = "0"

A ¬ (P3)

Non-essential instruction, since EMB = "0"

SMB

LD

ADATA,A

BDATA,A

(046H) ¬

(F8EH) ¬

A

;

2. If EMB = "1":

ADATA

BDATA

EQU

46H

8EH

15

A,P3

0

EQU

SMB

LD

;

Select memory bank 15

A ¬ (P3)

Select memory bank 0

SMB

LD

ADATA,A

BDATA,A

(046H) ¬

(08EH) ¬

A

;

3-9

ADDRESSING MODES

KS57C5404/P5404

+

PROGRAMMING TIP — 4-Bit Addressing Modes (Continued)

4-Bit Indirect Addressing

1. If EMB = "0", compare bank 0, locations 040H–046H with 060H–066H:

ADATA

BDATA

EQU

SMB

LD

CPSE

SRET

DECS

JR

46H

66H

15

HL,#BDATA

WX,#ADATA

A,@WL

A,@HL

;

Non-essential instruction, since EMB = "0"

COMP

;

A ¬ bank 0 (040H–046H)

If bank 0 (060H–066H) = A, skip

L

COMP

RET

;

2. If EMB = "1", exchange bank 0, 040H–046H with 060H–066H:

ADATA

BDATA

EQU

SMB

LD

46H

66H

0

HL,#BDATA

WX,#ADATA

A,@WL

A,@HL

TRANS

;

Select memory bank 0

TRANS

;

A ¬ bank 0 (040H–046H)

Bank 0 (060H–066H) ¬ A

XCHD

JR

3-10

KS57C5404/P5404

ADDRESSING MODES

8-BIT ADDRESSING

Table 3-4. 8-Bit Direct and Indirect RAM Addressing

Instruction

Notation

Addressing Mode

Description

EMB Flag

Setting

Addressable

Area

Memory

Bank

Hardware I/O

Mapping

DA

Direct: 8-bit address indicated

0

000H–07FH

F80H–FFFH

Bank 0

Bank15

–

by the RAM address

(DA = even number) and the

memory bank selection

All 8-bit

addressable

peripherals

(SMB = 15)

1

0

000H–FFFH

000H–0FFH

SMB = 0, 1, 15

Bank 0

@HL

Indirect: the 8-bit address indi-

cated by the memory bank

selection and register HL; (the

4-bit L register value must be

an even number)

–

1

000H–FFFH

SMB = 0, 1, 15

All 8-bit

addressable

peripherals

(SMB = 15)

+

PROGRAMMING TIP — 8-Bit Addressing Modes

8-Bit Direct Addressing:

1. If EMB = "0":

ADATA

BDATA

EQU

SMB

LD

46H

8EH

15

EA,P4

ADATA,EA

BDATA,EA

;

Non-essential instruction, since EMB = "0"

E ¬ (P5), A ¬ (P4)

(046H) ¬ A, (047H) ¬

(F8EH) ¬ A, (F8FH) ¬

E

;

2. If EMB = "1":

ADATA

BDATA

EQU

46H

8EH

15

EA,P4

0

EQU

SMB

LD

SMB

LD

;

Select memory bank 15

E ¬ (P5), A ¬ (P4)

Select memory bank 0

(046H) ¬ A, (047H) ¬

(08EH) ¬ A, (08FH) ¬

ADATA,EA

BDATA,EA

E

LD

3-11

ADDRESSING MODES

KS57C5404/P5404

+

PROGRAMMING TIP — 8-Bit Addressing Modes (Continued)

8-Bit Indirect Addressing

1. If EMB = "0":

ADATA

EQU

LD

8EH

HL,#ADATA

LD

EA,@HL

;

A ¬ (08EH), E ¬ (08FH)

;

2. If EMB = "1":

ADATA

EQU

SMB

LD

46H

0

HL,#ADATA

EA,@HL

LD

A ¬ (046H), E ¬ (047H)

;

3-12

KS57C5404/P5404

MEMORY MAP

4

MEMORY MAP

OVERVIEW

To support program control of peripheral hardware, I/O addresses for peripherals are memory-mapped to bank 15

of the RAM. Memory mapping allows you to use a mnemonic as the operand of an instruction in place of a

specific memory location.

Access to bank 15 is controlled by the select memory bank (SMB) instruction and by the enable memory bank

flag (EMB) setting. If the EMB flag is "0", bank 15 can be addressed using direct addressing, regardless of the

current SMB value. You can use 1-bit direct and indirect addressing, however, for specific locations in bank 15,

regardless of the current EMB value.

I/O MAP FOR HARDWARE REGISTERS

Table 4-1 contains detailed information about I/O mapping for peripheral hardware in bank 15 (register locations

F80H–FFFH). Use the I/O map as a quick-reference source when writing application programs. The I/O map

gives you the following information:

— Register address

— Register name (mnemonic for program addressing)

— Bit values (both addressable and non-manipulable)

— Read-only, write-only, or read and write addressability

— 1-, 4-, or 8-bit data manipulation characteristics

4-1

MEMORY MAP

KS57C5404/P5404

Table 4-1. I/O Map for Memory Bank 15

Memory Bank 15

Addressing Mode

1-Bit 4-Bit 8-Bit

Address

F80H

Register

Bit 3

.3

Bit 2

.2

Bit 1

.1

Bit 0

"0"

R/W

SP

R/W

No

Yes

F81H

.7

.6

.5

.4

Locations F82H–F84H are reserved.

F85H

F86H

F87H

F88H

BMOD

BCNT

.3

.2

.1

.0

W

R

.3

Yes

No

Yes

BUZMOD

TMOD0

“0”

.1

.0

W

No

.3

Yes

No

Yes

No

Yes

No

Location F89H is reserved.

F90H

F91H

F92H

.3

.2

.6

"0"

.5

"0"

.4

"0"

TOE0

"0"

R/W

R

Yes

No

Yes

Location F93H is reserved.

F94H

F95H

F96H

F97H

F98H

F99H

F9AH

TCNT0

TREF0

Yes

No

W

WDMOD

WDFLAG

PSW

.3

.7

.2

.6

.1

.5

.0

.4

W

WDTCF

"0"

W

Locations F9BH–FAFH are reserved.

FB0H

FB1H

FB2H

FB3H

FB4H

FB5H

FB6H

IS1

C ^(note)

IME

.3

IS0

SC2

.2

EMB

SC1

.1

ERB

SC0

.0

R/W

R

Yes

No

Yes

No

Yes

IPR

W

IME

No

Yes

No

PCON

IMOD0

IMOD1

IMODK

.2

.1

.0

W

“0”

"0"

“0”

.1

.0

W

No

"0"

.1

.0

W

No

"0"

.0

W

No

Location FB7H is reserved.

"0" IEB IRQB

FB8H

FBCH

"0"

R/W

Yes

No

Locations FB9H–FBBH are reserved.

"0" IET0 IRQT0 R/W

Location FBDH is reserved.

"0"

4-2

KS57C5404/P5404

MEMORY MAP

Table 4-1. I/O Map for Memory Bank 15 (Continued)

Memory Bank 15

Addressing Mode

Address

FBEH

FBFH

FC0H

FC1H

FC2H

FC3H

Register

Bit 3

IE1

"0"

Bit 2

IRQ1

"0"

Bit 1

IE0

Bit 0

IRQ0

IRQK

R/W

1-Bit

4-Bit

8-Bit

R/W

Yes

No

IEK

BSC0

BSC1

BSC2

BSC3

R/W

Yes

Locations FC4H–FCFH are reserved.

"0" .1 .0

Locations FD1H–FD4H are reserved.

FD0H

CLMOD

.3

W

No

Yes

No

FD5H

FD6H

FD7H

DAMOD

DADATA

“0”

.3

“0”

.2

“0”

.1

.0

.4

W

Yes

No

Yes

No

Yes

.7

.6

.5

Locations FD8H–FD9H are reserved.

FDAH

FDBH

FDCH

FDDH

PNE

PNE4.3 PNE4.2 PNE4.1 PNE4.0

PNE5.3 PNE5.2 PNE5.1 PNE5.0

W

No

Yes

PUMOD

"0"

PUR2

"0"

PUR1

PUR5

PUR0

PUR4

Locations FDEH–FE7H are reserved.

FE8H

FE9H

FEAH

FEBH

FECH

FEDH

PMG1

PMG2

PMG3

PM0.3

PM1.3

“0”

PM0.2

PM1.2

“0”

PM0.1

PM1.1

“0”

PM0.0

PM1.0

PM2.0

"0"

W

No

Yes

"0"

PM4.3

PM5.3

PM4.2

PM5.2

PM4.1

PM5.1

PM4.0

PM5.0

Locations FEEH–FEFH are reserved.

FF0H

FF1H

FF2H

Port 0

Port 1

Port 2

.3

–

.2

–

.1

–

.0

R/W

Yes

No

Location FF3H is reserved.

FF4H

FF5H

Port 4

Port 5

.3

.2

.1

.0

R/W

Yes

.3/.7

.2/.6

.1/.5

.0/.4

Locations FF6H–FFFH are reserved.

NOTE: The carry flag can be read or written by specific bit manipulation instructions only.

4-3

MEMORY MAP

KS57C5404/P5404

REGISTER DESCRIPTIONS

In this section, register descriptions are presented in a consistent format to familiarize you with the memory-

mapped I/O locations in bank 15 of the RAM. Figure 4-1 describes the features of the register description format.

Register descriptions are arranged in alphabetical order.

Counter registers, buffer registers, and reference registers, as well as the stack pointer and port I/O latches, are

not included in the description.

This section can be used as a quick-reference source when writing application programs.

More detailed information about each of these registers is included in Part II of this manual, "Hardware

Descriptions," in the context of the corresponding peripheral hardware module descriptions.

4-4

KS57C5404/P5404

MEMORY MAP

Register and bit IDs

used for bit addressing

Name of individual

bit or related bits

Associated

Register location

Register ID

Register name

hardware module

in RAM bank 15

CLMOD — Clock Output Mode Control Register

CPU

FD0H

3

2

1

0

Bit

Identifier

RESET

.3

.2

.1

.0

Value

0

W

4

0

W

4

0

W

4

Read/Write

Bit Addressing

W

4

Enable/Disable Clock Output Control Bit

CLMOD.3

0

1

Disable clock output

Enable clock output

Bit 2

CLMOD.2

0

Always logic zero

Clock Source and Frequency Selection Control

Bits

CLMOD.1 – .0

0

1

0

1

0

1

Select CPU clock source

Select main system clock fx/8 (524 kHz at 4.19 MHz)

Select main system clock fx/16 (262 kHz at 4.19 MHz)

Select main system clock fx/64 (65.5 kHz at 4.19 MHz)

R = Read-only

W = Write-only

R/W= Read/write

Bit value immediately

Bit number in

MSB to LSB

order

RESET

following a

Type of addressing

that must be used to

address the bit (1-bit,

4-bit, or 8-bit)

Description of the

effect of specific bit

settings

Bit identifier used

for bit addressing

Figure 4-1. Register Description Format

4-5

MEMORY MAP

KS57C5404/P5404

BMOD— Basic Timer Mode Register

BT

F85H

Bit

3

.3

2

.2

0

1

.1

0

.0

0

Identifier

RESET Value

Read/Write

Bit Addressing

0

W

1/4

W

4

W

4

W

4

BMOD.3

Basic Timer Restart Bit

Restart basic timer, then clear IRQB flag, BCNT and BMOD.3 to logic zero

1

BMOD.2 – .0

Input Clock Frequency and Signal Stabilization Interval Control Bits

fx/2¹²(1.02 kHz)

2²⁰/fx (250 ms)

0

1

0

1

0

1

0

1

Input clock frequency:

Signal stabilization interval:

fx/2⁹(8.18 kHz)

2¹⁷/fx (31.3 ms)

Input clock frequency:

Signal stabilization interval:

fx/2⁷(32.7 kHz)

2¹⁵/fx (7.82 ms)

Input clock frequency:

Signal stabilization interval:

fx/2⁵(131 kHz)

2¹³/fx (1.95 ms)

Input clock frequency:

Signal stabilization interval:

NOTES:

1. Signal stabilization interval is the time required to stabilize clock signal oscillation after stop mode is terminated by

an interrupt. The stabilization interval can also be interpreted as "Interrupt Interval Time".

2. When a RESET occurs, the oscillation stabilization time is 31.3 ms (2¹⁷/fx) at 4.19 MHz.

3. 'fx' is the system clock rate given a clock frequency of 4.19 MHz.

4-6

KS57C5404/P5404

MEMORY MAP

BUZMOD — Buzzer Mode Register

F88H

Bit

3

.3

0

2

"0"

0

1

.1

0

.0

0

Identifier

RESET Value

Read/Write

Bit Addressing

W

4

W

4

W

4

W

4

BUZMOD.3

Buzzer Mode Register Bit

0

1

Disable buzzer (BUZ) signal output

Enable buzzer (BUZ) signal output

BUZMOD.2

Bit 2

0

Always logic zero

BUZMOD.1 – .0

Clock Source and Frequency Selection Control Bits

0

1

0

1

0

1

0.5 kHz buzzer (BUZ) signal output

1 kHz buzzer (BUZ) signal output

2 kHz buzzer (BUZ) signal output

4 kHz buzzer (BUZ) signal output

NOTE: System clock frequency (fx) is assumed to be 4.19 MHz.

4-7

MEMORY MAP

KS57C5404/P5404

CLMOD — Clock Output Mode Register

CPU

FD0H

Bit

3

.3

0

2

"0"

0

1

.1

0

.0

0

Identifier

RESET Value

Read/Write

Bit Addressing

W

4

W

4

W

4

W

4

CLMOD.3

Enable/Disable Clock Output Control Bit

0

1

Disable clock output

Enable clock output

CLMOD.2

Bit 2

0

Always logic zero

CLMOD.1 – .0

Clock Source and Frequency Selection Control Bits

0

Select CPU clock source fx/4, fx/8, or fx/64 (1.05 MHz, 524 kHz,

or 65.6 kHz)

0

1

0

1

Select system clock fx/8 (524 kHz)

Select system clock fx/16 (262 kHz)

Select system clock fx/64 (65.5 kHz)

NOTE: 'fx' is the system clock, given a clock frequency of 4.19 MHz.

4-8

KS57C5404/P5404

MEMORY MAP

DADATA — D/A Converter Data Register

FD7H, FD6H

Bit

7

.7

0

6

.6

0

5

.5

0

4

.4

0

3

.3

0

2

.2

0

1

.1

0

.0

0

Identifier

RESET Value

Read/Write

Bit Addressing

W

8

W

8

W

8

W

8

W

8

W

8

W

8

W

8

DADATA.7 – .0

V

DATATA. DATATA. DATATA. DATATA. DATATA. DATATA. DATATA. DATATA.

DAO

7

0

1

6

0

5

0

4

0

3

0

2

0

1

0

V_DD/2¹

V_DD/2²

V_DD/2³

V_DD/2⁴

V_DD/2⁵

V_DD/2⁶

V_DD/2⁷

V_DD/2⁸

0

1

0

1

0

1

0

1

0

1

0

1

0

1

NOTE: These are the values determined by setting just one-bit of DADATA.0–DADATA.7. Other value of DAO can be

obtained with superimposition.

n

256

V_DAO= V_DD

´

(n = 0–255, DADATA value)

4-9

MEMORY MAP

KS57C5404/P5404

DAMOD — D/A Converter Mode Register

FD5H

Bit

3

"0"

0

2

"0"

0

1

"0"

0

.0

Identifier

RESET Value

Read/Write

Bit Addressing

0

W

1/4

DAMOD.3 – .1

DAMOD.0

Bit 3–1

0

Always logic zero

Digital-to-Analog Converter Enable Bit

0

1

Disable digital-to-analog converter

Enable digital-to-analog converter

4-10

KS57C5404/P5404

MEMORY MAP

IE0, 1, IRQ0, 1— INT0, 1 Interrupt Enable/Request Flags

CPU

FBEH

Bit

3

IE1

0

2

IRQ1

0

1

IE0

0

IRQ0

0

Identifier

RESET Value

Read/Write

Bit Addressing

R/W

1/4

R/W

1/4

R/W

1/4

R/W

1/4

IE1

INT1 Interrupt Enable Flag

0

1

Disable interrupt request at the INT1 pin

Enable interrupt request at the INT1 pin

IRQ1

IE0

INT1 Interrupt Request Flag

–

Generate INT1 interrupt (This bit is set and cleared by hardware when rising or

falling edge is detected at INT1 pin.)

INT0 Interrupt Enable Flag

0

1

Disable interrupt request at the INT0 pin

Enable interrupt request at the INT0 pin

IRQ0

INT0 Interrupt Request Flag

–

Generate INT0 interrupt (This bit is set and cleared automatically by hardware

when rising or falling edge is detected at INT0 pin.)

4-11

MEMORY MAP

KS57C5404/P5404

IEB, IRQB — INTB Interrupt Enable/Request Flags

CPU

FB8H

Bit

3

"0"

0

2

"0"

0

1

IEB

0

IRQB

0

Identifier

Value

Read/Write

R/W

1/4

R/W

1/4

R/W

1/4

R/W

1/4

Bit Addressing

.3 – .2

IEB

Bits 3–2

0

Always logic zero

INTB Interrupt Enable Flag

0

1

Disable INTB interrupt request

Enable INTB interrupt request

IRQB

INTB Interrupt Request Flag

–

Generate INTB interrupt (bit is set and cleared automatically by hardware when

reference interval signal received from basic timer.)

4-12

KS57C5404/P5404

MEMORY MAP

IEK, IRQK — Key Interrupt Enable/Request Register

CPU

FBFH

Bit

3

"0"

0

2

"0"

0

1

IEK

0

IRQK

0

Identifier

Value

Read/Write

R/W

1/4

R/W

1/4

R/W

1/4

R/W

1/4

Bit Addressing

.3 – .2

IEK

Bits 3–2

0

Always logic zero

Key Interrupt Request Enable Flag

0

1

Disable INTK interrupt request at the KS0–KS1 pins

Enable INTK interrupt request at the KS0–KS1 pins

IRQK

Key Interrupt Request Flag

–

Generate INTK interrupt. (This bit is set when falling edge is detected at any

one of the KS0–KS1 pins. INTK is a quasi-interrupt and IRQK must be cleared

by software.)

4-13

MEMORY MAP

KS57C5404/P5404

IET0, IRQT0 — INTT0 Interrupt Enable/Request Flags

CPU

FBCH

Bit

3

"0"

0

2

"0"

0

1

0

IRQT0

0

Identifier

IET0

0

Value

Read/Write

R/W

1/4

R/W

1/4

R/W

1/4

R/W

1/4

Bit Addressing

.3 – .2

IET0

Bits 3–2

0

Always logic zero

INTT0 Interrupt Enable Flag

0

1

Disable INTT0 interrupt request

Enable INTT0 interrupt request

IRQT0

INTT0 Interrupt Request Flag

–

Generate INTT0 interrupt (bit is set and cleared automatically by hardware

when contents of TCNT0 and TREF0 registers match.)

4-14

KS57C5404/P5404

MEMORY MAP

IMOD0 — External Interrupt 0 (INT0) Mode Register

CPU

FB4H

Bit

3

"0"

0

2

"0"

0

1

.1

0

.0

0

Identifier

Value

Read/Write

W

4

W

4

W

4

W

4

Bit Addressing

IMOD0.3 – .2

IMOD0.1 – .0

Bit 3–2

0

Always logic zero

External Interrupt Mode Control Bits

0

1

0

1

0

1

Interrupt request are triggered by a rising signal edge

Interrupt request are triggered by a falling signal edge

Interrupt request are triggered by both rising and falling signal edges

Interrupt request flag (IRQ0) cannot be set to logic one

4-15

MEMORY MAP

KS57C5404/P5404

IMOD1 — External Interrupt 1 (INT1) Mode Register

CPU

FB5H

Bit

3

"0"

0

2

"0"

0

1

"0"

0

.0

0

Identifier

Value

Read/Write

W

4

W

4

W

4

W

4

Bit Addressing

IMOD1.3 – .1

IMOD1.0

Bits 3–1

0

Always logic zero

External Interrupt 1 Edge Detection Control Bit

0

1

Rising edge detection

Falling edge detection

4-16

KS57C5404/P5404

MEMORY MAP

IMODK — Key Interrupt Mode Register

CPU

FB6H

Bit

3

"0"

0

2

"0"

0

1

.1

0

.0

0

Identifier

Value

Read/Write

W

4

W

4

W

4

W

4

Bit Addressing

IMODK.3 – .2

IMODK.1 – .0

Bits 3–2

0

Always logic zero

Key Interrupt Edge Detection Selection Bit

0

1

0

1

0

1

Disable key interrupt

Select falling edge at KS0

Select falling edge at KS1

Select falling edge at KS0–KS1

NOTE: If one of KS0 and KS1 is in Low input (or Low output) state, the key interrupt cannot be occurred.

Refer to the paged 7-11.

4-17

MEMORY MAP

KS57C5404/P5404

IPR — Interrupt Priority Register

CPU

FB2H

Bit

3

IME

0

2

.2

0

1

.1

0

.0

0

Identifier

Value

Read/Write

W

4

W

4

W

4

Bit Addressing

1/4

IME

Interrupt Master Enable Bit

0

1

Inhibit all interrupt processing

Enable processing for all interrupt service requests

IPR.2 – .0

Interrupt Priority Assignment Bits

0

1

0

1

0

1

0

1

Process all interrupt requests at low priority

Process INTB interrupts only

Process INT0 interrupts only

Process INT1 interrupts only

Process INTT0 interrupts only

4-18

KS57C5404/P5404

MEMORY MAP

PCON — Clock Power Control Register

CPU

FB3H

Bit

3

.3

0

2

.2

0

1

.1

0

.0

0

Identifier

Value

Read/Write

W

4

W

4

W

4

W

4

Bit Addressing

PCON.3 – .2

CPU Operating Mode Control Bits

0

1

0

1

0

Enable normal CPU operating mode

Initiate idle power-down mode

Initiate stop power-down mode

PCON.1 – .0

CPU Clock Frequency Selection Bits

0

1

0

1

Select fx/64

Select fx/8

Select fx/4

NOTE: fx = system clock

4-19

MEMORY MAP

KS57C5404/P5404

PMG1 — Port I/O Mode Flags (Group 1: Ports 0, 1)

I/O

FE9H, FE8H

Bit

7

6

5

4

3

2

1

0

Identifier

PM1.3

PM1.2

PM1.1

PM1.0

PM0.3

PM0.2

PM0.1

PM0.0

Value

0

W

8

0

W

8

0

W

8

0

W

8

0

W

8

0

W

8

0

W

8

0

W

8

Read/Write

Bit Addressing

PM1.3

PM1.2

PM1.1

PM1.0

PM0.3

PM0.2

PM0.1

PM0.0

P1.3 I/O Mode Selection Flag

0

1

Set P1.3 to input mode

Set P1.3 to output mode

P1.2 I/O Mode Selection Flag

0

1

Set P1.2 to input mode

Set P1.2 to output mode

P1.1 I/O Mode Selection Flag

0

1

Set P1.1 to input mode

Set P1.1 to output mode

P1.0 I/O Mode Selection Flag

0

1

Set P1.0 to input mode

Set P1.0 to output mode

P0.3 I/O Mode Selection Flag

0

1

Set P0.3 to input mode

Set P0.3 to output mode

P0.2 I/O Mode Selection Flag

0

1

Set P0.2 to input mode

Set P0.2 to output mode

P0.1 I/O Mode Selection Flag

0

1

Set P0.1 to input mode

Set P0.1 to output mode

P0.0 I/O Mode Selection Flag

0

1

Set P0.0 to input mode

Set P0.0 to output mode

4-20

KS57C5404/P5404

MEMORY MAP

PMG2 — Port I/O Mode Flags (Group 2: Port 2)

I/O

FEBH, FEAH

Bit

7

"0"

0

6

"0"

0

5

"0"

0

4

"0"

0

3

"0"

0

2

"0"

0

1

0

Identifier

"0"

0

PM2.0

Value

0

W

8

Read/Write

W

8

W

8

W

8

W

8

W

8

W

8

W

8

Bit Addressing

.7 – .1

PM2.0

Bits 7–1

0

Always logic zero

P2.0 I/O Mode Selection Flag

0

1

Set P2.0 to input mode

Set P2.0 to output mode

4-21

MEMORY MAP

KS57C5404/P5404

PMG3 — Port I/O Mode Flags (Group 3: Port 4, 5)

I/O

FEDH, FECH

Bit

7

6

5

4

3

2

1

0

Identifier

PM5.3

PM5.2

PM5.1

PM5.0

PM4.3

PM4.2

PM4.1

PM4.0

Value

0

W

8

0

W

8

0

W

8

0

W

8

0

W

8

0

W

8

0

W

8

0

W

8

Read/Write

Bit Addressing

PM5.3

PM5.2

PM5.1

PM5.0

PM4.3

PM4.2

PM4.1

P5.3 I/O Mode Selection Flag

0

1

Set P5.3 to input mode

Set P5.3 to output mode

P5.2 I/O Mode Selection Flag

0

1

Set P5.2 to input mode

Set P5.2 to output mode

P5.1 I/O Mode Selection Flag

0

1

Set P5.1 to input mode

Set P5.1 to output mode

P5.0 I/O Mode Selection Flag

0

1

Set P5.0 to input mode

Set P5.0 to output mode

P4.3 I/O Mode Selection Flag

0

1

Set P4.3 to input mode

Set P4.3 to output mode

P4.2 I/O Mode Selection Flag

0

1

Set P4.2 to input mode

Set P4.2 to output mode

P4.1 I/O Mode Selection Flag

0

1

Set P4.1 to input mode

Set P4.1 to output mode

PM4.0

P4.0 I/O Mode Selection Flag

0

1

Set P4.0 to input mode

Set P4.0 to output mode

4-22

KS57C5404/P5404

MEMORY MAP

PNE — N-channel Open-drain Enable Register

I/O

FDAH

Bit

7

6

5

4

3

2

1

0

Identifier

PNE5.3 PNE5.2 PNE5.1 PNE5.0 PNE4.3 PNE4.2 PNE4.1 PNE4.0

Value

0

W

8

0

W

8

0

W

8

0

W

8

0

W

8

0

W

8

0

W

8

0

W

8

Read/Write

Bit Addressing

PNE5.3

PNE5.2

PNE5.1

PNE5.0

PNE4.3

PNE4.2

PNE4.1

PNE4.0

P5.3 N-channel Open-drain Enable Bit

0

1

Set P5.3 Open-drain Disabled

Set P5.3 Open-drain Enabled

P5.2 N-channel Open-drain Enable Bit

0

1

Set P5.2 Open-drain Disabled

Set P5.2 Open-drain Enabled

P5.1 N-channel Open-drain Enable Bit

0

1

Set P5.1 Open-drain Disabled

Set P5.1 Open-drain Enabled

P5.0 N-channel Open-drain Enable Bit

0

1

Set P5.0 Open-drain Disabled

Set P5.0 Open-drain Enabled

P4.3 N-channel Open-drain Enable Bit

0

1

Set P4.3 Open-drain Disabled

Set P4.3 Open-drain Enabled

P4.2 N-channel Open-drain Enable Bit

0

1

Set P4.2 Open-drain Disabled

Set P4.2 Open-drain Enabled

P4.1 N-channel Open-drain Enable Bit

0

1

Set P4.1 Open-drain Disabled

Set P4.1 Open-drain Enabled

P4.0 N-channel Open-drain Enable Bit

0

1

Set P4.0 Open-drain Disabled

Set P4.0 Open-drain Enabled

4-23

MEMORY MAP

KS57C5404/P5404

PSW — Program Status Word

CPU

FB1H, FB0H

Bit

7

C

6

SC2

0

5

SC1

0

4

SC0

0

3

IS1

0

2

IS0

0

1

EMB

0

ERB

0

Identifier

(1)

Value

Read/Write

R/W

(2)

R

R/W

1/4

R/W

1/4

R/W

1

R/W

1

Bit Addressing

8

C

Carry Flag

0

1

No overflow or borrow condition exists

An overflow or borrow condition does exist

SC2 – SC0

IS1, IS0

Skip Condition Flags

0

1

No skip condition exists; no direct manipulation of these bits is allowed

A skip condition exists; no direct manipulation of these bits is allowed

Interrupt Status Flags

0

1

Service all interrupt requests

Service only the high-priority interrupt(s) as determined in the interrupt

priority register (IPR)

1

0

1

Do not service interrupt requests any more

Undefined

EMB

Enable Data Memory Bank Flag

0

Restrict program access to data memory to bank 15 (F80H–FFFH) and to

the locations 000H–07FH in the bank 0 only

1

Enable full access to data memory banks 0, 1, and 15

ERB

Enable Register Bank Flag

0

1

Select register bank 0 as working register area

Select register banks 0, 1, 2, or 3 as working register area in accordance with

the select register bank (SRB) instruction operand

NOTES:

1. The value of the carry flag is undefined after a

occurs during the normal operation. If a

occurs during

power-down mode (IDLE or STOP), the current value of the carry flag is retained.

2. The carry flag can only be addressed by a specific set of 1-bit manipulation instructions. See Section 2 for

detailed information.

4-24

KS57C5404/P5404

MEMORY MAP

PUMOD — Pull-up Register Mode Register

I/O

FDDH, FDCH

Bit

7

"0"

0

6

"0"

0

5

PUR5

0

4

PUR4

0

3

"0"

0

2

PUR2

0

1

0

Identifier

PUR1

PUR0

Value

0

W

8

0

W

8

Read/Write

W

8

W

8

W

8

W

Bit Addressing

8

.7 – .6

PUR5

Bits 7–6

0

Always cleared to logic zero

Connect/Disconnect Port 5 Pull-up Resistor Control Bit

0

1

Disconnect port 5 pull-up resistor

Connect port 5 pull-up resistor

PUR4

Connect/Disconnect Port 4 Pull-up Resistor Control Bit

0

1

Disconnect port 4 pull-up resistor

Connect port 4 pull-up resistor

.3

Bit 3

0

Always cleared to logic zero

PUR2

Connect/Disconnect Port 2 Pull-up Resistor Control Bit

0

1

Disconnect port 2 pull-up resistor

Connect port 2 pull-up resistor

PUR1

PUR0

Connect/Disconnect Port 1 Pull-up Resistor Control Bit

0

1

Disconnect port 1 pull-up resistor

Connect port 1 pull-up resistor

Connect/Disconnect Port 0 Pull-up Resistor Control Bit

0

1

Disconnect port 0 pull-up resistor

Connect port 0 pull-up resistor

4-25

MEMORY MAP

KS57C5404/P5404

TMOD0 — Timer/Counter 0 Mode Register

T/C0 F91H, F90H

Bit

3

"0"

0

2

.6

0

1

.5

0

.4

0

3

.3

2

.2

0

1

"0"

0

"0"

0

Identifier

Value

0

Read/Write

W

8

W

8

W

8

W

8

W

1/8

W

8

W

8

W

8

Bit Addressing

.7

Bit 7

0

Always logic zero

.6 – .4

Timer/Counter 0 Input Clock Selection Bits

0

1

0

1

0

1

0

1

0

1

External clock input at TCL0 pin on rising edge

External clock input at TCL0 pin on falling edge

Internal system clock (fx) of 4.19 MHz/2¹⁰(4.09 kHz)

Selected clock: fx/2⁶(65.5 kHz)

Selected clock: fx/2⁴(262 kHz)

Selected clock: fx (4.19 MHz)

.3

.2

Clear Counter and Resume Counting Control Bit

1

Clear TCNT0, IRQT0, and TOL0 and resume counting immediately.

(This bit is cleared automatically when counting starts.)

Enable/Disable Timer/Counter 0 Bit

0

1

Disable timer/counter 0; retain TCNT0 contents

Enable timer/counter 0

.1 – .0

Bits 1–0

Always logic zero

0

NOTE: System clock frequency (fx) is assumed to be 4.19 MHz.

4-26

KS57C5404/P5404

MEMORY MAP

TOE0 — Timer Output Enable Flag

T/C

F92H

Bit

3

"0"

0

2

TOE0

0

1

"0"

0

"0"

0

Identifier

Value

Read/Write

R/W

1/4

R/W

1/4

R/W

1/4

W

Bit Addressing

1/4

.3

Bit 3

0

Always logic zero

TOE0

Timer/Counter 0 Output Enable Flag

0

1

Disable timer/counter 0 output to the TCLO0 pin

Enable timer/counter 0 output to the TCLO0 pin

.1 – .0

Bits 1–0

Always logic zero

0

4-27

MEMORY MAP

KS57C5404/P5404

WDMOD — Watchdog Timer Mode Register

F99H, F98H

Bit

7

.7

1

6

.6

0

5

.5

1

4

.4

0

3

2

.2

1

.1

0

.0

1

Identifier

.3

Value

0

W

8

Read/Write

W

8

W

8

W

8

W

8

W

8

W

8

W

8

Bit Addressing

.7 - .0

Watchdog Timer Enable/Disable Control

5AH

Disable watch-dog timer function

Enable watch-dog timer function

Any other value

WDFLAG — Watchdog Timer Flag

F9AH

Bit

3

2

"0"

0

1

"0"

0

"0"

0

Identifier

WDTCF

Value

0

W

1

Read/Write

–

Bit Addressing

–

.3

Watch-dog timer’s counter clear bit

Clear and restart the watch-dog timer’s counter

NOTE: Instructions that clear the watch-dog timer (“BITS WDTCF”) should be executed at proper points in a program

1

within a given period. If the instructions are not executed within a given period and the watch-dog timer overflows,

a RESET signal is generated and the system is restarted in a reset status.

4-28

Oscillator Circuits

Interrupts

Power-Down

I/O Ports

Timers and Timer/Counter

Comparator

Serial I/O Interface

Electrical Data

Mechanical Data

KS57P5404 OTP

Development Tools

KS57C5404/P5404

OSCILLATOR CIRCUIT

6

OSCILLATOR CIRCUITS

OVERVIEW

The KS57C5404 has a system clock circuit. The CPU and peripheral hardware operate on the system clock

frequency supplied through these on-chip circuits. Specifically, a clock is required by the following peripheral

modules:

— Basic timer

— Timer/counter 0

— Clock output circuit

— Buzzer

The system clock frequency can be divided by 4, 8, or 64. By manipulating PCON bits 1 and 0, you can select

one of the following frequencies as the CPU clock.

fx fx fx

,

4

8 64

When the PCON register is cleared to zero after a

system clock of fx/64 is selected.

, the normal CPU operating mode is enabled and, a

Bits 3 and 2 of the PCON register can be manipulated by a STOP or IDLE instruction to engage stop or idle

power-down mode.

6-1

OSCILLATOR CIRCUIT

KS57C5404/P5404

System

Oscillator

Circuit

fx

X

IN

X

OUT

Basic Timer

Frequency

Dividing

Circuit

Timer/Counter 0

Clock Output Circuit

Buzzer Circuit

Oscillator

Stop

1/2

1/16

CPU

Selector

Clock

1/4

Cpu Stop Signal

(Idle Mode)

PCON.0

PCON.1

PCON.2

PCON.3

Idle

Wait Release Signal

Oscillator

Control

Circuit

RESET

Signal

Stop

Internal

Power-Down Release Signal

PCON.3,2 Clear

Figure 6-1. Clock Circuit Diagram

6-2

KS57C5404/P5404

OSCILLATOR CIRCUIT

SYSTEM OSCILLATOR CIRCUITS

X

IN

X

IN

X

OUT

X

OUT

Figure 6-2. Crystal/Ceramic Oscillator

Figure 6-3. External Clock

6-3

OSCILLATOR CIRCUIT

KS57C5404/P5404

POWER CONTROL REGISTER (PCON)

The power control register, PCON, is a 4-bit register that is used to select the CPU clock frequency and control

CPU operating and power-down modes. PCON is mapped to the RAM address FB3H and can be addressed di-

rectly by 4-bit write instructions or by the instructions IDLE and STOP.

FB3H

PCON.3

PCON.2

PCON.1

PCON.0

PCON bits 3 and 2 are controlled by the STOP and IDLE instructions to engage the idle and stop power-down

modes. Idle and stop modes can be initiated by these instruction regardless of the current value of the enable

memory bank flag (EMB). PCON bits 1 and 0 are used to select a specific system clock frequency.

A

sets PCON register values to logic zero. PCON.1 and PCON.0 divide the frequency (fx) by 4, 8, and 64.

PCON.3 and PCON.2 enable normal CPU operating mode.

Table 6-1. Power Control Register (PCON) Organization

PCON Bit Settings Resulting CPU Operating Mode

PCON.3

PCON.2

0

1

0

1

0

Normal CPU operating mode

Idle power-down mode

Stop power-down mode

PCON Bit Settings

Resulting CPU Clock Frequency

PCON.1

PCON.0

0

1

0

1

fx/64

fx/8

fx/4

+

PROGRAMMING TIP — Setting the CPU Clock

To set the CPU clock to 1.05 MHz at 4.19 MHz:

BITS

SMB

LD

EMB

15

A,#3H

PCON,A

LD

6-4

KS57C5404/P5404

OSCILLATOR CIRCUIT

INSTRUCTION CYCLE TIMES

The unit of time that equals one machine cycle varies depending on how the oscillator clock signal is divided (by

4, 8, or 64). Table 6-2 shows corresponding cycle times in microseconds.

Table 6-2. Instruction Cycle Times for CPU Clock Rates

Selected

CPU Clock

Resulting Frequency

Oscillation

Source

Cycle Time (µs)

fx/64

fx/8

65.5 kHz

524.0 kHz

1.05 MHz

fx = 4.19 MHz

15.3

1.91

0.95

fx/4

CLOCK OUTPUT MODE REGISTER (CLMOD)

The clock output mode register, CLMOD, is a 4-bit register that is used to enable or disable clock output to the

CLO pin and select the CPU clock source and frequency. CLMOD is mapped to the RAM address FD0H and is

addressable by 4-bit write instructions only.

FD0H

CLMOD.3

"0"

CLMOD.1

CLMOD.0

A

clears CLMOD to logic zero, which automatically selects the CPU clock as the clock source (without

initiating clock oscillation), and disables clock output.

CLMOD.3 is the enable/disable clock output control bit. CLMOD.1 and CLMOD.0 are used to select one of four

possible clock sources and frequencies: normal CPU clock, fx/8, fx/16, or fx/64.

Table 6-3. Clock Output Mode Register (CLMOD) Organization

CLMOD Bit Settings

Resulting Clock Output

CLMOD.1

CLMOD.0

Clock Source

Frequency

1.05 MHz, 524 kHz, 65.5 kHz

524 kHz

0

1

0

1

0

1

CPU clock (fx/4, fx/8, fx/64)

fx/8

fx/16

fx/64

262 kHz

65.5 kHz

CLMOD.3

Result of CLMOD.3 Setting

0

1

Clock output is disabled

Clock output is enabled

NOTE: Frequencies assume that fx = 4.19 MHz.

6-5

OSCILLATOR CIRCUIT

KS57C5404/P5404

CLOCK OUTPUT CIRCUIT

The clock output circuit, used to output clock pulses to the CLO pin, has the following components:

— 4-bit clock output mode register (CLMOD)

— Clock selector

— Output latch

— Port mode flag

— CLO output pin (P2.2)

CLO

CLMOD.3

CLMOD.2

4

CLMOD.1

CLOCK

P1.2 OUTPUT LATCH

PM1.2

SELECTOR

CLMOD.0

CLOCKS

(fx/8, fx/16, fx/64, CPU clock)

Figure 6-4. CLO Output Pin Circuit Diagram

CLOCK OUTPUT PROCEDURE

To output clock pulses to the CLO pin, follow this general procedure:

1. Disable clock output by clearing CLMOD.3 to logic zero.

2. Set the clock output frequency (CLMOD.1, CLMOD.0).

3. Load a "0" to the output latch of the CLO pin (P1.2).

4. Set the P1.2 mode flag (PM1.2) to output mode.

5. Enable clock output by setting CLMOD.3 to logic one.

+

PROGRAMMING TIP — CPU Clock Output to the CLO Pin

To output the CPU clock to the CLO pin:

BITS

SMB

LD

BITR

LD

EMB

15

;

OR BITR EMB

EA,#40H

PMG1,EA

P1.2

A,#8H

CLMOD,A

;

P1.2 ¬ Output mode

Clear P1.2 output latch

LD

6-6

KS57C5404/P5404

INTERRUPTS

7

INTERRUPTS

OVERVIEW

The KS57C5404 microcontrollers process three types of interrupts:

— Internal interrupts generated by on-chip processes

— External interrupts generated by external peripheral devices

— Quasi-interrupts used for edge detection and clock sources

Table 7-1. Interrupts and Corresponding I/O Pin(s)

Interrupt Name

Interrupt Type

External Interrupts

I/O Port Pin(s)

P0.0, P0.1

INT0, INT1

INTB, INTT0

INTK

Internal Interrupts

Quasi-interrupts

Not applicable

P0.2, P0.3 (KS0, KS1)

The interrupt control circuit has four functional components:

— Interrupt enable flags (IEx)

— Interrupt request flags (IRQx)

— Interrupt priority registers (IME and IPR)

— Power-down release signal circuit

Vectored Interrupts

Interrupt requests may be processed as vectored interrupts in hardware, or they can be generated by program

software. A vectored interrupt is generated when the following flags and register settings, corresponding to the

specific interrupt, are enabled (set to logic one):

— Interrupt enable flag (IEx)

— Interrupt master enable flag (IME)

— Interrupt request flag (IRQx)

— Interrupt status flags (IS0, IS1)

— Interrupt priority register (IPR)

If all conditions are satisfied, the start address of the interrupt is loaded into the program counter and the program

starts executing the service routine from this address.

7-1

INTERRUPTS

KS57C5404/P5404

Vectored Interrupts (Continued)

The EMB and ERB flags for the RAM memory and register banks are stored in the vector address area of the

ROM during interrupt service routines. The flags are stored at the beginning of the program with the VENT

instruction. Enable flag values are saved during the main routine, as well as the service routines. Any change you

make to enable flag values during a service routine is not stored in the vector address.

When an interrupt occurs, the enable flag values before the interrupt is initiated are saved along with the

program status word (PSW), and the enable flag values for the interrupt is fetched from the respective vector

address.

Then, if required, you can modify the enable flags during the interrupt service routine. When the interrupt service

routine returns to the main routine by the IRET instruction, however, the original values saved in the stack are

restored and the main program continues program execution with these values.

Software-Generated Interrupts

To generate an interrupt request from software, the program manipulates the IRQx flag appropriately. When the

interrupt request value in the IRQx flag is set, it is retained until all other conditions for the interrupt have been

met, and the service routine can be initiated.

Multiple Interrupts

By manipulating the two interrupt status flags (IS0 and IS1), you can control service routine initialization and

thereby process multiple interrupts simultaneously.

Power-Down Mode Release

An interrupt can be used to release power-down mode (stop or idle). Interrupts for power-down mode release are

initiated by setting the corresponding interrupt enable flag. Even if the IME flag is cleared to zero, power-down

mode will be released by an interrupt request signal when the interrupt enable flag is set. In such cases, the

interrupt routine will not be executed since IME = "0".

7-2

KS57C5404/P5404

INTERRUPTS

Interrupt is generated (INT xx)

Request flag (IRQx)

1

NO

IEx = 1?

YES

Retain value until IEx = 1

Generate corresponding vector interrupt

and release power-down mode

NO

IME = 1?

Retain value until IME = 1

YES

Retain value until interrupt

service routine is completed

IS1,0 = 0,0?

NO

IS1,0 = 0,1 ?

YES

NO

High-priority interrupt?

YES

IS1,0 = 0,1

IS1,0 = 1,0

Store contents of PC and PSW in the stack area;

set PC contents to corresponding vector address

Reset corresponding IRQx

Jump to interrupt start

Figure 7-1. Interrupt Execution Flowchart

7-3

INTERRUPTS

KS57C5404/P5404

IEB

IEK

IET0

IE1

IE0

IMOD1

IMOD0

IRQB

IRQ0

IRQ1

IRQT0

IRQK

INTB

@

INT0

INT1

@

INTT0

INTK (KS0-KS1)

IMODK

Power-Down Mode

Release Signal

IME

IPR

Interrupt Control Unit

IS1 IS0

Vector Interrupt Generator

@ = Edge Detection Circuit

Figure 7-2. Interrupt Control Circuit Diagram

7-4

KS57C5404/P5404

INTERRUPTS

MULTIPLE INTERRUPTS

The interrupt controller can service multiple interrupts in two ways: as two-level interrupts, where either all inter-

rupt requests or only those of highest priority are serviced, or as multi-level interrupts, when the interrupt service

routine for a lower-priority request is accepted during the execution of a higher priority routine.

Two-Level Interrupt Handling

Two-level interrupt handling is the standard method for processing multiple interrupts. When the IS1 and IS0 bits

of the PSW (FB0H.3 and FB0H.2, respectively) are both logic zero, program execution mode is normal and all

interrupt requests are serviced. See Figure 7-3.

Whenever an interrupt request is accepted, IS1 and IS0 are incremented by one ("0" ® "1" or "1" ® "0"), and the

values are stored in the stack along with other PSW bits. After the interrupt routine is serviced, the modified IS1

and IS0 values are automatically restored from the stack by an IRET instruction.

IS0 and IS1 can be manipulated directly by 1-bit write instructions, regardless of the current value of the enable

memory bank flag (EMB). Before you can modify an interrupt service flag, however, you must first disable

interrupt processing with a DI instruction.

When you set IS1 to "0" and IS0 to "1", you should inhibit all interrupt service routines except for the highest

priority interrupt currently defined by the interrupt priority register (IPR).

Normal Program

Processing

(Status 0)

High Or Low Level

Interrupt Processing

(Status 1)

High Level

Interrupt Processing

(Status 2)

Int Disable

Set IPR

Int Enable

Low or

High Level

Interrupt

High-Level

Interrupt

Generated

Figure 7-3. Two-Level Interrupt Handling

7-5

INTERRUPTS

KS57C5404/P5404

Multi-Level Interrupt Handling

With multi-level interrupt handling, a lower-priority interrupt request can be executed while a high-priority interrupt

is being serviced. This is done by manipulating the interrupt status flags, IS0 and IS1. See Figure 7-4.

When an interrupt is requested during the normal program execution, the interrupt status flags IS0 and IS1 are set

to "0" and "1", respectively. This setting allows only highest-priority interrupts to be serviced. When a high-priority

request is accepted, both interrupt status flags are then cleared to "0" by software so that a request of any priority

level can be serviced. In this way, the high-priority and low-priority requests are serviced in parallel.

Table 7-2. IS1 and IS0 Function

Process Status

Before INT

IS1 IS0

Effect of ISx Bit Setting

After INT ACK

IS1

0

IS0

1

0

1

0

1

All interrupt requests are serviced.

Only high-priority interrupts as determined by the

current settings in the IPR register are serviced.

1

0

2

–

1

0

1

No additional interrupt requests will be serviced.

Value undefined

–

Normal Program

Processing

(Status 0)

Single

Interrupt

2-Level

INT Disable

Set Ipr

Interrupt

3-Level

Interrupt

INT Disable

Status 1

INT Enable

Modify Status

Low or

High Level

Interrupt

INT Enable

Status 0

Low or High

Level Interrupt

Generated

High-Level

Interrupt

Generated

Status 1

Status 2

Generated

Status 0

Figure 7-4. Multiple-Level Interrupt Handling

7-6

KS57C5404/P5404

INTERRUPTS

INTERRUPT PRIORITY REGISTER (IPR)

The 4-bit interrupt priority register (IPR) is used to control multi-level interrupt handling. The IPR is mapped to the

RAM address FB2H, and its reset value is logic zero. Before the IPR is modified by 4-bit write instructions, all

interrupts must first be disabled by a DI instruction.

FB2H

IME

IPR.2

IPR.1

IPR.0

By manipulating the IPR settings, you can choose to process all interrupt requests with the same priority level, or

you can select one type of interrupt for high-priority processing. A low-priority interrupt can itself be interrupted by

a high-priority interrupt, but not by another low-priority interrupt. A high-priority interrupt cannot be interrupted by

any other interrupt source.

Table 7-3. Standard Interrupt Priorities

Interrupt

INTB

Default Priority

1

2

3

4

INT0

INT1

INTT0

The MSB of the IPR, the interrupt master enable flag (IME), enables and disables all interrupt processing. Even if

an interrupt request flag and its corresponding enable flag are set, a service routine cannot be executed until the

IME flag is set to logic one.

The IME flag is mapped to FB2H.3 and can be directly manipulated by EI and DI instructions, regardless of the

current enable memory bank (EMB) value.

Table 7-4. Interrupt Priority Register Settings

IPR.2

IPR.1

IPR.0

Result of IPR Bit Setting

Process all interrupt requests at low priority.

Process INTB interrupt at highest priority.

Process INT0 interrupt at highest priority.

Process INT1 interrupt at highest priority.

Process INTT0 interrupt at highest priority.

0

1

0

1

0

1

0

1

NOTE: When all interrupts are at low priority (the lower three bits of the IPR register are logic zero), the interrupt generated

first has the highest priority. Therefore, the interrupt generated first cannot be superceded by any other interrupt. If

two or more interrupt requests are received simultaneously, the priority level is determined according to the standard

interrupt priorities in Table 7-3 (e.g., the default priority assigned by hardware when the lower three IPR bits = "0"). In

this case, the highest-priority interrupt request is serviced and other interrupts are inhibited. Then, when the high-

priority interrupt returns from its service routine by an IRET instruction, the service routine of an interrupt inhibited is

started.

7-7

INTERRUPTS

KS57C5404/P5404

+

PROGRAMMING TIP — Setting the INT Interrupt Priority

Set the INT1 interrupt to high priority:

BITS

SMB

DI

LD

EMB

15

;

IPR.3 (IME) ¬

0

1

A,#3H

IPR,A

EI

EXTERNAL INTERRUPT MODE REGISTERS (IMOD0, IMOD1)

The following components are used to process external interrupts at the INT0 and INT1 pin:

— Noise filtering circuit for INT0

— Edge detection circuit

— Two mode registers, IMOD0 and IMOD1

The mode registers are used to control the triggering edge of the input signal. IMOD settings let you choose either

the rising or falling edge of the incoming signal at the INT0 and INT1 pins as the interrupt request trigger.

FB4H

FB5H

“0”

"0"

IMOD0.1

"0"

IMOD0.0

IMOD1.0

IMOD0 and IMOD1 bits are mapped to the RAM addresses FB4H (IMOD0) and FB5H (IMOD1), and they are

addressable by 4-bit write instructions. A

clears all IMOD values to logic zero, selecting rising edges as the

trigger for incoming interrupt requests.

Table 7-5. IMOD0 and IMOD1 Register Organization

IMOD0

IMOD1

0

IMOD0.1

IMOD0.0

Effect of IMOD0 Settings

Rising edge detection

0

1

0

1

0

1

Falling edge detection

Both rising and falling edge detection

IRQ0 flag cannot be set to "1"

0

IMOD1.0

Effect of IMOD1 Settings

Rising edge detection

0

1

Falling edge detection

7-8

KS57C5404/P5404

INTERRUPTS

EXTERNAL INTERRUPT 0 and 1 MODE REGISTERS (Continued)

INT0

Edge Detection

IRQ0

IRQ1

INT1

Edge Detection

IMOD1

IMOD0

P0.1

P0.0

Figure 7-5. Circuit Diagram for INT0 and INT1 Pins

When modifying the IMOD0 and IMOD1 registers, it is possible to accidentally set an interrupt request flag. To

avoid unwanted interrupts, take these precautions when writing your programs:

1. Disable all interrupts with a DI instruction.

2. Modify the IMOD0 or IMOD1 register.

3. Clear all relevant interrupt request flags.

4. Enable the interrupt by setting the IEx flag appropriately.

5. Enable all interrupts with an EI instruction.

7-9

INTERRUPTS

KS57C5404/P5404

KEY INTERRUPT MODE REGISTER (IMODK)

The mode register for external interrupts at the KS0–KS1 pins, IMODK, is a 4-bit register at the RAM address

FB6H. IMODK is addressable by 4-bit write instructions. A clears all IMODK bits to logic zero.

FB6H

"0"

IMODK.1 IMODK.0

When bits in the IMODK register are set to logic one, INTK uses the falling edge of an incoming signal at

corresponding pins as the interrupt request trigger. When a falling edge is detected at any of the pins KS0–KS1,

the IRQK flag is set to logic one and a release signal for power-down mode is generated.

If one of KS0 and KS1 is in Low input (or Low output) state, the key interrupt cannot be occurred.

Table 7-6. IMODK Register Bit Settings

IMODK

IMODK.1

IMODK.0

Effect of IMODK Settings

0

1

0

1

0

1

Disable key interrupt

Select falling edge at KS0

Select falling edge at KS1

Select falling edge at KS0–KS1

7-10

KS57C5404/P5404

INTERRUPTS

KS1

KS0

Falling Edge

Detection

Circuit

IMODK

IRQK

NOTES:

1. All of the pins used for key interrupt on a falling edge at P0.2/KS0-P0.3/KS1 must always

be configured to input mode.

2. If any of the KS0-KS1 pins used for interrupt stays low, a key interrupt is not generated.

Since all the KS0-KS1 pins are ANDed, the falling edge detection circuit cannot detects a

falling edge.

Figure 7-6. Circuit Diagram for KS0–KS1 Pins

+

PROGRAMMING TIP — Using INTK as a Key Input Interrupt

When the INTK interrupt is used as a key interrupt, the key interrupt pin must be set to input.

1. When KS0–KS1 are selected:

BITS

SMB

LD

EMB

15

A,#3H

LD

IMODK,A

EA,#00H

PMG1,EA

EA,#D1H

PUMOD,EA

;

(IMODK) ¬ #3H, KS0–KS1 falling edge select

P0 ¬ Input mode

LD

Enable P0 pull-up resistors

7-11

INTERRUPTS

KS57C5404/P5404

INTERRUPT FLAGS

There are three types of interrupt flags: interrupt request and interrupt enable flags that correspond to each

interrupt; the interrupt master enable flag, which enables or disables all interrupt processing.

Interrupt Master Enable Flag (IME)

The interrupt master enable flag, IME, enables or disables all interrupt processing. Therefore, even when an IRQx

flag is set and its corresponding IEx flag is enabled, the interrupt service routine is not executed until the IME flag

is set to logic one.

The IME flag is located in the IPR register (IPR.3), and mapped to the bit address FB2H.3. It can directly be

manipulated by EI and DI instructions, regardless of the current value of the enable memory bank flag (EMB).

Interrupt Enable Flags (IEx)

IEx flags, when set to logic one, enable specific interrupt requests to be serviced. When the interrupt request flag

is set to logic one, an interrupt will not be serviced until its corresponding IEx flag is also enabled.

Interrupt enable flags are mapped to the RAM address area FB8H–FBFH, and can be read, written, or tested

directly by 1-bit instructions (BITS and BITR). IEx flags can be addressed directly at their specific RAM

addresses, regardless of the current value of the enable memory bank (EMB) flag.

Interrupt Request Flags (IRQx)

Interrupt request flags, located in the RAM area FB8H-FBFH, are read/write addressable by 1-bit or 4-bit in-

structions. IRQx flags can be addressed directly at their specific RAM addresses, regardless of the current value

of the enable memory bank (EMB) flag.

When a specific IRQx flag is set to logic one, the corresponding interrupt request is generated. The flag is then

automatically cleared to logic zero by hardware when the interrupt is serviced. An exceptions is the key interrupt

request flag IRQK, which must be cleared by software after the interrupt service routine is executed. IRQx flags

are also used to execute interrupt requests from software. In summary, follow these guidelines for using IRQx

flags:

1. IRQx is set to request an interrupt when an interrupt meets the set condition for interrupt generation.

2. IRQx is set to "1" then cleared by hardware when the interrupt is serviced (except for IRQK).

3. When IRQx is set to "1" by software, an interrupt is generated.

7-12

KS57C5404/P5404

INTERRUPTS

INTERRUPT MASTER ENABLE FLAG (IME)

The interrupt master enable flag, IME, inhibits or enables all interrupt processing. Therefore, even when an IRQx

flag and its corresponding IEx flag are enabled, an interrupt request will not be serviced until the IME flag is set to

logic one. The IME flag is the most significant bit of the 4-bit IPR register at the RAM location FB2H.

IME

0

IPR.2

IPR.1

IPR.0

Effect of Bit Settings

Inhibit all interrupts

Enable all interrupts

1

You can manipulate the IME flag using EI and DI instructions, regardless of the current value of the enable

memory bank (EMB) flag.

INTERRUPT ENABLE FLAGS (IEx)

Interrupt enable flags are used to control the execution of service routines for specific interrupt requests. The

enable flag has priority over a request flag — even if the IRQx flag is enabled, the interrupt request will not be ser-

viced until the corresponding IEx flag is set to logic one.

Using 1-bit or 4-bit instructions and direct addressing, you can read, write, or test IEx (and IRQx) flags regardless

of the current enable memory bank (EMB) value. The IEx and IRQx flags are mapped to the RAM area

FB8H–FBFH.

Table 7-7. Interrupt Enable and Interrupt Request Flag Addresses

Address

FB8H

Bit 3

0

Bit 2

Bit 1

IEB

Bit 0

IRQB

IRQT0

IRQ0

IRQK

0

FBCH

FBEH

FBFH

0

IET0

IE0

IE1

0

IRQ1

0

IEK

NOTES:

1. IEx refers generically to all interrupt enable flags.

2. IRQx refers generically to all interrupt request flags.

3. IEx = 0 is interrupt disable mode.

4. IEx = 1 is interrupt enable mode.

7-13

INTERRUPTS

KS57C5404/P5404

INTERRUPT REQUEST FLAGS (IRQx)

When an interrupt request flag (IRQx) is set, a software-generated interrupt is enabled for the corresponding in-

terrupt. IRQx flags can be written by 1- or 4-bit RAM control instructions. IRQx flags are then cleared

automatically when the interrupt is serviced. An exception is the key interrupt request flag, IRQK, which must be

cleared by software after the interrupt service routine is executed.

Table 7-8. Interrupt Request Flag Conditions and Priorities

Interrupt

Source

Internal /

External

Pre-condition for IRQx Flag Setting

Interrupt

Priority

IRQx Flag

Name

INTB

INT0

I

Reference time interval signal from basic timer

Rising or falling edge detected at INT0 pin

1

2

3

5

–

IRQB

IRQ0

IRQ1

IRQT0

IRQK

E

I

INT1

Rising or falling edge detected at INT1 pin

INTT0

INTK ^(note)

Signals for TCNT0 and TREF0 registers coincide

Falling edge is detected at any one of the KS0–KS1 pins

E

NOTE: INTK is quasi-interrupt and used only for testing incoming signals.

7-14

KS57C5404/P5404

POWER-DOWN

8

POWER-DOWN

OVERVIEW

The KS57C5404 microcontroller has two power-down modes reducing power consumption: idle and stop. Idle

mode is initiated by the IDLE instruction and stop mode by the STOP instruction. (Several NOP instructions must

always follow an IDLE or STOP instruction in a program.) In idle mode, the CPU clock stops while peripherals and

the oscillation source continue to operate normally.

When a

occurs during the normal operation or a power-down mode, a reset operation is initiated and the

CPU enters idle mode. When the standard oscillation stabilization time interval (31.3 ms at 4.19 MHz) has

elapsed, the normal CPU operation resumes.

In stop mode, system clock oscillation is halted (assuming it currently has been operating), and peripheral hard-

ware components are powered-down. The effect of stop mode on specific peripheral hardware components —

CPU, basic timer, timer/counters 0, and — and on external interrupt requests, is detailed in Table 8-1.

NOTE

Do not use stop mode if you are using an external clock source because X_INinput must be restricted

internally to V_SSto reduce current leakage.

Idle or stop mode is terminated either by a

interrupt enable flag, IEx. When power-down mode is terminated by

, or by an interrupt, which are enabled by the corresponding

input, a normal reset operation is

executed. (Assuming that both the interrupt enable flag and the interrupt request flag are set to "1", power-down

mode is released immediately upon entering power-down mode.

When an interrupt is used to release power-down mode, the operation differs depending on the value of the

interrupt master enable flag (IME):

— If the IME flag = "0", program execution is started immediately after the instruction which issues the request to

enter power-down mode. The interrupt request flag remains set to logic one.

— If the IME flag = "1", two instructions are executed after the power-down mode release. Then, the vectored

interrupt is initiated. However, when the release signal is caused by INTK, the operation is identical to the IME

= 0 condition. That is, a vector interrupt is not generated.

8-1

POWER-DOWN

KS57C5404/P5404

Table 8-1. Hardware Operation During Power-Down Modes

Operation

Stop Mode (STOP)

Idle Mode (IDLE)

Clock oscillator

System clock oscillation stops

CPU clock oscillation stops (system clock

oscillation continues)

Basic timer

Basic timer stops

Basic timer operates (with IRQB set at

each reference interval)

Timer/counter 0

Operates only if TCL0 is selected as the Timer/counter 0 operates

counter clock

External interrupts

CPU

INT0, INT1 and INTK are acknowledged INT0, INT1 and INTK are acknowledged

All CPU operations are disabled

Power-down mode

release signal

Interrupt request signals which are

enabled by an interrupt enable flag or by enabled by an interrupt enable flag or by

Interrupt request signals which are

input

Buzzer

Buzzer operation is stopped

Buzzer operates

D/A Converter

D/A Converter retains the last analog

value

D/A Converter retains the last analog

value

8-2

KS57C5404/P5404

POWER-DOWN

IDLE MODE TIMING DIAGRAMS

Oscillation

Stabilization

(31.3 ms/4.19 MHz)

Idle

Instruction

RESET

Normal Mode

Idle Mode

Normal Mode

Normal Oscillation

Clock

Signal

Figure 8-1. Timing When Idle Mode is Released by

Idle

Instruction

Mode

Release

Signal

Interrupt Acknowledge (IME = 1)

Normal Mode

Idle Mode

Normal Mode

Normal Oscillation

Clock

Signal

Figure 8-2. Timing When Idle Mode is Released by an Interrupt

8-3

POWER-DOWN

KS57C5404/P5404

STOP MODE TIMING DIAGRAMS

Oscillation

Stabilization

(31.3 ms/4.19 MHz)

Stop

Instruction

RESET

Normal Mode

Stop Mode

Idle Mode

Normal Mode

Oscillation

Stops

Oscillation Resumes

Clock

Signal

Figure 8-3. Timing When Stop Mode is Released by

Oscillation

Stabilization

(Bmod Setting)

Stop

Instruction

Mode

Release

Signal

Int Ack (IME = 1)

Normal Mode

Stop Mode

Idle Mode

Oscillation

Stops

Oscillation Resumes

Clock

Signal

Figure 8-4. Timing When Stop Mode is Release by an Interrupt

8-4

KS57C5404/P5404

POWER-DOWN

I/O PORT PIN CONFIGURATION FOR POWER-DOWN

The following method describes how to configure I/O port pins to reduce power consumption during power-down

modes (stop, idle):

Condition 1: If the microcontroller is not configured to an external device:

1. Connect unused port pins according to the information in Table 8-2.

2. Disable all pull-up resistors for output pins by making appropriate modifications to the pull-up resistor mode

register, PUMOD. Reason: If output goes low when the pull-up resistor is enabled, there may be unexpected

surges of current through the pull-up.

3. Disable pull-up resistors for input pins configured to V_DDor V_SSlevels in order to check the current input

option. Reason: If the input level of a port pin is set to V_SSwhen a pull-up resistor is enabled, it will draw an

unnecessarily large current.

Condition 2: If the microcontroller is configured to an external device and the external device's V_DDsource is

turned off in power-down mode.

1. Connect unused port pins according to the information in Table 8-2.

2. Disable the pull-up resistors of output pins by making appropriate modifications to the pull-up resistor mode

register, PUMOD. Reason: If output goes low when the pull-up resistor is enabled, there may be unexpected

surges of current through the pull-up.

3. Disable pull-up resistors for input pins configured to V_DDor V_SSlevels in order to check the current input

option. Reason: If the input level of a port pin is set to V_SSwhen a pull-up resistor is enabled, it will draw an

unnecessarily large current.

4. Disable the pull-up resistors of input pins connected to the external device by making necessary

modifications to the PUMOD register.

5. Configure the output pins that are connected to the external device to low level. Reason: When the external

device's V_DDsource is turned off, and if the microcontroller's output pins are set to high level, V_DD–0.7 V is

supplied to the V_DDof the external device through its input pin. This causes the device to operate at the level

V_DD–0.7 V. In this case, total current consumption would not be reduced.

6. Determine the correct output pin state necessary to block current pass in accordance with the external

transistors (PNP, NPN).

8-5

POWER-DOWN

KS57C5404/P5404

RECOMMENDED CONNECTIONS FOR UNUSED PINS

To reduce overall power consumption, please configure unused pins according to the guidelines described in

Table 8-2.

Table 8-2. Unused Pin Connections for Reduced Power Consumption

Pin/Share Pin Names

P0.0/INT0

P0.1/INT1

P0.2/KS0

P0.3/KS1

Recommended Connection

Input mode: Connect to V_DD

Output mode: Do not connect

P1.0/TCL0

P1.1/TCLO0

P1.2/CLO

P1.3/BUZ

P2.0

P4.0–P4.3

P5.0–P5.3

DAO

No connection

8-6

KS57C5404/P5404

9

RESET

OVERVIEW

When a

signal is input during the normal operation or power-down mode, a reset operation is initiated and

the CPU enters idle mode. Then, when the standard oscillation stabilization interval of 31.3 ms at 4.19 MHz has

elapsed, the normal system operation resumes.

Regardless of when the

occurs — during normal operating mode or power-down mode — the effect on most

hardware register values is almost identical. The exceptions are as follows:

— Carry flag

— Data memory values

— General-purpose registers E, A, L, H, X, W, Z, and Y

If a

occurs during idle or stop mode, the current values in these registers are retained. Otherwise, their

values are undefined.

Oscillation

Stabilization

(31.3 ms/4.19 MHz)

RESET

Input

Idle Mode

Operating Mode

Normal Mode or

Power-Down Mode

Reset Operation

Figure 9-1. Timing for Oscillation Stabilization after

9-1

RESET

KS57C5404/P5404

HARDWARE REGISTER VALUES AFTER

Table 9-1 gives you detailed information about hardware register values after a

or normal operation mode.

occurs during power-down

Table 9-1. Hardware Register Values after

Hardware Component

or Subcomponent

If a

Occurs During

If a

Occurs During

Normal Operation

Power-Down Mode

Program counter (PC)

Lower three bits of address 0000H Lower three bits of address 0000H

are transferred to PC11–8, and

the contents of 0001H to PC7–0.

are transferred to PC11–8, and

the contents of 0001H to PC7–0.

Program Status Word (PSW):

Carry flag (C)

Retained

Undefined

Skip flag (SC0–SC2)

0

Interrupt status flags (IS0, IS1)

Bank enable flags (EMB, ERB)

Bit 6 of address 0000H in program Bit 6 of address 0000H in program

memory is transferred to the ERB memory is transferred to the ERB

flag, and bit 7 of the address to the flag, and bit 7 of the address to the

EMB flag.

Stack pointer (SP)

Undefined

Data Memory (RAM):

General registers E, A, L, H, X, W, Z, Y

General-purpose registers

Values retained

Undefined

0, 0

(note)

Values retained

Bank selection registers (SMB, SRB)

BSC register (BSC0–BSC3)

0, 0

0

Clocks:

Power control register (PCON)

0

Clock output mode register (CLMOD)

Interrupts:

Interrupt request flags (IRQx)

Interrupt enable flags (IEx)

Interrupt priority flag (IPR)

0

Interrupt master enable flag (IME)

INT0 mode register (IMOD0)

INT1 mode register (IMOD1)

INTK mode register (IMODK)

9-2

KS57C5404/P5404

Table 9-1. Hardware Register Values after

Hardware Component If a Occurs During

(Continued)

If a

Occurs During

or Subcomponent

Power-Down Mode

Normal Operation

I/O Ports:

Output buffers

Off

0

Off

0

Output latches

Port mode flags (PM)

0

Pull-up resistor mode reg (PUMOD)

Port open-drain enable register (PNE)

0

Watch-dog Timer:

WDT mode register (WDMOD)

WDT clear flag (WDTCF)

A5H

0

A5H

0

Basic Timer:

Count register (BCNT)

Mode register (BMOD)

Undefined

0

Undefined

0

Timer/Counter 0:

Count registers (TCNT0)

Reference registers (TREF0)

Mode registers (TMOD0)

Output enable flags (TOE0)

0

FFH

0

FFH

0

Buzzer:

Buzzer mode register (BUZMOD)

D/A Converter:

0

D/A converter mode register (DAMOD)

D/A converter DATA register (DADATA)

0

Undefined

NOTE: The value of the 0F8H–0FDH are not retained when a RESET signal is input.

9-3

RESET

KS57C5404/P5404

NOTES

9-4

KS57C5404/P5404

I/O PORTS

10 I/O PORTS

OVERVIEW

The KS57C5404 has five I/O ports. Pin addresses for all I/O ports are mapped to the locations

FF0H–FF5H in bank 15 of the RAM. The contents of I/O port pin latches can be read, written, or tested at the

corresponding address using bit manipulation instructions.

There are a total of 17 configurable I/O pins, including 8 high-current I/O pins for a maximum number of 17 I/O

pins.

Port Mode Flags

Port mode flags (PM) are used to configure I/O ports 0 and 1 (port mode group 1), port 2 (port mode group 2),

and ports 4 and 5 (port mode group 3) to input or output mode by setting or clearing the corresponding I/O buffer.

PM flags are stored in three 8-bit registers in the RAM area FE8H–FEDH, and they are addressable by 8-bit write

instructions only.

Pull-up Resistors

Pull-up resistors are assignable to input pins of ports 0, 1, 2, 4, and 5. When a configurable I/O port pin serves as

an output pin, its assigned pull-up resistor is automatically disabled, even though the pin's pull-up resistor is

enabled by a corresponding bit setting in the pull-up resistor mode register (PUMOD).

PUMOD Control Register

The pull-up mode register (PUMOD) is an 8-bit register used to assign internal pull-up resistors by software to

specific I/O ports.

When a configurable I/O port pin is used as an output pin, its assigned pull-up resistor is automatically disabled,

even though the pin's pull-up is enabled by a corresponding PUMOD bit setting.

PUMOD is mapped to the RAM address FDCH–FDDH and is addressable by 8-bit write instructions only. A

clears PUMOD register values to logic zero, automatically disconnecting all software-assignable port pull-up resis-

tors.

10-1

I/O PORTS

KS57C5404/P5404

Table 10-1. I/O Port Overview

Port

I/O

Pins

Pin Names

Address

Function Description

0

I/O

4

P0.0–P0.3

FF0H

4-bit I/O port. 1- or 4-bit read/write and test is

possible. Pull-up resistors are assignable to

input pins by software and are automatically

disabled for output pins. Pins are individually

configurable as input or output.

1

2

I/O

4

1

P1.0–P1.3

P2.0

FF1H

FF2H

Same as port 0.

1-bit I/O port. 1- or 4-bit read/write and test is

possible. Pull-up resistor is assignable to input

pin by software and is automatically disabled

for output pin.

4, 5

I/O

8

P4.0–P4.3

P5.0–P5.3

FF4H

FF5H

4-bit I/O ports. 1-, 4-, and 8-bit read/write/test

is possible. Pins are individually configurable

as input or output. Pull-up resistors are

assignable to input pins by software and are

automatically disabled for output pins.

The N-channel open drain or push-pull output

can be selected by software (1-bit unit)

Table 10-2. I/O Port Pin Status During Instruction Execution

Instruction Type

Example

Input Mode Status

Output Mode Status

1-bit test

BTST P0.1

Input or test data at each pin

Input or test data at output latch

1-bit input

4-bit input

8-bit input

LDB

LD

C,P1.3

A,P5

EA,P4

1-bit output

BITR P1.0

Output latch contents undefined

Output pin status is modified

4-bit output

8-bit output

LD

P2,A

P4,EA

Transfer accumulator data to the

output latch

Transfer accumulator data to the

output pin

10-2

KS57C5404/P5404

I/O PORTS

PORT MODE FLAGS (PM FLAGS)

Port mode flags (PM) are used to configure I/O ports 0–2, 4 and 5 to input or output mode by setting or clearing

the corresponding I/O buffer. PM flags are stored in three 8-bit registers in the RAM area FE8H–FEDH, and are

addressable by 8-bit write instructions only.

For convenient program reference, PM flags are organized into three groups — PMG1, PMG2, and PMG3, as

shown in Table 10-3.

Table 10-3. Port Mode Groups and Corresponding I/O Ports

Port Mode Group ID

PMG1

Corresponding I/O Ports

Ports 0 and 1

Port Mode Group Address

FE8H–FE9H

PMG2

Port 2

FEAH–FEBH

PMG3

Ports 4 and 5

FECH–FEDH

When a PM flag is "0", the port is set to input mode; when it is "1", the port is enabled for output. A

port mode flags to logic zero, automatically configuring the corresponding I/O ports to input mode.

clears all

Table 10-4. Port Mode Flag Map

PM Group ID

Address

FE8H

Bit 3

PM0.3

PM1.3

"0"

Bit 2

PM0.2

PM1.2

"0"

Bit 1

PM0.1

PM1.1

"0"

Bit 0

PMG1

PM0.0

PM1.0

PM2.0

"0"

FE9H

PMG2

PMG3

FEAH

FEBH

FECH

FEDH

"0"

PM4.3

PM5.3

PM4.2

PM5.2

PM4.1

PM5.1

PM4.0

PM5.0

NOTE: If bit = "0", the corresponding I/O pin is set to input mode. If bit = "1", the pin is set to output mode. All flags are

cleared to "0" after a

.

+

PROGRAMMING TIP — Configuring I/O Ports as Input or Output

Configure P0.0 and P3.0 as an output port and other ports as input ports:

BITS

SMB

LD

EMB

15

EA,#11H

PMG1,EA

EA,#00H

PMG2,EA

EA,#00H

PMG3,EA

;

P0.0 and P1.0 ¬ Output

P2 ¬ Input

P4, P5 ¬ Input

10-3

I/O PORTS

KS57C5404/P5404

PULL-UP RESISTOR MODE REGISTER (PUMOD)

The pull-up resistor mode register (PUMOD) is an 8-bit register used to assign internal pull-up resistors by soft-

ware to specific I/O ports. When a configurable I/O port pin is used as an output pin, its assigned pull-up resistor

is automatically disabled, even though the pin's pull-up is enabled by a corresponding PUMOD bit setting.

PUMOD is mapped to the RAM address FDCH–FDDH and is addressable by 8-bit write instructions only. A

clears PUMOD register values to logic zero, automatically disconnecting all software-assignable port pull-up resis-

tors.

Table 10-5. Pull-up Resistor Mode Register (PUMOD) Organization

Address

FDCH

Bit 3

"0"

Bit 2

PUR2

"0"

Bit 1

PUR1

PUR5

Bit 0

PUR0

PUR4

FDDH

"0"

NOTE: When bit = "1", a pull-up resistor is assigned to the corresponding I/O port: PUMOD.0 for port 0, PUMOD.1 for

port 1, and so on.

N-CHANNEL OPEN-DRAIN ENABLE REGISTER (PNE)

The N-channel, open-drain mode register, PNE, is used to configure ports 4 and 5 to n-channel, open-drain mode

or as push-pull outputs.

When a bit in the PNE register is set to "1", the corresponding output pin is configured to n-channel open-drain;

when set to "0", the output pin is configured to push-pull; PNE4.3 for P4.3, PNE4.2 for P4.2, PNE4.1 for P4.1,

PNE4.0 for P4.0, PNE5.3 for P5.3, PNE5.2 for P5.2, PNE5.1 for P5.1 and PNE5.0 for P5.0.

FDAH

FDBH

PNE4.3

PNE5.3

PNE4.2

PNE5.2

PNE4.1

PNE5.1

PNE4.0

PNE5.0

PNE4

PNE5

+

PROGRAMMING TIP — Enabling and Disabling I/O Port Pull-up Resistors

P5 pull-up resistor is enabled; P0, P1, and P4 pull-up resistors are disabled as follows:

BITS

SMB

LD

EMB

15

EA,#20H

PUMOD,EA

LD

; P5 enable

10-4

KS57C5404/P5404

I/O PORTS

PORT 0 CIRCUIT DIAGRAM

V

DD

PUR0

PM0.3

PM0.2

PM0.1

PM0.0

P0.0

P0.1

P0.2

P0.3

OUTPUT

LATCH

1, 4, 8

PM0.0

PM0.1

PM0.2

PM0.3

M

U

X

INT0

INT1

KS0

KS1

1, 4

NOTE: When a port pin serves as an output, its pull-up resistor is automatically disabled, even though

the port's pull-up resistor is enabled by bit settings to the pull-up resistor mode register (PUMOD).

Port 0 is a schmitt trigger input.

Figure 10-1. I/O Port 0 Circuit Diagram

10-5

I/O PORTS

KS57C5404/P5404

PORT 1 CIRCUIT DIAGRAM

V

DD

PUR1

PM1.3

PM1.2

PM1.1

PM1.0

PUR1

P1.0

P1.1

P1.2

P1.3

TCLO0

OUTPUT

LATCH

CLO

1, 4

BUZ

PM1.0

PM1.1

PM1.2

PM1.3

M

U

X

TCL0

1, 4

NOTE: When a port pin serves as an output, its pull-up resistor is automatically disabled, even

though the port's pull-up resistor is enabled by bit settings in the pull-up resistor mode

register (PUMOD).

Figure 10-2. Input Port 1 Circuit Diagram

10-6

KS57C5404/P5404

I/O PORTS

PORT 2 CIRCUIT DIAGRAM

V

DD

PUR2

PM2.0

1, 4

OUTPUT

LATCH

P2.0

M

U

X

PM2.0

1, 4

Figure 10-3. Port 2 Circuit Diagram

10-7

I/O PORTS

KS57C5404/P5404

PORTS 4 AND 5 CIRCUIT DIAGRAM

V

DD

a=4, 5

P-CH

8

PUMOD.a

PNE

P-CH

Output

Latch

Px.b

1, 4, 8

8

N-CH

PMx.b

x = 4, 5

b = 0, 1, 2, 3

V

SS

M

U

X

Figure 10-4. Circuit Diagram for Ports 4 and 5

10-8

KS57C5404/P5404

TIMERS and TIMER/COUNTER

11 TIMERS and TIMER/COUNTER

OVERVIEW

There are two timer and timer/counter function modules:

— 8-bit basic timer (BT)

— 8-bit timer/counter 0 (TC0)

The 8-bit basic timer (BT) is the microcontroller's main interval timer. It generates an interrupt request at a fixed

time interval by making appropriate modification to the mode register.

The basic timer also functions as a 'watchdog' timer and is used to determine clock oscillation stabilization time

when stop mode is released by an interrupt or a

.

The 8-bit timer/counter 0 (TC0) is a programmable timer/counter that is used primarily for event counting and

clock frequency modification and output.

11-1

TIMERS and TIMER/COUNTER

KS57C5404/P5404

BASIC TIMER (BT)

OVERVIEW

The 8-bit basic timer (BT) has six functional components:

— Clock selector logic

— 4-bit basic timer mode register (BMOD)

— 8-bit basic timer counter register (BCNT)

— 8-bit Watchdog timer mode register (WDMOD)

— Watchdog timer counter clear flag (WDTCF)

— 3-bit watchdog timer clear flag (WDCNT)

The basic timer generates interrupt requests at precise intervals, based on the frequency of the system clock.

You can use the basic timer as a "watchdog" timer for monitoring system events or use BT output to stabilize

clock oscillation when stop mode is released by an interrupt or after a

.

Use the basic timer mode register, BMOD, to turn the BT on and off, to select input clock frequency, and to con-

trol interrupt or stabilization intervals.

Interval Timer Function

The measurement of elapsed time intervals is the primary function the basic timer's. The standard interval is 256

BT clock pulses.

To restart the basic timer, set bit 3 of the mode register BMOD to logic one. The input clock frequency and the

interrupt and stabilization interval are selected by loading appropriate bit values to BMOD.2–BMOD.0.

The 8-bit counter register, BCNT, is incremented each time a clock signal that corresponds to the frequency

selected by BMOD is detected. BCNT continues incrementing as it counts BT clocks until an overflow occurs.

An overflow causes the BT interrupt request flag (IRQB) to be set to logic one to signal that the designated time

interval has elapsed. An interrupt request is then generated, BCNT is cleared to logic zero, and counting

continues from 00H.

Watchdog Timer Function

The basic timer can also be used as a "watchdog" timer that detecting any inadvertent program loop, that is, a

system or program operation error. For this purpose, instructions that clear the watchdog timer(BITS WDTCF)

should be executed at proper points in a program within a given period. If such an instruction is not executed

within the period and the watchdog timer overflows, a reset signal is generated and the system is restarted with a

reset. The operation of the watchdog timer is as follows:

¾

Write some values (except #5AH) to Watchdog Timer Mode register, WDMOD.

If WDCNT overflows, a system reset is generated.

Oscillation Stabilization Interval Control

Bits 2–0 of the BMOD register are used to select the input clock frequency for the basic timer. This setting also

determines the time interval (also referred to as 'wait time') required to stabilize clock signal oscillation when

power-down mode is released by an interrupt. When a

, the standard stabilization interval

for system clock oscillation after a

is 31.3 ms at 4.19 MHz.

11-2

KS57C5404/P5404

TIMERS and TIMER/COUNTER

Table 11-1. Basic Timer Register Overview

Register

Name

Type

Description

Size

RAM

Address

Addressing

Mode

Reset

Value

BMOD

Control Controls the clock frequency (mode)

of the basic timer and the oscillation

stabilization interval after power-down

a mode release or

4-bit

F85H

4-bit write-only;

BMOD.3 is also

1-bit writeable

"0"

U ^(note)

Counts clock pulses matching the

BMOD frequency setting

8-bit

read-only

BCNT

Counter

8-bit

F86H– F87H

WDMOD Control Controls watchdog timer operation.

WDTCF Control Clear the watchdog timer's counter.

8-bit

1-bit

F98H–F99H 8-bit write-only

F9AH.3 1-bit write-only

A5H

"0"

NOTE: 'U' means the value is undetermined after a

.

11-3

TIMERS and TIMER/COUNTER

KS57C5404/P5404

"Clear" Signal

Clear

BCNT

Clear

IRQB

Bits

Instruction

BMOD.3

BMOD.2

BMOD.1

BMOD.0

Interrupt

Request

Overflow

Clock

4

BCNT

8

IRQB

Selector

1-Bit R/W

CPU Clock Start Signal

(Power-Down Release)

Clock Input

1 pulse period = BT input clock 2 ⁸(1/2 duty)

3-Bit Counter

Overflow

WDCNT

RESET

RESET Signal

Generation

Clear

WDMOD

8

WDTCF

DELAY

Clear

(note)

STOP

WAIT

Bits Instruction

RESET

NOTES:

RESET

1. WAIT means the stabilization time after

2. The

or the Stabilization time after STOP mode release.

RESET

signal can be generated if the WDMOD is toggled eight times. “Toggle” means to change the

value of WDMOD from 5AH to another value, or vice versa.

Figure 11-1. Basic Timer Circuit Diagram

11-4

KS57C5404/P5404

TIMERS and TIMER/COUNTER

BASIC TIMER MODE REGISTER (BMOD)

The basic timer mode register, BMOD, is a 4-bit write-only register located at the RAM address F85H. Bit 3, the

basic timer start control bit, is also 1-bit addressable. All BMOD values are set to logic zero after a

interrupt request signal generation is set to the longest interval. (BT counter operation cannot be stopped.) BMOD

settings have the following effects:

— Restart the basic timer,

— Control the frequency of clock signal input to the basic timer,

— Determine time interval required for clock oscillation to stabilize after the release of stop mode by an interrupt.

By loading different values into the BMOD register, you can dynamically modify the basic timer clock frequency

12

5

during program execution. Four BT frequencies, ranging from fx/2 (1.02 kHz) to fx/2 (131 kHz), are selectable.

12

Since BMOD's reset value is logic zero, the default clock frequency setting is fx/2 . (kHz frequencies assume a

system clock (fx) frequency of 4.19 MHz.)

The most significant bit of the BMOD register, BMOD.3, is used to start the basic timer again. When BMOD.3 is

set to logic one (enabled) by a 1-bit write instruction, the contents of the BT counter register (BCNT) and the BT

interrupt request flag (IRQB) are both cleared to logic zero, and timer operation is restarted.

The combination of bit settings in the remaining three registers — BMOD.2, BMOD.1, and BMOD.0 — determines

the clock input frequency and oscillation stabilization interval.

Table 11-2. Basic Timer Mode Register (BMOD) Organization

BMOD.3

Basic Timer Enable/Disable Control Bit

1

Start basic timer; clear IRQB, BCNT, and BMOD.3 to "0"

BMOD.2

BMOD.1

BMOD.0

Basic Timer Input Clock

fx/2¹²(1.02 kHz)

fx/2⁹(8.18 kHz)

Oscillation Stabilization

2²⁰/fx (250 ms)

0

1

0

1

0

1

0

1

2¹⁷/fx (31.3 ms)

fx/2⁷(32.7 kHz)

2¹⁵/fx (7.82 ms)

fx/2⁵(131 kHz)

2¹³/fx (1.95 ms)

NOTES:

1. Clock frequencies and stabilization intervals assume a system oscillator clock frequency (fx) of 4.19 MHz.

2. fx = system clock frequency.

3. Oscillation stabilization time is the time required to stabilize clock signal oscillation after stop mode is released.

4. The standard stabilization time for system clock oscillation after a

is 31.3 ms at 4.19 MHz.

11-5

TIMERS and TIMER/COUNTER

KS57C5404/P5404

BASIC TIMER COUNTER (BCNT)

BCNT is an 8-bit counter register for the basic timer. It is mapped to the RAM addresses F86H–F87H and can be

addressed by 8-bit read instructions.

A

leaves the BCNT register value undetermined. BCNT is automatically cleared to logic zero whenever the

BMOD register control bit (BMOD.3) is set to "1" to restart the basic timer. It is incremented each time a clock

pulse of the frequency determined by the current BMOD bit settings is detected.

When BCNT has incremented to hexadecimal 'FFH' (256 clock pulses), it is cleared to '00H' and an overflow is

generated. The overflow causes the interrupt request flag, IRQB, to be set to logic one. When the interrupt

request is generated, BCNT immediately resumes counting incoming clock signals.

NOTE

Always execute a BCNT read operation twice to eliminate the possibility of reading unstable data while

the counter is incrementing. If, after two consecutive reads, the BCNT values match, you can select the

latter value as valid data. Until the results of the consecutive reads match, however, the read operation

must be repeated until the validation condition is met.

BASIC TIMER OPERATION SEQUENCE

The basic timer's sequence of operations may be summarized as follows:

1. Set bit BMOD.3 to logic one to restart basic timer operation

2. BCNT is incremented by one after each clock pulse corresponding to BMOD selection

3. BCNT overflows if BCNT ³ 255 (FFH)

4. When an overflow occurs, the IRQB flag is set to logic one by hardware

5. The interrupt request is generated

6. BCNT is automatically cleared to logic zero (BCNT = 00H)

7. BCNT resumes counting BT clock pulse

11-6

KS57C5404/P5404

TIMERS and TIMER/COUNTER

+

PROGRAMMING TIP — Using the Basic Timer

1. To read the basic timer count register (BCNT):

BITS

SMB

LD

EMB

15

BCNTR

EA,BCNT

YZ,EA

EA,BCNT

EA,YZ

BCNTR

CPSE

JR

2. When stop mode is released by an interrupt, set the oscillation stabilization interval to 31.3 ms (at 4.19 MHz):

BITS

SMB

LD

EMB

15

A,#0BH

BMOD,A

LD

;

Wait time is 31.3 ms

Set stop power-down mode

STOP

NOP

NORMAL

STOP MODE

IDLE MODE

(31.3 ms)

OPERATING MODE

CPU

OPERATION

STOP

INSTRUCTION

STOP MODE IS

RELEASED BY

INTERRUPT

3. To set the basic timer interrupt interval time to 1.95 ms (at 4.19 MHz):

BITS

SMB

LD

EMB

15

A,#0FH

BMOD,A

LD

EI

BITS

IEB

;

Basic timer interrupt enable flag is set to "1"

4. Clear BCNT and the IRQB flag and restart the basic timer:

BITS

SMB

BITS

EMB

15

BMOD.3

11-7

TIMERS and TIMER/COUNTER

KS57C5404/P5404

WATCHDOG TIMER MODE REGISTER (WDMOD)

The watchdog timer mode register, WDMOD, is an 8-bit write-only register located at the RAM address

F98H–F99H. WDMOD register controls enabling or disabling the watchdog timer function. WDMOD values are

set to logic "A5H" after a RESET and this value enables the watchdog timer. The watchdog timer's period is set to

the longest interval because a BT overflow signal is generated with the longest interval. (BT counter operation

cannot be stopped.)

Table 11-3. Watchdog Timer Mode Control Register

WDMOD

Watchdog Timer Enable/Disable Control

Disable Watchdog timer function value

Enable Watchdog timer function

5AH

Any other Value

WATCHDOG TIMER COUNTER (WDCNT)

WDCNT is a 3-bit counter. WDCNT is automatically cleared to logic zero whenever the WDTCF register control

bit (WDTCF) is set to "1" to restart WDCNT. Reset, stop, and wait signal also clear WDCNT to logic zero. WDCNT

is incremented each time a clock pulse of the overflow frequency determined by the current BMOD bit settings is

detected. When WDCNT has incremented to hexadecimal '07H' (8 BT overflow pulses), it is cleared to '00H' and

an overflow is generated. The overflow causes a system reset. When an interrupt request is generated, BCNT

immediately resumes counting incoming clock signals.

WATCHDOG TIMER'S COUNTER CLEAR FLAG (WDTCF)

WDTCF(F9AH.3) setting clears the WDT's counter to zero and restarts the WDT's counter.

Table 11-4. Watchdog Timer Interval Time

WDT Interval Time ⁽¹⁾

BMOD

x000b

x011b

x101b

x111b

BT Input Clock

fxx/2¹²

WDCNT Input Clock

fxx/(2¹²´ 2⁸)

fxx/(2⁹´ 2⁸)

(7 or 8) ´ (2¹²´ 2⁸) / fxx = 1.75–2 sec

(7 or 8) ´ (2⁹´ 2⁸) / fxx = 218.7–250 ms

(7 or 8) ´ (2⁷´ 2⁸) / fxx = 54.6–62.5 ms

(7 or 8) ´ (2⁵´ 2⁸) / fxx = 13.6–15.6 ms

fxx/2⁹

fxx/2⁷

fxx/(2⁷´ 2⁸)

fxx/2⁵

fxx/(2⁵´ 2⁸)

NOTES:

1. Clock frequencies assume a system oscillator clock frequency (fxx) of 4.19MHz .

2. fxx = system clock frequency.

11-8

KS57C5404/P5404

TIMERS and TIMER/COUNTER

8-BIT TIMER/COUNTER 0 (TC0)

Timer/counter 0 (TC0) is used to count system 'events' by identifying the transition (high-to-low or low-to-high) of

incoming square wave signals. To indicate that an event has occurred, or that a specified time interval has

elapsed, TC0 generates an interrupt request. Counting signal transitions and comparing the current counter value

with the reference register value, TC0 can be used to measure specific time intervals.

TC0 has a reloadable counter that consists of two parts: an 8-bit reference register (TREF0) into which you write

the counter reference value, and an 8-bit counter register (TCNT0) whose value is automatically incremented by

counter logic.

An 8-bit mode register, TMOD0, is used to activate the timer/counter and select the basic clock frequency to be

used for timer/counter operations. You can modify the basic frequency dynamically by loading new values into

TMOD0 during program execution.

TC0 FUNCTION SUMMARY

8-bit programmable timer

External event counter

Generates interrupts at specific time intervals based on the selected clock

frequency.

Counts various system "events" based on edge detection of external clock

signals at the TC0 input pin, TCL0. To start the event counting operation,

TMOD0.2 is set to "1" and TMOD0.6 is cleared to "0".

Arbitrary frequency output

External signal divider

Outputs selectable clock frequencies to the TC0 output pin, TCLO0.

Divides the frequency of an incoming external clock signal according to a modi-

fiable reference value (TREF0), and outputs the modified frequency to the

TCLO0 pin.

11-9

TIMERS and TIMER/COUNTER

KS57C5404/P5404

TC0 COMPONENT SUMMARY

Mode register (TMOD0)

Activates the timer/counter and selects the internal clock frequency or the

external clock source at the TCL0 pin.

Reference register (TREF0)

Counter register (TCNT0)

Clock selector circuit

Stores the reference value for the desired number of clock pulses between in-

terrupt requests.

Counts internal or external clock pulses based on the bit settings in TMOD0

and TREF0.

Together with the mode register (TMOD0), lets you select one of four internal

clock frequencies, or external clock frequency.

8-bit comparator

Determines when to generate an interrupt by comparing the current value of

the counter register (TCNT0) with the reference value previously programmed

into the reference register (TREF0).

Output latch (TOL0)

A TC0 interrupt request or clock pulse is stored output latch, which is

connected to the TC0 output pin, TCLO0.

When the contents of the TCNT0 and TREF0 registers coincide, the

timer/counter interrupt request flag (IRQT0) is set to "1", the status of TOL0 is

inverted, and an interrupt is generated.

Output enable flag (TOE0)

You must set this flag to logic one before the contents of the TOL0 latch can be

output to TCLO0.

Interrupt request flag (IRQT0) This flag is cleared when TC0 operation starts and the TC0 interrupt service

routine is executed and is enabled whenever the counter value and reference

value coincide.

Interrupt enable flag (IET0)

Must be set to logic one before the interrupt requests generated by

timer/counter can be processed.

Table 11-5. TC0 Register Overview

Type

Description

Size

Register

Name

RAM

Address

Addressing

Mode

Reset

Value

TMOD0

Control

8-bit

F90H–F91H

"0"

Controls TC0 restart (bit 2);

clears and resumes counting

operation (bit 3); sets input

clock and clock frequency (bits

6–4)

8-bit

write-only;

(TMOD0.3

is also 1-bit

write-only)

TCNT0

TREF0

TOE0

Counter

Counts clock pulses matching

the TMOD0 frequency setting

8-bit

1-bit

F94H–F95H

F96H–F97H

F92H.2

8-bit

read-only

"0"

FFH

"0"

Reference Stores reference value for the

timer/counter 0 interval setting

8-bit

write-only

Flag

Controls timer/counter 0 output

to the TCLO0 pin

1/4-bit

write-only

11-10

KS57C5404/P5404

TIMERS and TIMER/COUNTER

CLOCK

10

6

4

(fx/2 , fx/2 , fx/2 , fx)

TCL0

8

TMOD0.7

8-BIT

COMPARATOR

TMOD0.6

TMOD0.5

TMOD0.4

TMOD0.3

TMOD0.2

TMOD0.1

TMOD0.0

TCNT0

TREF0

CLOCK

SELECTOR

8

CLEAR

INVERTED

SET

TOL0

IRQT0

TCLO0

PM1.1

P1.1 LATCH

TOE0

Figure 11-2. TC0 Circuit Diagram

TC0 ENABLE/DISABLE PROCEDURE

Enable Timer/Counter 0

— Set TMOD.2 to logic one (RAM address F90H.2)

— Set the TC0 interrupt enable flag IET0 to logic one (RAM address FBCH.1)

— Set TMOD0.3 to logic one (RAM address F90H.3)

TCNT0, IRQT0, and TOL0 are cleared to logic zero, and timer/counter operation starts.

Disable Timer/Counter

— Set TMOD0.2 to logic zero (RAM address F90H.2)

Clock signal input to the counter register TCNT0 is halted. The current TCNT0 value is retained and can be read if

necessary.

11-11

TIMERS and TIMER/COUNTER

KS57C5404/P5404

TC0 PROGRAMMABLE TIMER/COUNTER FUNCTION

Timer/counter 0 can be programmed to generate interrupt requests at various intervals, based on the system

clock frequency you select.

The 8-bit TC0 mode register, TMOD0, is used to activate the timer/counter and to select the clock frequency. The

reference register, TREF0, stores your value for the number of clock pulses to be generated between interrupt

requests. The counter register, TCNT0, counts the incoming clock pulses, which are compared to the TREF0

value as TCNT0 is incremented. When there is a match (TREF0 = TCNT0), an interrupt request is generated.

To program the timer/counter to generate interrupt requests at specific intervals, you should choose one of four

internal clock frequencies (divisions of the system clock, fx) and load your own counter reference value into the

TREF0 register.

TCNT0 is incremented each time an internal counter pulse is detected with the reference clock frequency

specified by TMOD0.4–TMOD0.6 settings. When the TC0 interrupt request flag (IRQT0) is set to logic one and the

status of TOL0 is inverted, the interrupt is generated. The content of TCNT0 is then cleared to 00H, and TC0

continues counting.

The interrupt request mechanism for the programmable timer/counter consists of the TC0 interrupt enable flag

IET0 and the TC0 interrupt request flag IRQT0.

TC0 OPERATION SEQUENCE

The general sequence of operations when using TC0 as a programmable timer/counter can be summarized as

follows:

1. Set TMOD0.2 to "1" to enable TC0

2. Set TMOD0.6 to "1" to enable the system clock (fx) input

n

3. Set TMOD0.5 and TMOD0.4 bits to desired internal frequency (fx/2 )

4. Load a value to TREF0 to specify the interval between interrupt requests

5. Set the TC0 interrupt enable flag (IET0) to "1"

6. Set TMOD0.3 bit to "1" to clear TCNT0, IRQT0, and TOL0, and start counting

7. TCNT0 increments with each internal clock pulse

8. When the comparator shows TCNT0 = TREF0, the IRQT0 flag is set to "1"

9. Output latch (TOL0) logic toggles high or low

10. Interrupt request is generated

11. TCNT0 is cleared to 00H and counting resumes

12. Programmable timer/counter operation continues until TMOD0.2 is cleared to "0".

11-12

KS57C5404/P5404

TIMERS and TIMER/COUNTER

TC0 EVENT COUNTER FUNCTION

Timer/counter 0 can be used to monitor or detect system 'events' by using the external clock input at the TCL0 pin

(I/O port 1.0) as the counter source. The TC0 mode register is used to specify rising or falling edge detection for

incoming clock signals. The counter register TCNT0 is incremented each time the selected state transition of the

external clock signal occurs. To activate the TC0 event counter function,

— Set TMOD0.2 to "1" to enable TC0

— Clear TMOD0.6 to "0" to select the external clock source at the TCL0 pin

— Select TCL0 edge detection for rising or falling signal edges by loading appropriate values to TMOD0.5 and

TMOD0.4.

— P1.0 must be set to input mode.

Table 11-6. TMOD0 Settings for TCL0 Edge Detection

TMOD0.5

TMOD0.4

TCL0 Edge Detection

Rising edges

0

1

Falling edges

With the exception of the different TMOD0.4–TMOD0.6 settings, the operation sequence for TC's event counter

function is identical to its programmable counter/timer function.

11-13

TIMERS and TIMER/COUNTER

KS57C5404/P5404

TC0 CLOCK FREQUENCY OUTPUT

Using the timer/counter, you can output a modifiable clock frequency to the TC0 clock output pin, TCLO0. To

select the clock frequency, you should load appropriate values to the TC0 mode register, TMOD0. The clock

interval is determined by loading the desired reference value into the reference register TREF0. Then, to enable

the output to the TCLO0 pin at I/O port 1.1, the following conditions must be met:

— TC0 output enable flag TOE0 must be set to "1"

— I/O mode flag for P1.1 (PM1.1) must be set to output mode ("1")

— Output latch value for P1.1 must be set to "0"

In summary, the operational sequence required to output a TC0-generated clock signal to the TCLO0 pin is as

follows:

1. Load your reference value to TREF0

2. Set the clock frequency in TMOD0

3. Initiate TC0 clock output to TCLO0 (TMOD0.2 = "1")

4. Set port 1.1 mode flag (PM1.1) to "1"

5. Set P1.1 output latch to "0"

6. Set TOE0 flag to "1"

Each time the contents of TCNT0 and TREF0 coincide and an interrupt request is generated, the state of the

output latch TOL0 is inverted and the TC0-generated clock signal is output to the TCLO0 pin.

+

PROGRAMMING TIP — TC0 Signal Output to the TCLO0 Pin

Output a 30 ms pulse width signal to the TCLO0 pin:

BITS

SMB

LD

BITR

BITS

EMB

15

EA,#79H

TREF0,EA

EA,#4CH

TMOD0,EA

EA,#20H

PMG1,EA

P1.1

;

P1.1 ¬ Output mode

P1.1 clear

TOE0

11-14

KS57C5404/P5404

TIMERS and TIMER/COUNTER

TC0 EXTERNAL INPUT SIGNAL DIVIDER

By selecting an external clock source and loading a reference value into the TC0 reference register, TREF0, you

can divide the incoming clock signal by the TREF0 value and then output this modified clock frequency to the

TCLO0 pin. The sequence of operations used to divide external clock input may be summarized as follows:

1. Load a signal divider value to the TREF0 buffer register

2. Clear TMOD0.6 to "0" to enable external clock input at the TCL0 pin

3. Set TMOD0.5 and TMOD0.4 to desired TCL0 signal edge detection

4. Set port 1.1 mode flag (PM1.1) to output ("1")

5. Set P1.1 output latch to "0"

6. Set TOE0 flag to "1" to enable output of the divided frequency

Divided clock signals are then output to the TCLO0 pin.

+

PROGRAMMING TIP — External TCL0 Clock Output to the TCLO0 Pin

Output external TCL0 clock pulse to the TCLO0 pin (divide by four):

EXTERNAL (TCL0)

CLOCK PULSE

TCLO0

OUTPUT

PULSE

BITS

SMB

LD

BITR

BITS

EMB

15

EA,#01H

TREF0,EA

EA,#0CH

TMOD0,EA

EA,#20H

PMG1,EA

P1.1

;

P1.1 ¬ Output mode

P1.1 clear

TOE0

11-15

TIMERS and TIMER/COUNTER

KS57C5404/P5404

TC0 MODE REGISTER (TMOD0)

TMOD0 is the 8-bit mode control register for the timer/counter. It is located at the RAM addresses F90H–F91H

and is addressable by 8-bit write instructions. One bit, TMOD0.3, is also 1-bit writeable. A

bits to logic zero and disables TC0 operations.

clears all TMOD0

F90H

F91H

TMOD0.3

"0"

TMOD0.2

TMOD0.6

"0"

TMOD0.5

TMOD0.4

TMOD0.2 is the enable/disable bit for the timer/counter. When TMOD0.3 is set to "1", the contents of TCNT0,

IRQT0, and TOL0 are cleared, counting starts from 00H, and TMOD0.3 is automatically reset to "0" for normal

TC0 operation. When TC0 operation stops (TMOD0.2 = "0"), the contents of the TC0 counter register, TCNT0, are

retained until TC0 is re-enabled.

Use TMOD0.6, TMOD0.5, and TMOD0.4 bit settings together to select the TC0 clock source. This selection

involves two variables:

— Synchronization of timer/counter operations with either the rising edge or the falling edge of the clock signal

input at the TCL0 pin, and

— Selection of one of four frequencies, based on the division of the incoming system clock frequency, for use in

internal TC0 operation.

Table 11-7. TC0 Mode Register (TMOD0) Organization

Bit Name

TMOD0.7

TMOD0.6

TMOD0.5

TMOD0.4

TMOD0.3

Setting

Resulting TC0 Function

MSB value always logic zero

Address

0

F91H

0,1

Specify input clock edge and internal frequency

1

Clear TCNT0, IRQT0, and TOL0 and resume counting immedi-

ately (This bit is automatically cleared to logic zero immediately

after counting resumes.)

F90H

TMOD0.2

0

1

0

Disable timer/counter; retain TCNT0 contents

Enable timer/counter

TMOD0.1

TMOD0.0

Value always logic zero

LSB value always logic zero

11-16

KS57C5404/P5404

TIMERS and TIMER/COUNTER

Table 11-8. TMOD0.6, TMOD0.5, and TMOD0.4 Bit Settings

TMOD0.6

TMOD0.5

TMOD0.4

Resulting Counter Source and Clock Frequency

External clock input (TCL0) on rising edges

0

1

0

1

0

1

0

1

0

External clock input (TCL0) on falling edges

10

fx/2 = 4.09 kHz

6

fx/2 = 65.5 kHz

4

fx/2 = 262 kHz

1

fx = 4.19 MHz

NOTE: 'fx' = system clock

+

PROGRAMMING TIP — Restarting TC0 Counting Operation

1. Set TC0 timer interval to 4.09 kHz:

BITS

SMB

LD

EMB

15

EA,#4CH

TMOD0,EA

LD

EI

BITS

IET0

2. Clear TCNT0, IRQT0, and TOL0 and restart TC0 counting operation:

BITS

SMB

BITS

EMB

15

TMOD0.3

11-17

TIMERS and TIMER/COUNTER

KS57C5404/P5404

TC0 COUNTER REGISTER (TCNT0)

The 8-bit counter register for the timer/counter, TCNT0, is mapped to the RAM addresses F94H–F95H. It is read-

only and can be addressed by 8-bit RAM control instructions. A

(00H).

sets all TCNT0 register values to logic zero

Whenever TMOD0.3 are enabled, TCNT0 is cleared to logic zero and counting begins. The TCNT0 register value

is incremented each time an incoming clock signal that matches the signal edge and frequency setting of the

TMOD0 register (specifically, TMOD0.6, TMOD0.5, and TMOD0.4) is detected.

Each time TCNT0 is incremented, the new value is compared to the reference value stored in the TC0 reference

register, TREF0. When TCNT0 = TREF0, an overflow occurs in the TCNT0 register, the interrupt request flag,

IRQT0, is set to logic one, and an interrupt request is generated to indicate that the specified timer/counter interval

has elapsed.

Count

Clock

TREF0

TCNT0

Reference Value = n

0

1

2

n-1

n

0

1

2

n-1

n

0

1

2

3

Match

TOL0

INTERVAL TIME

Timer Start

Instruction

IRQT0 Set

Figure 11-3. TC0 Timing Diagram

11-18

KS57C5404/P5404

TIMERS and TIMER/COUNTER

TC0 REFERENCE REGISTER (TREF0)

The TC0 reference register TREF0 is an 8-bit write-only register that is mapped to the RAM locations F96H and

F97H. It is addressable by 8-bit RAM control instructions. A initializes the TREF0 value to 'FFH'.

TREF0 is used to store a reference value to be compared to the incrementing TCNT0 register in order to identify

an elapsed time interval. Reference values will differ depending upon the specific function that TC0 is being used

to perform — as a programmable timer/counter, event counter, clock signal divider, or arbitrary frequency output

source.

During timer/counter operation, the value loaded into the reference register is compared to the TCNT0 value.

When TCNT0 = TREF0, the TC0 output latch (TOL0) is inverted and an interrupt request is generated to signal

the interval or event.

The TREF0 value, together with the TMOD0 clock frequency selection, determines the specific TC0 timer interval.

Use the following formula to calculate the correct value to load to the TREF0 reference register:

1

TC0 timer interval = (TREF0 value + 1)

´

TMOD0 frequency setting

( assuming a TREF0 value ¹ 0 )

TC0 OUTPUT ENABLE FLAG (TOE0)

The 8-bit timer/counter 0 output enable flag TOE0 controls output from timer/counter 0 to the TCLO0 pin. TOE0 is

mapped to RAM location F92H.2 and is addressable by 1/4-bit read or write instructions.

Bit 3

0

Bit 2

Bit 1

0

Bit 0

0

F92H

TOE0

When you set the TOE0 flag to "1", the contents of TOL0 can be output to the TCLO0 pin. Whenever a

occurs, TOE0 is automatically set to logic zero, disabling all TC0 output. Even when the TOE0 flag is disabled, the

timer/counter can continue to output an internally-generated clock frequency, via TOL0.

TC0 OUTPUT LATCH (TOL0)

TOL0 is the output latch for the timer/counter. When the 8-bit comparator detects a correspondence between the

value of the counter register TCNT0 and the reference value stored in the TREF0 buffer, the TOL0 value is

inverted — the latch toggles high-to-low or low-to-high.

Whenever the state of TOL0 is switched, the TC0 signal is output. TC0 output may be directed to the TCLO0 pin

at P1.1.

Assuming TC0 is enabled, when bit 3 of the TMOD0 register is set to "1", the TOL0 latch is cleared to logic zero,

along with the counter register TCNT0 and the interrupt request flag, IRQT0, and counting resumes immediately.

When TC0 is disabled (TMOD0.2 = "0"), the contents of the TOL0 latch are retained and can be read, if

necessary.

11-19

TIMERS and TIMER/COUNTER

KS57C5404/P5404

+

PROGRAMMING TIP — Setting a TC0 Timer Interval

To set a 30 ms timer interval for TC0, given fx = 4.19 MHz, follow these steps.

1. Select the timer/counter mode register with a maximum setup time of 62.5 ms (assume the TC0 counter

10

clock = fx/2 , and TREF0 is set to FFH):

2. Calculate the TREF0 value:

TREF0 value + 1

30 ms =

4.09 kHz

30 ms

244 µs

TREF0 + 1 =

= 122.9 = 7AH

TREF0 value = 7AH – 1 = 79H

3. Load the value 79H to the TREF0 register:

BITS

SMB

LD

EMB

15

EA,#79H

TREF0,EA

EA,#4CH

TMOD0,EA

LD

11-20

KS57C5404/P5404

BUZZER

12 BUZZER

OVERVIEW

Buzzer signal output is used to generate 4 specific frequency signals for buzzer sound. This function is controlled

by the buzzer mode register, BUMOD. By writing an appropriate value to the buzzer mode register, the signal can

be generated to the buzzer output pin. The signal frequency is selected by the buzzer mode register. The buzzer

output circuit has the following components:

— 4-bit buzzer mode register (BUZMOD)

— Buzzer output pin (BUZ)

FUNCTION DESCRIPTION

The buzzer signal output circuit can generate a steady 0.5 kHz, 1 kHz, 2 kHz, or 4 kHz signal to the BUZ pin. To

generate the buzzer frequency, load an appropriate value to the BUZMOD. Then the frequency selected

according to the value of BUZMOD is generated to BUZ pin to actuate an external buzzer sound when the buzzer

signal frequency is generated, P1.3 shared with BUZ pin must be assigned to output port and the value of output

latch must be logic zero.

P1.3 LATCH

PM1.3

BUZMOD.3

0

BUZ

4

BUZMOD.1

BUZMOD.0

MUX

fx/2¹³

fx/2¹⁰

(0.5 kHz)

(4 kHz)

fx/2¹²

fx/2¹¹

(1 kHz) (2 kHz)

Figure 12-1. Buzzer Circuit Diagram

12-1

BUZZER

KS57C5404/P5404

BUZZER MODE REGISTER (BUZMOD)

F88H

BUZMOD.3

“0”

BUZMOD.1 BUZMOD.0

Buzzer signal output is controlled by the buzzer mode register, BUZMOD. It is a 4-bit write-only addressable

register. Bit position BUZMOD. 3 enables or disables buzzer output operation. If BUZMOD.3 is set to logic one,

buzzer output operation. If BUZMOD.3 is set to logic one, buzzer output is enabled. BUZMOD.0–1 is used to

select the signal frequency for buzzer sound. A RESET clears all BUZMOD bits to logic zero and the buzzer

output operation is disabled.

Table 12-1. Buzzer Mode Register (BUZMOD) Organization

Bit Name

Values

Function

Disable buzzer (BUZ) signal output

Enable buzzer (BUZ) signal output

Always logic zero

Address

BUZMOD.3

0

1

F88H

BUZMOD.2

“0”

BUZMOD.1–.0

0

1

0

1

0

1

0.5 kHz buzzer (BUZ) signal output

1 kHz buzzer (BUZ) signal output

2 kHz buzzer (BUZ) signal output

4 kHz buzzer (BUZ) signal output

NOTE: System clock frequency (fx) is assumed to be 4.19 MHz.

+

PROGRAMMING TIP — BUZ Signal Output to the BUZ Pin

Output a 1 kHz buzzer signal to the BUZ pin

BITS

SMB

LD

BITR

LD

EMB

15

EA, #80H

PMG1, EA

P1.3

A, #9H

BUZMOD, A

;

P1.3 ¬ output mode

P1.3 clear

LD

;

1 kHz buzzer signal output

12-2

KS57C5404/P5404

D/A CONVERTER

13 D/A CONVERTER

OVERVIEW

The 8-bit D/A Converter (DAC) module uses successive approximation logic to convert 8-bit digital values to

1

equivalent analog levels between V_DD(1 –

) and V_SS.

256

This D/A Converter consists of R–2R array structure. The D/A Converter has the following components:

— R–2R array structure

— Digital-to-analog converter mode register (DAMOD)

— Digital-to-analog converter data register (DADATA)

— Digital-to-analog converter output pin (DAO)

FUNCTION DESCRIPTION

To initiate a digital-to-analog conversion procedure, you should set the digital-to-analog converter enable bit

(DAMOD.0).

The DAMOD register is an 1/4-bit write-only register located at the RAM address FD5H. You should write the

digital value calculated to digital-to-analog converter data register (DADATA).

The DADATA register is an 8-bit write-only register located at the RAM address FD6H–FD7H.

NOTE

If the chip enters to power-down mode, STOP or IDLE, in conversion process, there will be current path in

D/A Converter block. So. It is necessary to cut off the current path before the instruction execution enters

power-down mode.

13-1

D/A CONVERTER

KS57C5404/P5404

Data Bus

DADATA

.0

.1

.2

.3

.4

.5

.6

.7

2R

R

2R

R

2R

R

2R

R

2R

R

DAO

2R

DAMOD.0

Figure 13-1. DAC Circuit Diagram

D/A CONVERTER MODE REGISTER (DAMOD)

The Digital-to-Analog Converter (DAC) mode register, DAMOD is a 1/4-bit write-only register located at the RAM

address FD5H. DAMOD controls enabling or disabling DAC. DAMOD values are set to logic “0H” after a RESET

and this value disables DAC.

DAMOD – Digital-to-Analog mode register

FD5H

Bit

3

"0"

0

2

"0"

0

1

"0"

0

.0

0

Identifier

RESET Value

Read/Write

W

DAMOD.0

Digital-to-Analog Converter Enable/Disable control

0

1

Disable Digital-to-Analog Converter

Enable Digital-to-Analog Converter

13-2

KS57C5404/P5404

D/A CONVERTER

D/A CONVERTER DATA REGISTER (DADATA)

The DAC DATA register, DATATA, is an 8-bit write-only register located at the RAM address, FD6H–FD7H.

DADATA specifies the digital data to generate analog voltage. A RESET initializes the DADATA value to “00H”.

The D/A Converter output value, V_DAO, is calculated by the following formula.

n

256

V_DAO= V_DD

´

(n = 0–255, DADATA value)

Table 13-1. DADATA Setting to Generate Analog Voltage

V

DADATA.7 DADATA.6 DADATA.5 DADATA.4 DADATA.3 DADATA.2 DADATA.1 DADATA.0

DAO

0

1

0

V_DD/2¹

V_DD/2²

V_DD/2³

V_DD/2⁴

V_DD/2⁵

V_DD/2⁶

V_DD/2⁷

V_DD/2⁸

0

1

0

1

0

1

0

1

0

1

0

1

0

1

NOTE: These are the values determined by setting just one-bit of DADATA.0–DADATA.7. Other values of DAO can be

obtained with superimposition.

13-3

D/A CONVERTER

KS57C5404/P5404

NOTES

13-4

KS57C5404/P5404

ELECTRICAL DATA

14 ELECTRICAL DATA

OVERVIEW

In this section, KS57C5404 electrical characteristics are presented in tables and graphs. The information is

arranged in the following order:

Standard Electrical Characteristics

— Absolute maximum ratings

— D.C. electrical characteristics

— Main system clock oscillator characteristics

— Subsystem clock oscillator characteristics

— I/O capacitance

— A.C. electrical characteristics

— Operating voltage range

Miscellaneous Timing Waveforms

— A.C timing measurement point

— Clock timing measurement at X

in

— Clock timing measurement at XT

— TCL timing

in

— Input timing for RESET

— Input timing for external interrupts

— Serial data transfer timing

Stop Mode Characteristics and Timing Waveforms

— RAM data retention supply voltage in stop mode

— Stop mode release timing when initiated by RESET

— Stop mode release timing when initiated by an interrupt request

14-1

ELECTRICAL DATA

KS57C5404/P5404

Table 14-1. Absolute Maximum Ratings

°

(T = 25 C)

A

Parameter

Symbol

Conditions

Rating

Units

V_DD

V_I

Supply Voltage

Input Voltage

–

– 0.3 to + 6.5

V

– 0.3 to V_DD+ 0.3

– 5

All I/O ports

V

V_O

I_OH

Output Voltage

Output Current High

–

One I/O port active

mA

All I/O ports active

One I/O port active

– 35

I_OL

Output Current Low

+ 30 (peak)

mA

+ 15 ^(note)

+ 100 (peak)

+ 60 ^(note)

All I/O ports active

°

T_A

Operating Temperature

Storage Temperature

–

– 40 to + 85

– 65 to + 150

C

°

C

T_stg

NOTE: The values for output current low (I ) are calculated as peak value ´ Duty .

OL

Table 14-2. D.C. Electrical Characteristics

°

(T = – 40 C to + 85 C, V

DD

= 1.8 V to 5.5 V)

A

Parameter

Symbol

Conditions

Min

Typ

Max

Units

V_IH1

All input pins except V_IH2–V_IH3

0.7 V_DD

V_DD

Input High

Voltage

–

V

V_IH2

V_IH3

V_IL1

0.8 V_DD

V_DD– 0.1

–

V_DD

P0 and

–

X_INand X_OUT

All input pins except V_IH2–V_IH3

0.3 V_DD

V

Input Low

Voltage

V_IL2

V_IL3

0.2 V_DD

0.1

P0 and

X_INand X_OUT

14-2

KS57C5404/P5404

ELECTRICAL DATA

Table 14-2. D.C. Electrical Characteristics (Continued)

°

(T_A= – 40 C to + 85 C, V_DD= 1.8 V to 5.5 V)

Parameter

Symbol

Conditions

Min

Typ

Max

Units

V_OH

V

_DD= 4.5 V to 5.5 V

V_DD– 1.0

Output High

Voltage

–

V

I_OH= – 1 mA

V_OL1

V_OL2

I_LIH1

V_DD= 4.5 V to 5.5 V

–

2

V

Output Low

Voltage

I_OL= 15 mA

Ports 4, 5

V_DD= 1.8 V to 5.5 V

0.4

2

I_OL= 1.6 mA

V_DD= 4.5V to 5.5 V

I

= 4 mA

OL

All out ports except ports 4, 5

V_DD= 1.8 V to 5.5 V

0.6

3

I_OL= 1.6 mA

V_IN= V_DD

All input pins except X_INand X_OUT

Input High

Leakage

Current

–

mA

I_LIH2

V_IN= V_DD

X_INand X_OUT

20

I_LIL1

V

IN

= 0 V

Input Low

Leakage

Current

– 3

All input pins except X_IN, X_OUT

and

I_LIL2

V_IN= 0 V

X_INand X_OUT

– 20

3

I_LOH

V_O= V_DD

All output pins

–

Output High

Leakage

Current

mA

kW

I_LOL

V_O= 0 V

Output Low

Leakage

Current

– 3

All output pins

R_L1

V_DD= 5 V; V = 0 V

I

Pull-up

25

45

100

Resistor

except

V_DD= 3 V

50

90

200

400

800

R_L2

V_DD= 5 V; V = 0 V; RESET

100

200

220

450

I

V_DD= 3 V

14-3

ELECTRICAL DATA

KS57C5404/P5404

Table 14-2. D.C. Electrical Characteristics (Concluded)

°

(T_A= – 40 C to + 85 C, V_DD= 1.8 V to 5.5 V)

Parameter

Symbol

Conditions

Min

Typ

Max

Units

mA

I_DD1

Supply

6.0MHz

–

3.4

10.0

Run mode; V_DD= 5.0 V ± 10%

Current ⁽¹⁾

(DAC on) Crystal oscillator; C1 = C2 = 22pF

4.19MHz

6.0MHz

2.7

2.3

8.0

mA

I_DD2

–

Run mode; V_DD= 5.0 V ± 10%

(DAC off) Crystal oscillator; C1 = C2 = 22pF

4.19MHz

6.0MHz

1.7

1.1

5.5

4.0

V_DD= 3 V ± 10%

4.19MHz

6.0MHz

0.8

0.7

3.0

2.5

I_DD3

Idle mode; V_DD= 5.0 V ± 10%

Crystal oscillator; C1 = C2 = 22pF

4.19MHz

6.0MHz

0.5

0.3

1.8

1.5

V_DD= 3 V ± 10%

4.19MHz

0.2

1.0

3.0

I_DD4

Stop mode; V_DD= 5.0 V ± 10%

Stop mode; V_DD= 3.0 V ± 10%

mA

0.1

2.0

NOTES:

1. D.C. electrical values for supply current (I

to I ) do not include the current drawn through internal pull-up

DD3

DD1

resistors.

2.

I

typical values are measured when DADATA register value is 055H.

DD1

Main Osc. Freq.

6 MHz

CPU CLOCK

1.5 MHz

0.75 MHz

3 MHz

15.625 kHz

400 kHz

7

1.8

1

2

^2.73

4

5

6

SUPPLY VOLTAGE (V)

CPU CLOCK = 1/n x oscillator frequency (n = 4, 8 or 64)

Figure 14-1. Standard Operating Voltage Range

14-4

KS57C5404/P5404

ELECTRICAL DATA

Table 14-3. Oscillators Characteristics

°

(T_A= – 40 C + 85 C, V_DD= 1.8 V to 5.5 V)

Oscillator

Parameter

Test Condition

Min Typ Max Units

Clock

Configuration

Oscillation frequency ⁽¹⁾

V_DD= 2.7 V to 5.5 V

Ceramic

Oscillator

0.4

–

6.0

MHz

Xin

Xout

C1

C2

V_DD= 1.8 V to 5.5 V

V_DD= 3.0 V

0.4

–

3

4

Stabilization time ⁽²⁾

ms

Oscillation frequency ⁽¹⁾

V_DD= 2.7 V to 5.5 V

Crystal

0.4

6.0

MHz

Xin

Xout

Oscillator

C1

C2

V_DD= 1.8 V to 5.5 V

V_DD= 3.0 V

0.4

–

3

Stabilization time ⁽²⁾

10

6.0

ms

X_INinput frequency ⁽¹⁾

V_DD= 2.7 V to 5.5 V

External

Clock

0.4

MHz

Xin

Xout

V_DD= 1.8 V to 5.5 V

–

0.4

–

3

X_INinput high and low

83.3

ns

125

0

level width (t_XH, t_XL

)

NOTES:

1. Oscillation frequency and X input frequency data are for oscillator characteristics only.

IN

2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is

terminated.

14-5

ELECTRICAL DATA

KS57C5404/P5404

Table 14-4. Recommended Oscillator Constants

°

(T = – 40 C + 85 C, V_DD= 1.8 V to 5.5 V)

A

Manufacturer

Series

Number ⁽¹⁾

Frequency Range

Load Cap (pF)

Oscillator Voltage

Range (V)

Remarks

C1

33

(2)

C2

33

(2)

MIN

2.0

MAX

5.5

TDK

3.58 MHz–6.0 MHz

Leaded Type

FCR” ðÿM5

2.0

5.5

On-chip C

FCR” ðÿMC5

Leaded Type

(3)

3.58 MHz–6.0 MHz

2.0

5.5

On-chip C

SMD Type

CCR” ðÿMC3

NOTES:

1. Please specify normal oscillator frequency.

2. On-chip C: 30pF built in.

3. On-chip C: 38pF built in.

Table 14-5. Input/Output Capacitance

°

(T = 25 C, V_DD= 0 V )

A

Parameter

Input

Capacitance

Symbol

Condition

Min

Typ

Max

15

Units

C_IN

–

pF

f = 1 MHz; Unmeasured pins

are returned to V_SS

C_OUT

C_IO

Output

Capacitance

15

pF

I/O Capacitance

Table 14-6. D/A Converter Electrical Characteristics

(T_A= – 40 C to + 85 C, V_DD= 3.5 V to 5.5 V, V_SS= 0 V)

°

Parameter

Resolution

Symbol

Condition

Min

–

Typ

–

Max

Units

bits

–

8

3

1

5

Absolute Accuracy

Differential Linearity Error

Setup Time

– 3

– 1

–

LSB

ms

DLE

t_su

–

R_O

Output Resistance

4.5

5

5.5

KW

14-6

KS57C5404/P5404

ELECTRICAL DATA

Table 14-7. A.C. Electrical Characteristics

°

(T = – 40 C to + 85 C, V_DD= 1.8 V to 5.5 V)

A

Parameter

Symbol

Conditions

Min

Typ

Max

Units

t_CY

V_DD= 2.7 V to 5.5 V

Instruction Cycle

Time

0.67

–

64

ms

V_DD= 1.8 V to 5.5 V

_DD= 2.7 V to 5.5 V

1.33

0

f_TI

V

–

1.5

MHz

TCL0 Input

Frequency

V_DD= 1.8 V to 5.5 V

_DD= 2.7 V to 5.5 V

1

–

MHz

t

_TIH,t_TIL

V

TCL0 Input High,

Low Width

0.48

ms

V_DD= 1.8 V to 5.5 V

INT0, INT1, KS0–KS1

1.8

10

t_{INTH, INTL}

t

Interrupt Input

High, Low Width

–

ms

t_RSL

RESET Input Low

Input

–

10

Width

Table 14-8. RAM Data Retention Supply Voltage in Stop Mode

°

(T_A= – 40 C to + 85 C)

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

V_DDDR

Data retention supply voltage

–

1.8

–

5.5

10

V

I_DDDR

V

DDDR

= 1.8 V

Data retention supply current

–

0.1

mA

t_SREL

t_WAIT

Release signal set time

–

0

–

ms

2¹⁷/fx

Oscillator stabilization wait

time ⁽¹⁾

Released by RESET

ms

(2)

Released by interrupt

–

ms

NOTES:

1. During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator

start-up.

2. Use the basic timer mode register (BMOD) interval timer to delay the execution of CPU instructions during the wait time.

14-7

ELECTRICAL DATA

KS57C5404/P5404

TIMING WAVEFORMS

INTERNAL RESET

OPERATION

IDLE MODE

STOP MODE

OPERATING

MODE

DATA RETENTION MODE

V

DD

V_DDDR

EXECUTION OF

STOP INSTRUCTION

RESET

t_WAIT

t_SREL

Figure 14-2. Stop Mode Release Timing When Initiated by RESET

IDLE MODE

NORMAL

STOP MODE

OPERATING

MODE

DATA RETENTION

V

DD

V_DDDR

t_SREL

EXECUTION OF

STOP INSTRUCTION

t_WAIT

POWER-DOWN MODE TERMINATING

(INTERRUPT REQUEST)

Figure 14-3. Stop Mode Release Timing When Initiated by Interrupt Request

14-8

KS57C5404/P5404

ELECTRICAL DATA

0.8 V

0.2 V

0.8 V

0.2 V

DD

MEASUREMENT

POINTS

DD

Figure 14-4. A.C. Timing Measurement Points (Except for X_IN)

1 / f

x

t

XH

XL

X

IN

V

– 0.1 V

DD

0.1 V

Figure 14-5. Clock Timing Measurement at X_IN

14-9

ELECTRICAL DATA

KS57C5404/P5404

1 / f

TI

t

TIH

TIL

TCL

0.7 V

0.3 V

DD

Figure 14-6. TCL Timing

t

RSL

RESET

0.2 V

DD

Figure 14-7. Input Timing for RESET Signal

t

INTL

INTH

INT0, 1

KS0 to KS1

0.8 V

0.2 V

DD

Figure 14-8. Input Timing for External Interrupts

14-10

KS57C5404/P5404

MECHANICAL DATA

15 MECHANICAL DATA

This section contains the following information about the device package:

— Package dimensions in millimeters

— Pad diagram

— Pad/pin coordinate data table

30

16

0 ~ 15

°

30-SDIP-400

#1

15

27.48 ± 0.2

(1.30)

1.778

0.56 ± 0.1

1.12 ± 0.1

NOTE: Typical dimensions are in millimeters.

Figure 15-1. 30-SDIP-400 Package Dimensions

15–1

MECHANICAL DATA

KS57C5404/P5404

NOTES

15–2

KS57C5404/P5404

KS57P5404 OTP

16 KS57P5404 OTP

OVERVIEW

The KS57P5404 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the

KS57C5404 microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by

serial data format.

The KS57P5404 is fully compatible with the KS57C5404, both in function and in pin configuration. Because of its

simple programming requirements, the KS57P5404 is ideal for use as an evaluation chip for the KS57C5404.

V

/V

X

OUT

X

V

/V

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

16

15

14

13

SS SS

DD DD

P5.3/SCLK

P5.2/SDAT

P5.1

P5.0

P4.3

P4.2

P4.1

P4.0

P2.0

IN

V

/TEST

PP

P0.0/INT0

DAO

P0.1/INT1

RESET /RESET

P0.2/KS0

P0.3/KS1

P1.0/TCL0

P1.1/TCLO0

9

10

11

12

P1.3/BUZ

P1.2/CLO

Figure 16-1. KS57P5404 Pin Assignments (24 SOP-375, 24 SDIP-300 Package)

16-1

KS57P5404 OTP

KS57C5404/P5404

Table 16-1. Descriptions of Pins Used to Read/Write the EPROM

During Programming

Main Chip

Pin Name

P5.2

Pin Name

Pin No.

I/O

Function

SDAT

22

I/O

Serial data pin. Output port when reading and input

port when writing. Can be assigned as a Input /

push-pull output port.

P5.3

SCLK

TEST

23

4

I/O

I

Serial clock pin. Input only pin.

TEST

Power supply pin for EPROM cell writing (indicates

that OTP enters into the writing mode). When 12.5

V is applied, OTP is in writing mode and when 5 V is

applied, OTP is in reading mode. (Option)

Hold GND when OTP is operating.

RESET

8

I

Chip initialization

V

/V

V

/V

24/1

–

Logic power supply pin. VDD should be tied to +5 V

during programming.

DD SS

NOTE: ( ) means the 32-SOP OTP pin number.

Table 16-2. Comparison of KS57P5404 and KS57C5404 Features

Characteristic KS57P5404 KS57C5404

4 K-byte EPROM

1.8 V (3 MHz) to 5.5 V

= 5 V, V (TEST) = 12.5 V

Program Memory

4 K-byte mask ROM

Operating Voltage (V

)

1.8 V (3 MHz) to 5.5 V

–

DD

OTP Programming Mode

V

DD

PP

Pin Configuration

24 SOP, 24 SDIP

EPROM Programmability

User Program one time

Programmed at the factory

OPERATING MODE CHARACTERISTICS

When 12.5 V is supplied to the V (TEST) pin of the KS57P5404, the EPROM programming mode is entered.

PP

The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in

Table 16-3 below.

Table 16-3. Operating Mode Selection Criteria

V

DD

R/W

MODE

VPP

(TEST)

REG/

MEM

ADDRESS

(A15-A0)

5 V

0

1

0000H

0E3FH

1

0

1

0

EPROM read

12.5 V

EPROM program

EPROM verify

EPROM read protection

NOTE: "0" means Low level; "1" means High level.

16-2

KS57C5404/P5404

KS57P5404 OTP

OTP ELECTRICAL DATA

Table 16-4. Absolute Maximum Ratings

°

(T = 25 C)

A

Parameter

Symbol

Conditions

Rating

Units

V_DD

V_I

Supply Voltage

Input Voltage

–

– 0.3 to + 6.5

V

– 0.3 to V_DD+ 0.3

All I/O ports

V

V_O

I_OH

Output Voltage

Output Current High

–

One I/O port active

All I/O ports active

One I/O port active

– 5

– 35

mA

I_OL

Output Current Low

+ 30 (peak)

mA

+ 15 ^(note)

+ 100 (peak)

+ 60 ^(note)

All I/O ports active

°

T_A

Operating Temperature

Storage Temperature

–

– 40 to + 85

– 65 to + 150

C

°

C

T_stg

NOTE: The values for output current low (I ) are calculated as peak value ´ Duty .

OL

Table 16-5. D.C. Electrical Characteristics

°

(T = – 40 C to + 85 C, V

DD

= 1.8 V to 5.5 V)

Conditions

A

Parameter

Symbol

Min

Typ

Max

Units

V_IH1

All input pins except V_IH2–V_IH3

0.7 V_DD

V_DD

Input High

Voltage

–

V

V_IH2

V_IH3

V_IL1

0.8 V_DD

V_DD– 0.1

–

V_DD

P0 and

–

X_INand X_OUT

All input pins except V_IH2–V_IH3

0.3 V_DD

Input Low

Voltage

V

V_IL2

V_IL3

0.2 V_DD

0.1

P0 and

X_INand X_OUT

16-3

KS57P5404 OTP

KS57C5404/P5404

Table 16-5. D.C. Electrical Characteristics (Continued)

°

(T_A= – 40 C to + 85 C, V_DD= 1.8 V to 5.5 V)

Parameter

Symbol

Conditions

Min

Typ

Max

Units

V_OH

V

_DD= 4.5 V to 5.5 V

V_DD– 1.0

–

V

Output High

Voltage

I_OH= – 1 mA

V_OL1

V_OL2

I_LIH1

V_DD= 4.5 V to 5.5 V

Output Low

Voltage

–

2

V

I_OL= 15 mA

Ports 4, 5

V_DD= 1.8 V to 5.5 V

0.4

2

I_OL= 1.6 mA

V_DD= 4.5V to 5.5 V

I

= 4 mA

OL

All out ports except ports 4, 5

V_DD= 1.8 V to 5.5 V

0.6

3

I_OL= 1.6 mA

V_IN= V_DD

All input pins except X_INand X_OUT

Input High

Leakage

Current

–

mA

I_LIH2

V_IN= V_DD

X_INand X_OUT

20

I_LIL1

V

IN

= 0 V

Input Low

Leakage

Current

– 3

All input pins except X_IN, X_OUT

and

I_LIL2

V_IN= 0 V

X_INand X_OUT

– 20

3

I_LOH

V_O= V_DD

All output pins

Output High

Leakage

Current

–

mA

kW

I_LOL

V_O= 0 V

– 3

Output Low

Leakage

Current

All output pins

R_L1

V_DD= 5 V; V = 0 V

I

Pull-up

25

50

100

Resistor

except

V_DD= 3 V

50

100

250

500

200

400

800

R_L2

V_DD= 5 V; V = 0 V; RESET

100

200

I

V_DD= 3 V

16-4

KS57C5404/P5404

KS57P5404 OTP

Table 16-5. D.C. Electrical Characteristics (Concluded)

°

(T_A= – 40 C to + 85 C, V_DD= 1.8 V to 5.5 V)

Parameter

Symbol

Conditions

Min

Typ

Max

Units

mA

I_DD1

Supply

–

6.0MHz

3.4

10.0

Run mode; V_DD= 5.0 V ± 10%

Current ⁽¹⁾

(DAC on) Crystal oscillator; C1 = C2 = 22pF

4.19MHz

6.0MHz

2.7

2.3

8.0

mA

I_DD2

–

Run mode; V_DD= 5.0 V ± 10%

(DAC off) Crystal oscillator; C1 = C2 = 22pF

4.19MHz

6.0MHz

1.7

1.1

5.5

4.0

V_DD= 3 V ± 10%

4.19MHz

6.0MHz

0.8

0.7

3.0

2.5

I_DD3

Idle mode; V_DD= 5.0 V ± 10%

Crystal oscillator; C1 = C2 = 22pF

4.19MHz

6.0MHz

0.5

0.3

1.8

1.5

V_DD= 3 V ± 10%

4.19MHz

0.2

1.0

3.0

I_DD4

Stop mode; V_DD= 5.0 V ± 10%

Stop mode; V_DD= 3.0 V ± 10%

mA

0.1

2.0

NOTES:

1. D.C. electrical values for supply current (I

to I

) do not include the current drawn through internal pull-up resistors.

typical values are measured when DADATA register value is 055H .

DD1

DD3

2.

I

DD1

Main Osc. Freq.

6 MHz

CPU CLOCK

1.5 MHz

0.75 MHz

3 MHz

15.625 kHz

400 kHz

7

1

^1.82

^2.73

4

5

6

SUPPLY VOLTAGE (V)

CPU CLOCK = 1/n x oscillator frequency (n = 4, 8 or 64)

Figure 16-2. Standard Operating Voltage Range

16-5

KS57P5404 OTP

KS57C5404/P5404

Table 16-6. Oscillators Characteristics

°

(T_A= – 40 C + 85 C, V_DD= 1.8 V to 5.5 V)

Oscillator

Clock

Parameter

Test Condition

Min

Typ Max Units

Configuration

Oscillation frequency ⁽¹⁾

V_DD= 2.7 V to 5.5 V

Ceramic

Oscillator

0.4

–

6.0

MHz

Xin

Xout

C1

C2

V_DD= 1.8 V to 5.5 V

V_DD= 3.0 V

0.4

–

3

4

Stabilization time ⁽²⁾

ms

Oscillation frequency ⁽¹⁾

V_DD= 2.7 V to 5.5 V

0.4

6.0

MHz

Crystal

Oscillator

Xin

Xout

C1

C2

V_DD= 1.8 V to 5.5 V

V_DD= 3.0 V

0.4

–

3

Stabilization time ⁽²⁾

10

6.0

ms

V_DD= 2.7 V to 5.5 V

External

Clock

0.4

MHz

Xin

Xout

X_INinput frequency ⁽¹⁾

V_DD= 1.8 V to 5.5 V

–

0.4

–

3

X_INinput high and low

83.3

1250

ns

level width (t_XH, t_XL

)

NOTES:

1. Oscillation frequency and X input frequency data are for oscillator characteristics only.

IN

2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is

terminated.

16-6

KS57C5404/P5404

KS57P5404 OTP

Table 16-7. Input/Output Capacitance

°

(T = 25 C, V_DD= 0 V )

A

Parameter

Input

Capacitance

Symbol

Condition

Min

Typ

Max

Units

C_IN

–

15

pF

f = 1 MHz; Unmeasured pins

are returned to V_SS

C_OUT

C_IO

15

pF

Output

Capacitance

I/O Capacitance

Table 16-8. Comparator Electrical Characteristics

(T_A= – 40 C to + 85 C, V_DD= 3.5 V to 5.5 V, V_SS= 0 V)

°

Parameter

Resolution

Symbol

Condition

Min

–

Typ

–

Max

Units

bits

–

8

3

1

5

Absolute Accuracy

Differential Linearity Error

Setup Time

– 3

– 1

–

LSB

ms

DLE

t_su

–

R_O

Output Resistance

4.5

5

5.5

KW

Table 16-9. A.C. Electrical Characteristics

(T = – 40 C to + 85 C, V_DD= 1.8 V to 5.5 V)

°

A

Parameter

Symbol

Conditions

Min

Typ

Max

Units

t_CY

V_DD= 2.7 V to 5.5 V

0.67

–

64

Instruction Cycle

Time

ms

V_DD= 1.8 V to 5.5 V

V_DD= 2.7 V to 5.5 V

1.33

0

f_TI

TCL0 Input

Frequency

–

1.5

MHz

V_DD= 1.8 V to 5.5 V

V_DD= 2.7 V to 5.5 V

1

–

MHz

t_{TIH, TIL}

t

0.48

TCL0 Input High,

Low Width

ms

V_DD= 1.8 V to 5.5 V

INT0, INT1, KS0–KS1

1.8

10

t_{INTH, INTL}

t

Interrupt Input

High, Low Width

–

ms

t_RSL

RESET Input Low

Input

–

10

Width

16-7

KS57P5404 OTP

KS57C5404/P5404

Table 16-10. RAM Data Retention Supply Voltage in Stop Mode

°

(T_A= – 40 C to + 85 C)

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

V_DDDR

Data retention supply voltage

–

1.8

–

5.5

V

I_DDDR

V

DDDR

= 1.8 V

Data retention supply current

–

0.1

10

mA

t_SREL

t_WAIT

Release signal set time

–

0

–

ms

2¹⁷/fx

ms

Oscillator stabilization wait

time ⁽¹⁾

Released by

(2)

Released by interrupt

–

ms

NOTES:

1. During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator

start-up.

2. Use the basic timer mode register (BMOD) interval timer to delay the execution of CPU instructions during the wait time.

16-8

KS57C5404/P5404

DEVELOPMENT TOOLS

17 DEVELOPMENT TOOLS

OVERVIEW

Samsung provides a powerful and easy-to-use development support system in turnkey form. The development

support system is configured with a host system, debugging tools, and support software. For the host system, any

standard computer that operates with MS-DOS as its operating system can be used. One type of debugging tool

including hardware and software is provided: the sophisticated and powerful in-circuit emulator, SMDS2+, for

KS56, KS57, KS86, KS88 families of microcontrollers. The SMDS2+ is a new and improved version of SMDS2.

Samsung also offers support software that includes debugger, assembler, and a program for setting options.

SHINE

Samsung Host Interface for In-Circuit Emulator, SHINE, is a multi-window based debugger for SMDS2+. SHINE

provides pull-down and pop-up menus, mouse support, function/hot keys, and context-sensitive hyper-linked help.

It has an advanced, multiple-windowed user interface that emphasizes ease of use. Each window can be sized,

moved, scrolled, highlighted, added, or removed completely.

SAMA ASSEMBLER

The Samsung Arrangeable Microcontroller (SAM) Assembler, SAMA, is a universal assembler, and generates

object code in standard hexadecimal format. Assembled program code includes the object code that is used for

ROM data and required SMDS program control data. To assemble programs, SAMA requires a source file and an

auxiliary definition (DEF) file with device specific information.

SASM57

The SASM57 is a relocatable assembler for Samsung's KS57-series microcontrollers. The SASM57 takes a

source file containing assembly language statements and translates into a corresponding source code, object

code and comments. The SASM57 supports macros and conditional assembly. It runs on the MS-DOS operating

system. It produces the relocatable object code only, so the user should link object file. Object files can be linked

with other object files and loaded into memory.

HEX2ROM

HEX2ROM file generates ROM code from HEX file which has been produced by assembler. ROM code must be

needed to fabricate a microcontroller which has a mask ROM. When generating the ROM code (.OBJ file) by

HEX2ROM, the value 'FF' is filled into the unused ROM area upto the maximum ROM size of the target device

automatically.

17-1

DEVELOPMENT TOOLS

TARGET BOARDS

KS57C5404/P5404

Target boards are available for all KS57-series microcontrollers. All required target system cables and adapters

are included with the device-specific target board.

OTPs

One time programmable microcontroller (OTP) for the KS57C5404 microcontroller and OTP programmer (Gang)

are now available.

IBM-PC AT or Compatible

RS-232C

SMDS2+

TARGET

APPLICATION

SYSTEM

PROM/OTP WRITER UNIT

RAM BREAK/ DISPLAY UNIT

TRACE/TIMER UNIT

PROBE

ADAPTER

TB575404A

POD

SAM4 BASE UNIT

TARGET

BOARD

EVA

CHIP

POWER SUPPLY UNIT

Figure 17-1. SMDS Product Configuration (SMDS2+)

17-2

KS57C5404/P5404

DEVELOPMENT TOOLS

TB575404A TARGET BOARD

The TB575404A target board is used for the KS57C5404/P5404 microcontroller. It is supported by the SMDS2+

development system.

TB575404A

To User_Vcc

STOP

IDLE

OFF

ON

RESET

+

74HC11

25

J101

1

30

80 QFP

KS57E5400

EVA CHIP

1

24

1

15

16

SM1262A

Figure 17-2. TB575404A Target Board Configuration

17-3

DEVELOPMENT TOOLS

KS57C5404/P5404

Table 17-1. Power Selection Settings for TB575404A

Operating Mode

'To User_Vcc' Settings

Comments

The SMDS2/SMDS2+

supplies V to the target

To User_Vcc

CC

OFF

ON

board (evaluation chip) and

the target system.

TARGET

SYSTEM

TB575404A

V

CC

V

SS

V

CC

SMDS2/SMDS2+

TB575404A

The SMDS2/SMDS2+

To User_Vcc

supplies V

only to the

CC

OFF

ON

target board (evaluation chip).

The target system must have

its own power supply.

External

TARGET

SYSTEM

V

CC

V

SS

V

CC

SMDS2/SMDS2+

IDLE LED

This LED is ON when the evaluation chip (KS57E5400) is in idle mode.

STOP LED

This LED is ON when the evaluation chip (KS57E5400) is in stop mode.

17-4

KS57C5404/P5404

DEVELOPMENT TOOLS

J101

V

NC

1

2

3

4

5

6

7

8

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

V

DD

SS

P5.3

P5.2

P5.1

P5.0

P4.3

NC

V

SS

P0.0/INT0

DAO

P0.1/INT1

NC

P4.2

P4.1

P4.0

NC

P2.0

NC

RESET

9

P0.2/KS0

P0.3/KS1

P1.0/TCL0

P1.1/TCLO0

P1.2/CLO

P1.3/BUZ

10

11

12

13

14

15

NC

Figure 17-3. 30-Pin Connector for TB575404A

TARGET BOARD

TARGET SYSTEM

J101

30

1

24

Part Name: AP24SD-A

Order Code: SM6531

15 16

12 13

Figure 17-4. TB575404A Adapter Cable for 24-SDIP Package (KS57C5404/P5404)

17-5

DEVELOPMENT TOOLS

KS57C5404/P5404

NOTES

17-6


型号：	KS57C5404S-XX
厂家：	SAMSUNG
描述：	Microcontroller, 4-Bit, MROM, CMOS, PDSO24, 0.375 INCH, SOP-24 时钟微控制器光电二极管外围集成电路
文件：	总162页 (文件大小：1201K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

KS57C5404S-XX [SAMSUNG]

相关型号：

KS57C5532

KS57C5532N-XX

KS57C5532Q-XX

KS57C5616

KS57C7002IS

KS57C7002N

KS57C7002Q

KS57P0002ID

KS57P0002IS

KS57P0108MTPN

KS57P0108MTPQ

KS57P01504N