M381L6423BT0-CB0 [SAMSUNG]
Synchronous DRAM Module, 64MX72, 0.75ns, CMOS, DIMM-184;
| 型号： | M381L6423BT0-CB0 |
| 厂家： | 
SAMSUNG |
| 描述： | Synchronous DRAM Module, 64MX72, 0.75ns, CMOS, DIMM-184 动态存储器 |
| 文件： | 总14页 (文件大小：178K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
184pin Unbuffered DDR SDRAM MODULE
M381L6423BT0
512MB DDR SDRAM MODULE
(64Mx72(32Mx72*2 bank) based on 32Mx8 DDR SDRAM)
Unbuffered 184pin DIMM
72-bit ECC/Parity
Revision 0.5
April. 2000
Rev. 0.5 April. 2000
184pin Unbuffered DDR SDRAM MODULE
M381L6423BT0
Revision History
Revision 0 (Aug 1998)
1. First release for internal usage
Revision 0.1 (Aug. 1999)
1. Modified binning policy
From
To
-Z (133Mhz)
-8 (125Mhz)
-0 (100Mhz)
-Z (133Mhz/266Mbps@CL=2)
-Y (133Mhz/266Mbps@CL=2.5)
-0 (100Mhz/200Mbps@CL=2)
2.Modified the following AC spec values
From.
-Z
To.
-0
-Z
-Y
-0
tAC
+/- 0.75ns
+/- 0.75ns
+/- 1ns
+/- 0.75ns
+/- 0.75ns
+/- 0.5ns
0.5 ns
+/- 0.75ns
+/- 0.75ns
+/- 0.5ns
0.5 ns
+/- 0.8ns
+/- 0.8ns
+/- 0.6ns
0.6 ns
tDQSCK
tDQSQ
tDS/tDH
+/- 1ns
+/- 0.5ns
+/- 0.75ns
0.75 ns
0.5 ns
tCDLR*1
tPRE*1
tRPST*1
tHZQ*1
2.5tCK-tDQSS
1tCK +/- 0.75ns
tCK/2 +/- 0.75ns
tCK/2 +/- 0.75ns
2.5tCK-tDQSS
1tCK +/- 1ns
tCK/2 +/- 1ns
tCK/2 +/- 1ns
1tCK
1tCK
1tCK
0.9/1.1 tCK
0.4/0.6 tCK
+/- 0.75ns
0.9/1.1 tCK
0.4/0.6 tCK
+/- 0.75ns
0.9/1.1 tCK
0.4/0.6 tCK
+/-0.8ns
*1 : Changed description method for the same functionality. This means no difference from the previous version.
3.Changed the following AC parameter symbol From tDQCK To tAC
Output data access time from CK/CK
Revision 0.2 (Sept. 1999)
1. Changed the odering information.
1-1. Exclude KM mark.
From
To
KMM381...
M381.....
1-2. PCB Revison
From
To
- Blank: 1st generation
- 0: 1st gernation
- 1: 2nd generation
- 2: 3nd generation
M381L6423AT0
- A
- B
: 2nd generation
: 2nd generation
Example:KMM381L6423AT
1-3. Modified binning policy
From
To
- 0 (100Mhz/200Mbps@CL=2)
- Z (133Mhz/266Mbps@CL=2)
- Y (133Mhz/266Mbps@CL=2.5)
- A0 (100Mhz/200Mbps@CL=2)
- A2 (133Mhz/266Mbps@CL=2)
- B0 (133Mhz/266Mbps@CL=2.5)
Rev. 0.5 April. 2000
- 0 -
184pin Unbuffered DDR SDRAM MODULE
M381L6423BT0
Revision 0.3 (December. 1999)
1. Changed from 3.3V to 2.5V in VDDSPD power.
Revision 0.4 (April. 2000)
< Page 3 >
1. Changed from 1450mil to 1250mil in PCB height.
2. Changed pin 90 from WP to NC in pin configuration table.
3. Changed in pin configuration table as followings.
pin 16 : CK0 -> CK1
pin 17 : CK0 -> /CK1
pin 137 : CK1 -> CK0
pin 138 : CK1 -> /CK0
4. Removed WP in pin description.
< Page 4>
5. Changed bypassing to reflect common Vdd/Vddq plane.
6. Added A13, BA1.
7. Removed WP from serial PD.
< Page 5>
8. Changed Power & DC operating condition.
From
To
Parameter
I/O Reference voltage
Symbol
Min
Max
1.35
Min
0.49*VDDQ
VREF+0.15
-0.3
Max
0.51*VDDQ
VDDQ+0.3
VREF-0.15
2
VREF
VIH(DC)
VIL(DC)
II
1.15
Input logic high voltage
Input logic low voltage
Input leakage current
Output High Current (V
VREF+0.18
-0.3
VDDQ+0.3
VREF-0.18
5
-5
-2
= 1.95V)
= 0.35V)
IOH
-15.2
15.2
-16.8
OUT
OUT
Output Low Current (V
IOL
16.8
< Page 6 >
9. Added Overshoot/Undershoot spec
. Vih(max) = 4.2V, the overshoot voltage duration is £ 3ns at VDD.
. Vil(min) =- 1.5V, the overshoot voltage duration is £ 3ns at VSS.
< Page 6,7 >
10. Changed AC operating conditions as follows.
From
To
Parameter/Condition
Symbol
Min
Max
Min
Max
Input High (Logic 1) Voltage, DQ, DQS and DM signals VIH(AC) VREF + 0.35
Input Low (Logic 0) Voltage, DQ, DQS and DM signals. VIL(AC)
VREF + 0.31
0.62
VREF - 0.35
VDDQ+0.6
VREF - 0.31
VDDQ+0.6
Input Differential Voltage, CK and CK inputs
VID(AC) 0.7
Rev. 0.5 April. 2000
- 1 -
184pin Unbuffered DDR SDRAM MODULE
M381L6423BT0
< Page 7 >
11. Changed Input/Output capacitance as follows.
From
To
Parameter
Symbol
Min
Max
Min
Max
Input capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS,
WE )
CIN1
-
98
69
87
Input capacitance(CKE0,CKE1)
Input capacitance( CS0,CS1 )
Input capacitance( CLK0, CLK1, CLK2)
Input capacitance(DM0~DM8)
CIN2
CIN3
CIN4
CIN5
-
-
-
-
67
60
38
16
44
44
27
6
53
53
34
8
Data & DQS input/output capacitance(DQ0~DQ63)
Data input/output capacitance(CB0~CB7)
COUT1
COUT2
-
-
16
16
6
6
8
8
< page 8, 9>
12. Changed AC parameters as follows.
Parameter
tDQSQ
tDV
from
to
Comments
Removed
+/- 0.5(PC266), +/- 0.6(PC200)
+/- 0.35tCK
+0.5(PC266), +0.6(PC200)
-
13. Added AC parameters as follows
-A2(PC266@CL=2) -B0(PC266@CL=2.5) -A0(PC200@CL=2)
Parameter
Symbol
Min
Max
Min
Max
Min
Max
tHPmin
-0.75ns
tHPmin
-0.75ns
tHPmin
-1.0ns
Output DQS valid window
Clock half period
tQH
tHP
-
-
-
tCLmin
or tCH-
tCLmin
or tCHmin
tCLmin
or tCHmin
-
-
-
QFC setup to first DQS edge on reads
QFC hold after last DQS edge on reads
Write command to QFC delay on write
Write burst end to QFC delay on write
tQCS
0.9
0.4
0.9
0.4
0.9
0.4
1.1
0.6
1.1
0.6
1.1
0.6
tDQCH
tQCSW
tQCHW
4.0
4.0
4.0
1.25ns
1.25ns
0.5tCK
1.25ns
1.25ns
0.5tCK
1.25ns
1.25ns
0.5tCK
Write burst end to QFC delay on write inter-
rupted
tQCHWI
1.5tCK
1.5tCK
1.5tCK
by Precharge
< Page 12>
14. Changed from 1450mil to 1250mil in Package dimension.
Revision 0.5 (April. 2000)
1. Changed from A-die to B-die.
Rev. 0.5 April. 2000
- 2 -
184pin Unbuffered DDR SDRAM MODULE
M381L6423BT0
M381L6423BT0 DDR SDRAM 184pin DIMM
64Mx72 DDR SDRAM 184pin DIMM based on 32Mx8
FEATURE
GENERAL DESCRIPTION
• Performance range
The Samsung M381L6423BT0 is 64M bit x 72 Double Data
Rate SDRAM high density memory modules based on first
gen. of 256Mb DDR SDRAM respectively. The Samsung
M381L6423BT0 consists of eighteen CMOS 32M x 8 bit with
4banks Double Data Rate SDRAMs in 66pin TSOP-II(400mil)
packages mounted on a 184pin glass-epoxy substrate. Four
0.1uF decoupling capacitors are mounted on the printed circuit
board in parallel for each DDR SDRAM. The M381L6423BT0
is Dual In-line Memory Modules and intended for mounting into
184pin edge connector sockets.
Part No.
Max Freq.
Interface
•
•
•
M381L6423BT0-C(L)A2
133MHz(7.5ns@CL=2)
133MHz(7.5ns@CL=2.5)
100MHz(10ns@CL=2)
•
•
•
•
•
•
•
•
•
•
•
•
•
SSTL_2
M381L6423BT0-C(L)B0
M381L6423BT0-C(L)A0
• Power supply
Vdd: 2.5V ± 0.2V
Power: C - normal, L - Low power
• MRS cycle with address key programs
CAS Latency (Access from column address):2,2.5
Burst length ;2, 4, 8
Synchronous design allows precise cycle control with the use
of system clock. Data I/O transactions are possible on both
edges of DQS. Range of operating frequencies, programmable
latencies and burst lengths allow the same device to be useful
for a variety of high bandwidth, high performance memory sys-
tem applications.
Data scramble ;Sequential & Interleave
• Serial presence detect with EEPROM
• PCB : Height 1250 (mil), double sided component
PIN CONFIGURATIONS (Front side/back side)
PIN DESCRIPTION
Pin Front Pin Front Pin Front Pin
Back
Pin
Back
Pin
Back
Pin Name
A0 ~ A12
Function
Address input (Multiplexed)
Bank Select Address
1
2
3
VREF 32
DQ0 33 DQ24 63
VSS 34 VSS 64 DQ41 95
A5
62 VDDQ 93
VSS
DQ4
DQ5
VDDQ
DM0
DQ6
DQ7
VSS
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
VSS
A6
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
/RAS
DQ45
VDDQ
/CS0
/CS1
DM5
BA0 ~ BA1
/WE 94
DQ28
DQ29
VDDQ
DM3
A3
DQ30
VSS
DQ31
CB4
CB5
VDDQ
CK0
/CK0
VSS
DM8
A10
DQ0 ~ DQ63
CB0 ~ CB7
Data input/output
4
5
DQ1 35 DQ25 65
DQS0 36 DQS3 66
/CAS
VSS
96
97
Check bit(Data-in/data-out)
Data Strobe input/output
DQS0 ~ DQS8
6
DQ2 37
A4
67 DQS5 98
CK0,CK0 ~ CK2, CK2 Clock input
7
8
VDD 38 VDD 68 DQ42 99
DQ3 39 DQ26 69 DQ43 100
VSS
DQ46
DQ47
NC
VDDQ
DQ52
DQ53
NC
CKE0,CKE1
CS0, CS1
RAS
Clock enable input
9
10
NC
NC
40 DQ27 70
41 A2 71
VDD 101
NC 102
NC
NC
Chip select input
Row address strobe
Column address strobe
Write enable
11 VSS 42 VSS 72 DQ48 103
*A13
VDDQ
DQ12
DQ13
DM1
VDD
DQ14
DQ15
CKE1
VDDQ
*BA2
DQ20
A12
VSS
DQ21
A11
DM2
VDD
DQ22
A8
CAS
12 DQ8 43
13 DQ9 44
14 DQS1 45
15 VDDQ 46 VDD 76
16 CK1
A1
73 DQ49 104
CB0 74
VSS
/CK2 106
CK2 107
47 DQS8 77 VDDQ 108
105
WE
CB1 75
DM0 ~ DM8
VDD
Data - in mask
VDD
DM6
Power supply (2.5V)
Power Supply for DQs(2.5V)
Ground
17 /CK1 48
18 VSS 49
A0
78 DQS6 109
DQ54
DQ55
VDDQ
NC
DQ60
DQ61
VSS
VDDQ
VSS
CB2 79 DQ50 110
19 DQ10 50 VSS 80 DQ51 111
CB6
VDDQ
CB7
VREF
Power supply for reference
20 DQ11 51
21 CKE0 52
22 VDDQ
CB3 81
BA1 82 VDDID 113
KEY 83 DQ56 114
VSS
112
VDDSPD
Serial EEPROM Power
Supply (2.5V)
KEY
23 DQ16 53 DQ32 84 DQ57 115
24 DQ17 54 VDDQ 85 VDD 116
25 DQS2 55 DQ33 86 DQS7 117
26 VSS 56 DQS4 87 DQ58 118
145
146
147
148
149
150
151
152
153
VSS
DQ36
DQ37
VDD
SDA
Serial data I/O
DM7
SCL
Serial clock
DQ62
DQ63
VDDQ
SA0
SA1
SA2
SA0 ~ 2
VDDID
NC
Address in EEPROM
VDD identification flag
No connection
27
28 DQ18 58 VSS 89
29 A7 59 BA0 90
A9
57 DQ34 88 DQ59 119
DM4
VSS
NC
120
121
DQ38
DQ39
VSS
*
These pins are not used in this module.
30 VDDQ 60 DQ35 91
31 DQ19 61 DQ40 92
SDA 122
SCL 123
DQ23
DQ44
184 VDDSPD
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Rev. 0.5 April. 2000
- 3 -
184pin Unbuffered DDR SDRAM MODULE
M381L6423BT0
Functional Block Diagram
CS1
CS0
DQS4
DM4
DQS0
DM0
DQS
DM
I/O 7
DQS
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
D4
CS
DM
I/O 7
DQS
DM
CS
D0
CS DQS
D9
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
D13
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQS5
DM5
DQS1
DM1
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQS
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
D5
CS
DQS
DM
DQS
DQS
CS
CS
D1
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
D14
D10
DQS6
DM6
DQS2
DM2
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DQS
CS
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS DQS
D6
CS DQS
D15
DM
CS DQS
D2
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
D11
DQS7
DM7
DQS3
DM3
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS DQS
D7
CS DQS
D16
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS DQS
D3
CS DQS
D12
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQS8
DM8
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DQS
CS DQS
D8
CS
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
*Clock Net Wiring
D17
Dram1
Dram2
Dram3
R=120W
* Clock Wiring
Serial PD
Clock
Input
SDRAMs
Card
Edge
SCL
Dram4
Dram5
SDA
6 SDRAMs
6 SDRAMs
6 SDRAMs
CK0/CK0
CK1/CK1
CK2/CK2
A0
A1
A2
SA0 SA1 SA2
Dram6
BA0-BA1: SDRAMs D0 - D17
A0-A13: SDRAMs D0 - D17
BA0 - BA1
A0 - A13
CKE1
CKE0
WE
CKE: SDRAMs D9 - D17
CKE: SDRAMs D0 - D8
WE: SDRAMs D0 - D17
RAS
CAS
RAS: SDRAMs D0 - D17
CAS: SDRAMs D0 - D17
Notes:
1. DQ-to-I/O wiring is shown as recom-
mended but may be changed.
2. DQ/DQS/DM/CKE/S relationships must
be maintained as shown.
3. DQ, DQS, DM resistors: 22 Ohms.
4. VDDID strap connections
V
/V
DD DDQ
D0 - D17
0.1uF
D0 - D17
0.1uF
VREF
D0 - D17
0.1uF
V
D0 - D17
(for memory device VDD, VDDQ):
SS
STRAP OUT (OPEN): VDD = VDDQ
V
DDID
Strap: see Note 4
STRAP IN (VSS): VDD VDDQ.
¹
Rev. 0.5 April. 2000
- 4 -
184pin Unbuffered DDR SDRAM MODULE
M381L6423BT0
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on VDD supply relative to Vss
Voltage on VDDQ supply relative to Vss
Storage temperature
Symbol
VIN, VOUT
VDD
Value
-0.5 ~ 3.6
-1.0 ~ 4.6
-0.5 ~ 3.6
-55 ~ +150
18
Unit
V
V
V
VDDQ
TSTG
°C
W
Power dissipation
PD
Short circuit current
IOS
50
mA
Note :
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
POWER & DC OPERATING CONDITIONS (SSTL_2 In/Out)
Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 70°C)
Parameter
Supply voltage(for device with a nominal VDD of 2.5V)
I/O Supply voltage
Symbol
VDD
Min
2.3
Max
2.7
Unit
Note
VDDQ
VREF
2.3
2.7
V
V
I/O Reference voltage
0.49*VDDQ
VREF-0.04
VREF+0.15
-0.3
0.51*VDDQ
VREF+0.04
VDDQ+0.3
VREF-0.15
VDDQ+0.3
VDDQ+0.6
2
1
2
I/O Termination voltage(system)
Input logic high voltage
V
V
TT
VIH(DC)
VIL(DC)
VIN(DC)
VID(DC)
II
V
Input logic low voltage
V
Input Voltage Level, CK and CK inputs
Input Differential Voltage, CK and CK inputs
Input leakage current
-0.3
V
0.3
V
3
-2
uA
uA
mA
mA
Output leakage current
IOZ
-5
5
Output High Current (V
= 1.95V)
= 0.35V)
IOH
-16.8
16.8
OUT
OUT
Output Low Current (V
IOL
Notes 1. VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the DC level of the same. Peak-
to-peak noise on VREF may not exceed 2% of the DC value
2.V is not applied directly to the device. V is a system supply for signal termination resistors, is expected to be set equal to
TT
TT
VREF, and must track variations in the DC level of VREF
3. VID is the magnitude of the difference between the input level on CK and the input level on CK.
Rev. 0.5 April. 2000
- 5 -
184pin Unbuffered DDR SDRAM MODULE
M381L6423BT0
DC CHARACTERISTICS
Recommended operating conditions Unless Otherwise Noted,TA=0to70°C)
Version
-B0
CAS
Latency
Parameter
Operating Current
Symbol
Test Condition
Unit Note
-A2
-A0
Burst=2 tRC=tRC(min), CL=2.5
IDD1
T.B.D T.B.D T.B.D mA 1
I
=0mA, Active-Read-Precharge
(One Bank Active)
OUT
Precharge Power-down Standby
Current
IDD2P
IDD2N
IDD3P
IDD3N
CKE£VIL(max), tCK=tCK(min), All banks idle
CKE³ VIH(min), CS³ VIH(min), tCK=tCK(min)
All banks idle,CKE£VIL(max),tCK=tCK(min)
T.B.D
T.B.D
T.B.D
mA
mA
mA
mA
Precharge Standby Current
in Non Power-down mode
Active Standby Current
in Power-down mode
One bank; Active-Precharge, tRC=tRAS(max),
tCK=tCK(min)
Active Standby Current
in Non Power-down mode
T.B.D
2.5
2
T.B.D T.B.D T.B.D
Burst=2, tCK=tCK(min),
=0mA
Operating Current(Read)
Operating Current(Write)
I
IDD4R
IDD4W
T.B.D T.B.D T.B.D mA
1
OUT
Burst=2, tCK=tCK(min)
2.5
2
T.B.D T.B.D T.B.D
T.B.D T.B.D T.B.D mA
1
2
Auto Refresh Current
Self Refresh Current
IDD5
IDD6
mA
mA
T.B.D
T.B.D
tRC³ tRFC(min)
CKE£0.2V
Note : 1. Measured with outputs open.
2. Refresh period is 64ms
AC Operating Conditions
Parameter/Condition
Symbol
Min
Max
Unit
V
Note
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.
Input Differential Voltage, CK and CK inputs
VIH(AC) VREF + 0.31
VIL(AC)
1
2
3
4
VREF - 0.31
VDDQ+0.6
V
VID(AC) 0.62
V
Input Crossing Point Voltage, CK and CK inputs
VIX(AC) 0.5*VDDQ-0.2
0.5*VDDQ+0.2
V
Note 1. Vih(max) = 4.2V. The overshoot voltage duration is £ 3ns at VDD.
2. Vil(min) = -1.5V. The undershoot voltage duration is £ 3ns at VSS.
3. VID is the magnitude of the difference between the input level on CK and the input on CK.
4. The value of V is expected to equal 0.5*V of the transmitting device and must track variations in the DC level of the same.
IX
DDQ
Rev. 0.5 April. 2000
- 6 -
184pin Unbuffered DDR SDRAM MODULE
M381L6423BT0
AC OPERATING TEST CONDITIONS (VDD=2.5V, VDDQ=2.5V, TA= 0 to 70°C)
Parameter
Value
Unit
Note
Input reference voltage for Clock
0.5 * VDDQ
V
Input signal maximum peak swing
1.5
V
Input signal minimum slew rate
Input Levels(VIH/VIL)
1.0
V/ns
V
VREF+0.31/VREF-0.31
Input timing measurement reference level
Output timing measurement reference level
Output load condition
VREF
Vtt
V
V
See Load Circuit
Vtt=0.5*VDDQ
RT=50W
Output
Z0=50W
VREF
=0.5*VDDQ
CLOAD=30pF
(Fig. 1) Output Load Circuit (SSTL_2)
Input/Output CAPACITANCE (VDD=2.5V, VDDQ=2.5V, TA= 25°C, f=1MHz)
Parameter
Symbol
Min
Max
Unit
Input capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS,
WE )
CIN1
69
87
pF
Input capacitance(CKE0,CKE1)
CIN2
CIN3
44
44
27
6
53
53
34
8
pF
pF
pF
pF
pF
pF
Input capacitance( CS0, CS1)
Input capacitance( CLK0, CLK1, CLK2)
Input capacitance(DM0~DM8)
CIN4
CIN5
Data & DQS input/output capacitance(DQ0~DQ63)
Data input/output capacitance(CB0~CB7)
COUT1
COUT2
6
8
6
8
Rev. 0.5 April. 2000
- 7 -
184pin Unbuffered DDR SDRAM MODULE
M381L6423BT0
AC CHARACTERISTICS. (These AC charicteristics were tested on the Component)
- A2(PC266@CL=2)
- B0(PC266@CL=2.5) - A0(PC200@CL=2)
Parameter
Symbol
Unit Note
Min
65
Max
Min
65
Max
Min
70
Max
Row cycle time
tRC
ns
ns
Refresh row cycle time
Row active time
tRFC
tRAS
tRCD
tRP
75
75
80
45
12K
48
12K
48
12K
ns
RAS to CAS delay
20
20
20
ns
Row precharge time
20
20
20
ns
Row active to Row active delay
Write recovery time
tRRD
tWR
15
15
15
ns
2
2
2
tCK
tCK
tCK
tCK
ns
Last data in to Read command
Last data in to Write command
Col. address to Col. address delay
tCDLR
tCDLW
tCCD
tCK
1
1
1
0
0
0
1
1
1
Clock cycle time
CL=2.0
CL=2.5
7.5
7
15
15
10
15
15
10
15
7.5
0.45
0.45
-0.75
-0.75
-
8
15
ns
Clock high level width
Clock low level width
tCH
0.45
0.45
-0.75
-0.75
-
0.55
0.55
+0.75
+0.75
+0.5
1.1
0.55
0.55
+0.75
+0.75
+0.5
1.1
0.45
0.45
-0.8
-0.8
-
0.55
0.55
+0.8
+0.8
+0.6
1.1
tCK
tCK
ns
tCL
DQS-out access time from CK/CK
Output data access time from CK/CK
Data strobe edge to ouput data edge
Read Preamble
tDQSC
tAC
ns
tDQSQ
tRPRE
tRPST
tHZQ
tDQSS
tWPRE
tWPRE
tDQSH
tDQSL
tDSC
tIS
ns
0.9
0.4
-0.75
0.75
0
0.9
0.4
-0.75
0.75
0
0.9
0.4
-0.8
0.75
0
tCK
tCK
Read Postamble
0.6
0.6
0.6
Data out high impedence time from CK/
CK to valid DQS-in
+0.75
1.25
+0.75
1.25
+0.8
1.25
ns
tCK
ns
2
3
DQS-in setup time
DQS-in hold time
0.25
0.4
0.4
0.9
0.9
0.9
15
0.25
0.4
0.4
0.9
0.9
0.9
15
0.25
0.4
0.4
0.9
1.1
1.1
16
tCK
tCK
tCK
tCK
ns
DQS-in high level width
0.6
0.6
1.1
0.6
0.6
1.1
0.6
0.6
1.1
DQS-in low level width
DQS-in cycle time
Address and Control Input setup time
Address and Control Input hold time
Mode register set cycle time
DQ & DM setup time to DQS
DQ & DM hold time to DQS
DQ & DM input pulse width
Power down exit time
tIH
ns
tMRD
tDS
ns
0.5
0.5
1.75
10
0.5
0.5
1.75
10
0.6
0.6
2
ns
tDH
ns
tDIPW
tPDEX
tXSW
ns
10
ns
Exit self refresh to write command
95
116
ns
Rev. 0.5 April. 2000
- 8 -
184pin Unbuffered DDR SDRAM MODULE
M381L6423BT0
-A2(PC266@CL=2) -B0(PC266@CL=2.5) -A0(PC200@CL=2)
Unit Note
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Exit self refresh to bank active command
Exit self refresh to read command
tXSA
tXSR
tREF
75
75
80
ns
Cycle
us
7
1
200
7.8
200
7.8
200
7.8
Refresh interval time
256Mb
tHPmin
-0.75ns
tHPmin
-0.75ns
tHPmin
-1.0ns
Output DQS valid window
tQH
-
-
-
-
-
-
ns
ns
tCLmin
or tCH-
tCLmin
or tCHmin
tCLmin
or tCHmin
Clock half period
tHP
DQS write postamble time
tWPST
0.25
35
0.25
35
0.25
35
tCK
ns
4
Auto precharge write recovery + Precharge time tDAL
QFC setup to first DQS edge on reads
QFC hold after last DQS edge on reads
Write command to QFC delay on write
Write burst end to QFC delay on write
tQCS
0.9
0.4
0.9
0.4
0.9
0.4
tCK
tCK
ns
1.1
0.6
1.1
0.6
1.1
0.6
tDQCH
tQCSW
tQCHW
4.0
4.0
4.0
1.25ns
1.25ns
0.5tCK
1.25ns
1.25ns
0.5tCK
1.25ns
1.25ns
0.5tCK
5
6
Write burst end to QFC delay on write inter-
rupted
tQCHWI
1.5tCK
1.5tCK
1.5tCK
by Precharge
Note : 1. Maximum burst refresh of 8
2. tHZQ transitions occurs in the same access time windows as valid data transitions. These parameters are not referenced
to a specific voltage level, but specify when the device output is no longer driving.
3. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from
High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress,
DQS could be High at this time, depending on tDQSS.
4. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter,
but system performance (bus turnaround) will degrade accordingly.
5. The value of tQCSW min. is 1.25ns from the last low going data strobe edge to QFC high. And the value of
tQCSW max. is 0.5tcK from the first high going clock edge after the last low going data strobe edge to QFC
high.
6. the value of tQCSWI max. is 1.5tcK from the first high going clock edge after the last low going data strobe
edge to QFC high.
7. A write command can be applied with tRCD satisfied after this command.
Rev. 0.5 April. 2000
- 9 -
184pin Unbuffered DDR SDRAM MODULE
M381L6423BT0
SIMPLIFIEDTRUTHTABLE
COMMAND
A11,A12
CKEn-1
CKEn
CS
RAS
CAS
WE
BA0,1
A10/AP
Note
A9 ~ A0
Register
Register
Extended MRS
Mode Register Set
Auto Refresh
H
H
X
X
H
L
L
L
L
L
L
L
L
L
OP CODE
OP CODE
1, 2
1, 2
3
H
L
L
L
H
X
X
Entry
3
Refresh
Self
L
H
L
H
X
L
H
X
H
H
X
H
3
Refresh
Exit
L
H
H
H
X
X
3
Bank Active & Row Addr.
V
V
Row Address
Column
Address
(A0~A9)
Read &
Column Address
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
L
H
L
4
4
L
H
L
H
Column
Address
(A0~A9)
Write &
Column Address
4
H
H
H
X
X
X
L
L
L
H
H
L
L
H
H
L
L
L
V
H
X
L
4, 6
7
Burst Stop
Precharge
Bank Selection
All Banks
V
X
X
H
5
H
L
X
V
X
X
H
X
V
X
X
H
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry
Exit
H
L
L
H
L
Active Power Down
X
X
X
H
L
Entry
H
Precharge Power Down Mode
H
L
Exit
L
H
H
H
DM
X
X
8
9
9
H
L
X
H
X
H
No operation (NOP) : Not defined
X
(V=Valid, X=Don¢t Care, H=Logic High, L=Logic Low)
Note : 1. OP Code : Operand Code. A0 ~ A12 & BA0 ~ BA1 : Program keys. (@EMRS/MRS)
2.EMRS/ MRS can be issued only at all banks precharge state.
A new command can be issued 2 clock cycles after EMRS or MRS.
3. Auto refresh functions are same as the CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.
If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected.
Rev. 0.5 April. 2000
- 10
184pin Unbuffered DDR SDRAM MODULE
M381L6423BT0
6. During burst write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
7. Burst stop command is valid at every burst length.
8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).
9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.
Rev. 0.5 April. 2000
- 11
184pin Unbuffered DDR SDRAM MODULE
M381L6423BT0
PACKAGE DIMENSIONS
Units : Inches (Millimeters)
5.25 ± 0.006
(133.350 ± 0.15)
0.089
(2.26)
5.077
(128.950)
1.25
(31.75
± 0.006
0.15)
±
A
B
2.500
0.10 M
C
B A
0.145 Max
(3.67 Max)
1.95
(49.53)
2.55
(64.77)
0.050 ± 0.0039
(1.270 ± 0.10)
0.118
(3.00)
0.250
(6.350)
0.157
(4.00)
0.039 ± 0.002
(1.000 ± 0.050)
0.26
(6.62)
0.0787
(2.00)
0.1496
(3.80)
0.0078 ±0.006
(0.20 ±0.15)
2.175
0.071
(1.80)
0.050
(1.270)
0.1575
(4.00)
0.10
Detail A
M
C
A
B
M
Detail B
Tolerances : ± 0.005(.13) unless otherwise specified.
The used device is 32Mx8 SDRAM, TSOP.
SDRAM Part NO : K4H560838A-TC
Rev. 0.5 April. 2000
- 12
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