S3P7434XX-AQ [SAMSUNG]
Microcontroller, 4-Bit, OTPROM, 6MHz, CMOS, PDIP42, 0.600 INCH, SDIP-42;
| 型号： | S3P7434XX-AQ |
| 厂家： | 
SAMSUNG |
| 描述： | Microcontroller, 4-Bit, OTPROM, 6MHz, CMOS, PDIP42, 0.600 INCH, SDIP-42 可编程只读存储器 时钟 微控制器 光电二极管 外围集成电路 |
| 文件： | 总50页 (文件大小：345K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S3C7414/P7414/C7424/P7424/C7434/P7434
PRODUCT OVERVIEW
1
PRODUCT OVERVIEW
OVERVIEW
The S3C7414/C7424/C7434 single-chip CMOS microcontroller has been designed for very high performance
using Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontroller).
With an A/D converter, LED direct drive pins, an 8-bit serial I/O interface, and an 8-bit timer/counter, the
S3C7414/C7424/C7434 offers you an excellent design solution for a wide variety of home appliance applications
— electric fans, cookers, boilers, and air conditioners, for example.
Up to 35 pins of the 42-pin SDIP or 44-pin QFP package can be dedicated to I/O. Seven vectored interrupts
provide fast response to internal and external events.
In addition, the S3C7414/C7424/C7434's advanced CMOS technology provides for low power consumption and a
wide operating voltage range.
OTP
The S3C7414/C7424/C7434 microcontroller is also available in OTP (One Time Programmable) version,
S3P7414/P7424/P7434. S3P7414/P7424/P7434 microcontroller has an on-chip 4-Kbyte one-time-programmable
EPROM instead of masked ROM. The S3P7414/P7424/P7434 is comparable to S3C7414/C7424/C7434, in
function, in D.C. electrical characteristics and in pin configuration.
DEVELOPMENT SUPPORT
The Samsung Microcontroller Development System, SMDS, provides you with a complete PC-based develop-
ment environment for S3C7-series microcontrollers that is powerful, reliable, and portable. In addition to its
window-based program development structure, the SMDS toolset includes versatile debugging, trace, instruction
timing, and performance measurement applications.
The Samsung Generalized Assembler (SAMA) has been designed specifically for the SMDS environment and
accepts assembly language sources in a variety of microprocessor formats. SAMA generates industry-standard
hex files that also contain program control data for SMDS compatibility.
1-1
PRODUCT OVERVIEW
S3C7414/P7414/C7424/P7424/C7434/P7434
FEATURES SUMMARY
Memory
Built-in reset circuit (S3C7434 only)
Built-in power-on reset circuit
•
•
•
256 ´ 4-bit RAM
4,096 ´ 8-bit ROM
Interrupts
•
•
•
Five internal vectored interrupts
(INTB, INTT0, INTT1, INTS, INTAD)
35 I/O Pins
•
I/O: 31 pins including 8 LED direct drive pins
Three external vectored interrupts
(INT0, INT1, INT4)
(S3C7414/C7434)
18 pins including 8 LED direct drive pins
(S3C7424)
Two quasi-interrupts (INT2, INTW)
•
Input only: 4 pins
Bit Sequential Carrier
A/D Converter
•
Supports 16-bit serial data transfer in
arbitrary format
•
•
6-channel with 8-bit resolution
22.89 µs conversion speed at 4.19 MHz
Memory-Mapped I/O Structure
Data memory bank 15
•
Basic Timer
•
•
•
One 8-bit basic timer
Two Power-Down Modes
Watchdog timer functions
Four interval clock selection
•
•
Idle mode (only CPU clock stops)
Stop mode (system oscillation stops)
Timer/Counters
Oscillation Sources
•
•
•
•
•
Two 8-bit timer/counter (TC0, TC1)
Programmable 8-bit timer
External event counter
•
•
•
•
Crystal, Ceramic, or RC for system clock
Crystal, Ceramic: 0.4–6.0 MHz
RC: 4 MHz (typ)
Arbitrary clock frequency output
PWM output mode (TC1)
CPU clock divider circuit (by 4, 8, or 64)
Instruction Execution Times
Watch Timer
•
•
0.95, 1.91, 15.3 µs at 4.19 MHz
0.67, 1.33, 10.7 µs at 6.0 MHz
•
•
One watch timer 8-bit
Time interval generation: 0.5 s, 3.9 ms at
4.19 MHz
Operating Temperature
•
Four frequency outputs to BUZ pin
°
°
•
– 40 C to 85 C
8-bit Serial I/O Interface
Operating Voltage Range
•
•
•
•
8-bit transmit/receive mode
•
•
1.8 V to 5.5 V (S3C7414/C7424)
2.5 V to 5.5 V (S3C7434)
8-bit receive mode
LSB-first or MSB-first transmission selectable
Internal or external clock source
Package Type
42-pin SDIP, 44-pin QFP (S3C7414/C7434)
30-pin SDIP, 28-pin SOP (S3C7424)
•
1-2
S3C7414/P7414/C7424/P7424/C7434/P7434
PRODUCT OVERVIEW
S3C7434
Table 1-1. Comparision Table
S3C7414 S3C7424
Feature
Core
ROM
RAM
I/O
SAM47
SAM47
Same
SAM47
4 K bytes
Same
256 nibbles
35 (4 input only)
None
Same
Same
21 (3 input only)
None
35 (4 input only)
Built in/ Typ: 2.0 V
Same
POR (1)
SIO
8-bit SIO x 1
8-bit timer/counter
Same
Timer0
Same
Same
Timer1(PWM)
8-bit timer/counter
(8-bit PWM x 1)
Same
Same
Watchdog timer
Watch-dog
Same
Same
4 selectable interval
ADC
8-bit x 6
None (2)
8-bit x 4
Same
8-bit x 6
Same
AVSS
Interrupt
External x 3
Internal x 5
External x 2
Internal x 5
External x 3
Internal x 5
Quasi x 2 (KS0–KS3)
Quasi x 1 ( – )
Quasi x 2 (KS0–KS3)
Power down
Oscillator
Stop/Idle
Same
Same
Crystal, Ceramic, RC
0.4–6 MHz
1.8–5.5 V
Same
Same
Operating frequency
Operating voltage
OTP/MTP
Same
Same
1.8–5.5 V
Same
2.5–5.5 V
Same
OTP
Package
42SDIP/44QFP
30SDIP/28SOP
42SDIP/44QFP
NOTES
1. POR (power on reset)/Typ 2.0 V low voltage detector.
2. Internal A/D converter ground (bonded to V internally)
SS
1-3
PRODUCT OVERVIEW
S3C7414/P7414/C7424/P7424/C7434/P7434
BLOCK DIAGRAM
BASIC
TIMER
WATCH
TIMER
INT0, INT1, INT2,INT4
X
IN
X
OUT
8-BIT
TIMER/
RESET
P0.0/
P0.1/SO
P0.2/SI
P0.3/BUZ
SCK
COUNTER 0
I/O PORT 2
INTERRUPT
CONTROL
BLOCK
INSTRUCTION
REGISTER
CLOCK
8-BIT
TIMER/
SERIAL
I/O
COUNTER 1
PROGRAM
COUNTER
INTERNAL
P1.0/INT0
P1.1/INT1
P1.2/INT2
P1.3/INT4
P4.0-4.3
P5.0-5.3
I/O PORT 4
I/O PORT 5
INTERRUPTS
INPUT
PORT 1
PROGRAM
STATUS WORD
INSTRUCTION DECODER
P6.0/KS0
P6.1/KS1
P6.2/KS2
P6.3/KS3
P2.0-P2.3/
AD0-AD3
I/O PORT 2
ARITHMETIC
AND
LOGIC UNIT
I/O PORT 6
I/O PORT 7
I/O PORT 8
STACK
POINTER
A/D
CONVERTER
AV
REF
P7.0-7.3
P3.0/AD4
P3.1/AD5
P3.2/CLO/TCL1
P3.3/PWM / TCLO1
P8.0/TCL0
P8.1/TCLO0
P8.2
I/O PORT 3
256x 4-BIT
DATA
MEMORY
4 K BYTE
PROGRAM
MEMORY
Figure 1-1. S3C7414/C7424/C7434Simplified Block Diagram
1-4
S3C7414/P7414/C7424/P7424/C7434/P7434
PRODUCT OVERVIEW
PIN ASSIGNMENTS
P8.2
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
P2.0/AD0
P2.1/AD1
P2.2/AD2
P2.3/AD3
P3.0/AD4
P3.1/AD5
AVREF
1
2
3
4
5
6
7
8
P8.1/TCLO0
P8.0/TCL0
P7.3
P7.2
P7.1
P7.0
P6.3/KS3
P6.2/KS2
P6.1/KS1
P6.0/KS0
P1.3/INT4
P1.2/INT2
P1.1/INT1
P1.0/INT0
P0.3/BUZ
P0.2/SI
P0.1/SO
P0.0/SCK
P5.3
P3.2/CLO/TCL1
P3.3/PWM/TCLO1
P4.0
9
S3C7414
10
11
12
13
14
15
16
17
18
19
20
21
VDD
VSS
XOUT
XIN
TEST
P4.1
P4.2
RESET
P4.3
(42-SDIP)
P5.0
P5.1
P5.2
Figure 1-2. S3C7414 Pin Assignment (42-SDIP)
1-5
PRODUCT OVERVIEW
S3C7414/P7414/C7424/P7424/C7434/P7434
P7.2
P7.1
P7.0
33
32
31
30
29
28
27
26
25
24
23
AVREF
P3.2/CLO/TCL1
P3.3/PWM/TCLO1
1
2
3
4
5
6
7
8
P6.3/KS3
P6.2/KS2
P6.1/KS1
P6.0/KS0
P1.3/INT4
P1.2/INT2
P1.1/INT1
P1.0/INT0
P4.0
VDD
VSS
XOUT
XIN
TEST
P4.1
P4.2
S3C7414
(44-QFP)
9
10
11
Figure 1-3. S3C7414 Pin Assignment (44-QFP)
1-6
S3C7414/P7414/C7424/P7424/C7434/P7434
PRODUCT OVERVIEW
VDD
P4.0
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
VSS
XOUT
XIN
TEST
P4.1
P4.2
RESET
NC
1
2
3
4
5
6
7
8
P3.3/PWM/TCLO1
P3.2/CLO/TCL1
AVREF
NC
S3C7424
P2.3/AD3
P2.2/AD2
P2.1/AD1
P2.0/AD0
P1.2/INT2
P1.1/INT1
P1.0/INT0
P0.3/BUZ
P0.2/SI
P4.3
P5.0
P5.1
P5.2
9
(30-SDIP)
10
11
12
13
14
15
P5.3
P0.0/SCK
P0.1/SO
Figure 1-4. S3C7424 Pin Assignment (30-SDIP)
VDD
P4.0
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VSS
XOUT
XIN
TEST
P4.1
P4.2
1
2
3
4
5
6
7
8
P3.3/PWM/TCLO1
P3.2/CLO/TCL1
AVREF
P2.3/AD3
P2.2/AD2
P2.1/AD1
P2.0/AD0
P1.2/INT2
P1.1/INT1
P1.0/INT0
P0.3/BUZ
P0.2/SI
S3C7424
RESET
P4.3
P5.0
P5.1
P5.2
P5.3
9
(28-SOP)
10
11
12
13
14
P0.0/SCK
P0.1/SO
Figure 1-5. S3C7424 Pin Assignment (28-SOP)
1-7
PRODUCT OVERVIEW
S3C7414/P7414/C7424/P7424/C7434/P7434
P8.2
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
P2.0/AD0
P2.1/AD1
P2.2/AD2
P2.3/AD3
P3.0/AD4
P3.1/AD5
AVREF
1
2
3
4
5
6
7
8
P8.1/TCLO0
P8.0/TCL0
P7.3
P7.2
P7.1
P7.0
P6.3/KS3
P6.2/KS2
P6.1/KS1
P6.0/KS0
P1.3/INT4
P1.2/INT2
P1.1/INT1
P1.0/INT0
P0.3/BUZ
P0.2/SI
P0.1/SO
P0.0/SCK
P5.3
P3.2/CLO/TCL1
P3.3/PWM/TCLO1
P4.0
9
S3C7434
10
11
12
13
14
15
16
17
18
19
20
21
VDD
VSS
XOUT
XIN
TEST
P4.1
P4.2
RESET
P4.3
(42-SDIP)
P5.0
P5.1
P5.2
Figure 1-6. S3C7434 Pin Assignment (42-SDIP)
1-8
S3C7414/P7414/C7424/P7424/C7434/P7434
PRODUCT OVERVIEW
P7.2
P7.1
P7.0
33
32
31
30
29
28
27
26
25
24
23
AVREF
P3.2/CLO/TCL1
P3.3/PWM/TCLO1
1
2
3
4
5
6
7
8
P6.3/KS3
P6.2/KS2
P6.1/KS1
P6.0/KS0
P1.3/INT4
P1.2/INT2
P1.1/INT1
P1.0/INT0
P4.0
VDD
VSS
XOUT
XIN
TEST
P4.1
P4.2
S3C7434
(44-QFP)
9
10
11
Figure 1-7. S3C7434 Pin Assignment (44-QFP)
1-9
PRODUCT OVERVIEW
S3C7414/P7414/C7424/P7424/C7434/P7434
PIN DESCRIPTIONS
Table 1-2. S3C7414/C7434 Pin Descriptions
Description
Pin Name Pin Type
Number
Share Pin
P0.0
P0.1
P0.2
P0.3
I/O
4-bit I/O port.
24 (18)
25 (19)
26 (20)
27 (21)
SCK
SO
SI
1-bit or 4-bit read/write and test is possible.
Individual pins are software configurable as input or
output.
4-bit pull-up resistors are software assignable; pull-up
resistors are automatically disabled for output pins.
BUZ
P1.0
P1.1
P1.2
P1.3
I
4-bit input port.
28 (23)
29 (24)
30 (25)
31 (26)
INT0
INT1
INT2
INT4
1-bit and 4-bit read and test is possible.
3-bit pull-up resistors are individually assignable by
software to pins P1.0, P1.1, and P1.2.
P2.0
P2.1
P2.2
P2.3
I/O
4-bit I/O port.
N-channel open-drain output.
1-bit or 4-bit write and test is possible.
Individual pins are software configurable as AD input
or output.
1 (38)
2 (39)
3 (40)
4 (41)
AD0
AD1
AD2
AD3
4-bit pull-up resistors are software assignable; pull-up
resistors are automatically disabled for output pins.
P3.0
P3.1
P3.2
P3.3
I/O
I/O
Same as Port 0 (P0.0–P0.3)
5 (42)
6 (43)
8 (2)
AD4
AD5
CLO/TCL1
PWM/TCLO1
9 (3)
P4.0
P4.1
P4.2
P4.3
4-bit I/O ports.
10 (4)
16 (10)
17 (11)
19 (13)
20–23
–
Ports 4 and 5 can be configured individually as n-
channel open-drain or as CMOS push-pull output by
software.
1-bit and 4-bit read/write and test is possible.
Ports 4 and 5 can be paired to enable 8-bit data
transfer.
P5.0–P5.3
(14–17)
4-bit pull-up resistors are software assignable; pull-up
resistors are automatically disabled for output pins.
P6.0–P6.3
P7.0–P7.3
I/O
Same as Port 0 except port 8 is a 3-bit I/O port
32–35
(27–30)
36–39
KS0–KS3
–
(31–34)
40 (35)
41 (36)
42 (37)
P8.0
P8.1
P8.2
TCL0
TCLO0
–
1-10
S3C7414/P7414/C7424/P7424/C7434/P7434
PRODUCT OVERVIEW
Table 1-2. S3C7414/C7434 Pin Descriptions (Continued)
Pin Name Pin Type
Description
Number
Share Pin
I/O
Serial I/O interface clock signal
24 (18)
P0.0
SCK
SO
I/O
I/O
I/O
Serial data output
Serial data input
25 (19)
26 (20)
27 (21)
P0.1
P0.2
P0.3
SI
BUZ
2 kHz, 4kHz, 8kHz, or 16 kHz frequency output at the
watch timer clock frequency of 32.768 kHz
INT0, INT1
I
External interrupts. The triggering edge for INT0 and
INT1 is selectable. Only INT0 is synchronized with the
system clock.
28–29
(23–24)
P1.0, P1.1
INT2
INT4
I
I
Quasi-interrupt input with rising edge detection
30 (25)
31 (26)
P1.2
P1.3
External interrupts with detection of rising and falling
edges
AD0–AD3
AD4–AD5
I/O
A/D converter analog inputs
1–4
(38–41)
5–6
P2.0–P2.3
P3.0–P3.1
(42–43)
TCL0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
External clock input for timer/counter0
Timer/counter clock output
Clock output
40 (35)
41 (36)
8 (2)
P8.0
P8.1
TCLO0
CLO
P3.2
TCL1
External clock input for timer/counter1
PWM output
8 (2)
P3.2
PWM
9 (3)
P3.3
TCLO1
KS0–KS3
Timer/counter clock output1
Quasi-interrupt input with falling edge detection
9 (3)
P3.3
32–35
P6.0–P6.3
(27–30)
VDD
VSS
–
–
I
Main power supply
Ground
11 (5)
12 (6)
–
–
–
–
Reset signal
18 (12)
RESET
XIN, Xout
–
Crystal, ceramic, or RC oscillator signal for system
clock.
14, 13
(8, 7)
AVREF
TEST
NC
–
I
A/D converter analog reference voltage
7 (1)
15 (9)
–
–
–
Test signal input (must be connected to VSS
)
–
No connection (no bonding pin)
(22, 44)
NOTE: Parentheses indicate 44-QFP pin number.
1-11
PRODUCT OVERVIEW
Pin Name Pin Type
S3C7414/P7414/C7424/P7424/C7434/P7434
Table 1-3. S3C7424 Pin Descriptions
Description
Number
Share Pin
P0.0
P0.1
P0.2
P0.3
I/O
4-bit I/O port.
14 (13)
15 (14)
16 (15)
17 (16)
SCK
SO
SI
1-bit or 4-bit read/write and test is possible.
Individual pins are software configurable as input or
output.
4-bit pull-up resistors are software assignable; pull-up
resistors are automatically disabled for output pins.
BUZ
P1.0
P1.1
P1.2
I
4-bit input port.
18 (17)
19 (18)
20 (19)
INT0
INT1
INT2
1-bit and 4-bit read and test is possible.
3-bit pull-up resistors are individually assignable by
software to pins P1.0, P1.1, and P1.2.
P2.0
P2.1
P2.2
P2.3
I/O
4-bit I/O port.
N-channel open-drain output.
1-bit or 4-bit write and test is possible.
Individual pins are software configurable as AD input
or output.
21 (20)
22 (21)
23 (22)
24 (23)
AD0
AD1
AD2
AD3
4-bit pull-up resistors are software assignable; pull-up
resistors are automatically disabled for output pins.
P3.2
P3.3
I/O
I/O
Same as Port 0 (P0.0–P0.3)
27 (25)
28 (26)
CLO/TCL1
PWM/TCLO1
P4.0
P4.1
P4.2
P4.3
4-bit I/O ports.
29 (27)
5 (5)
6 (6)
–
Ports 4 and 5 can be configured individually as n-
channel open-drain or as CMOS push-pull output by
software.
9 (8)
1-bit and 4-bit read/write and test is possible.
Ports 4 and 5 can be paired to enable 8-bit data
transfer.
P5.0–P5.3
10–13
(9–12)
4-bit pull-up resistors are software assignable; pull-up
resistors are automatically disabled for output pins.
1-12
S3C7414/P7414/C7424/P7424/C7434/P7434
PRODUCT OVERVIEW
Table 1-3. S3C7424 Pin Descriptions (Continued)
Pin Name Pin Type
Description
Number
Share Pin
I/O
Serial I/O interface clock signal
14 (13)
P0.0
SCK
SO
I/O
I/O
I/O
Serial data output
Serial data input
15 (14)
16 (15)
17 (16)
P0.1
P0.2
P0.3
SI
BUZ
2 kHz, 4kHz, 8kHz, or 16 kHz frequency output at the
watch timer clock frequency of 32.768 kHz
INT0, INT1
I
External interrupts. The triggering edge for INT0 and
INT1 is selectable. Only INT0 is synchronized with the
system clock.
18, 19
(17, 18)
P1.0, P1.1
INT2
I
Quasi-interrupt input with rising edge detection
A/D converter analog inputs
20 (19)
P1.2
AD0–AD3
I/O
21–24
P2.0–P2.3
(20–23)
CLO
I/O
I/O
I/O
I/O
–
Clock output
27 (25)
27 (25)
28 (26)
28 (26)
30 (28)
1 (1)
P3.2
P3.2
P3.3
P3.3
–
TCL1
PWM
TCLO1
External clock input for timer/counter1
PWM output
Timer/counter clock output1
Main power supply
Ground
V
DD
V
SS
–
–
I
Reset signal
7 (7)
–
RESET
XIN, XOUT
–
Crystal, ceramic, or RC oscillator signal for system
clock.
3, 2
(3, 2)
–
AVREF
TEST
NC
–
I
Internal A/D converter analog reference voltage
26 (24)
4 (4)
–
–
–
Test signal input (must be connected to VSS
)
–
No connection (no bonding pin)
8, 25
NOTE: Parentheses indicate 28-SOP pin number.
1-13
PRODUCT OVERVIEW
S3C7414/P7414/C7424/P7424/C7434/P7434
Table 1-4. Overview of S3C7414/C7424/C7434Pin Data
Pin Names
Share Pins
I/O Type
Reset Value
Input
Circuit Type
Type D
P0.0–P0.3
I/O
I
SCK, SO, SI, BUZ
INT0 (note)
INT1 (note)
INT2 (note)
P1.0
P1.1
P1.2
Input
Type A-1
P1.3
INT4
I
Input
AD input
Input
Type A
P2.0–P2.3
AD0–AD3
I/O
I/O
Type F-3
P3.0
P3.1
P3.2
P3.3
AD4
AD5
CLO/TCL1
TCLO1/PWM
Type F
Type F
Type D
Type D
P4.0–P4.3
P5.0–P5.3
–
I/O
I/O
Input
Input
Type E
KS0 (note)
KS1 (note)
KS2 (note)
KS3 (note)
Type D
P6.0
P6.1
P6.2
P6.3
I/O
I/O
Type D
Type D
P7.0–P7.3
–
Input
Input
TCL0 (note)
TCLO0
–
P8.0
P8.1
P8.2
VDD, VSS
XIN, XOUT
–
–
–
–
–
I
–
–
–
–
–
–
Type B-2 (note)
–
RESET
AVREF
–
–
–
TEST
NC
–
–
I
–
–
–
–
NOTE: A noise filter circuit is built-in.
1-14
S3C7414/P7414/C7424/P7424/C7434/P7434
PRODUCT OVERVIEW
PIN CIRCUIT DIAGRAMS
V
DD
V
DD
P-CHANNEL
1M
W
IN
RESET
7pF
-
N CHANNEL
Figure 1-10. Pin Circuit Type B-2
Figure 1-8. Pin Circuit Type A
V
DD
V
DD
P-CHANNEL
OUT
PULL-UP
RESISTOR
ENABLE
DATA
N-CHANNEL
OUTPUT
DISABLE
IN
CIRCUIT TYPE A
Figure 1-9. Pin Circuit Type A-1
Figure 1-11. Pin Circuit Type C
1-15
PRODUCT OVERVIEW
KS57C4104/P4104/C4204/P4204 MICROCONTROLLER (Preliminary Spec)
V
DD
V
DD
PULL-UP
RESISTOR
ENABLE
PULL-UP
RESISTOR
ENABLE
DATA
CIRCUIT
TYPE C
IN/OUT
OUTPUT
DISABLE
DATA
CIRCUIT
TYPE C
I/O
OUTPUT
DISABLE
DATA
CIRCUIT TYPE A
TO ADC
ADC INPUT SELECT
Figure 1-12. Pin Circuit Type D
Figure 1-14. Pin Circuit Type F
V
DD
V
DD
V
DD
PNE
PULL-UP
RESISTOR
ENABLE
PULL-UP
RESISTOR
ENABLE
IN/OUT
DATA
OUTPUT
DISABLE
IN/OUT
DATA
OUTPUT
DISABLE
DATA
TO ADC
INPUT
ADC INPUT SELECT
Figure 1-15. Pin Circuit Type F-3
Figure 1-13. Pin Circuit Type E
1-16
S3C7414/P7414/C7424/P7424/C7434/P7434
ELECTRICAL DATA
14 ELECTRICAL DATA
OVERVIEW
In this section, information on S3C7414/C7424/C7434 electrical characteristics is presented as tables and
graphics. The information is arranged in the following order:
Standard Electrical Characteristics
— Absolute maximum ratings
— D.C. electrical characteristics
— System clock oscillator characteristics
— Operating voltage range
— A.C. electrical characteristics
— A/D converter electrical characteristics
— I/O capacitance
Stop Mode Characteristics and Timing Waveforms
— RAM data retention supply voltage in stop mode
— Stop mode release timing when initiated by RESET
— Stop mode release timing when initiated by an interrupt request
Miscellaneous Timing Waveforms
— A.C timing measurement points (except for XIN)
— Clock timing measurement at XIN
— TCL0/1 timing
— Input timing for RESET signal
— Input timing for external interrupts and quasi-interrupts
— S3C7434 power-on RESET timing
— Serial data transfer timing
14-1
ELECTRICAL DATA
S3C7414/P7414/C7424/P7424/C7434/P7434
Table 14-1. S3C7414/C7424 Absolute Maximum Ratings
°
(TA = 25 C)
Parameter
Symbol
Conditions
Rating
Units
V
VDD
Supply Voltage
Input Voltage
–
– 0.3 to + 6.5
VI
– 0.3 to VDD + 0.3
– 0.3 to VDD + 0.3
All I/O ports
One pin
V
VO
IOH
Output Voltage
Output Current High
–
V
– 15
mA
All output pins
One pin
– 35
+ 30
peak value (note)
rms value
peak value (note)
rms value
–
IOL
Output Current Low
mA
+ 15
+ 100
All pins
+ 60
TA
°
C
Operating Temperature
Storage Temperature
– 40 to + 85
Tstg
°
C
–
– 65 to + 150
NOTE: The values for Output Current Low (I ) are calculated as Peak Value ´ Duty .
OL
14-2
S3C7414/P7414/C7424/P7424/C7434/P7434
ELECTRICAL DATA
Table 14-2. S3C7414/C7424 D.C. Electrical Characteristics
°
°
(TA = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
Parameter
Input High
Symbol
Conditions
Min
Typ
Max
Units
VIH1
0.7 VDD
VDD
All input pins except those specified
–
V
below for V –V
Voltage
IH2 IH3
VIH2
VIH3
VIL1
0.8 VDD
VDD – 0.1
–
VDD
VDD
Ports 0, 1, 3, 6 and RESET
XIN, XOUT
0.3 VDD
Input Low
Voltage
All input pins except those specified
–
V
below for V –V
IL2 IL3
VIL2
VIL3
VOH
0.2 VDD
Ports 0, 1, 3, 6 and RESET
XIN, XOUT
0.1
–
V
DD
= 4.5 V to 5.5 V
VDD – 1.0
Output High
Voltage
–
V
V
IOH = – 1 mA
Ports 0, 2–8
VOL
V
DD
= 4.5 V to 5.5 V
Output Low
Voltage
–
0.4
2
3
IOL = 15 mA
Ports 4 and 5 only
IOL = 4 mA
0.2
–
All output ports except ports 4 and 5
VI = VDD
ILIH1
Input High
Leakage Current
–
–
µA
µA
All input pins except those specified
below for I
LIH2
ILIH2
ILIL1
VI = VDD
XIN and XOUT only
20
VI = 0 V
Input Low
–
– 3
Leakage Current
All input pins except XIN and XOUT
,
RESET
ILIL2
VI = 0 V
– 20
XIN and XOUT only
ILOH
ILOL
RL1
VO = VDD
Output High
Leakage Current
–
–
–
–
3
µA
µA
kW
All output pins
VO = 0 V
Output Low
Leakage Current
– 3
All output pins
Pull-up Resistor
25
50
50
100
200
400
800
VI = 0 V; VDD = 5 V except RESET
VI = 0 V; VDD = 3 V except RESET
VI = 0 V; VDD = 5 V; RESET
100
250
500
RL2
Pull-up Resistor
100
200
kW
VI = 0 V; VDD = 3 V; RESET
14-3
ELECTRICAL DATA
S3C7414/P7414/C7424/P7424/C7434/P7434
Table 14-2. S3C7414/C7424 D.C. Electrical Characteristics (Continued)
°
°
(TA = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
Parameter Symbol
Conditions
= 5.0 V ± 10%
Min
Typ
3.0
2.3
1.4
1.1
1.1
1.0
0.5
0.4
0.1
0.1
Max
8.0
5.5
4.0
3.0
2.5
1.8
1.5
1.0
5.0
3.0
Units
mA
I
I
I
Supply
6.0MHz
4.19MHz
6.0MHz
4.19MHz
6.0MHz
4.19MHz
6.0MHz
4.19MHz
–
Run mode; V
DD
DD1
Current (1)
Crystal oscillator; C1=C2=22pF
= 3 V ± 10%
V
DD
mA
–
–
Idle mode; V
= 5.0 V ± 10%
DD2
DD
Crystal oscillator; C1=C2=22pF
= 3 V ± 10%
V
DD
Stop mode; V
Stop mode; V
= 5.0 V ± 10%
= 3.0 V ± 10%
mA
DD3
DD
DD
NOTES:
1. D.C. electrical values for Supply current (I
to I
) do not include current drawn through internal pull-up registers,
DD3
DD1
output port drive currents and ADC.
2. The supply current assumes a CPU clock of fx/4.
14-4
S3C7414/P7414/C7424/P7424/C7434/P7434
ELECTRICAL DATA
Table 14-3. S3C7414/C7424 System Clock Oscillator Characteristics
°
°
(TA = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
Oscillator
Clock
Parameter
Test Condition
Min Typ Max Units
Configuration
Oscillation frequency (1)
V
DD
= 2.7 V to 5.5 V
Ceramic
Oscillator
0.4
–
6.0
MHz
Xin
Xout
C1
C2
V
DD
V
DD
V
DD
V
DD
= 2.0 V to 5.5 V
= 1.8 V to 5.5 V
= 3.0 V
0.4
0.4
–
–
–
–
–
4.2
3.0
4
Stabilization time (2)
ms
Oscillation frequency (1)
= 2.7 V to 5.5 V
Crystal
Oscillator
0.4
6.0
MHz
Xin
Xout
C1
C2
V
DD
V
DD
V
DD
V
DD
= 2.0 V to 5.5 V
= 1.8 V to 5.5 V
= 3.0 V
0.4
0.4
–
–
–
–
–
4.2
3.0
10
Stabilization time (2)
ms
XIN input frequency (1)
= 2.7 V to 5.5 V
External
Clock
0.4
6.0
MHz
Xin
Xout
V
V
= 2.0 V to 5.5 V
= 1.8 V to 5.5 V
–
0.4
0.4
–
–
–
4.2
3.0
DD
DD
XIN input high and low
83.3
1250
ns
level width (t , t
)
XH XL
VDD = 5 V
RC
Oscillator
Oscillation frequency
limitation
–
4
–
MHz
Xin
Xout
R = 8.2 KW
R
NOTES:
1. Oscillation frequency and Xin input frequency data are for oscillator characteristics only.
2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is
terminated.
14-5
ELECTRICAL DATA
S3C7414/P7414/C7424/P7424/C7434/P7434
Main Oscillator Frequency
(Divided by 4)
CPU CLOCK
1.5 MHz
6 MHz
1.05 MHz
0.75 MHz
4.2 MHz
3 MHz
15.6 kHz
1
2
3
4
5
6
1.8
2.7
5.5
SUPPLY VOLTAGE (V)
CPU CLOCK = 1/n x oscillator frequency (n = 4, 8 or 64)
Figure 14-1. S3C7414/C7424 Standard Operating Voltage Range
Table 14-4. S3C7414/C7424 A.C. Electrical Characteristics
°
°
(T = – 40 C to + 85 C, V
= 1.8 V to 5.5 V)
DD
A
Parameter
Instruction Cycle
Time
Symbol
Conditions
= 2.7 V to 5.5 V
= 1.8 V to 5.5 V
= 2.7 V to 5.5 V
= 1.8 V to 5.5 V
= 2.7 V to 5.5 V
= 1.8 V to 5.5 V
= 2.7 V to 5.5 V
Min
0.67
1.33
0
Typ
Max
Units
t
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
–
64
ms
CY
f
TCL0/1 Input
Frequency
–
–
–
1.5
0.75
–
MHz
MHz
ms
TI
t
, t
TCL0/1 Input High,
Low Width
0.48
1.8
TIH TIL
t
800
–
ns
KCY
SCK Cycle Time
External SCK source
Internal SCK source
670
V
DD
= 1.8 V to 5.5 V
3200
External SCK source
Internal SCK source
3800
14-6
S3C7414/P7414/C7424/P7424/C7434/P7434
ELECTRICAL DATA
Table 14-4. S3C7414/C7424 A.C. Electrical Characteristics (Continued)
°
°
(T = – 40 C to + 85 C, V
= 1.8 V to 5.5 V)
A
DD
Parameter
Symbol
Conditions
Min
Typ
Max
–
Units
t
, t
KH KL
V
DD
= 2.7 V to 5.5 V
335
–
ns
SCK High, Low
Width
External SCK source
Internal SCK source
t
/2 – 50
KCY
V
DD
= 1.8 V to 5.5 V
1600
External SCK source
Internal SCK source
t
KCY/2 – 150
100
t
V
DD
= 2.7 V to 5.5 V
SI Setup Time to
–
–
–
–
ns
ns
ns
SIK
SCK High
External SCK source
Internal SCK source
150
150
V
DD
= 1.8 V to 5.5 V
External SCK source
Internal SCK source
500
400
t
V
DD
= 2.7 V to 5.5 V
SI Hold Time to
–
KSI
SCK High
External SCK source
Internal SCK source
400
600
V
DD
= 1.8 V to 5.5 V
External SCK source
Internal SCK source
500
–
(1)
V
DD
= 2.7 V to 5.5 V
Output Delay for
300
t
KSO
SCK to SO
External SCK source
Internal SCK source
250
V
DD
= 1.8 V to 5.5 V
1000
External SCK source
1000
–
Internal SCK source
(2)
t
t
,
Interrupt Input
High, Low Width
INT0
–
–
ms
ms
INTH
INTL
INT1, INT2, INT4, KS0–KS3
Input
10
10
t
–
RSL
RESET Input
Low Width
NOTES:
1. R(1KW) and C (100pF) are the load resistance and load capacitance of the SO output line.
2. Minimum value for INT0 is based on a clock of 2tCY or 128/fx as assigned by the IMOD0 register setting.
14-7
ELECTRICAL DATA
S3C7414/P7414/C7424/P7424/C7434/P7434
Table 14-5. S3C7434 Absolute Maximum Ratings
°
(TA = 25 C)
Parameter
Symbol
Conditions
Rating
Units
V
VDD
Supply Voltage
Input Voltage
–
– 0.3 to + 6.5
VI
– 0.3 to VDD + 0.3
– 0.3 to VDD + 0.3
All I/O ports
One pin
V
VO
IOH
Output Voltage
Output Current High
–
V
– 15
mA
All output pins
One pin
– 35
+ 30
peak value (note)
rms value
peak value (note)
rms value
–
IOL
Output Current Low
mA
+ 15
+ 100
All pins
+ 60
TA
°
C
Operating Temperature
Storage Temperature
– 40 to + 85
Tstg
°
C
–
– 65 to + 150
NOTE: The values for Output Current Low (I ) are calculated as Peak Value ´ Duty .
OL
14-8
S3C7414/P7414/C7424/P7424/C7434/P7434
ELECTRICAL DATA
Table 14-6. S3C7434 D.C. Electrical Characteristics
(TA = – 40 C to + 85 C, VDD = 2.5 V to 5.5 V)
°
°
Parameter
Input High
Symbol
Conditions
Min
Typ
Max
Units
VIH1
0.7 VDD
VDD
All input pins except those specified
–
V
below for V –V
Voltage
IH2 IH3
VIH2
VIH3
VIL1
0.8 VDD
VDD – 0.1
–
VDD
VDD
Ports 0, 1, 3, 6 and RESET
XIN, XOUT
0.3 VDD
Input Low
Voltage
All input pins except those specified
–
V
below for V –V
IL2 IL3
VIL2
VIL3
VOH
0.2 VDD
Ports 0, 1, 3, 6 and RESET
XIN, XOUT
0.1
–
V
DD
= 4.5 V to 5.5 V
VDD – 1.0
Output High
Voltage
–
V
V
IOH = – 1 mA
Ports 0, 2–8
VOL
V
DD
= 3.5 V
Output Low
Voltage
–
0.4
2
3
IOL = 15 mA
Ports 4 and 5 only
IOL = 4 mA
0.2
–
All output ports except ports 4 and 5
VI = VDD
ILIH1
Input High
Leakage Current
–
–
µA
µA
All input pins except those specified
below for I
LIH2
ILIH2
ILIL1
VI = VDD
XIN and XOUT only
20
VI = 0 V
Input Low
–
– 3
Leakage Current
All input pins except XIN and XOUT,
RESET
ILIL2
VI = 0 V
– 20
XIN and XOUT only
ILOH
ILOL
RL1
VO = VDD
Output High
Leakage Current
–
–
–
–
3
µA
µA
kW
All output pins
VO = 0 V
Output Low
Leakage Current
– 3
All output pins
Pull-Up Resistor
25
50
50
100
200
400
800
VI = 0 V; VDD = 5 V except RESET
VI = 0 V; VDD = 3 V except RESET
VI = 0 V; VDD = 5 V; RESET
100
250
500
RL2
Pull-Up Resistor
100
200
kW
VI = 0 V; VDD = 3 V; RESET
14-9
ELECTRICAL DATA
S3C7414/P7414/C7424/P7424/C7434/P7434
Table 14-6. S3C7434 D.C. Electrical Characteristics (Continued)
°
°
(TA = – 40 C to + 85 C, VDD = 2.5 V to 5.5 V)
Parameter Symbol
Conditions
Min
Typ
3.1
2.4
1.5
1.2
1.2
1.1
0.6
0.5
120
100
Max
8.0
5.5
4.0
3.0
2.5
1.8
1.5
1.0
200
150
Units
mA
I
I
I
Supply
6.0MHz
4.19MHz
6.0MHz
4.19MHz
6.0MHz
4.19MHz
6.0MHz
4.19MHz
–
Run mode; VDD = 5.0 V ± 10%
DD1
Current (1)
Crystal oscillator; C1 = C2 = 22pF
V
= 3 V ± 10%
DD
mA
–
–
Idle mode; VDD = 5.0 V ± 10%
DD2
Crystal oscillator; C1 = C2 = 22pF
V
DD
= 3 V ± 10%
Stop mode; VDD = 5.0 V ± 10%
Stop mode; V = 3.0 V ± 10%
mA
DD3
DD
NOTES:
1. D.C. electrical values for Supply current (I
to I
) do not include current drawn through internal pull-up registers,
DD3
DD1
output port drive currents and ADC.
2. The supply current assumes a CPU clock of fx/4.
Table 14-7. S3C7434 Power-On Reset Circuit Characteristics
°
°
(TA = – 40 C to + 85 C, VDD = 2.5 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
VDDH
Power-On Reset
Voltage High
2.5
5.5
V
VDDL
tr
Power-On Reset
Voltage Low
0
2.0
2.2
V
us
s
Power Supply
Voltage Rise Time
10
0.5
(1)
toff
Power Supply
Voltage Off Time
IDDPR
VDD = 5 V ± 10%
VDD = 3 V ± 10%
120
100
200
150
uA
uA
Power-On Reset Circuit
Cunsumption Current (2)
NOTES:
17
1.
2 /fx (= 31.3 ms at fx = 4.19 MHz)
2. Current consumed when power-on reset circuit is provided internally.
14-10
S3C7414/P7414/C7424/P7424/C7434/P7434
ELECTRICAL DATA
Table 14-8. S3C7434 System Clock Oscillator Characteristics
°
°
(TA = – 40 C to + 85 C, VDD = 2.5 V to 5.5 V)
Oscillator
Clock
Parameter
Test Condition
Min Typ Max Units
Configuration
Oscillation frequency (1)
V
DD
= 2.7 V to 5.5 V
Ceramic
Oscillator
0.4
–
6.0
MHz
Xin
Xout
C1
C2
V
DD
V
DD
V
DD
= 2.5 V to 5.5 V
= 3.0 V
0.4
–
–
–
–
4.2
4
Stabilization time (2)
ms
Oscillation frequency (1)
= 2.7 V to 5.5 V
Crystal
Oscillator
0.4
6.0
MHz
Xin
Xout
C1
C2
V
DD
V
DD
V
DD
= 2.5 V to 5.5 V
= 3.0 V
0.4
–
–
–
–
4.2
10
Stabilization time (2)
ms
XIN input frequency (1)
= 2.7 V to 5.5 V
External
Clock
0.4
6.0
MHz
Xin
Xout
V
DD
= 2.5 V to 5.5 V
–
0.4
–
–
4.2
XIN input high and low
83.3
1250
ns
level width (t , t
)
XH XL
Xin
Xout
VDD = 5 V
RC
Oscillator
Oscillation frequency
limitation
–
4
–
MHz
R = 8.2 KW
R
NOTES:
1. Oscillation frequency and Xin input frequency data are for oscillator characteristics only.
2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is
terminated.
14-11
ELECTRICAL DATA
S3C7414/P7414/C7424/P7424/C7434/P7434
Main Oscillator Frequency
(Divided by 4)
CPU CLOCK
1.5 MHz
6 MHz
1.05 MHz
0.75 MHz
4.2 MHz
3 MHz
15.6 kHz
1
2
3
4
5
6
1.8
2.7
2.5
5.5
SUPPLY VOLTAGE (V)
CPU CLOCK = 1/n x oscillator frequency (n = 4, 8 or 64)
Figure 14-2. S3C7434 Standard Operating Voltage Range
14-12
S3C7414/P7414/C7424/P7424/C7434/P7434
ELECTRICAL DATA
Table 14-9. S3C7434 A.C. Electrical Characteristics
(TA = – 40 C to + 85 C, VDD = 2.5 V to 5.5 V)
°
°
Parameter
Symbol
Conditions
Min
Typ
Max
Units
tCY
VDD = 2.7 V to 5.5 V
Instruction Cycle
Time
0.67
–
64
µs
fTI0
VDD = 2.7 V to 5.5 V
TCL0/1 Input
Frequency
0
–
–
–
1.5
–
MHz
µs
tTIH0, tTIL0 VDD = 2.7 V to 5.5 V
TCL0/1 Input
High, Low Width
0.48
800
tKCY
tKH, tKL
tSIK
VDD = 2.7 V to 5.5 V
–
ns
SCK Cycle Time
External SCK source
670
325
Internal SCK source
VDD = 2.7 V to 5.5 V
External SCK source
–
–
–
–
–
–
ns
ns
ns
ns
SCK High, Low
Width
tKCY/2 – 50
100
Internal SCK source
VDD = 2.7 V to 5.5 V
External SCK source
SI Setup Time to
SCK High
150
400
Internal SCK source
VDD = 2.7 V to 5.5 V
External SCK source
tKSI
SI Hold Time to
–
SCK High
400
–
Internal SCK source
VDD = 2.7 V to 5.5 V
External SCK source
tKSO
Output Delay for
300
SCK to SO
250
–
Internal SCK source
tINTH
tINTL
tRSL
,
Interrupt Input
INT0
–
–
µs
µs
(NOTE)
10
High, Low Width
INT1, INT2, INT4, KS0–KS3
Input
10
–
RESET Input
Low Width
NOTE: Minimum value for INT0 is based on a clock of 2tCY or 128/fx as assigned by the IMOD0 register setting.
14-13
ELECTRICAL DATA
S3C7414/P7414/C7424/P7424/C7434/P7434
Table 14-10. A/D Converter Electrical Characteristics
°
°
(TA = – 10 C to + 70 C, VDD = 3.5 V to 5.5 V, VSS = AVSS = 0 V)
Parameter
Resolution
Symbol
Condition
Min
8
Typ
8
Max
8
Units
bit
–
–
–
Absolute accuracy (1)
Conversion time (2)
2.5 V < AVREF < VDD
–
–
LSB
± 1.5
–
96/fx (3)
–
tCON
–
–
–
–
AVSS
–
µs
V
VIAN
RAN
AVREF
Analog input voltage
Analog input impedance
1000
–
MW
NOTES:
1. Absolute accuracy does not include the quantization error (± 1/2 LSB).
2. Conversion time is the time required from the moment a conversion operation starts until it ends (EOC = 0).
3. 'fx' is the abbreviation for system clock.
Table 14-11. Input/Output Capacitance
°
(TA = 25 C, VDD = 0 V )
Parameter
Input
Capacitance
Symbol
Condition
Min
Typ
Max
Units
CIN
f = 1 MHz; Unmeasured pins
are returned to VSS
–
–
15
pF
COUT
CIO
Output
Capacitance
–
–
–
–
15
15
pF
pF
I/O Capacitance
Table 14-12. RAM Data Retention Supply Voltage in Stop Mode
°
°
(T = – 40 C to + 85 C)
A
Parameter
Symbol
Conditions
Min
1.8
–
Typ
–
Max
Unit
V
VDDDR
Data retention supply voltage
Data retention supply current
Release signal set time
–
–
–
5.5
10
–
IDDDR
tSREL
tWAIT
0.1
–
µA
ms
ms
0
Oscillation stabilization time (1)
217/fx
When released by
–
–
RESET
(2)
When released by
interrupt
–
–
ms
NOTES:
1. During oscillation stabilization time, CPU operation must be stopped to avoid unstable operation upon oscillation start.
2. The basic timer causes a delay of 217/fx after a reset.
14-14
S3C7414/P7414/C7424/P7424/C7434/P7434
ELECTRICAL DATA
TIMING WAVEFORMS
INTERNAL RESET
OPERATION
IDLE MODE
STOP MODE
OPERATING
MODE
DATA RETENTION MODE
V
DD
VDDDR
EXECUTION OF
STOP INSTRUCTION
RESET
tWAIT
tSREL
Figure 14-3. Stop Mode Release Timing When Initiated By RESET
IDLE MODE
NORMAL
STOP MODE
OPERATING
MODE
DATA RETENTION
V
DD
VDDDR
tSREL
EXECUTION OF
STOP INSTRUCTION
tWAIT
POWER-DOWN MODE TERMINATING
(INTERRUPT REQUEST)
Figure 14-4. Stop Mode Release Timing When Initiated By Interrupt Request
14-15
ELECTRICAL DATA
S3C7414/P7414/C7424/P7424/C7434/P7434
0.8 V
0.2 V
0.8 V
DD
DD
DD
MEASUREMENT
POINTS
0.2 V
DD
Figure 14-5. A.C. Timing Measurement Points (Except for XIN)
1 / f
x
t
t
XH
XL
X
IN
V
– 0.5 V
DD
0.4 V
Figure 14-6. Clock Timing Measurement at XIN
1 / f
TI0
t
t
TIH0
TIL0
TCL0
0.8 V
0.2 V
DD
DD
Figure 14-7. TCL0/1 Timing
14-16
S3C7414/P7414/C7424/P7424/C7434/P7434
ELECTRICAL DATA
t
RSL
RESET
0.2 V
DD
Figure 14-8. Input Timing for RESET Signal
t
t
INTL
INTH
INT0, 1, 2, 4
KS0 to KS3
0.8 V
0.2 V
DD
DD
Figure 14-9. Input Timing for External Interrupts and Quasi-Interrupts
14-17
ELECTRICAL DATA
S3C7414/P7414/C7424/P7424/C7434/P7434
t
t
r
off
V
V
V
DD
DDH
DDL
Figure 14-10. S3C7434 Power-On RESET Timing
t
KCY
t
t
KH
KL
0.8 V
0.2 V
DD
DD
SCK
t
t
KSI
SIK
0.8 V
0.2 V
DD
DD
SI
INPUT DATA
t
KSO
SO
OUTPUT DATA
Figure 14-11. Serial Data Transfer Timing
14-18
S3C7414/P7414/C7424/P7424/C7434/P7434
MECHANICAL DATA
15 MECHANICAL DATA
This section contains the following information about the device package:
— Package dimensions in millimeters
— Pad diagram
#42
#22
°
0-15
42-SDIP-600
#1
#21
39.50 MAX
39.10 ± 0.2
0.50 ± 0.1
1.00 ± 0.1
(1.77)
1.778
NOTE: Dimensions are in millimeters.
Figure 15-1. 42-SDIP-600 Package Dimensions
15-1
MECHANICAL DATA
S3C7414/P7414/C7424/P7424/C7434/P7434
13.20 ± 0.3
10.00 ± 0.2
0-8°
0.15 -+00..1005
44-QFP-1010
0.10 MAX
#44
0.05 MIN
2.05 ± 0.10
2.30 MAX
+0.10
- 0.05
#1
0.35
(1.00)
0.80
NOTE: Dimensions are in millimeters.
Figure 15-2. 44-QFP-1010 Package Dimensions
15-2
S3C7414/P7414/C7424/P7424/C7434/P7434
MECHANICAL DATA
#30
#16
0-15
°
30-SDIP-400
#1
#15
27.88 MAX
27.48 ± 0.2
± 0.1
0.56
1.778
(1.30)
1.12 ± 0.1
NOTE: Dimensions are in millimeters.
Figure 15-3. 30-SDIP-400 Package Dimensions
15-3
MECHANICAL DATA
S3C7414/P7414/C7424/P7424/C7434/P7434
0-8°
#28
#15
28-SOP-375
+0.10
- 0.05
#1
#14
0.15
18.02 MAX
17.62 ± 0.2
0.10 MAX
1.27
± 0.1
0.41
(0.56)
NOTE: Dimensions are in millimeters.
Figure 15-4. 28-SOP-375 Package Dimensions
15-4
S3C7414/P7414/C7424/P7424/C7434/P7434
S3P7414/P7424/P7434 OTP
16 S3P7414/P7424/P7434 OTP
OVERVIEW
The S3P7414/P7424/P7434 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of
the S3C7414/C7424/C7434 microcontroller. It has an on-chip OTP ROM instead of masked ROM. Samsung¢s
own serial protocol used for OTP program pin information regarding OTP program can be referred OTP pin
description.
The S3P7414/P7424/P7434 is fully compatible with the S3C7414/C7424/C7434, in function, in D.C. electrical
characteristics and in pin configuration. Because of its simple programming requirements, the
S3P7414/P7424/P7434 is ideal for use as an evaluation chip for the S3C7414/C7424/C7434.
16-1
S3P7414/P7424/P7434 OTP
S3C7414/P7414/C7424/P7424/C7434/P7434
P8.2
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
P2.0/AD0
P2.1/AD1
P2.2/AD2
P2.3/AD3
P3.0/AD4
1
2
3
4
5
6
7
8
P8.1/TCLO0
P8.0/TCL0
P7.3
P7.2
P7.1
P3.1/AD5
P7.0
AVREF
P3.2/CLO/TCL1
SDAT/P3.3/PWM/TCLO1
P6.3/KS3
P6.2/KS2
P6.1/KS1
P6.0/KS0
P1.3/INT4
P1.2/INT2
P1.1/INT1
P1.0/INT0
P0.3/BUZ
P0.2/SI
P0.1/SO
P0.0/SCK
P5.3
9
S3P7414
SCLK/P4.0
VDD/VDD
VSS/VSS
XOUT
XIN
VPP/TEST
P4.1
10
11
12
13
14
15
16
17
18
19
20
21
(42-SDIP)
P4.2
RESET/RESET
P4.3
P5.0
P5.1
P5.2
NOTE:
The bolds indicate an OTP pin name.
Figure 16-1. S3P7414 Pin Assignments (42-SDIP)
16-2
S3C7414/P7414/C7424/P7424/C7434/P7434
S3P7414/P7424/P7434 OTP
P7.2
P7.1
P7.0
33
32
31
30
29
28
27
26
25
24
23
AVREF
P3.2/CLO/TCL1
SDAT/P3.3/PWM/TCLO1
1
2
3
4
5
6
7
8
P6.3/KS3
P6.2/KS2
P6.1/KS1
P6.0/KS0
P1.3/INT4
P1.2/INT2
P1.1/INT1
P1.0/INT0
SCLK/P4.0
VDD/VDD
VSS/VSS
XOUT
XIN
VPP/TEST
P4.1
S3P7414
(44-QFP)
9
10
11
P4.2
NOTE:
The bolds indicate an OTP pin name.
Figure 16-2. S3P7414 Pin Assignments (44-QFP)
16-3
S3P7414/P7424/P7434 OTP
S3C7414/P7414/C7424/P7424/C7434/P7434
VDD/VDD
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
VSS/VSS
1
2
3
4
5
6
7
8
P4.0/SCLK
P3.3/PWM/TCLO1/SDAT
P3.2/CLO/TCL1
AVREF
XOUT
XIN
VPP/TEST
P4.1
NC
P4.2
RESET/RESET
NC
S3P7424
P2.3/AD3
P2.2/AD2
P2.1/AD1
P2.0/AD0
P1.2/INT2
P1.1/INT1
P1.0/INT0
P0.3/BUZ
P0.2/SI
P4.3
P5.0
P5.1
P5.2
9
(30-SDIP)
10
11
12
13
14
15
P5.3
P0.0/SCK
P0.1/SO
NOTE:
The bolds indicate an OTP pin name.
Figure 16-3. S3P7424 Pin Assignments (30-SDIP)
VDD/VDD
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VSS/VSS
XOUT
XIN
VPP/TEST
P4.1
1
2
3
4
5
6
7
8
P4.0/SCLK
P3.3/PWM/TCLO1/SDAT
P3.2/CLO/TCL1
AVREF
P2.3/AD3
P2.2/AD2
P2.1/AD1
P2.0/AD0
P1.2/INT2
P1.1/INT1
P1.0/INT0
P0.3/BUZ
P4.2
RESET/RESET
P4.3
S3P7424
P5.0
P5.1
P5.2
P5.3
9
(28-SOP)
10
11
12
13
14
P0.0/SCK
P0.1/SO
P0.2/SI
NOTE:
The bolds indicate an OTP pin name.
Figure 16-4. S3P7424 Pin Assignments (28-SOP)
16-4
S3C7414/P7414/C7424/P7424/C7434/P7434
S3P7414/P7424/P7434 OTP
P8.2
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
P2.0/AD0
P2.1/AD1
P2.2/AD2
P2.3/AD3
P3.0/AD4
P3.1/AD5
AVREF
1
2
3
4
5
6
7
8
P8.1/TCLO0
P8.0/TCL0
P7.3
P7.2
P7.1
P7.0
P6.3/KS3
P6.2/KS2
P6.1/KS1
P6.0/KS0
P1.3/INT4
P1.2/INT2
P1.1/INT1
P1.0/INT0
P0.3/BUZ
P0.2/SI
P3.2/CLO/TCL1
SDAT/P3.3/PWM/TCLO1
SCLK/P4.0
VDD/VDD
9
S3P7434
10
11
12
13
14
15
16
17
18
19
20
21
VSS/VSS
(42-SDIP)
XOUT
XIN
VPP/TEST
P4.1
P4.2
RESET/RESET
P4.3
P0.1/SO
P0.0/SCK
P5.3
P5.0
P5.1
P5.2
NOTE:
The bolds indicate an OTP pin name.
Figure 16-5. S3P7434 Pin Assignments (42-SDIP)
16-5
S3P7414/P7424/P7434 OTP
S3C7414/P7414/C7424/P7424/C7434/P7434
P7.2
P7.1
P7.0
33
32
31
30
29
28
27
26
25
24
23
AVREF
P3.2/CLO/TCL1
SDAT/P3.3/PWM/TCLO1
1
2
3
4
5
6
7
8
P6.3/KS3
P6.2/KS2
P6.1/KS1
P6.0/KS0
P1.3/INT4
P1.2/INT2
P1.1/INT1
P1.0/INT0
SCLK/P4.0
VDD/VDD
VSS/VSS
XOUT
XIN
VPP/TEST
P4.1
S3P7434
(44-QFP)
9
10
11
P4.2
NOTE:
The bolds indicate an OTP pin name.
Figure 16-6. S3P7434 Pin Assignments (44-QFP)
16-6
S3C7414/P7414/C7424/P7424/C7434/P7434
S3P7414/P7424/P7434 OTP
Table 16-1. Pin Descriptions of S3P7414/P7434 Used to Read/Write the EPROM
Main Chip
Pin Name
P3.3
During Programming
I/O
Pin Name
Pin No.
Function
SDAT
9 (3)
I/O
Serial data pin. Output port when reading and input
port when writing. Can be assigned as a Input /
push-pull output port.
P4.0
SCLK
10 (4)
15 (9)
I/O
I
Serial clock pin. Input only pin.
VPP (TEST)
TEST
Power supply pin for EPROM cell writing (indicates
that OTP enters into the writing mode). When 12.5
V is applied, OTP is in writing mode and when 5 V
is applied, OTP is in reading mode. (Option)
18 (12)
I
I
Chip initialization
RESET
RESET
VDD/VSS
VDD/VSS
Logic power supply pin. VDD should be tied to +5 V
during programming.
11/12 (5/6)
NOTE: Parentheses indicate 44-QFP pin number.
Table 16-2. Pin Descriptions of S3P7424 Used to Read/Write the EPROM
During Programming
Main Chip
Pin Name
P3.3
Pin Name
Pin No.
I/O
Function
SDAT
28 (26)
I/O
Serial data pin. Output port when reading and input
port when writing. Can be assigned as a Input /
push-pull output port.
P4.0
SCLK
29 (27)
4 (4)
I/O
I
Serial clock pin. Input only pin.
VPP (TEST)
TEST
Power supply pin for EPROM cell writing (indicates
that OTP enters into the writing mode). When 12.5
V is applied, OTP is in writing mode and when 5 V
is applied, OTP is in reading mode. (Option)
7 (7)
I
I
Chip initialization
RESET
RESET
VDD/VSS
VDD/VSS
Logic power supply pin. VDD should be tied to +5 V
during programming.
30/1 (28/1)
NOTE: Parentheses indicate 28-SOP pin number.
16-7
S3P7414/P7424/P7434 OTP
S3C7414/P7414/C7424/P7424/C7434/P7434
Table 16-3. Comparison of S3P7414/P7424 and S3C7414/C7424 Features
Characteristic
Program Memory
Operating Voltage (VDD
S3P7414/P7424
4 K byte EPROM
S3C7414/C7424
4 K byte mask ROM
1.8 V to 5.5 V
)
1.8 V to 5.5 V
VDD = 5 V, VPP(TEST)=12.5V
OTP Programming Mode
Pin Configuration
42 SDIP, 44 QFP, 30 SDIP, 28 SOP
User Program 1 time
42 SDIP, 44 QFP, 30 SDIP, 28 SOP
Programmed at the factory
EPROM Programmability
Table 16-4. Comparison of S3P7434 and S3C7434 Features
S3P7434
Characteristic
Program Memory
Operating Voltage (VDD
S3C7434
4 K byte EPROM
2.5 V to 5.5 V
4 K byte mask ROM
2.5 V to 5.5 V
)
VDD = 5 V, VPP(TEST)=12.5V
OTP Programming Mode
Pin Configuration
42 SDIP, 44 QFP
42 SDIP, 44 QFP
EPROM Programmability
User Program 1 time
Programmed at the factory
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the VPP(TEST) pin of the S3P7414/P7424/P7434, the EPROM programming mode is
entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins
listed in Table 16-4 below.
Table 16-5. Operating Mode Selection Criteria
VDD
VPP
(TEST)
REG/
MEM
Address
(A15-A0)
R/W
Mode
5 V
5 V
0
0
0
1
0000H
0000H
0000H
0E3FH
1
0
1
0
EPROM read
12.5 V
12.5 V
12.5 V
EPROM program
EPROM verify
EPROM read protection
NOTE: "0" means Low level; "1" means High level.
16-8
S3C7414/P7414/C7424/P7424/C7434/P7434
S3P7414/P7424/P7434 OTP
START
Address= First Location
V
=5V, V =12.5V
PP
DD
x = 0
Program One 1ms Pulse
Increment X
YES
x = 10
NO
FAIL
FAIL
NO
Verify Byte
Verify 1 Byte
Last Address
Increment Address
V
= V = 5 V
PP
DD
FAIL
Compare All Byte
PASS
Device Failed
Device Passed
Figure 16-7. OTP Programming Algorithm
16-9
S3P7414/P7424/P7434 OTP
S3C7414/P7414/C7424/P7424/C7434/P7434
Table 16-6. S3P7414/P7424 D.C. Electrical Characteristics
°
°
(TA = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
Parameter Symbol Conditions
Min
Typ
3.0
2.3
1.4
1.1
1.1
1.0
0.5
0.4
0.1
0.1
Max
8.0
5.5
4.0
3.0
2.5
1.8
1.5
1.0
5.0
3.0
Units
mA
IDD1
IDD2
IDD3
Supply
6.0MHz
4.19MHz
6.0MHz
4.19MHz
6.0MHz
4.19MHz
6.0MHz
4.19MHz
–
Run mode; VDD = 5.0 V ± 10%
Crystal oscillator; C1=C2=22pF
VDD = 3 V ± 10%
Current (1)
mA
–
–
Idle mode; V
= 5.0 V ± 10%
DD
Crystal oscillator; C1=C2=22pF
= 3 V ± 10%
V
DD
Stop mode; VDD = 5.0 V ± 10%
Stop mode; VDD = 3.0 V ± 10%
mA
NOTES:
1. D.C. electrical values for Supply current (I
to I
) do not include current drawn through internal pull-up registers,
DD3
DD1
output port drive currents and ADC.
2. The supply current assumes a CPU clock of fx/4.
Main Oscillator Frequency
(Divided by 4)
CPU CLOCK
1.5 MHz
6 MHz
1.05 MHz
0.75 MHz
4.2 MHz
3 MHz
15.6 kHz
1
2
3
4
5
6
1.8
2.7
5.5
SUPPLY VOLTAGE (V)
CPU CLOCK = 1/n x oscillator frequency (n = 4, 8 or 64)
Figure 16-8. S3P7414/P7424 Standard Operating Voltage Range
16-10
S3C7414/P7414/C7424/P7424/C7434/P7434
S3P7414/P7424/P7434 OTP
Table 16-7. S3P7434 D.C. Electrical Characteristics
(TA = – 40 C to + 85 C, VDD = 2.5 V to 5.5 V)
Parameter Symbol Conditions
= 5.0 V ± 10%
°
°
Min
Typ
3.1
2.4
1.5
1.2
1.2
1.1
0.6
0.5
120
100
Max
8.0
5.5
4.0
3.0
2.5
1.8
1.5
1.0
200
150
Units
mA
I
I
I
Supply
6.0MHz
4.19MHz
6.0MHz
4.19MHz
6.0MHz
4.19MHz
6.0MHz
4.19MHz
–
Run mode; V
DD
DD1
DD2
DD3
Current (1)
Crystal oscillator; C1=C2=22pF
= 3 V ± 10%
V
DD
mA
–
–
Idle mode; V
= 5.0 V ± 10%
DD
Crystal oscillator; C1=C2=22pF
= 3 V ± 10%
V
DD
Stop mode; V
Stop mode; V
= 5.0 V ± 10%
= 3.0 V ± 10%
mA
DD
DD
NOTES:
1. D.C. electrical values for Supply current (I
to I
) do not include current drawn through internal pull-up registers,
DD3
DD1
output port drive currents and ADC.
2. The supply current assumes a CPU clock of fx/4.
Main Oscillator Frequency
(Divided by 4)
CPU CLOCK
1.5 MHz
6 MHz
1.05 MHz
15.6 kHz
4.2 MHz
1
2
3
4
5
6
2.5
5.5
SUPPLY VOLTAGE (V)
CPU CLOCK = 1/n x oscillator frequency (n = 4, 8 or 64)
Figure 16-9. S3P7434 Standard Operating Voltage Range
16-11
S3P7414/P7424/P7434 OTP
S3C7414/P7414/C7424/P7424/C7434/P7434
NOTES
16-12
相关型号：
S3P7515
The S3C7515/P7515 single-chip CMOS microcontroller has been designed for high-performance using Samsungs newest 4-bit CPU core, SAM47
SAMSUNG
S3P7515-AT
Microcontroller, 4-Bit, OTPROM, SAM47 CPU, 6MHz, CMOS, PDIP64, 0.750 INCH, SDIP-64
SAMSUNG
S3P7515-QT
Microcontroller, 4-Bit, OTPROM, SAM47 CPU, 6MHz, CMOS, PQFP64, 14 X 20 MM, QFP-64
SAMSUNG
S3P7528
The S3C7524/C7528/C7534/C7538 single-chip CMOS microcontroller has been designed for high-performance using SAM 47
SAMSUNG
S3P7538
The S3C7524/C7528/C7534/C7538 single-chip CMOS microcontroller has been designed for high-performance using SAM 47
SAMSUNG
S3P7544-AM
Microcontroller, 4-Bit, OTPROM, SAM47 CPU, 6MHz, CMOS, PDIP24, 0.300 INCH, SDIP-24
SAMSUNG
S3P7544-SM
Microcontroller, 4-Bit, OTPROM, SAM47 CPU, 6MHz, CMOS, PDSO24, 0.375 INCH, SOP-24
SAMSUNG
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