S3P7544 [SAMSUNG]
Single-chip CMOS microcontroller, 512 x 4-bit RAM, 4096 x 8-bit ROM; 单芯片CMOS微控制器， 512 ×4位的RAM ， 4096 ×8位ROM
| 型号： | S3P7544 |
| 厂家： | 
SAMSUNG |
| 描述： | Single-chip CMOS microcontroller, 512 x 4-bit RAM, 4096 x 8-bit ROM |
| 文件： | 总27页 (文件大小：206K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S3C7544/P7544
PRODUCT OVERVIEW
1
PRODUCT OVERVIEW
OVERVIEW
The S3C7544 single-chip CMOS microcontroller is designed for high-performance using Samsung's newest
4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers).
With a versatile 8-bit timer/counter and a D/A converter, the S3C7544 offers an excellent design solution for a
wide variety of telecommunication applications.
Up to 17 pins of the 24-pin SDIP package can be dedicated to I/O. Four vectored interrupts provide fast response
to internal and external events. In addition, the S3C7544’s advanced CMOS technology has realized substantially
lower power consumption with a wide operating voltage range — all at a substantially lower cost.
OTP
The S3C7544 microcontroller is also available in OTP (One Time Programmable) version, S3P7544.
S3P7544 microcontroller has an on-chip 4-Kbyte one-time-programmable EPROM instead of masked ROM. The
S3P7544 is comparable to S3C7544, both in function and in pin configuration.
1-1
PRODUCT OVERVIEW
S3C7544/P7544
FEATURES SUMMARY
Memory
Bit Sequential Carrier
·
·
512 ´ 4-bit RAM
4096 ´ 8-bit ROM
·
Supports 16-bit serial data transfer in arbitrary
format
Power-Down Modes
I/O Pins
·
·
Idle mode (only CPU clock stops)
Stop mode (system clock stops)
·
·
17 pins I/O
N-channel open-drain I/O: 8 pins
Oscillation Sources
8-Bit Basic Timer
·
·
·
Crystal, or ceramic for system clock
Crystal, ceramic: 0.4–6.0 MHz
·
·
Programmable interval timer
Watchdog timer
CPU clock divider circuit (by 4, 8, or 64)
Interval 8-Bit Timer/Counter
Instruction Execution Times
·
·
·
Programmable interval timer
·
·
0.95, 1.91, and 15.3 ms at 4.19 MHz
0.67, 1.33, 10.7 ms at 6.0 MHz
External event counter function
Timer/counter clock output to TCLO0 pin
Operating Temperature
Buzzer Output
°
·
– 40 C to 85 °C
·
Four frequency output to BUZ pin
Operating Voltage Range
D/A Converter
·
·
1.8 V to 5.5 V (at 3 MHz)
2.7 V to 5.5 V (at 6 MHz)
·
8-bit D/A converter
Interrupts
Package Types
·
·
·
Two external interrupt vectors
·
·
24-pin SOP-375
24-pin SDIP-300
Two internal interrupt vectors
One quasi-interrupt
Memory-Mapped I/O Structure
·
Data memory bank 15
1-2
S3C7544/P7544
PRODUCT OVERVIEW
BLOCK DIAGRAM
Watchdog
Timer
INT0, INT1
X
X
OUT
RESET
IN
Basic
Timer
8-bit
Timer/
Counter
Interrupt
Stack
Control
Block
Clock
Pointer
Buzzer
I/O Port 0
I/O Port 1
I/O Port 2
D/A
Converter
DAO
Program
Counter
P0.0/INT0
P0.1/INT1
P0.2/KS0
P0.3/KS1
Internal
Interrupts
Program
Status
Word
P4.0–P4.3
P5.0–P5.3
I/O Port 4
I/O Port 5
Instruction Decoder
Arithmetic Logic Unit
P1.0/TCL0
P1.1/TCLO0
P1.2/CLO
P1.3/BUZ
Flags
P2.0
512 x 4-bit
Data
Memory
4 K byte
Program
Memory
Figure 1-1. S3C7544 Simplified Block Diagram
1-3
PRODUCT OVERVIEW
S3C7544/P7544
PIN ASSIGNMENTS
V
V
DD
P5.3
P5.2
P5.1
P5.0
P4.3
P4.2
P4.1
P4.0
P2.0
P1.3/BUZ
P1.2/CLO
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
16
15
14
13
SS
X
OUT
X
IN
TEST
P0.0/INT0
DAO
P0.1/INT1
RESET
P0.2/KS0
P0.3/KS1
P1.0/TCL0
P1.1/TCLO0
9
10
11
12
Figure 1-2. S3C7544 Pin Assignment Diagrams
1-4
S3C7544/P7544
PRODUCT OVERVIEW
PIN DESCRIPTIONS
Table 1-1. S3C7544 Pin Descriptions
Description
Pin Name
Pin Type
Share Pin
P0.0
P0.1
P0.2
P0.3
I
4-bit I/O port. 1- or 4-bit read/write and test is possible.
Pull-up resistors are assignable to input pins by software and are
automatically disabled for output pins. Pins are individually
configurable as input or output.
INT0
INT1
KS0
KS1
P1.0
P1.1
P1.2
P1.3
I/O
4-bit I/O port. 1- or 4-bit read/write and test is possible.
Pull-up resistors are assignable to input pins by software and are
automatically disabled for output pins. Pins are individually
configurable as input or output.
TCL0
TCLO0
CLO
BUZ
P2.0
I/O
I/O
1-bit I/O port. 1- or 4-bit read/write and test is possible.
Pull-up resistors are assignable to input pins by software and are
automatically disabled for output pins.
–
P4.0–P4.3
P5.0–P5.3
4-bit I/O port. 1- or 4-bit read/write and test is possible.
Pins are individually configurable as input or output.
Pull-up resistors are assignable to input pins by software and are
automatically disabled for output pins.
–
The N-channel open drain or push-pull output can be selected by
software (1-bit unit).
INT0
INT1
I/O
I/O
I/O
External interrupts with rising/falling edge detection
External interrupts with rising/falling edge detection
Quasi-interrupt input with falling edge detection
P0.0
P0.1
KS0
KS1
P0.2
P0.3
TCL0
TCLO0
CLO
I/O
I/O
I/O
I/O
O
External clock input for timer/counter
Timer/counter clock output
P1.0
P1.1
P1.2
P1.3
–
CPU clock output
BUZ
0.5, 1, 2, or 4 kHz frequency output at 4.19 MHz for buzzer sound
8-bit D/A converter output
DAO
VDD
–
Main power supply
–
VSS
–
I
Ground
–
–
Reset signal
RESET
TEST
I
Chip test input pin. Hold GND when the device is operating.
Crystal, ceramic oscillator signal for system clock
–
–
XIN, XOUT
–
1-5
PRODUCT OVERVIEW
S3C7544/P7544
Table 1-2. Overview of S3C7544 Pin Data
SDIP Pin Numbers
Share Pins
I/O Type
Reset Value
Circuit Type
VSS
–
–
–
–
–
–
XOUT, XIN
–
–
TEST
–
INT0, INT1
–
I
I/O
I
–
Input
–
–
D-4
B
P0.0, P0.1
RESET
P0.2
P0.3
KS0
KS1
I/O
Input
D-4
P1.0
P1.1
P1.2
P1.3
TCL0
TCLO0
CLO
I/O
Input
D-2
BUZ
P2.0
–
–
–
–
–
I/O
O
Input
Output
Input
Input
–
D-2
–
DAO
P4.0–P4.3
P5.0–P5.3
VDD
I/O
I/O
–
E-2
E-2
–
1-6
S3C7544/P7544
PRODUCT OVERVIEW
PIN CIRCUIT DIAGRAMS
V
V
DD
DD
P-Channel
Out
P-Channel
Data
IN
N-Channel
-
N Channel
Output
Disable
Figure 1-3. Pin Circuit Type A
Figure 1-5. Pin Circuit Type C
V
DD
V
DD
Pull-up
Resistor
Pull-up
Enable
P-Channel
Data
Circuit
Type C
IN
In/Out
Output
Disable
Schmitt Trigger
Figure 1-6. Pin Circuit Type D-2
Figure 1-4. Pin Circuit Type B
1-7
PRODUCT OVERVIEW
S3C7544/P7544
V
DD
V
DD
Pull-Up
Resistor
PNE
V
DD
Resistor
Enable
Pull-up
Enable
P-Channel
In/Out
Data
Data
Circuit
Type C
In/Out
Output
Disable
Output
Disable
Figure 1-8. Pin Circuit Type E-2
Figure 1-7. Pin Circuit Type D-4
1-8
S3C7544/P7544
ELECTRICAL DATA
14 ELECTRICAL DATA
OVERVIEW
In this section, S3C7544 electrical characteristics are presented in tables and graphs. The information is
arranged in the following order:
Standard Electrical Characteristics
— Absolute maximum ratings
— D.C. electrical characteristics
— Main system clock oscillator characteristics
— Subsystem clock oscillator characteristics
— I/O capacitance
— A.C. electrical characteristics
— Operating voltage range
Miscellaneous Timing Waveforms
— A.C timing measurement point
— Clock timing measurement at X
in
— Clock timing measurement at XT
— TCL timing
in
— Input timing for RESET
— Input timing for external interrupts
— Serial data transfer timing
Stop Mode Characteristics and Timing Waveforms
— RAM data retention supply voltage in stop mode
— Stop mode release timing when initiated by RESET
— Stop mode release timing when initiated by an interrupt request
14-1
ELECTRICAL DATA
S3C7544/P7544
Table 14-1. Absolute Maximum Ratings
°
(T = 25 C)
A
Parameter
Symbol
Conditions
Rating
Units
VDD
VI
Supply Voltage
Input Voltage
–
– 0.3 to + 6.5
– 0.3 to VDD + 0.3
V
All I/O ports
V
V
VO
IOH
– 0.3 to VDD + 0.3
– 5
Output Voltage
Output Current High
–
One I/O port active
mA
All I/O ports active
One I/O port active
– 35
IOL
Output Current Low
+ 30 (peak)
mA
+ 15 (note)
+ 100 (peak)
+ 60 (note)
All I/O ports active
TA
°
Operating Temperature
Storage Temperature
–
–
– 40 to + 85
C
Tstg
°
C
– 65 to + 150
NOTE: The values for output current low (I ) are calculated as peak value ´ Duty .
OL
Table 14-2. D.C. Electrical Characteristics
°
°
(T = – 40 C to + 85 C, V
= 1.8 V to 5.5 V)
DD
A
Parameter
Symbol
Conditions
Min
Typ
Max
Units
VIH1
All input pins except VIH2–VIH3
0.7 VDD
VDD
Input High
Voltage
–
V
VIH2
VIH3
VIL1
0.8 VDD
VDD – 0.1
–
VDD
VDD
–
–
–
P0 and RESET
XIN and XOUT
All input pins except VIH2–VIH3
0.3 VDD
Input Low
Voltage
V
VIL2
VIL3
0.2 VDD
0.1
P0 and RESET
XIN and XOUT
14-2
S3C7544/P7544
ELECTRICAL DATA
Table 14-2. D.C. Electrical Characteristics (Continued)
°
°
(TA = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
VDD = 4.5 V to 5.5 V
IOH = – 1 mA
Min
Typ
Max
Units
VOH
VDD – 1.0
Output High
Voltage
–
–
V
VOL1
VOL2
ILIH1
VDD = 4.5 V to 5.5 V
IOL = 15 mA
Output Low
Voltage
–
–
2
V
Ports 4, 5
VDD = 1.8 V to 5.5 V
IOL = 1.6 mA
0.4
2
VDD = 4.5V to 5.5 V
I
= 4 mA
OL
All out ports except ports 4, 5
VDD = 1.8 V to 5.5 V
IOL = 1.6 mA
0.6
3
VIN = VDD
All input pins except XIN and XOUT
Input High
Leakage
Current
–
–
–
–
mA
mA
ILIH2
VIN = VDD
XIN and XOUT
20
ILIL1
V
IN
= 0 V
Input Low
Leakage
Current
– 3
All input pins except XIN, XOUT
and RESET
ILIL2
VIN = 0 V
XIN and XOUT
– 20
3
ILOH
VO = VDD
Output High
Leakage
Current
–
–
–
–
mA
mA
kW
All output pins
ILOL
VO = 0 V
Output Low
Leakage
Current
– 3
All output pins
RL1
VDD = 5 V; V = 0 V
I
Pull-up
25
45
100
Resistor
except
RESET
VDD = 3 V
50
90
200
400
RL2
100
220
VDD = 5 V; V = 0 V; RESET
I
VDD = 3 V
200
450
800
14-3
ELECTRICAL DATA
S3C7544/P7544
Table 14-2. D.C. Electrical Characteristics (Concluded)
°
°
(TA = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
mA
IDD1
Supply
6.0MHz
–
3.4
10.0
Run mode; VDD = 5.0 V ± 10%
Current (1)
(DAC on) Crystal oscillator; C1 = C2 = 22pF
4.19MHz
6.0MHz
2.7
2.3
8.0
8.0
mA
mA
IDD2
–
–
–
Run mode; VDD = 5.0 V ± 10%
(DAC off) Crystal oscillator; C1 = C2 = 22pF
4.19MHz
6.0MHz
1.7
1.1
5.5
4.0
VDD = 3 V ± 10%
4.19MHz
6.0MHz
0.8
0.7
3.0
2.5
IDD3
Idle mode; VDD = 5.0 V ± 10%
Crystal oscillator; C1 = C2 = 22pF
4.19MHz
6.0MHz
0.5
0.3
1.8
1.5
VDD = 3 V ± 10%
4.19MHz
0.2
0.2
1.0
3.0
IDD4
Stop mode; VDD = 5.0 V ± 10%
mA
0.1
2.0
Stop mode; VDD = 3.0 V ± 10%
NOTES:
1. D.C. electrical values for supply current (I
to I
) do not include the current drawn through internal pull-up
DD3
DD1
resistors.
2.
I
typical values are measured when DADATA register value is 055H.
DD1
Main Osc. Freq.
6 MHz
CPU CLOCK
1.5 MHz
0.75 MHz
3 MHz
15.625 kHz
400 kHz
7
1.8
2.7
1
2
3
4
5
6
SUPPLY VOLTAGE (V)
CPU CLOCK = 1/n x oscillator frequency (n = 4, 8 or 64)
Figure 14-1. Standard Operating Voltage Range
14-4
S3C7544/P7544
ELECTRICAL DATA
Table 14-3. Oscillators Characteristics
°
°
(TA = – 40 C + 85 C, VDD = 1.8 V to 5.5 V)
Oscillator
Clock
Parameter
Test Condition
Min Typ Max Units
Configuration
Oscillation frequency (1)
VDD = 2.7 V to 5.5 V
Ceramic
Oscillator
0.4
–
6.0
MHz
Xin
Xout
C1
C2
VDD = 1.8 V to 5.5 V
VDD = 3.0 V
0.4
–
–
–
–
3
4
Stabilization time (2)
ms
Oscillation frequency (1)
VDD = 2.7 V to 5.5 V
Crystal
Oscillator
0.4
6.0
MHz
Xin
Xout
C1
C2
VDD = 1.8 V to 5.5 V
VDD = 3.0 V
0.4
–
–
–
–
3
Stabilization time (2)
XIN input frequency (1)
10
6.0
ms
VDD = 2.7 V to 5.5 V
External
Clock
0.4
MHz
Xin
Xout
VDD = 1.8 V to 5.5 V
–
0.4
–
–
3
XIN input high and low
level width (tXH, tXL)
83.3
1250
ns
NOTES:
1. Oscillation frequency and X input frequency data are for oscillator characteristics only.
IN
2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is
terminated.
14-5
ELECTRICAL DATA
S3C7544/P7544
Table 14-4. Recommended Oscillator Constants
°
°
(T = – 40 C + 85 C, VDD = 1.8 V to 5.5 V)
A
Manufacturer
Series
Number (1)
Frequency Range
Load Cap (pF)
Oscillator Voltage
Range (V)
Remarks
C1
33
(2)
C2
33
(2)
MIN
2.0
MAX
5.5
TDK
3.58 MHz–6.0 MHz
3.58 MHz–6.0 MHz
Leaded Type
FCR” ðÿM5
2.0
5.5
On-chip C
FCR” ðÿMC5
Leaded Type
(3)
(3)
3.58 MHz–6.0 MHz
2.0
5.5
On-chip C
SMD Type
CCR” ðÿMC3
NOTES:
1. Please specify normal oscillator frequency.
2. On-chip C: 30pF built in.
3. On-chip C: 38pF built in.
Table 14-5. Input/Output Capacitance
°
(T = 25 C, VDD = 0 V )
A
Parameter
Input
Capacitance
Symbol
Condition
Min
Typ
Max
Units
CIN
f = 1 MHz; Unmeasured pins
are returned to VSS
–
–
15
pF
COUT
CIO
Output
Capacitance
15
15
pF
pF
I/O Capacitance
Table 14-6. D/A Converter Electrical Characteristics
(TA = – 40 C to + 85 C, VDD = 3.5 V to 5.5 V, VSS = 0 V)
°
°
Parameter
Resolution
Symbol
Condition
Min
–
Typ
–
Max
Units
bits
–
–
–
8
3
1
5
Absolute Accuracy
Differential Linearity Error
Setup Time
– 3
– 1
–
–
LSB
LSB
ms
DLE
tsu
–
–
RO
Output Resistance
4.5
5
5.5
KW
14-6
S3C7544/P7544
ELECTRICAL DATA
Table 14-7. A.C. Electrical Characteristics
°
°
(T = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
A
Parameter
Symbol
Conditions
Min
Typ
Max
Units
tCY
VDD = 2.7 V to 5.5 V
Instruction Cycle
Time
0.67
–
64
ms
VDD = 1.8 V to 5.5 V
VDD = 2.7 V to 5.5 V
1.33
0
fTI
TCL0 Input
Frequency
–
–
1.5
MHz
VDD = 1.8 V to 5.5 V
VDD = 2.7 V to 5.5 V
1
–
MHz
tTIH, TIL
t
TCL0 Input High,
Low Width
0.48
ms
VDD = 1.8 V to 5.5 V
INT0, INT1, KS0–KS1
1.8
10
tINTH, INTL
t
Interrupt Input
High, Low Width
–
–
–
ms
ms
tRSL
Input
–
10
RESET Input Low
Width
Table 14-8. RAM Data Retention Supply Voltage in Stop Mode
°
°
(TA = – 40 C to + 85 C)
Parameter
Symbol
Conditions
–
Min
1.8
–
Typ
–
Max
Unit
VDDDR
Data retention supply voltage
Data retention supply current
5.5
10
V
IDDDR
V
= 1.8 V
0.1
mA
DDDR
tSREL
tWAIT
Release signal set time
–
0
–
–
–
–
ms
217/fx
Oscillator stabilization wait
time (1)
ms
Released by RESET
(2)
Released by interrupt
–
–
ms
NOTES:
1. During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator
start-up.
2. Use the basic timer mode register (BMOD) interval timer to delay the execution of CPU instructions during the wait time.
14-7
ELECTRICAL DATA
S3C7544/P7544
TIMING WAVEFORMS
INTERNAL RESET
OPERATION
IDLE MODE
OPERATING
STOP MODE
DATA RETENTION MODE
MODE
V
DD
VDDDR
EXECUTION OF
STOP INSTRUCTION
RESET
tWAIT
tSREL
Figure 14-2. Stop Mode Release Timing When Initiated by RESET
IDLE MODE
NORMAL
OPERATING
MODE
STOP MODE
DATA RETENTION
V
DD
VDDDR
tSREL
EXECUTION OF
STOP INSTRUCTION
tWAIT
POWER-DOWN MODE TERMINATING
(INTERRUPT REQUEST)
Figure 14-3. Stop Mode Release Timing When Initiated by Interrupt Request
14-8
S3C7544/P7544
ELECTRICAL DATA
0.8 V
0.2 V
0.8 V
0.2 V
DD
DD
DD
MEASUREMENT
POINTS
DD
Figure 14-4. A.C. Timing Measurement Points (Except for XIN)
1 / f
x
t
t
XH
XL
X
IN
V
– 0.1 V
DD
0.1 V
Figure 14-5. Clock Timing Measurement at XIN
14-9
ELECTRICAL DATA
S3C7544/P7544
1 / f
TI
t
t
TIH
TIL
TCL
0.7 V
0.3 V
DD
DD
Figure 14-6. TCL Timing
t
RSL
RESET
0.2 V
DD
Figure 14-7. Input Timing for RESET Signal
t
t
INTL
INTH
INT0, 1
KS0 to KS1
0.8 V
0.2 V
DD
DD
Figure 14-8. Input Timing for External Interrupts
14-10
S3C7544/P7544
MECHANICAL DATA
15 MECHANICAL DATA
This section contains the following information about the device package:
— Package dimensions in millimeters
— Pad diagram
— Pad/pin coordinate data table
30
#1
16
0 ~ 15 °
30-SDIP-400
15
27.48 ± 0.2
(1.30)
1.778
0.56 ± 0.1
1.12 ± 0.1
NOTE
: Typical dimensions are in millimeters.
Figure 15-1. 30-SDIP-400 Package Dimensions
15–1
S3C7544/P7544
S3P7544 OTP
16 S3P7544 OTP
OVERVIEW
The S3P7544 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C7544
microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by serial data
format.
The S3P7544 is fully compatible with the S3C7544, both in function and in pin configuration. Because of its
simple programming requirements, the S3P7544 is ideal for use as an evaluation chip for the S3C7544.
V
/V
X
OUT
X
V
/V
DD
DD
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
16
15
14
13
SS
SS
P5.3/SCLK
P5.2/SDAT
P5.1
P5.0
P4.3
P4.2
P4.1
P4.0
P2.0
IN
V
/TEST
PP
P0.0/INT0
DAO
P0.1/INT1
RESET /RESET
P0.2/KS0
9
P0.3/KS1
P1.0/TCL0
P1.1/TCLO0
10
11
12
P1.3/BUZ
P1.2/CLO
Figure 16-1. S3P7544 Pin Assignments (24 SOP-375, 24 SDIP-300 Package)
16-1
S3P7544 OTP
S3C7544/P7544
Table 16-1. Descriptions of Pins Used to Read/Write the EPROM
During Programming
Main Chip
Pin Name
P5.2
Pin Name
Pin No.
I/O
Function
SDAT
22
I/O
Serial data pin. Output port when reading and input
port when writing. Can be assigned as a Input /
push-pull output port.
P5.3
SCLK
TEST
23
4
I/O
I
Serial clock pin. Input only pin.
TEST
Power supply pin for EPROM cell writing (indicates
that OTP enters into the writing mode). When 12.5
V is applied, OTP is in writing mode and when 5 V
is applied, OTP is in reading mode. (Option)
Hold GND when OTP is operating.
8
I
Chip initialization
RESET
RESET
VDD/VSS
VDD/VSS
Logic power supply pin. VDD should be tied to +5 V
during programming.
24/1
–
NOTE: ( ) means the 32-SOP OTP pin number.
Table 16-2. Comparison of S3P7544 and S3C7544 Features
S3P7544
Characteristic
Program Memory
Operating Voltage (VDD
S3C7544
4 K-byte EPROM
4 K-byte mask ROM
)
1.8 V (3 MHz) to 5.5 V
1.8 V (3 MHz) to 5.5 V
VDD = 5 V, VPP (TEST) = 12.5 V
OTP Programming Mode
–
Pin Configuration
24 SOP, 24 SDIP
24 SOP, 24 SDIP
EPROM Programmability
User Program one time
Programmed at the factory
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the VPP(TEST) pin of the S3P7544, the EPROM programming mode is entered. The
operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in
Table 16-3 below.
Table 16-3. Operating Mode Selection Criteria
VDD
VPP
(TEST)
REG/
MEM
Address
(A15-A0)
R/W
Mode
5 V
5 V
0
0
0
1
0000H
0000H
0000H
0E3FH
1
0
1
0
EPROM read
12.5 V
12.5 V
12.5 V
EPROM program
EPROM verify
EPROM read protection
NOTE: "0" means Low level; "1" means High level.
16-2
S3C7544/P7544
S3P7544 OTP
OTP ELECTRICAL DATA
Table 16-4. Absolute Maximum Ratings
°
(T = 25 C)
A
Parameter
Symbol
Conditions
Rating
Units
VDD
VI
Supply Voltage
Input Voltage
–
– 0.3 to + 6.5
– 0.3 to VDD + 0.3
V
All I/O ports
V
V
VO
IOH
– 0.3 to VDD + 0.3
– 5
Output Voltage
Output Current High
–
One I/O port active
mA
All I/O ports active
One I/O port active
– 35
IOL
Output Current Low
+ 30 (peak)
mA
+ 15 (note)
+ 100 (peak)
+ 60 (note)
All I/O ports active
°
TA
Operating Temperature
Storage Temperature
–
–
– 40 to + 85
C
°
C
Tstg
– 65 to + 150
NOTE: The values for output current low (I ) are calculated as peak value ´ Duty .
OL
Table 16-5. D.C. Electrical Characteristics
°
°
(T = – 40 C to + 85 C, V
= 1.8 V to 5.5 V)
DD
A
Parameter
Symbol
Conditions
Min
Typ
Max
Units
VIH1
All input pins except VIH2–VIH3
0.7 VDD
VDD
Input High
Voltage
–
V
VIH2
VIH3
VIL1
0.8 VDD
VDD – 0.1
–
VDD
VDD
–
–
–
P0 and RESET
XIN and XOUT
All input pins except VIH2–VIH3
0.3 VDD
Input Low
Voltage
V
VIL2
VIL3
0.2 VDD
0.1
P0 and RESET
XIN and XOUT
16-3
S3P7544 OTP
S3C7544/P7544
Table 16-5. D.C. Electrical Characteristics (Continued)
°
°
(TA = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
VOH
VDD = 4.5 V to 5.5 V
VDD – 1.0
Output High
Voltage
–
–
V
IOH = – 1 mA
VOL1
VOL2
ILIH1
VDD = 4.5 V to 5.5 V
IOL = 15 mA
Output Low
Voltage
–
–
2
V
Ports 4, 5
VDD = 1.8 V to 5.5 V
IOL = 1.6 mA
0.4
2
VDD = 4.5V to 5.5 V
I
= 4 mA
OL
All out ports except ports 4, 5
VDD = 1.8 V to 5.5 V
IOL = 1.6 mA
0.6
3
VIN = VDD
All input pins except XIN and XOUT
Input High
Leakage
Current
–
–
–
–
mA
mA
ILIH2
VIN = VDD
XIN and XOUT
20
ILIL1
V
IN
= 0 V
Input Low
Leakage
Current
– 3
All input pins except XIN, XOUT
and RESET
ILIL2
VIN = 0 V
XIN and XOUT
– 20
3
ILOH
VO = VDD
Output High
Leakage
Current
–
–
–
–
mA
mA
kW
All output pins
ILOL
VO = 0 V
Output Low
Leakage
Current
– 3
All output pins
RL1
VDD = 5 V; V = 0 V
I
Pull-up
25
50
100
Resistor
except
RESET
VDD = 3 V
50
100
250
200
400
RL2
100
VDD = 5 V; V = 0 V; RESET
I
VDD = 3 V
200
500
800
16-4
S3C7544/P7544
S3P7544 OTP
Table 16-5. D.C. Electrical Characteristics (Concluded)
°
°
(TA = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
mA
IDD1
Supply
6.0MHz
–
3.4
10.0
Run mode; VDD = 5.0 V ± 10%
Current (1)
(DAC on) Crystal oscillator; C1 = C2 = 22pF
4.19MHz
6.0MHz
2.7
2.3
8.0
8.0
mA
mA
IDD2
–
–
–
Run mode; VDD = 5.0 V ± 10%
(DAC off) Crystal oscillator; C1 = C2 = 22pF
4.19MHz
6.0MHz
1.7
1.1
5.5
4.0
VDD = 3 V ± 10%
4.19MHz
6.0MHz
0.8
0.7
3.0
2.5
IDD3
Idle mode; VDD = 5.0 V ± 10%
Crystal oscillator; C1 = C2 = 22pF
4.19MHz
6.0MHz
0.5
0.3
1.8
1.5
VDD = 3 V ± 10%
4.19MHz
0.2
0.2
1.0
3.0
IDD4
Stop mode; VDD = 5.0 V ± 10%
mA
0.1
2.0
Stop mode; VDD = 3.0 V ± 10%
NOTES:
1. D.C. electrical values for supply current (I
to I
) do not include the current drawn through internal pull-up
DD3
DD1
resistors.
2.
I
typical values are measured when DADATA register value is 055H .
DD1
Main Osc. Freq.
6 MHz
CPU CLOCK
1.5 MHz
0.75 MHz
3 MHz
15.625 kHz
400 kHz
7
1.8
2.7
1
2
3
4
5
6
SUPPLY VOLTAGE (V)
CPU CLOCK = 1/n x oscillator frequency (n = 4, 8 or 64)
Figure 16-2. Standard Operating Voltage Range
16-5
S3P7544 OTP
S3C7544/P7544
Table 16-6. Oscillators Characteristics
°
°
(TA = – 40 C + 85 C, VDD = 1.8 V to 5.5 V)
Oscillator
Clock
Parameter
Test Condition
Min
Typ Max Units
Configuration
Oscillation frequency (1)
VDD = 2.7 V to 5.5 V
Ceramic
Oscillator
0.4
–
6.0
MHz
Xin
Xout
C1
C2
VDD = 1.8 V to 5.5 V
VDD = 3.0 V
0.4
–
–
–
–
3
4
Stabilization time (2)
ms
Oscillation frequency (1)
VDD = 2.7 V to 5.5 V
Crystal
Oscillator
0.4
6.0
MHz
Xin
Xout
C1
C2
VDD = 1.8 V to 5.5 V
VDD = 3.0 V
0.4
–
–
–
–
3
Stabilization time (2)
XIN input frequency (1)
10
6.0
ms
VDD = 2.7 V to 5.5 V
External
Clock
0.4
MHz
Xin
Xout
VDD = 1.8 V to 5.5 V
–
0.4
–
–
3
XIN input high and low
level width (tXH, tXL)
83.3
1250
ns
NOTES:
1. Oscillation frequency and X input frequency data are for oscillator characteristics only.
IN
2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is
terminated.
16-6
S3C7544/P7544
S3P7544 OTP
Table 16-7. Input/Output Capacitance
°
(T = 25 C, VDD = 0 V )
A
Parameter
Input
Capacitance
Symbol
Condition
Min
Typ
Max
Units
CIN
f = 1 MHz; Unmeasured pins
are returned to VSS
–
–
15
pF
COUT
CIO
Output
Capacitance
15
15
pF
pF
I/O Capacitance
Table 16-8. Comparator Electrical Characteristics
(TA = – 40 C to + 85 C, VDD = 3.5 V to 5.5 V, VSS = 0 V)
°
°
Parameter
Resolution
Symbol
Condition
Min
–
Typ
–
Max
Units
bits
–
–
–
8
3
1
5
Absolute Accuracy
Differential Linearity Error
Setup Time
– 3
– 1
–
–
LSB
LSB
ms
DLE
tsu
–
–
RO
Output Resistance
4.5
5
5.5
KW
Table 16-9. A.C. Electrical Characteristics
(T = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
°
°
A
Parameter
Symbol
Conditions
Min
Typ
Max
Units
tCY
VDD = 2.7 V to 5.5 V
Instruction Cycle
Time
0.67
–
64
ms
VDD = 1.8 V to 5.5 V
VDD = 2.7 V to 5.5 V
1.33
0
fTI
TCL0 Input
Frequency
–
–
1.5
MHz
VDD = 1.8 V to 5.5 V
VDD = 2.7 V to 5.5 V
1
–
MHz
tTIH, TIL
t
TCL0 Input High,
Low Width
0.48
ms
VDD = 1.8 V to 5.5 V
INT0, INT1, KS0–KS1
1.8
10
tINTH, INTL
t
Interrupt Input
High, Low Width
–
–
–
ms
ms
tRSL
Input
–
10
RESET Input Low
Width
16-7
S3P7544 OTP
S3C7544/P7544
Table 16-10. RAM Data Retention Supply Voltage in Stop Mode
°
°
(TA = – 40 C to + 85 C)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
VDDDR
Data retention supply voltage
–
1.8
–
5.5
10
V
IDDDR
VDDDR = 1.8 V
Data retention supply current
–
0.1
mA
tSREL
tWAIT
Release signal set time
–
0
–
–
–
–
ms
217/fx
Oscillator stabilization wait
time (1)
ms
Released by RESET
(2)
Released by interrupt
–
–
ms
NOTES:
1. During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator
start-up.
2. Use the basic timer mode register (BMOD) interval timer to delay the execution of CPU instructions during the wait time.
16-8
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