S3P7528 [SAMSUNG]
The S3C7524/C7528/C7534/C7538 single-chip CMOS microcontroller has been designed for high-performance using SAM 47; 在S3C7524 / C7528 / C7534 / C7538单芯片CMOS微控制器是专为使用SAM 47高性能
| 型号： | S3P7528 |
| 厂家： | 
SAMSUNG |
| 描述： | The S3C7524/C7528/C7534/C7538 single-chip CMOS microcontroller has been designed for high-performance using SAM 47 |
| 文件： | 总34页 (文件大小：227K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S3C7524/C7528/P7528/C7534/C7538/P7538
PRODUCT OVERVIEW
1
PRODUCT OVERVIEW
The S3C7524/C7528/C7534/C7538 single-chip CMOS microcontroller has been designed for high-performance
using SAM 47 (Samsung Arrangeable Microcontrollers). SAM 47, Samsung's newest 4-bit CPU core is notable
for its low energy consumption and low operating voltage.
You can select from two ROM sizes: 4K or 8K bytes
Except for the difference in ROM size, the features and functions of the S3C7524 and the S3C7528, the
S3C7534 and the S3C7538 are identical.
With it's DTMF generator, watchdog timer function, and versatile 8-bit timer/counters, theS3C7524/C7528
/C5304/C5308 offers an excellent design solution for a wide variety of telecommunication applications.
Up to 35 pins of the available 42-pin SDIP or 44-pin QFP package for the S3C7524/C7528, and up to 23 pins of
the available 30-pin SDIP or 32-pin SOP package for the S3C7534/C7538 can be assign to I/O. Six vectored
interrupts for S3C7524/C7528 and four vectored interrupts for S3C7534/C7538 provide fast response to internal
and external events. In addition, the S3C7524/C7528/C7534/C7538 's advanced CMOS technology provides for
low power consumption and a wide operating voltage range.
OTP
The S3C7524/C7528 microcontroller is also available in OTP (One Time Programmable) version, S3P7528. The
S3C7534/C7538 microcontroller is also available in OTP (One Time Programmable) version, S3P7538. The
S3P7528/P7538 microcontroller has an on-chip 8K-byte one-time-programable EPROM instead of masked ROM.
The S3P7528 is comparable to S3C7524/C7528, both in function and in pin configuration. Also, the S3P7538 is
comparable to the S3C7534/C7538, both in function and in pin configuration.
1-1
PRODUCT OVERVIEW
S3C7524/C7528/P7528/C7534/C7538/P7538
FEATURES SUMMARY
Memory
Interrupts
·
·
768 ´ 4-bit RAM
·
3 external interrupt vectors (S3C7524/C7528)
1 external interrupt vectors (S3C7534/C7538)
4,096 ´ 8-bit ROM (S3C7524/C7534)
8,192 ´ 8-bit ROM (S3C7528/C7538)
·
·
3 internal interrupt vectors
2 quasi-interrupts
35 I/O Pins
Power-Down Modes
·
·
·
Input only: 4 pins (S3C7524/C7528)
1 pins (S3C7534/C7538)
·
·
Idle: Only CPU clock stops
Stop: System clock stops
I/O: 23 pins (S3C7524/C7528)
14 pins (S3C7534/C7538)
N-channel open-drain I/O: 8 pins
Oscillation Sources
·
·
Crystal, or ceramic for main system clock
Memory-Mapped I/O Structure
Data memory bank 15
Main system clock frequency: 0.4–6.0 MHz
(typical)
·
·
CPU clock divider circuit (by 4, 8, or 64)
DTMF Generator
16 dual-tone frequencies for tone dialing
·
Instruction Execution Times
·
·
·
0.95, 1.91, and 15.3 ms at 4.19 MHz
1.12, 2.23, 17.88 ms at 3.58 MHz
0.67, 1.33, 10.7 ms at 6.0 MHz
8-Bit Basic Timer
·
·
Programmable interval timer
Watchdog timer
Operating Temperature
Two 8-Bit Timer/Counters
°
– 40 C to 85 °C
·
·
·
·
Programmable 8-bit timer
External event counter function
Arbitrary clock frequency output
Operating Voltage Range
2.0 V to 5.5 V
·
Watch Timer
Package Types
·
·
Real-time and interval time measurement
Four frequency outputs to the BUZ pin
·
·
42 SDIP, 44 QFP (S3C7524/C7528)
30 SDIP, 32 SOP (S3C7534/C7538)
Bit Sequential Carrier
·
Supports 8-bit serial data transfer in arbitrary
format
1-2
S3C7524/C7528/P7528/C7534/C7538/P7538
PRODUCT OVERVIEW
BLOCK DIAGRAM
INT0, INT1, INT2, INT4
Xin
Xout
RESET
BASIC
8-BIT
TIMER/
TIMER
COUNTER 0
WATCH
TIMER
INTERRUPT
CONTROL
BLOCK
STACK
POINTER
CLOCK
8-BIT
TIMER/
WATCH-DOG
TIMER
COUNTER 1
PROGRAM
COUNTER
P6.0–P6.3 /
KS0–KS3
P1.0 / INT0
P1.1 / INT1
P1.2 / INT2
P1.3 / INT4
INTERNAL
INTERRUPTS
I/O PORT 6
I/O PORT 7
INPUT
PORT 1
P7.0–P7.3 /
KS4–KS7
PROGRAM
STATUS WORD
INSTRUCTION DECODER
P2.0 / TCLO0
P2.1 / TCLO1
P2.2 / CLO
P8.0–P8.3
P9.0–P9.2
I/O PORT 8
I/O PORT 9
I/O PORT 2
I/O PORT 3
ARITHMETIC
AND
LOGIC UNIT
P2.3 / BUZ
P3.0 / TCL0
P3.1 / TCL1
P3.2
FLAGS
P3.3
P4.0 / BTCO
I/O PORT 4
I/O PORT 5
P4.1 P4.3
-
P5.0–P5.3
DTMF
PROGRAM MEMORY
S3C7524/C7534: 4 KBytes
S3C7528/C7538: 8 KBytes
768x 4-BIT
DATA
MEMORY
DTMF
GENERATOR
S3C7534/C7538 does not use P1.1/INT1, P1.2/INT2, P1.3/INT3, P3.2, P3.3, INT1, INT2,
INT4, P8.0-P8.3, and P9.0-P9.2.
NOTE:
Figure 1–1. S3C7524/C7528 Simplified Block Diagram
1-3
PRODUCT OVERVIEW
S3C7524/C7528/P7528/C7534/C7538/P7538
PIN ASSIGNMENTS
P1.0 / INT0
P1.1 / INT1
P1.2 / INT2
P1.3 / INT4
P2.0 / TCLO0
P2.1 / TCLO1
P2.2 / CLO
P2.3 / BUZ
P3.0 / TCL0
P3.1 / TCL1
1
2
3
4
5
6
7
8
42
P9.2
P9.1
P9.0
DTMF
P7.3 / KS7
P7.2 / KS6
P7.1 / KS5
P7.0 / KS4
P6.3 / KS3
P6.2 / KS2
P6.1 / KS1
P6.0 / KS0
P5.3
P5.2
P5.1
P5.0
P8.3
P8.2
P8.1
P8.0
P4.3
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
9
10
11
12
13
14
15
16
17
18
19
20
21
V
V
DD
SS
X
OUT
X
IN
TEST
P4.0 / BTCO
P4.1
RESET
P3.2
P3.3
P4.2
Figure 1–2. S3C7524/C7528 Pin Assignment Diagrams (42–SDIP)
1-4
S3C7524/C7528/P7528/C7534/C7538/P7538
PRODUCT OVERVIEW
P2.2 / CLO
P2.3 / BUZ
P3.0 / TCL0
P3.1 / TCL1
1
2
3
4
5
6
7
8
33
32
31
30
29
28
27
26
25
24
23
P7.3 / KS7
P7.2 / KS6
P7.1 / KS5
P7.0 / KS4
P6.3 / KS3
P6.2 / KS2
P6.1 / KS1
P6.0 / KS0
P5.3
V
KS57C5204/C5208
(44-QFP-1010B)
DD
SS
V
X
OUT
X
IN
TEST
P4.0 / BTCO
P4.1
9
10
11
P5.2
P5.1
Figure 1–3. S3C7524/C7528 Pin Assignment Diagrams (44–QFP)
1-5
PRODUCT OVERVIEW
S3C7524/C7528/P7528/C7534/C7538/P7538
V
1
2
3
4
5
6
7
8
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
V
SS
DD
X
P3.1 / TCL1
P3.0 / TCL0
P2.3 / BUZ
P2.2 / CLO
P2.1 / TCLO1
P2.0 / TCLO0
P1.0 / INT0
DTMF
P7.3 / KS7
P7.2 / KS6
P7.1 / KS5
P7.0 / KS4
P6.3 / KS3
P6.2 / KS2
OUT
X
TEST
P4.0 / BTCO
IN
P4.1
RESET
P4.2
P4.3
P5.0
P5.1
P5.2
9
10
11
12
13
14
15
P5.3
P6.0 / KS0
P6.1 / KS1
Figure 1–4. S3C7534/C7538 Pin Assignment Diagrams (30–SDIP)
V
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
DD
SS
X
P3.1 / TCL1
P3.0 / TCL0
P2.3 / BUZ
P2.2 / CLO
P2.1 / TCLO1
P2.0 / TCLO0
P1.0 / INT0
NC
OUT
X
IN
TEST
P4.0 / BTCO
P4.1
RESET
P4.2
NC
P4.3
P5.0
P5.1
P5.2
P5.3
9
10
11
12
13
14
15
16
DTMF
P7.3 / KS7
P7.2 / KS6
P7.1 / KS5
P7.0 / KS4
P6.3 / KS3
P6.2 / KS2
P6.0 / KS0
P6.1 / KS1
Figure 1–5. S3C7534/C7538 Pin Assignment Diagrams (32–SOP)
1-6
S3C7524/C7528/P7528/C7534/C7538/P7538
PRODUCT OVERVIEW
PIN DESCRIPTIONS
Table 1-1. S3C7524/C7528 Pin Descriptions
Description
Pin
Pin Reset
Pin
Share Circuit
Name Type Value
Number
Pin
Type
P1.0
P1.1
P1.2
P1.3
I
I
4-bit input port.
1-bit and 4-bit read and test is possible.
Each pull-up resistors are assignable by software.
1 (39)
2 (40)
3 (41)
4 (42)
INT0
INT1
INT2
INT4
A-4
P2.0
P2.1
P2.2
P2.3
I/O
I
4-bit I/O port.
5 (43)
6 (44)
7 (1)
TCLO0
TCLO1
CLO
D-2
D-4
E-2
1-bit and 4-bit read/write and test is possible.
Individual pins are software configurable as input or
output.
8 (2)
BUZ
P3.0
P3.1
P3.2
P3.3
4-bit pull-up resistors are software assignable to input
pins and are automatically disabled for output pins.
Ports 2 and 3 can be paired to enable 8-bit data
transfer.
9 (3)
10 (4)
19 (13)
20 (14)
TCL0
TCL1
P4.0
P4.1
P4.2
P4.3
I/O
I
4-bit I/O ports.
16 (10)
17 (11)
21 (15)
22 (17)
BTCO
1-bit and 4-bit read/write and test is possible.
Individual pins are software configurable as input or
output.
4-bit pull-up resistors are software assignable to input
pins and are automatically disabled for output pins.
N-channel open-drain or push-pull output can be
selected by software (1-bit unit)
P5.0–P5.3
27–30
(22–25)
Ports 4 and 5 can be paired to support 8-bit data
transfer.
P6.0–P6.3 I/O
P7.0–P7.3
I
I
4-bit I/O ports.
31–34
(26–29)
35–38
KS0–KS3
KS4–KS7
D-4
D-2
1-bit or 4-bit read/write and test is possible.
Individual pins are software configurable as input or
output.
4-bit pull-up resistors are software assignable to input
pins and are automatically disabled for output pins.
Ports 6 and 7 can be paired to enable 8-bit data
transfer.
(30–33)
23–26
(18–21)
40–42
P8.0–P8.3 I/O
P9.0–P9.2
4-bit I/O port.
–
1-bit or 4-bit read/write and test is possible.
Individual pins are software configurable as input or
output.
(35–37)
4-bit pull-up resistors are software assignable to input
pins and are automatically disabled for output pins.
Ports 8 and 9 can be paired to enable 8-bit data
transfer.
1-7
PRODUCT OVERVIEW
S3C7524/C7528/P7528/C7534/C7538/P7538
Table 1-1. S3C7524/C7528 Pin Descriptions (Continued)
Pin
Name
Pin Reset
Type Value
Description
Pin
Number
Share Circuit
Pin
Type
G-6
E-2
DTMF
O
I/O
I
–
I
DTMF output.
39 (34)
16 (10)
–
BTCO
Basic timer clock output
P4.0
INT0
INT1
I
External interrupts. The triggering edge for INT0 and
INT1 is selectable.
1 (39)
2 (40)
P1.0
P1.1
A-3
INT2
INT4
I
I
I
I
Quasi-interrupt with detection of rising edges
3 (41)
4 (42)
P1.2
P1.3
A-3
A-3
External interrupt with detection of rising and falling
edges.
TCLO0
TCLO1
CLO
I/O
I/O
I/O
I/O
I
I
I
I
Timer/counter 0 clock output
Timer/counter 1 clock output
Clock output
5 (43)
6 (44)
7 (1)
P2.0
P2.1
P2.2
P2.3
D-2
D-2
D-2
D-2
BUZ
2 kHz, 4 kHz, 8 kHz, or 16 kHz frequency output at
the watch timer clock frequency of 4.19 MHz for
buzzer sound
8 (2)
TCL0
TCL1
I/O
I/O
I
I
I
External clock input for timer/counter 0
External clock input for timer/counter 1
Quasi-interrupt inputs with falling edge detection
9 (3)
P3.0
P3.1
D-4
D-4
D-4
10 (4)
KS0–KS3 I/O
31–34
(26–29)
35–38
P6.0–
P6.3
P7.0–
P7.3
KS4–KS7
(30–33)
V
V
–
–
–
–
–
–
–
–
Power supply
Ground
11 (5)
12 (6)
–
–
–
–
–
–
B
–
DD
SS
18 (12)
RESET
RESET signal
X
in
Crystal, or ceramic oscillator signal for main system
clock. (For external clock input, use X and input
14 (8)
13 (7)
X
out
in
X 's reverse phase to X
in
)
out
TEST
NC
–
–
–
–
Test signal input
No connection
15 (9)
–
–
–
–
(16, 38)
NOTE: Parentheses indicate pin number for 44 QFP package.
1-8
S3C7524/C7528/P7528/C7534/C7538/P7538
PRODUCT OVERVIEW
Table 1-2. S3C7534/C7538 Pin Descriptions
Pin
Name
Pin
Type
Description
Pin
Number
Share
Pin
Circuit
Type
P1.0
I
1-bit input port.
23 (25)
INT0
A-4
1-bit and 4-bit read and test is possible.
Each bit pull-up resistors are assignable.
P2.0
P2.1
P2.2
P2.3
I/O
4-bit I/O port.
24 (26)
25 (27)
26 (28)
27 (29)
TCLO0
TCLO1
CLO
D-2
1-bit and 4-bit read/write and test is possible.
Each individual pin can be assignable as input or
output. 4-bit pull-up resisters are software
assignable to input pins and are automatically
disabled for output pins.
BUZ
Ports 2 and 3 can be paired to enable 8-bit data
transfer.
P3.0
P3.1
28 (30)
29 (31)
TCL0
TCL1
D-4
E-2
P4.0
P4.1
P4.2
P4.3
I/O
4-bit I/O ports.
5 (5)
6 (6)
8 (8)
9 (10)
10–13
(11–14)
BTCO
1-bit and 4-bit read/write and test is possible.
Each individual pin can be assignable as input or
output. 4-bit pull-up resisters are software
assignable to input pins and are automatically
disabled for output pins.
P5.0–P5.3
The N-channel open-drain or push-pull output
can be selected by software (1-bit unit).
Ports 4 and 5 can be paired to enable 8-bit data
transfer.
P6.0–P6.3
P7.0–P7.3
I/O
4-bit I/O ports.
14–17
(15–18)
18–21
KS0–KS3
KS4–KS7
D-4
1-bit and 4-bit read/write and test is possible.
Each individual pin can be assignable as input or
output. 4-bit pull-up resisters are software
assignable to input pins and are automatically
disabled for output pins.
(19–22)
Ports 6 and 7 can be paired to enable 8-bit data
transfer.
1-9
PRODUCT OVERVIEW
S3C7524/C7528/P7528/C7534/C7538/P7538
Table 1-1. S3C7534/C7538 Pin Descriptions (Continued)
Pin
Name
I/O
Type
Description
Pin
Number
Share
Pin
Circuit
Type
DTMF
O
I
DTMF output.
22 (23)
23 (25)
–
G-6
A-3
INT0
External interrupt input.
P1.0
The triggering edge for INT0 is selectable.
TCLO0
TCLO1
CLO
I/O Timer/counter 0 clock output
I/O Timer/counter 1 clock output
I/O Clock output
24 (26)
25 (27)
26 (28)
27 (29)
P2.0
P2.1
P2.2
P2.3
D-2
D-2
D-2
D-2
BUZ
I/O 2 kHz, 4 kHz, 8 kHz, or 16 kHz frequency output at the
watch timer clock frequency of 4.19 MHz for buzzer
sound
TCL0
TCL1
BTCO
I/O External clock input for timer/counter 0
I/O External clock input for timer/counter 1
I/O Basic timer clock output
28 (30)
29 (31)
5 (5)
P3.0
P3.1
P4.0
–
D-4
D-4
E-2
–
V
DD
–
–
–
Power supply
Ground
30 (32)
1 (1)
V
SS
–
–
X
in
Crystal, or ceramic oscillator signal for main system
clock. (For external clock input, use X and input X 's
3 (3)
2 (2)
–
–
X
out
in
in
reverse phase to X
No connection
Test signal input
RESET signal
)
out
NC
–
–
–
(9, 24)
4 (4)
–
–
–
–
–
TEST
RESET
7 (7)
B
KS0–KS3 I/O Quasi-interrupt inputs with falling edge detection
14–17
(15–18)
18–21
P6.0–
P6.3
P7.0–
P7.3
D-4
KS4–KS7
(19–22)
NOTE: Parentheses indicate the pin number for 32-SOP package.
1-10
S3C7524/C7528/P7528/C7534/C7538/P7538
PRODUCT OVERVIEW
PIN CIRCUIT DIAGRAMS
V
DD
V
DD
PULL-UP
RESISTOR
P-CHANNEL
RESISTOR
ENABLE
P-CHANNEL
IN
IN
-
N CHANNEL
SCHMITT TRIGGER
Figure 1–8. Pin Circuit Type A-4
Figure 1–6. Pin Circuit Type A
V
DD
V
DD
PULL-UP
RESISTOR
-
P CHANNEL
DATA
OUT
IN
-
N CHANNEL
OUTPUT
DISABLE
SCHMITT TRIGGER
Figure 1–9. Pin Circuit Type C
Figure 1–7. Pin Circuit Type B
1-11
PRODUCT OVERVIEW
KS57C5204/C5208/P5208/C5304/C5308/P5308 MICROCONTROLLER
V
V
DD
DD
PULL-UP
PNE
RESISTOR
V
DD
PULL-UP
RESISTOR
PULL-UP
RESISTOR
ENABLE
RESISTOR
ENABLE
DATA
P-CHANNEL
I/O
P-CHANNEL
I/O
DATA
CIRCUIT
TYPE C
OUTPUT
DISABLE
OUTPUT
DISABLE
N-CHANNEL
Figure 1–12. Pin Circuit Type E-2
Figure 1–10. Pin Circuit Type D-2
V
DD
PULL-UP
RESISTOR
RESISTOR
ENABLE
P-CHANNEL
I/O
DTMF OUT
DATA
CIRCUIT
TYPE C
OUTPUT
DISABLE
OUTPUT
DISABLE
SCHMITT TRIGER
Figure 1–11. Pin Circuit Type D-4
Figure 1–13. Pin Circuit Type G-6
1-12
S3C7524/C7528/P7528/C7534/C7538/P7538
ELECTRICAL DATA
13 ELECTRICAL DATA
In this section, information on S3C7524/C7528 electrical characteristics is presented as tables and graphics. The
information is arranged in the following order:
Standard Electrical Characteristics
— Absolute maximum ratings
— D.C. electrical characteristics
— System clock oscillator characteristics
— I/O capacitance
— A.C. electrical characteristics
— Operating voltage range
Miscellaneous Timing Waveforms
— A.C timing measurement point
— Clock timing measurement at X and X
in
out
— TCL timing
— Input timing for RESET
— Input timing for external interrupts
— Serial data transfer timing
Stop Mode Characteristics and Timing Waveforms
— RAM data retention supply voltage in stop mode
— Stop mode release timing when initiated by RESET
— Stop mode release timing when initiated by an interrupt request
13–1
ELECTRICAL DATA
S3C7524/C7528/P7528/C7534/C7538/P7538
Table 13-1. Absolute Maximum Ratings
°
(TA = 25 C)
Parameter
Symbol
Conditions
Rating
Units
VDD
Supply Voltage
Input Voltage
–
– 0.3 to + 6.5
– 0.3 to VDD + 0.3
V
VI1
VO
All I/O ports
V
V
– 0.3 to VDD + 0.3
– 15
Output Voltage
Output Current High
–
IOH
One I/O port active
mA
All I/O ports active
One I/O port active
– 35
IOL
Output Current Low
+ 30 (Peak value)
mA
+ 15 (note)
All I/O ports active
+ 100 (Peak value)
+ 60 (note)
°
TA
Operating Temperature
Storage Temperature
–
– 40 to + 85
C
°
C
Tstg
–
– 65 to + 150
NOTE: The values for output current low ( IOL ) are calculated as peak value ´
Duty .
Table 13-2. D.C. Electrical Characteristics
(TA = – 40 °C to + 85 °C, VDD = 2.0 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
VIH1
0.7 VDD
VDD
Input high
voltage
All input pins except those
specified below for VIH2 – VIH3
–
V
VIH2
VIH3
VIL1
0.8 VDD
VDD
VDD
Ports 1, 3, 6, 7, and RESET
Xin and Xout
V
DD – 0.1
0.3 VDD
Input low
voltage
All input pins except those
specified below for VIL2–VIL3
–
–
V
VIL2
VIL3
0.2 VDD
0.1
Ports 1, 3, 6, 7, and RESET
X and X
in
out
13–2
S3C7524/C7528/P7528/C7534/C7538/P7538
ELECTRICAL DATA
Table 13-2. D.C. Electrical Characteristics (Continued)
(TA = – 40 °C to + 85 °C, VDD = 2.0 V to 5.5 V)
Parameter
Symbol
Conditions
IOH = – 1 mA
Min
Typ
Max
Units
VOH
VDD – 1.0
Output high
voltage
–
–
V
Ports except 1
VOL1
VOL2
ILIH1
VDD = 4.5 V to 5.5 V
IOL = 15 mA, Ports 4 and 5 only
Output low
voltage
–
0.4
2
V
V
VDD = 2.0 to 5.5 V, IOL = 1.6mA
–
–
–
–
0.4
2
VDD = 4.5 V to 5.5 V
IOL= 4 mA, all out ports except 4,5
VDD = 2.0 to 5.5 V, IOL = 1.6mA
V = V
–
–
–
–
0.4
3
Input high
µA
I
DD
leakage current
All input pins except those specified
below
ILIH2
ILIL1
ILIL2
VI = VDD
Xin and Xout
20
– 3
VI = 0 V
Input low
leakage current
–
–
µA
All input pins except below and RESET
VI = 0 V
– 20
X and Xout only
i
n
ILOH
ILOL
VO = VDD
Output high
leakage current
–
–
–
–
3
µA
µA
All out pins
VO = 0 V
Output low
– 3
leakage current
Xin and Xout only
RL1
VDD = 5 V; VI = 0 V
except RESET
VDD = 3 V
Pull-up resistor
25
47
100
kW
50
95
200
400
800
RL2
100
200
220
450
VDD = 5 V; V = 0 V; RESET
I
VDD = 3 V
13–3
ELECTRICAL DATA
S3C7524/C7528/P7528/C7534/C7538/P7538
Table 13-2. D.C. Electrical Characteristics (Concluded)
°
°
(TA = – 40 C to + 85 C, VDD = 2.0 V to 5.5 V)
Parameter
Supply
Symbol
Conditions
Min
Typ
Max Units
Run mode; VDD = 5 V ± 10% (2)
IDD1
–
2.9
5.0
mA
(1)
current
(DTMF on)
3.58 MHz crystal oscillator,
C1 = C2 = 22 pF
VDD = 3 V ± 10%
1.6
2.6
3.0
8.0
IDD2
6.0 MHz
–
–
–
mA
Run mode; VDD = 5 V ± 10%
(DTMF off) crystal oscillator, C1 = C2 = 22 pF 3.58 MHz
1.8
1.8
1.2
0.7
4.0
4.0
2.3
2.5
VDD = 3 V ± 10%
6.0 MHz
3.58 MHz
6.0 MHz
IDD
3
mA
µA
Idle mode; = VDD = 5 V ± 10%
crystal oscillator, C1 = C2 = 22 pF 3.58 MHz
0.6
0.3
1.8
1.5
1.0
3
VDD = 3 V ± 10%
6.0 MHz
3.58 MHz
0.2
IDD4
Stop mode; VDD = 5 V ± 10%
Stop mode; VDD = 3 V ± 10%
0.01
0.01
2
VROW
VDD = 5 V ± 10%
VDD = 3 V ± 10%
VDD = 2 V
Row tone level
– 16.0 – 14.0 – 11.0 dBV
RL = 5kW
dBCR
THD
VDD = 5 V ± 10%
VDD = 3 V ± 10%
VDD = 2 V
Ratio of column
to row tone
1
–
2
–
3
5
RL = 5kW
VDD = 5 V ± 10%
VDD = 3 V ± 10%
VDD = 2 V
Distortion
(Dual tone)
%
RL = 5kW, 1MHz band
NOTES
1. D.C. electrical values for Supply Current (IDD1 to IDD3) do not include current drawn through internal pull-up registers.
2. For D.C. electrical values, the power control register (PCON) must be set to 0011B.
13–4
S3C7524/C7528/P7528/C7534/C7538/P7538
ELECTRICAL DATA
Table 13-3. Main System Clock Oscillator Characteristics
(TA = – 40 °C + 85 C, VDD = 2.0 V to 5.5 V)
°
Oscillator
Clock
Parameter
Test Condition
Min
Typ
Max Units
Configuration
(1)
VDD = 2.7 V to 5.5 V
Ceramic
Oscillator
0.4
–
6.0
MHz
Oscillation frequency
Xin
Xout
C1
C2
VDD = 2.0 V to 5.5 V
VDD = 3 V
0.4
–
–
–
–
4.2
4
(2)
ms
Stabilization time
(1)
VDD = 2.7 V to 5.5 V
Crystal
Oscillator
0.4
6.0
MHz
Oscillation frequency
Xin
Xout
C1
C2
VDD = 2.0 V to 5.5 V
VDD = 3 V
0.4
–
–
–
–
4.2
10
(2)
ms
Stabilization time
(1)
VDD = 2.7 V to 5.5 V
External
Clock
0.4
6.0
MHz
Xin
Xout
X input frequency
in
VDD = 2.0 V to 5.5V
–
0.4
–
–
4.2
X input high and low
in
83.3
1250
ns
level width (tXH, tXL)
NOTES
1. Oscillation frequency and Xin input frequency data are for oscillator characteristics only.
2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is
terminated.
13–5
ELECTRICAL DATA
S3C7524/C7528/P7528/C7534/C7538/P7538
Table 13-4. Input/Output Capacitance
°
(TA = 25 C, VDD = 0 V )
Parameter
Input
Capacitance
Symbol
Condition
Min
Typ
Max
Units
CIN
COUT
CIO
f = 1 MHz; Unmeasured pins
are returned to VSS
–
–
15
pF
Output
Capacitance
–
–
–
–
15
15
pF
pF
I/O Capacitance
Table 13-5. A.C. Electrical Characteristics
(TA = – 40 °C to + 85 C, VDD = 2.0 V to 5.5 V)
°
Parameter
Symbol
tCY
Conditions
Min
Typ
Max
Units
VDD = 2.7 V to 5.5 V
Instruction Cycle
0.67
–
64
µs
(1)
Time
VDD = 2.0 V to 5.5 V
VDD = 2.7 V to 5.5 V
0.95
0
fTI0
f
TI1
TCL0, TCL1 Input
Frequency
–
–
1.5
MHz
,
VDD = 2.0 V to 5.5V
VDD = 2.7 V to 5.5 V
1
–
MHz
µs
tTIH0, tTIL0
tTIH1, tTIL1
TCL0, TCL1 Input
High, Low Width
0.48
VDD = 2.0 V to 5.5 V
1.8
10
tINTH, tINTL
tRSL
Interrupt Input
High, Low Width
INT0, INT1, INT2, INT4,
KS0–KS7
–
–
–
–
µs
µs
Input
10
RESET Input Low
Width
13–6
S3C7524/C7528/P7528/C7534/C7538/P7538
ELECTRICAL DATA
CPU CLOCK
1.5 MHz
Main Osc. Freq.
6 MHz
1.05 MHz
4.2 MHz
15.625 kHz
1
2
3
4
5
6
7
2.7 V
SUPPLY VOLTAGE (V)
CPU CLOCK = oscillator frequency x 1/n (n = 4, 8, 64)
Figure 13-1. Standard Operating Voltage Range
Table 13-6. RAM Data Retention Supply Voltage in Stop Mode
°
°
(T = – 40 C to + 85 C)
A
Parameter
Symbol
Conditions
–
Min
1.5
–
Typ
Max
Unit
V
V
DDDR
Data retention supply voltage
Data retention supply current
Release signal set time
–
0.1
5.5
10
–
I
V
= 1.5 V
µA
µs
DDDR
DDDR
t
–
0
–
SREL
217/fx (2)
t
Oscillator stabilization wait
time (1)
–
–
ms
ms
Released by RESET
Released by interrupt
WAIT
NOTES
1. During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator start-up.
2. Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time.
13–7
ELECTRICAL DATA
S3C7524/C7528/P7528/C7534/C7538/P7538
TIMING WAVEFORMS
INTERNAL RESET
OPERATION
IDLE MODE
OPERATING
MODE
STOP MODE
DATA RETENTION MODE
VDD
VDDDR
EXECUTION OF
STOP INSTRUCTION
RESET
tWAIT
tSREL
Figure 13-2. Stop Mode Release Timing When Initiated By RESET
IDLE MODE
NORMAL
OPERATING
MODE
STOP MODE
DATA RETENTION MODE
VDD
VDDDR
tSREL
EXECUTION OF
STOP INSTRUCTION
tWAIT
POWER-DOWN MODE TERMINATING SIGNAL
(INTERRUPT REQUEST)
Figure 13-3. Stop Mode Release Timing When Initiated By Interrupt Request
13–8
S3C7524/C7528/P7528/C7534/C7538/P7538
Timing Waveforms (continued)
ELECTRICAL DATA
0.8 VDD
0.2 VDD
0.8 VDD
0.2 VDD
MEASUREMENT
POINTS
Figure 13-4. A.C. Timing Measurement Points (Except for X )
in
1 / f
x
t
t
XH
XL
X
in
V
0.1 V
-
DD
0.1 V
Figure 13-5. Clock Timing Measurement at X
in
1 / f
TI
t
t
TIH
TIL
TCL
0.8 V
0.2 V
DD
DD
Figure 13-6. TCL Timing
13–9
ELECTRICAL DATA
S3C7524/C7528/P7528/C7534/C7538/P7538
tRSL
RESET
0.2 VDD
Figure 13-7. Input Timing for RESET Signal
t
t
INTL
INTH
INT0, 1, 2, 4
K0 to K7
0.8 V
0.2 V
DD
DD
Figure 13-8. Input Timing for External Interrupts and Quasi-Interrupts
13–10
S3C7524/C7528/P7528/C7534/C7538/P7538
MECHANICAL DATA
14 MECHANICAL DATA
This section contains the following information about the device package:
— Package dimensions in millimeters
— Pad diagram
— Pad/pin coordinate data table
#42
#22
0-15
42-SDIP-600
#1
#21
39.50 MAX
39.10 ± 0.20
0.50 ± 0.10
1.00 ± 0.10
1.78
(1.77)
NOTE: Dimensions are in millimeters.
Figure 14-1. 42-SDIP-600 Package Dimensions
14–1
MECHANICAL DATA
S3C7524/C7528/P7528/C7534/C7538/P7538
13.20 ± 0.30
10.00 ± 0.20
0-8
+ 0.10
- 0.05
0.15
0.10 MAX
44-QFP-1010B
#44
+ 0.10
0.35 - 0.05
#1
0.05 MIN
2.05 ± 0.10
2.30 MAX
0.80
(1.00)
0.15 MAX
NOTE: Dimensions are in millimeters.
Figure 14-2. 44-QFP-1010B Package Dimensions
14–2
S3C7524/C7528/P7528/C7534/C7538/P7538
MECHANICAL DATA
#30
#16
0-15
30-SDIP-400
#1
#15
27.88 MAX
27.48 ± 0.20
0.56 ± 0.10
1.12 ± 0.10
1.778
(1.30)
NOTE: Dimensions are in millimeters.
Figure 14-3. 30-SDIP-400 Package Dimensions
14–3
MECHANICAL DATA
S3C7524/C7528/P7528/C7534/C7538/P7538
0-8
#32
#17
32-SOP-450A
+ 0.10
0.25 - 0.05
#1
#16
20.30 MAX
19.90 ± 0.20
0.10 MAX
1.27
(0.43)
0.40 ± 0.10
NOTE: Dimensions are in millimeters.
Figure 14-4. 32-SOP-450A Package Dimensions
14–4
S3C7524/C7528/P7528/C7534/C7538/P7538
S3P7528/P7538 OTP
15 S3P7528/P7538 OTP
OVERVIEW
The S3P7528/P7538 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the
S3C7524/C7528/C7534/C7538 microcontroller. It has an on-chip EPROM instead of masked ROM. The EPROM
is accessed by a serial data format.
The S3P7528/P7538 is fully compatible with the S3C7528/C7538, both in function and in pin configuration.
Because of its simple programming requirements, the S3P7528/P7538 is ideal for use as an evaluation chip for
the S3C7528/C7538.
P1.0 / INT0
P1.1 / INT1
P1.2 / INT2
1
2
3
4
5
6
7
8
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
P9.2
P9.1
P9.0
DTMF
P7.3 / KS7
P7.2 / KS6
P7.1 / KS5
P7.0 / KS4
P6.3 / KS3
P6.2 / KS2
P6.1 / KS1
P6.0 / KS0
P5.3
P5.2
P5.1
P5.0
P8.3
P8.2
P8.1
P8.0
P4.3
P1.3 / INT4
P2.0 / TCLO0
P2.1 / TCLO1
P2.2 / CLO
P2.3 / BUZ
SDAT / P3.0 / TCL0
SCLK / P3.1 / TCL1
9
10
11
12
13
14
15
16
17
18
19
20
21
V
V
V
DD / DD
V
SS / SS
X
OUT
X
IN
TEST
V
PP /
P4.0 / BTCO
P4.1
RESET / RESET
P3.2
P3.3
P4.2
NOTE: The bold words indicate OTP pin names.
Figure 15-1. S3P7528 Pin Assignments (42-SDIP)
15–1
S3P7528/P7538 OTP
S3C7524/C7528/P7528/C7534/C7538/P7538
/ V
X
X
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
DD /
V
V
DD
SS
OUT
IN
SS
P3.1 / TCL1 /
P3.0 / TCL0 /
P2.3 / BUZ
P2.2 / CLO
P2.1 / TCLO1
P2.0 / TCLO0
P1.0 / INT0
NC
SCLK
SDAT
/ TEST
V
PP
P4.0 / BTCO
P4.1
RESET / RESET
P4.2
NC
P4.3
P5.0
P5.1
9
10
11
12
13
14
15
16
DTMF
P7.3 / KS7
P7.2 / KS6
P7.1 / KS5
P7.0 / KS4
P6.3 / KS3
P6.2 / KS2
P5.2
P5.3
P6.0 / KS0
P6.1 / KS1
Figure 15-2. S3P7528 Pin Assignments (44-QFP)
15–2
S3C7524/C7528/P7528/C7534/C7538/P7538
S3P7528/P7538 OTP
1
2
3
4
5
6
7
8
V
/
V
DD
/ V
X
X
V
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
DD
SS
OUT
IN
SS
P3.1 / TCL1 /
P3.0 / TCL0 /
P2.3 / BUZ
P2.2 / CLO
P2.1 / TCLO1
P2.0 / TCLO0
P1.0 / INT0
DTMF
P7.3 / KS7
P7.2 / KS6
P7.1 / KS5
P7.0 / KS4
P6.3 / KS3
P6.2 / KS2
SCLK
SDAT
/ TEST
P4.0 / BTCO
P4.1
V
PP
RESET / RESET
P4.2
P4.3
P5.0
P5.1
P5.2
9
10
11
12
13
14
15
P5.3
P6.0 / KS0
P6.1 / KS1
Figure 15-3. S3P7538 Pin Assignments (30-SDIP)
15–3
S3P7528/P7538 OTP
S3C7524/C7528/P7528/C7534/C7538/P7538
/ V
X
X
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
DD /
V
V
DD
SS
OUT
IN
SS
P3.1 / TCL1 /
P3.0 / TCL0 /
P2.3 / BUZ
P2.2 / CLO
P2.1 / TCLO1
P2.0 / TCLO0
P1.0 / INT0
NC
SCLK
SDAT
/ TEST
V
PP
P4.0 / BTCO
P4.1
RESET / RESET
P4.2
NC
P4.3
P5.0
P5.1
9
10
11
12
13
14
15
16
DTMF
P7.3 / KS7
P7.2 / KS6
P7.1 / KS5
P7.0 / KS4
P6.3 / KS3
P6.2 / KS2
P5.2
P5.3
P6.0 / KS0
P6.1 / KS1
Figure 15-4. S3P7538 Pin Assignments (32-SOP)
15–4
S3C7524/C7528/P7528/C7534/C7538/P7538
S3P7528/P7538 OTP
Table 15-1. S3P7528 Pin Descriptions Used to Read/Write the EPROM
During Programming
Main Chip
Pin Name
Pin Name
SDAT
Pin No.
I/O
Function
P3.0
9 (3)
I/O
Serial data pin. Output port when reading and
input port when writing. Can be assigned as a
Input / push-pull output port.
P3.1
SCLK
10 (4)
15 (9)
I/O
I
Serial clock pin. Input only pin.
VPP (TEST)
TEST
Power supply pin for EPROM cell writing
(indicates that OTP enters into the writing mode).
When 12.5 V is applied, OTP is in writing mode
and when 5 V is applied, OTP is in reading mode.
(Option)
18 (12)
I
I
Chip initialization
RESET
RESET
VDD / VSS
VDD / VSS
Logic power supply pin. VDD should be tied to +5
V during programming.
11/12
(5/6)
NOTE: Parentheses indicate pin numbers of 44 QFP package.
Table 15-2. S3P7538 Pin Descriptions Used to Read/Write the EPROM
During Programming
Main Chip
Pin Name
Pin Name
SDAT
Pin No.
I/O
Function
P3.0
28 (30)
I/O
Serial data pin. Output port when reading and
input port when writing. Can be assigned as a
Input / push-pull output port.
P3.1
SCLK
29 (31)
4 (4)
I/O
I
Serial clock pin. Input only pin.
VPP (TEST)
TEST
Power supply pin for EPROM cell writing
(indicates that OTP enters into the writing mode).
When 12.5 V is applied, OTP is in writing mode
and when 5 V is applied, OTP is in reading mode.
(Option)
7 (7)
I
I
Chip initialization
RESET
RESET
VDD / VSS
VDD / VSS
Logic power supply pin. VDD should be tied to +5
V during programming.
30/1
(32/1)
NOTE: Parentheses indicate pin numbers of 32 SDIP package.
15–5
S3P7528/P7538 OTP
S3C7524/C7528/P7528/C7534/C7538/P7538
Table 15-3. Comparison of S3P7528 and S3C7528 Features
Characteristic S3P7528
8 K byte EPROM
S3C7528
8 K byte mask ROM
2.0 V to 5.5 V
Program Memory
Operating Voltage (VDD
)
2.0 V to 5.5 V
VDD = 5 V, VPP (TEST) = 12.5 V
OTP Programming Mode
–
Pin Configuration
42 SDIP / 44 QFP
42 SDIP / 44 QFP
EPROM Programmability
User Program 1 time
Programmed at the factory
Table 15-4. Comparison of S3P7538 and S3C7538 Features
S3P7538
Characteristic
S3C7538
Program Memory
8 K byte EPROM
2.0 V to 5.5 V
8 K byte mask ROM
2.0 V to 5.5 V
Operating Voltage (VDD
)
VDD = 5 V, VPP (TEST) = 12.5 V
OTP Programming Mode
–
Pin Configuration
30 SOP / 32 SOP
30 SOP / 32 SOP
Programmed at the factory
EPROM Programmability
User Program 1 time
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the VPP(TEST) pin of the S3P7528, the EPROM programming mode is entered. The
operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in
Table 15-3 below.
Table 15-5. Operating Mode Selection Criteria
V
DD
Vpp
(TEST)
REG/
Address
(A15-A0)
Mode
R/W
MEM
5 V
5 V
0
0
0
1
0000H
0000H
0000H
0E3FH
1
0
1
0
EPROM read
12.5V
12.5V
12.5V
EPROM program
EPROM verify
EPROM read protection
NOTE: "0" means Low level; "1" means High level.
15–6
S3C7524/C7528/P7528/C7534/C7538/P7538
S3P7528/P7538 OTP
START
Address= First Location
V
=5V, V =12.5V
PP
DD
x = 0
Program One 1ms Pulse
Increment X
YES
x = 10
NO
FAIL
FAIL
NO
Verify Byte
Verify 1 Byte
Last Address
Increment Address
V
= V = 5 V
PP
DD
FAIL
Compare All Byte
PASS
Device Failed
Device Passed
Figure 15-5. OTP Programming Algorithm
15–7
S3P7528/P7538 OTP
S3C7524/C7528/P7528/C7534/C7538/P7538
NOTES
15–8
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