S3P8469-QT [SAMSUNG]
Microcontroller, 8-Bit, OTPROM, SAM87 CPU, 12MHz, CMOS, PQFP64, 14 X 20 MM, QFP-64;
| 型号： | S3P8469-QT |
| 厂家： | 
SAMSUNG |
| 描述： | Microcontroller, 8-Bit, OTPROM, SAM87 CPU, 12MHz, CMOS, PQFP64, 14 X 20 MM, QFP-64 可编程只读存储器 时钟 微控制器 外围集成电路 |
| 文件： | 总33页 (文件大小：228K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S3C8465/C8469/P8469
PRODUCT OVERVIEW
1
PRODUCT OVERVIEW
SAM8 PRODUCT FAMILY
Samsung's new SAM8 family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide
range of integrated peripherals, and various mask-programmable ROM sizes.
A dual address/data bus architecture and a large number of bit- or nibble-configurable I/O ports provide a flexible
programming environment for applications with varied memory and I/O requirements. Timer/counters with
selectable operating modes are included to support real-time operations. Many SAM8 microcontrollers have an
external interface that provides access to external memory and other peripheral devices.
A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more
interrupt sources and vectors. Fast interrupt processing (within a minimum six CPU clocks) can be assigned to
one interrupt level at a time.
S3C8465/C8469 MICROCONTROLLER
The S3C8465/C8469 single-chip 8-bit microcontroller is designed for useful 10-bit resolution A/D converter,
UART, SIO, ZCD extended PWM application field. Its powerful SAM87 CPU architecture includes. The internal
register file is logically expanded to increase the on-chip register space.
The S3C8465/C8469 has 16/32K bytes of on-chip program ROM. A sophisticated bus interface enables access to
external memory and other peripherals when you use the chip in ROM-less mode. Following Samsung's modular
design approach, the following peripherals are integrated with the SAM87 core:
— Large number of programmable I/O ports (total 56 pins)
— One asynchronous UART module
— One synchronous SIO module
— Analog-to-digital converter with eight input channels and 10-bit resolution
— One 8-bit basic timer for watchdog function
— One 8-bit timer/counter with three operating modes (timer 0)
— One 8-bit timer for zero-cross detection circuit (timer 2)
— Two general-purpose 16-bit timer/counters with four operating modes (timer module 1)
— PWM block with one capture module, 16-bit timer/counter, PWM extension mode, and two PWM outputs
— One zero cross detection module
The S3C8465/C8469 is a versatile general-purpose microcontroller that is ideal for use in a wide range of
electronics applications requiring complex timer/counter, PWM, capture, SIO, UART and ZCD functions.
It is available in a 64-pin SDIP or 64-pin QFP package.
OTP
The S3P8469 is an OTP (One Time Programmable) version of the S3C8465/C8469 microcontroller. The
S3P8469 microcontroller has an on-chip 32-Kbyte one-time-programmable EPROM instead of a masked ROM.
The S3P8469 is comparable to the S3C8465/C8469, both in function and in pin configuration.
1-1
PRODUCT OVERVIEW
S3C8465/C8469/P8469
FEATURES
CPU
Timer/Counters
•
SAM87 CPU core
•
•
One 8-bit basic timer for watchdog function
One 8-bit timer/counter with three operating
modes (timer 0)
Memory
•
•
•
528-byte general purpose register area
•
•
One 8-bit timer for the zero-cross detection
circuit
16/32K-byte internal program memory
ROM-less operating mode
Two 16-bit general-purpose timer/counters with
four operating modes (timer C and D)
External Interface
UART
•
•
64K-byte external data memory area
•
•
One UART module
64K-byte external program memory area
(ROM-less mode)
Full duplex serial I/O interface with three UART
modes
Instruction Set
A/D Converter
•
•
79 instructions
•
•
•
Eight analog input pins
IDLE and STOP instructions added for
power-down modes
10-bit conversion resolution
20 µs conversion time (10 MHz CPU clock)
Instruction Execution Time
500 ns at 12 MHz fOSC (minimum)
Zero Cross Detection Circuit
•
•
Zero cross detection circuit that generates a
digital signal in synchronization with an AC
signal input
Interrupts
•
•
•
21 interrupt sources and 21 vectors
Eight interrupt levels
Buzzer Frequency Output
200 Hz to 20 kHz signal can be generated
Fast interrupt processing
•
General I/O
Oscillator Frequency
•
•
Seven I/O ports (total 56 pins)
Seven bit-programmable ports
•
•
1 MHz to 12 MHz external crystal oscillator
Maximum 12 MHz CPU clock
PWM and Capture
Operating Temperature Range
•
•
Two 14-bit PWM output
One capture
° °
– 40 C to + 85 C
•
Operating Voltage Range
2.7 V to 5.5 V
Serial I/O
•
•
•
•
One synchronous serial I/O module
Package Types
64-pin SDIP, 64-pin QFP
Selectable transmit and receive rates
•
Selectable baud rate for Rx and Tx respectively
1-2
S3C8465/C8469/P8469
PRODUCT OVERVIEW
BLOCK DIAGRAM
P0.0-P0.7
(A8-A15)
P1.0-P1.7
(AD0-AD7)
P2.0-P2.3
P2.4/ZCD-P2.7/INT3
Basic
Timer
Port 0
Port 1
Port 0
SAM8 BUS
XIN
XOUT
OSC
Port 3
P3.0-P3.7
T0CK
T0
Port I/O and Interrupt
Control
Timer
TCG
TDG
TCCK
TDCK
Timers
C and D
P4.0/INT4-
P4.7/INT11
Port 4
Port 5
Port 6
PWM0
PWM1
CAPA
PWM/
CAP
SAM8 CPU
SI
SO
SCK
P5.0-P5.7
P6.0-P6.7
SIO
UART
ADC
RxD
TxD
16/32-Kbyte
ROM
528-byte
Register File
ADC0
-ADC7
Figure 1-1. Block Diagram
1-3
PRODUCT OVERVIEW
S3C8465/C8469/P8469
PIN ASSIGNMENTS
P1.0/AD0
P1.1/AD1
P1.2/AD2
P1.3/AD3
P1.4/AD4
P1.5/AD5
P1.6/AD6
P1.7/AD7
P5.7/ADC7
P5.6/ADC6
P5.5/ADC5
P5.4/ADC4
P5.3/ADC3
P5.2/ADC2
P5.1/ADC1
P5.0/ADC0
AVSS
AVREF
P6.7
P6.6
P6.5
P6.4
P6.3
P6.2
P6.1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P0.7/A15
P0.6/A14
P0.5/A13
P0.4/A12
P0.3/A11
P0.2/A10
P0.1/A9
1
2
3
4
5
6
7
8
P0.0/A8
P4.7/INT11/TDG
P4.6/INT10/TCG
P4.5/INT9/TDCK
P4.4/INT8/TCCK
P4.3/INT7/CAPA
P4.2/INT6
P4.1/INT5/RxD
VDD
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
S3C8465
S3C8469
VSS
XOUT
XIN
EA
64-SDIP-750
(Top View)
P4.0/INT4
P3.7/TxD
RESET
P3.6/SO
P3.5/SI
P3.4/SCK
P3.3/T0CK
P3.2/T0
P3.1/PWM1
P3.0/PWM0
P2.7/INT3
P2.6/INT2
P6.0
P2.0/AS
P2.1/DS
P2.2/R/W
P2.3/DM
P2.4/ZCD
P2.5/BUZ
Figure 1-2. Pin Assignment Diagram (64-SDIP)
1-4
S3C8465/C8469/P8469
PRODUCT OVERVIEW
P1.6/AD6
P1.7/AD7
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P0.0/A8
1
2
3
4
5
6
7
8
P4.7/INT11/TDG
P4.6/INT10/TCG
P4.5/INT9/TDCK
P4.4/INT8/TCCK
P4.3/INT7CAPA
P4.2/INT6
P4.1/INT5/RxD
VDD
P5.7/ADC7
P5.6/ADC6
P5.5/ADC5
P5.4/ADC4
P5.3/ADC3
P5.2/ADC2
P5.1/ADC1
P5.0/ADC0
AVSS
AVREF
P6.7
P6.6
P6.5
S3C8465/C8469
9
64-QFP-1420F
VSS
XOUT
XIN
EA
10
11
12
13
14
15
16
17
18
19
(Top View)
P4.0/INT4
P3.7/TxD
RESET
P3.6/SO
P3.5/SI
P6.4
P6.3
P6.2
P6.1
P3.4/SCK
Figure 1-3. Pin Assignment Diagram (64-Pin QFP Package)
1-5
PRODUCT OVERVIEW
S3C8465/C8469/P8469
Table 1-1. S3C8465/C8469 Pin Descriptions
Pin
Name
Pin
Type
Pin Description
Circuit
Number
Pin
Number
Share
Pins
P0.0–P0.7
I/O
Bit-programmable I/O port for Schmitt trigger
input or push-pull, open-drain, output. Pull-up
resistors are assignable by software.
Port 0 can also be configured as external
interface address line A8–A15
1
8–1
(1, 64–58)
–
A8–A15
P1.0–P1.7
P2.0–P2.3
I/O
I/O
Same general characteristics as port 0.
Port 1 can also be configured as external
interface address/data lines AD0–AD7
1
2
64–57
(57–50)
–
AD0–AD7
Bit-programmable I/O port for Schmitt trigger
input or push-pull output. P2.0–P2.3 can be
configured for external bus control signals.
P2.4–P2.7 are used for general I/O or for the
ZCD, BUZ, INT2 and INT3
38–35
(31–28)
–
AS, DS
DM, R/W
ZCD, BUZ
INT2, INT3
P2.4–P2.7
P3.0–P3.7
3
4
34–31
(27–24)
I/O
Bit-programmable I/O port for Schmitt trigger
input or push-pull output. Each port 3 pin has
an alternative function:
30–22
(23–15)
(See pin
description)
P3.0: PWM0 (PWM0 module output)
P3.1: PWM1 (PWM1 module ouptut)
P3.2: T0 (T0 capture input or PWM output)
P3.3: T0CK (timer 0 external clock input)
P3.4: SCK (SIO module input)
P3.5: SI (SIO module clock I/O)
P3.6: SO (SIO module output)
P3.7: TxD: SO1
(The T0 function for P3.2 is selected using the
T0CON register.)
P4.0–P4.7
I/O
Bit-programmable I/O port for Schmitt trigger
input or push-pull output. Port 4 pins are used
external interrupts INT4–INT11 or for the
following share functions:
5
21, 15–9
(14–2)
(See pin
description)
P4.1: RxD (UART module input)
P4.3: CAPA (capture input)
P4.4: TCCK (timer/counter C clock input)
P4.5: TDCK (timer/counter D clock input)
P4.6: TCG (timer C gate input)
P4.7: TDG (timer D gate input)
1-6
S3C8465/C8469/P8469
PRODUCT OVERVIEW
Table 1-1. S3C8465/C8469 Pin Descriptions (Continued)
Pin
Name
Pin
Type
Pin Description
Circuit
Number
Pin
Number
Share
Pins
P5.0–P5.7
I/O
Bit-programmable I/O port for Schmitt trigger
input or push-pull, output. Pull-up resistors are
assignable by software. Port 5 pins can also be
used as A/D converter inputs.
6
49–56
(42–49)
ADC0–
ADC7
P6.0–P6.7
AD0–AD7
I/O
Individual pins are software configurable as
input or push-pull, open-drain, output. Pull-up
resistors are assignable by software.
1
39–46
(32–39)
–
I/O
I/O
External interface address/data line
6
2
64–57
(57–50)
P1.0–P1.7
P2.0–P2.3
External bus control signals
38–35
(31–28)
AS
DS
R/W
DM
ZCD
BUZ
I/O
I/O
Zero cross detector input
2
2
34 (27)
33 (26)
P2.4
P2.5
200 Hz–20 kHz frequency output for buzzer
sound
PWM0
PWM1
I/O
PWM output
3
30, 29
(23, 22)
P3.0–P3.1
T0 (CAP)
T0CK
I/O
I/O
I/O
I/O
T0 capture input or PWM output
External clock input for Timer 0
SIO clock signal
3
3
3
3
28 (21)
27 (20)
26 (19)
P3.2
P3.3
SCK
P3.4
SI, SO
SIO data input/output
25, 24
P3.5–P3.6
(18, 17)
TxD
I/O
I/O
UART data output
3
2
22 (15)
P3.7
INT2–INT3
External interrupts: the triggering edge is
selectable.
32, 31
(25, 24)
P2.6–P2.7
INT4
I/O
I/O
I/O
External interrupts: the triggering edge is
selectable.
4
4
4
21 (14)
15 (8)
P4.0
P4.1
RxD/INT5
UART data input or external interrupt: the
triggering edge is selectable.
INT6
CAPA/INT7
Capture module input or external interrupt: the
triggering edge is selectable.
14,13
(7, 6)
P4.2–P4.3
1-7
PRODUCT OVERVIEW
S3C8465/C8469/P8469
Table 1-1. S3C8465/C8469 Pin Descriptions (Concluded)
Pin
Name
Pin
Type
Pin Description
Circuit
Number
Pin
Number
Share
Pins
TCCK/INT8
TCDK/INT9
I/O
I/O
I/O
–
Timer/counter C and D clock input or external
interrupts: the triggering edge is selectable.
4
4
5
–
12, 11
(5, 4)
P4.4–P4.5
P4.6–P4.7
P5.0–P5.7
–
TCG/INT10
TDG/INT11
Timer/counter C and D clock input or external
interrupts: the triggering edge is selectable.
10, 9
(3, 2)
ADC0–
ADC7
A/D converter inputs
49–56
(42–49)
XIN, XOUT
System clock input and output pins
19, 18
(12, 11)
I
I
System reset pin
7
–
23 (16)
20 (13)
–
–
RESET
EA
External access (EA) pin with three modes:
0 V: Normal operation (internal ROM)
5 V: ROM-less operation (external interface)
12.5 V: OTP read/write mode
AVREF
AVSS
,
–
–
A/D converter reference voltage input and
ground
–
–
47, 48
(40, 41)
–
–
VDD ,VSS
Voltage input pin and ground
16, 17
(9, 10)
NOTE: Pin numbers shown in parentheses "( )" are for the 64-pin QFP package.
1-8
S3C8465/C8469/P8469
PRODUCT OVERVIEW
PIN CIRCUITS
Table 1-2. Pin Circuit Assignments for the S3C8465/C8469
Circuit Number
Circuit Type
S3C8465/C8469 Assignments
Port 0,1 and port 6
1
2
3
4
5
6
7
I/O
I/O
I/O
I/O
I/O
I/O
I
Port 2 (P2.0–P2.3 only)
Port 2 (P2.4–P2.7 only)
Port 3
Port 4
Port 5
RESET
NOTE: Diagrams of circuit types 1–7 are presented below.
1-9
PRODUCT OVERVIEW
S3C8465/C8469/P8469
VDD
Pull-up Resistor
(Typical Value: 47 KW)
Pull-up
Enable
VDD
Data
In/Out
Open-drain
Output DIsable
In
Figure 1-4. Pin Circuit Type 1 (Port 0,1 and Port 6)
VDD
Pull-up Resistor
(Typical Value: 47 KW)
Pull-up
Enable
Select
VDD
Port 2 (Low Byte) Data
M
U
X
Data
External Interface
(AS, DS, R/W, DM)
In/Out
Output DIsable
In
Figure 1-5. Pin Circuit Type 2 (Port 2, P2.0–P2.3 only)
1-10
S3C8465/C8469/P8469
PRODUCT OVERVIEW
VDD
Pull-up Resistor
(Typical Value: 47 KW)
Pull-up
Enable
Select
VDD
Port 2 (High Byte) Data
Control Output (BUZ)
M
U
X
In/Out
Output DIsable
External
Interrupt Input
Noise Filter
Normal
Input
ZCD Input
Figure 1-6. Pin Circuit Type 3 (Port 2, P2.4–P2.7 only)
1-11
PRODUCT OVERVIEW
S3C8465/C8469/P8469
VDD
Pull-up Resistor
(Typical Value: 47 KW)
Pull-up
Enable
Select
VDD
Port 3
M
U
X
Data
Control
Output
In/Out
Output
DIsable
Normal
Input
Figure 1-7. Pin Circuit Type 4 (Port 3)
VDD
Pull-up Resistor
(Typical Value: 47 KW)
Pull-up
Enable
VDD
Data
In/Out
Output
DIsable
External
Interrupt Input
Noise Filter
Alternative
Input
Normal
Input
Figure 1-8. Pin Circuit Type 5 (Port 4)
1-12
S3C8465/C8469/P8469
PRODUCT OVERVIEW
VDD
Pull-up Resistor
(Typical Value: 47 KW)
Pull-up
Enable
VDD
Data
In/Out
Output
DIsable
Normal
Input
Analog
Input
Figure 1-9. Pin Circuit Type 6 (Port 5)
VDD
Pull-up Resistor
(Typical Value: 200 KW)
RESET
Figure 1-10. Pin Circuit Type 7 (RESET)
1-13
S3C8465/C8469/P8469
ELECTRICAL DATA
19 ELECTRICAL DATA
OVERVIEW
In this chapter, S3C8465/C8469 electrical characteristics are presented in tables and graphs. The information is
arranged in the following order:
— Absolute maximum ratings
— Input/output capacitance
— D.C. electrical characteristics
— A.C. electrical characteristics
— Oscillation characteristics
— Oscillation stabilization time
— Data retention supply voltage in stop mode
— Serial I/O timing characteristics
— UART timing characteristics in mode 0
— A/D converter electrical characteristics
— Zero crossing detector
— External memory timing characteristics
19-1
ELECTRICAL DATA
S3C8465/C8469/P8469
Table 19-1. Absolute Maximum Ratings
°
(TA = 25 C)
Parameter
Supply Voltage
Input Voltage
Symbol
Conditions
–
Rating
Unit
V
VDD
– 0.3 to + 6.5
– 0.3 to VDD + 0.3
– 0.3 to VDD + 0.3
– 18
VI
All input ports
All output ports
One I/O pin active
V
VO
IOH
Output Voltage
Output Current High
V
mA
All I/O pins active
One I/O pin active
– 60
+ 30
IOL
Output Current Low
mA
Total pin current for ports 0, 2–4, and 6
+ 100
+ 200
Total pin current for ports 1 and 5
–
TA
°
C
Operating
– 40 to + 85
Temperature
TSTG
°
C
Storage Temperature
–
– 65 to + 150
Table 19-2. Input/Output Capacitance
°
°
(TA = – 40 C to 85 C, VDD = 0 V )
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
CIN
Input Capacitance
f = 1 MHz; unmeasured pins
are tied to VSS
–
–
10
pF
COUT
CIO
Output Capacitance
I/O Capacitance
19-2
S3C8465/C8469/P8469
ELECTRICAL DATA
Table 19-3. D.C. Electrical Characteristics
°
°
(T = – 40 C to + 85 C, VDD = 2.7 V to 5.5 V)
A
Parameter
Symbol
Conditions
VDD = 2.7 V to 5.5 V
All Port and RESET
Min
Typ
Max
Unit
VIH1
0.8 VDD
VDD
Input High Voltage
–
V
VIH2
VIL1
VIL2
VOH
VDD = 4.5 V to 5.5 V
XIN and XOUT
VDD – 1.0
VDD = 2.7 V to 5.5 V
0.2 VDD
Input Low Voltage
–
–
V
All Ports and RESET
VDD = 4.5 V to 5.5 V
XIN and XOUT
0.1
–
VDD = 4.5 V to 5.5 V
IOH = – 1 mA
All Ports
VDD – 1.0
Output High Voltage
Output Low Voltage
–
V
V
VOL1
VDD = 4.5 V to 5.5 V
IOL = 15 mA
–
0.4
2.0
Ports 1,5, and 6
VOL2
VDD = 4.5 V to 5.5 V
IOL = 4 mA
Ports 0, 2, 3, and 4
ILIH1
ILIH2
ILIL1
VIN = VDD
All input pins except ILIH2
Input High Leakage
Current
–
–
–
–
1
µA
µA
VIN = VDD
XIN, XOUT
20
– 1
VIN = 0 V
Input Low Leakage
Current
All input pins except and
ILIL2 and RESET
ILIL2
VIN = 0 V
XIN, XOUT
– 20
ILOH1
ILOL
VOUT = VDD
All output pins
VOUT = 0 V
Output High
Leakage Current
–
–
–
–
2
µA
µA
Output Low Leakage
Current
– 2
All output pins
19-3
ELECTRICAL DATA
S3C8465/C8469/P8469
Table 19-3. D.C. Electrical Characteristics (Continued)
°
°
(T = – 40 C to + 85 C, VDD = 2.7 V to 5.5 V)
A
Parameter
Symbol
Conditions
Min
30
Typ
47
Max
70
Unit
RP1
VDD = 5 V; VIN = 0 V
Pull-up Resistor
kW
VDD = 3 V; Ports 0–6
VDD = 5 V; VIN = 0 V
30
–
350
400
800
RP2
100
200
200
400
VDD = 3 V; RESET only
IDD1
VDD = 4.5 V to 5.5 V
Supply Current
(note)
–
16
30
mA
RUN mode
12 MHz CPU clock
VDD = 2.7 V to 3.3 V
8 MHz CPU clock
5.5
3
12
6
IDD2
VDD = 4.5 V to 5.5 V
Idle mode
12 MHz CPU clock
VDD = 2.7 V to 3.3 V
8 MHz CPU clock
VDD = 4.5 V to 5.5 V
Stop mode
1
1
2.5
5
IDD3
µA
VDD = 2.7 V to 3.3 V
Stop mode
NOTE: Supply current does not include current drawn through internal pull-up resistors, ZCD, ADC and external output
current loads.
Table 19-4. A.C. Electrical Characteristics
°
°
(TA = – 40 C to + 85 C, VDD = 2.7 V to 5.5 V)
Parameter
Symbol
Conditions
Ports 2, 3, and 4
Min
Typ
Max
Unit
tINTH
,
tINTL
Interrupt Input
High, Low Width
–
270
–
ns
tRSL
Input
–
1500
–
ns
RESET Input
Low Width
tINTL
tRSL
tINTH
0.8 VDD
0.2 VDD
Figure 19-1. Input Timing Measurement Points
19-4
S3C8465/C8469/P8469
ELECTRICAL DATA
Table 19-5. Oscillation Characteristics
°
°
(T = – 40 C + 85 C)
A
Oscillator
Main Crystal or
Ceramic
Clock Circuit
Test Condition
Min
1
Typ
–
Max
12
8
Unit
VDD = 4.5 V to 5.5 V
MHz
VDD = 2.7 V to 4.5 V
1
–
XIN
XOUT
C1
C2
VDD = 4.5 V to 5.5 V
VDD = 2.7 V to 4.5 V
External Clock
(Main System)
1
1
–
–
12
8
MHz
XIN
XOUT
Main Oscillator Frequency
CPU Clock
12 kHz
8 kHz
1 kHz
1
2
3
4
5
6
7
2.7 V
5.5 V
Supply Voltage (V)
Figure 19-2. Operating Voltage Range
19-5
ELECTRICAL DATA
S3C8465/C8469/P8469
Table 19-6. Oscillation Stabilization Time
°
°
(TA = – 40 C + 85 C, VDD = 2.7 V to 5.5 V)
Oscillator
Main Crystal
Main Ceramic
Test Condition
Min
–
Typ
–
Max
20
Unit
ms
fOSC > 400 kHz;
Oscillation stabilization occurs when VDD is equal
to the minimum oscillator voltage range.
XIN input High and Low width (tXH, tXL)
–
–
10
ms
External Clock
(Main System)
25
–
–
500
–
ns
tWAIT when released by a reset (1)
216/fOSC
Oscillator
ms
Stabilization
Wait Time
tWAIT when released by an interrupt (2)
–
–
–
ms
NOTES:
1.
f
is the oscillator frequency.
OSC
2. The duration of the oscillator stabilization wait time, t
settings in the basic timer control register, BTCON.
, when it is released by an interrupt is determined by the
WAIT
19-6
S3C8465/C8469/P8469
ELECTRICAL DATA
Table 19-7. Data Retention Supply Voltage in Stop Mode
°
°
(TA = – 40 C to + 85 C, VDD = 2.7 V to 5.5 V)
Parameter
Symbol
Conditions
Stop mode
Min
Typ
Max
Unit
VDDDR
Data Retention
Supply Voltage
2
–
5.5
V
IDDDR
Stop mode, VDDDR = 2.0 V
Data Retention
Supply Current
–
–
5
µA
NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads.
RESET
Oscillation
occurs
Stabilzation
Time
Stop Mode
Data Retention Mode
VDD
Normal
Operating
Mode
VDDDR
Execution of
STOP Instrction
RESET
tWAIT
NOTE: tWAIT is the same as 4096 x 16 x 1/fOSC.
Figure 19-3. Stop Mode Release Timing When Initiated by a Reset
19-7
ELECTRICAL DATA
S3C8465/C8469/P8469
Table 19-8. Serial I/O Timing Characteristics
°
°
(TA = – 40 C to + 85 C, VDD = 2.7 V to 5.5 V)
Parameter
SCK Cycle Time
Symbol
Conditions
Min
1000
Typ
Max
Unit
tCKY
–
–
ns
External SCK source
Internal SCK source
External SCK source
Internal SCK source
External SCK source
Internal SCK source
External SCK source
Internal SCK source
External SCK source
Internal SCK source
1000
tKH, tKL
500
–
–
–
–
–
–
–
SCK High, Low Width
tKCY/2 – 50
tSIK
250
250
400
400
–
SI Setup Time to SCK Low
SI Hold Time to SCK High
Output Delay for SCK to SO
tKSI
tKSO
300
250
NOTE: "SCK" means serial I/O clock frequency, "SI" means serial data input, and "SO" means serial data output.
tKCY
tKL
tKH
SCK
0.8 VDD
0.2 VDD
tSIK
tKSI
0.8 VDD
0.2 VDD
SI
Input Data
tKSO
SO
Output Data
Figure 19-4. Serial Data Transfer Timing
19-8
S3C8465/C8469/P8469
ELECTRICAL DATA
Table 19-9. UART Timing Characteristics in Mode 0 (10 MHz)
°
°
(T = – 40 C to + 85 C, VDD = 2.7 V to 5.5 V, Load capacitance = 80 pF)
A
Parameter
Symbol
Min
Typ
Max
Unit
tSCK
Serial port clock cycle time
500
700
–
ns
t
t
CPU ´ 6
tS1
tS2
tH1
tH2
Output data setup to clock rising edge
Clock rising edge to input data valid
Output data hold after clock rising edge
Input data hold after clock rising edge
Serial port clock High, Low level width
300
CPU ´ 5
–
tCPU
–
–
tCPU – 50
0
300
–
–
tHIGH, LOW
t
200
400
t
CPU ´ 3
NOTES:
1. All timings are in nanoseconds (ns) and assume a 10-MHz CPU clock frequency.
2. The unit tCPU means one CPU clock period.
tSCK
tHIGH
tLOW
0.8 VDD
0.2 VDD
Figure 19-5. Waveform for UART Timing Characteristics
19-9
ELECTRICAL DATA
S3C8465/C8469/P8469
Figure 19-6. A.C. Timing Waveform for the UART Module
19-10
S3C8465/C8469/P8469
ELECTRICAL DATA
Table 19-10. A/D Converter Electrical Characteristics
°
°
(T = – 40 C to + 85 C, VDD = 2.7 V to 5.5 V, VSS = 0 V)
A
Parameter
Resolution
Symbol
Test Conditions
Min
–
Typ
10
–
Max
Unit
bit
–
VDD = 5.12 V
Total accuracy
–
LSB
± 3
Integral linearity
error
ILE
CPU clock = 10 MHz
AVREF = 5.12 V
–
± 2
AVSS = 0 V
Differential
linearity error
DLE
EOT
EOB
tCON
–
± 1
± 0.5
–
± 1
± 3
± 2
–
Offset error of
top
Offset error of
bottom
Conversion time
(1)
10-bit conversion
50 x 4/fOSC (3), fOSC = 10 MHz
20
ms
VIAN
RAN
AVSS
2
AVREF
–
Analog input
voltage
–
–
–
–
–
–
V
MW
V
Analog input
impedance
AVREF
VDD
Analog
2.5
reference
voltage
AVSS
IADIN
VSS
–
VSS + 0.3
10
Analog ground
–
–
–
V
AVREF = VDD = 5 V
Analog input
current
mA
conversion time = 20 ms
AVREF = VDD = 5 V
IADC
Analog block
current (2)
1
3
mA
mA
nA
conversion time = 20 ms
AVREF = VDD = 3 V
0.5
100
1.5
500
conversion time = 20 ms
AVREF = VDD = 5 V
when power down mode
NOTES:
1. "Conversion time" is the time required from the moment a conversion operation starts until it ends.
2.
I
is operating current during A/D conversion.
ADC
OSC
3.
f
is the main oscillator clock.
19-11
ELECTRICAL DATA
S3C8465/C8469/P8469
Table 19-11. Zero Crossing Detector
°
°
(T = – 40 C to + 85 C, VDD = 4.5 V to 5.5 V, VSS = 0 V)
A
Parameter
Symbol
Test Conditions
AC connection
c = 0.1 mF
Min
Typ
Max
Unit
VZC
Zero-crossing
detection input
voltage
1.0
–
3.0
Vp-p
VAZC
fZC = 60 Hz (sine wave)
VDD = 5 V
fOSC = 10 MHz
Zero-crossing
detection accuracy
–
–
–
mV
Hz
± 150
–
fZC
Zero-crossing
detection input
frequency
40
200
1/fzc
AC input
VAZC
VAZ (P-P)
ZCINT
Figure 19-7. Zero Crossing Waveform Diagram
19-12
S3C8465/C8469/P8469
ELECTRICAL DATA
Table 19-12. External Memory Timing Characteristics (8 MHz)
°
°
(T = – 40 C to + 85 C, V
= 2.7 V to 5.5 V)
A
DD
Number
Symbol
Parameter
Normal Timing (ns)
Min
Max
t
t
t
t
t
t
t
t
t
t
t
t
t
t
(AS)
(A)
1
2
10
–
dA
Address valid to AS • delay
AS • to address float delay
AS • to read data required valid
AS Low width
35
–
140
–
dAS
dAS
wAS
(DR)
3
–
4
43.75 (35)
(DS)
5
0
–
dA
Address float to DS ¯
(read)
(write)
(DR)
(DR)
(A)
6a
6b
7
156.25 (125)
–
wDS
wDS
dDS
hDS
dDS
dDS
dDO
dRW
dDS
DS (read) Low width
81.25 (65)
–
DS (write) Low width
–
80
–
DS ¯ to read data required valid
Read data to DS • hold time
DS • to address active delay
DS • to AS ¯ delay
8
0
9
20
30
10
20
20
–
(AS)
(DS)
(AS)
(DW)
10
11
12
13
–
–
Write data valid to DS (write) ¯ delay
R/W valid to AS • delay
DS • to write data not valid delay
–
–
NOTES:
1. All times are in nanoseconds (ns) and assume an 8-MHz input frequency.
2. Wait states add 100 ns to the time of numbers 3, 6a, 6b, and 7.
3. The values for t
and t
that are shown in parentheses "( )" assume a 10-MHz input clock.
wDS
wAS
19-13
ELECTRICAL DATA
S3C8465/C8469/P8469
R/W (P2.2)
12
Port 0
DM (P2.3)
A8-A15, DM
3
9
Port 1
AS (P2.0)
DS (P2.1)
A0-A7
D0-D7 Out
D0-D7
In
8
Out
10
1
4
2
11
5
7
6
13
Figure 19-8. External Memory Read and Write Timing
(See Table 19-10 for a description of each timing point.)
19-14
S3C8465/C8469/P8469
MECHANICAL DATA
20 MECHANICAL DATA
OVERVIEW
The S3C8465/C8469/P8469 microcontrollers are available in a 64-SDIP-750, 64-QFP-1420F package.
#64
#33
0-15
64-SDIP-750
#1
#32
58.20 MAX
57.80 ± 0.20
0.45 ± 0.10
1.00 ± 0.10
1.778
(1.34)
NOTE: Dimensions are in millimeters.
Figure 20-1. 64-SDIP-750 Package Dimensions
20-1
MECHANICAL DATA
S3C8465/C8469/P8469
23.90 ± 0.30
20.00 ± 0.20
0-8
+ 0.10
- 0.05
0.15
0.10 MAX
64-QFP-1420F
#64
+ 0.10
0.40 - 0.05
#1
0.05 MIN
2.65 ± 0.10
3.00 MAX
1.00
0.15 MAX
(1.00)
0.80 ± 0.20
NOTE: Dimensions are in millimeters.
Figure 20-2. 64-QFP-1420F Package Dimensions
20-2
S3C8465/C8469/P8469
KS88P4632 OTP
21 S3P8469 OTP
OVERVIEW
The S3P8469 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the
S3C8465/C8469 microcontroller. It has an on-chip OTP ROM instead of a masked ROM. The EPROM is
accessed by serial data format.
The S3P8469 is fully compatible with the S3C8465/C8469, both in function in D.C. electrical characteristics and
in pin configuration. Because of its simple programming requirements, the S3P8469 is ideal as an evaluation
chip for the S3C8465/C8469.
21-1
KS88P4632 OTP
S3C8465/C8469/P8469
P1.0/AD0
P1.1/AD1
P1.2/AD2
P1.3/AD3
P1.4/AD4
P1.5/AD5
P1.6/AD6
P1.7/AD7
P5.7/ADC7
P5.6/ADC6
P5.5/ADC5
P5.4/ADC4
P5.3/ADC3
P5.2/ADC2
P5.1/ADC1
P5.0/ADC0
AVSS
AVREF
P6.7
P6.6
P6.5
P6.4
P6.3
P6.2
P6.1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P0.7/A15
P0.6/A14
P0.5/A13
P0.4/A12
P0.3/A11
P0.2/A10
P0.1/A9
P0.0/A8
1
2
3
4
5
6
7
8
P4.7/INT11/TDG
P4.6/INT10/TCG
P4.5/INT9/TDCK
P4.4/INT8/TCCK
P4.3/INT7/CAPA
SDAT/P4.2/INT6
SCLK/P4.1/INT5/RxD
VDD/VDD
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
S3C8465
S3C8469
(64-SDIP)
VSS/VSS
XOUT
XIN
VPP/EA
P4.0/INT4
Top View
P3.7/TxD
RESET/RESET
P3.6/SO
P3.5/SI
P3.4/SCK
P6.0
P2.0/AS
P2.1/DS
P2.2/R/W
P2.3/DM
P2.4/ZCD
P2.5/BUZ
P3.3/T0CK
P3.2/T0
P3.1/PWM1
P3.0/PWM0
P2.7/INT3
P2.6/INT2
NOTE:
The bolds indicate an OTP pin name.
Figure 21-1. S3P8469 Pin Assignments (64-SDIP Package)
21-2
S3C8465/C8469/P8469
KS88P4632 OTP
P1.6/AD6
P1.7/AD7
P5.7/ADC7
P5.6/ADC6
P5.5/ADC5
P5.4/ADC4
P5.3/ADC3
P5.2/ADC2
P5.1/ADC1
P5.0/ADC0
AVSS
AVREF
P6.7
P6.6
P6.5
P6.4
P6.3
P6.2
P6.1
P0.0/A8
P4.7/INT11/TDG
P4.6/INT10/TCG
P4.5/INT9/TDCK
P4.4/INT8/TCCK
P4.3/INT7CAPA
SDAT/P4.2/INT6
SCLK/P4.1/INT5/RxD
VDD/VDD
S3C8465
S3C8469
(64-QFP)
VSS/VSS
XOUT
XIN
VPP/EA
P4.0/INT4
Top View
P3.7/TxD
RESET/RESET
P3.6/SO
P3.5/SI
P3.4/SCK
NOTE:
The bolds indicate an OTP pin name.
Figure 21-2. S3P8469 Pin Assignments (64-QFP Package)
21-3
KS88P4632 OTP
S3C8465/C8469/P8469
Table 21-1. Descriptions of Pins Used to Read/Write the EPROM
During Programming
Main Chip
Pin Name
P4.2
Pin Name
Pin No.
I/O
Function
SDAT
14(7)
I/O
Serial data pin. Output port when reading and
input port when writing. Can be assigned as a
Input/push-pull output port.
P4.1
EA
SCLK
VPP
15(8)
I
I
Serial clock pin. Input only pin.
20(13)
Power supply pin for EPROM cell writing
(indicates that OTP enters into the writing mode).
When 12.5 V is applied, OTP is in writing mode
and when 5 V is aplied, OTP is in reading mode.
(Option)
23(16)
I
Chip Initialization
RESET
RESET
VDD/VSS
VDD/VSS
16(9)/17(10)
–
Logic power supply pin. VDD should be tied to
+5 V during programming.
NOTE: ( ) means 64 QFP package.
Table 21-2. Comparison of S3P8469 and S3C8465/C8469 Features
Characteristic S3P8469 S3C8465/C8469
32K-byte EPROM
Program Memory
16/32K-byte mask ROM
2.7 V to 5.5 V
Operating Voltage (VDD
)
2.7 V to 5.5 V
OTP Programming Mode
VDD = 5 V, VPP (EA) = 12.5 V
Pin Configuration
64 SDIP/64 QFP
64 SDIP/64 QFP
EPROM Programmability
User Program 1 time
Programmed at the factory
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the VPP (EA) pin of the S3P8469, the EPROM programming mode is entered. The
operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in
Table 21-3 below.
Table 21-3. Operating Mode Selection Criteria
V
ADDRESS
(A15–A0)
VDD
REG/
R/W
MODE
PP
(EA)
MEM
5 V
5 V
0
0
0
1
0000H
0000H
0000H
0E3FH
1
0
1
0
EPROM read
12.5 V
12.5 V
12.5 V
EPROM program
EPROM verify
EPROM read protection
NOTE: "0" means Low level; "1" means High level.
21-4
相关型号：
S3P8475-AQ
Microcontroller, 8-Bit, OTPROM, SAM87RC CPU, 12MHz, CMOS, PDIP42, 0.600 INCH, SDIP-42
SAMSUNG
S3P8475-QZ
Microcontroller, 8-Bit, OTPROM, SAM87RC CPU, 12MHz, CMOS, PQFP44, 10 X 10 MM, QFP-44
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