S6B0107 [SAMSUNG]
64CH COMMON DRIVER FOR DOT MATRIX LCD; 64路公共驱动器点阵LCD
| 型号： | S6B0107 |
| 厂家： | 
SAMSUNG |
| 描述： | 64CH COMMON DRIVER FOR DOT MATRIX LCD |
| 文件： | 总23页 (文件大小：228K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
64CH COMMON DRIVER FOR DOT MATRIX LCD
S6B0107
INTRODUCTION
The S6B0107 (TQFP type: S6B2107) is an LCD driver LSI with 64 channel outputs for dot m atrix liquid
crystal graphic display system s. This device provides 64 shift registers and 64 output drivers. It
generates the tim ing signal to control the S6B0108 (64 channel segm ent driver – TQFP type: S6B2108).
The S6B0107 is fabricated by low power CMOS high voltage process technology, and is com posed of the
liquid crystal display system in com bination with the S6B0108 (64 channel segm ent driver).
FEATURES
·
·
·
·
·
·
·
Dot m atrix LCD com m on driver with 64 channel output
64-bit shift register at internal LCD driver circuit
Internal tim ing generator circuit for dynam ic display
Selection of m aster/ slave m ode
Applicable LCD duty: 1/ 48, 1/ 64, 1/ 96, 1/ 128
Power supply voltage: + 5V ± 10%
LCD driving voltage: 8V - 17V (VDD-VEE
Interface
)
·
Driver
COMMON
Controller
SEGMENT
S6B0108
Other S6B0107
MPU
·
·
High voltage CMOS process
100QFP / 100TQFP or bare chip available
1
S6B0107
64CH COMMON DRIVER FOR DOT MATRIX LCD
BLOCK DIAGRAM
V0L
V1L
V4L
V5L
V0R
V1R
V4R
V5R
64 bit 4- Level Driver
64 bit Bi-Directional Shift
Register
DIO1
PCLK2
SHL
Data Shift Direction & Phase
Selection Control Circuit
DIO2
M
CL2
C
R
CR
FRM
CLK1
CLK2
Tim ing Generator
Circuit
OSC
2
64CH COMMON DRIVER FOR DOT MATRIX LCD
S6B0107
PIN CONFIGURATION
100 QFP
C43
C44
C45
C46
C47
C48
C49
C50
C51
C52
C53
C54
C55
C56
C57
C58
C59
C60
C61
C62
C63
C64
VEE
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
C22
C21
C20
C19
C18
C17
C16
C15
C14
C13
C12
C11
C10
C9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
C8
C7
C6
C5
C4
C3
C2
C1
VEE
V1R
V4R
V5R
V0R
NC
V1L
V4L
V5L
V0L
VDD
CL2
NC
DIO1
FS
3
S6B0107
64CH COMMON DRIVER FOR DOT MATRIX LCD
PAD DIAGRAM (CHIP LAYOUT FOR THE 100QFP)
C21
C20
C19
C18
C17
C16
C15
C14
2
3
4
5
6
7
8
9
79 C44
78 C45
77 C46
76 C47
75 C48
74 C49
73 C50
72 C51
71 C52
70 C53
69 C54
68 C55
67 C56
66 C57
65 C58
64 C59
Y
C13 10
C12 1 1
C11 12
C10 13
C9 14
C8 15
C7 16
C6 17
C5 18
C4 19
C3 20
C2 21
C1 22
(0, 0)
X
Chip size: 3450
´
4000
PAD size: 100 100
Unit
63 C60
62 C61
61 C62
60 C63
59 C64
´
:m m
VEE
23
58
VEE
V1L 24
V4L 25
V5L 26
V0L 27
57 V1R
56 V4R
55 V5R
54 V0R
There is the m ark S6B0107 on the center of the chip.
4
64CH COMMON DRIVER FOR DOT MATRIX LCD
PAD CENTER COORDINATES (100QFP)
S6B0107
Pad
Pad
Coordinate
Pad
Pad
Coordinate
Pad
Pad
Coordinate
Number Name
Number Name
Number Name
X
Y
X
Y
X
Y
1
C22
C21
C20
C19
C18
C17
C16
C15
C14
C13
C12
C11
C10
C9
-1314.5 1775.4
32
34
35
37
39
40
42
43
44
46
47
49
50
52
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
DS2
C
-677.6
-527.6
-377.6
-227.6
-77.6
-1775
-1775
-1775
-1775
-1775
-1775
-1775
-1775
-1775
-1775
-1775
-1775
-1775
-1775
-1495
-1370
-1245
-1120
-995
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
C52
C51
C50
C49
C48
C47
C46
C45
C44
C43
C42
C41
C40
C39
C38
C37
C36
C35
C34
C33
C32
C31
C30
C29
C28
C27
C26
C25
C24
C23
1500.9
1500.9
1500.9
1500.9
1500.9
1500.9
1500.9
1500.9
1500.9
630
2
-1499.9
-1499.9
-1499.9
-1499.9
-1499.9
-1499.9
-1499.9
-1499.9
-1499.9
-1499.9
-1499.9
-1499.9
-1499.9
-1499.9
-1499.9
-1499.9
-1499.9
-1499.9
-1499.9
-1499.9
-1499.9
-1499.9
1630
1505
1380
1255
1130
1005
880
755
3
R
880
4
CR
1005
1130
1255
1380
1505
1630
5
SHL
VSS
MS
6
113.8
308.7
458.7
608.7
758.7
908.7
7
8
CLK2
CLK1
FRM
M
9
755
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
630
1310.5 1775.4
1185.5 1775.4
1060.5 1775.4
505
380
PCLK2 1058.7
255
DI02
CL2
V0R
V5R
V4R
V1R
VEE
C64
C63
C62
C61
C60
C59
C58
C57
C56
C55
C54
C53
1208.7
1358.7
1500.9
1500.9
1500.9
1500.9
1500.9
1500.9
1500.9
1500.9
1500.9
1500.9
1500.9
1500.9
1500.9
1500.9
1500.9
1500.9
1500.9
935.5
810.5
685.5
560.5
435.5
310.5
185.5
60.5
1775.4
1775.4
1775.4
1775.4
1775.4
1775.4
1775.4
1775.4
1775.4
130
C8
5
C7
-120
-245
-370
-495
-620
-745
-870
-995
C6
C5
C4
C3
-870
C2
-745
-64.5
C1
-620
-189.5 1775.4
-314.5 1775.4
-439.5 1775.4
-564.5 1775.4
-689.5 1775.4
-814.5 1775.4
-939.5 1775.4
-1064.5 1775.4
-1189.5 1775.4
VEE
V1L
V4L
V5L
V0L
VDD
DI01
FS
-495
-1499.9 -1120
-1499.9 -1245
-1499.9 -1370
-1499.9 -1495
-1345.6 -1775
-1127.6 -1775
-370
-245
-120
5
130
255
-977.6
-827.6
-1775
-1775
380
DS1
505
5
S6B0107
64CH COMMON DRIVER FOR DOT MATRIX LCD
100 TQFP (S6B2107)
NC
50
C44
C43
C42
C41
C40
C39
C38
C37
C36
C35
C34
C33
C32
C31
C30
C29
C28
C27
C26
C25
C24
C23
C22
C21
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
CL2
49
NC
48
DIO2
47
PCLK2
46
NC
45
M
44
FRM
43
NC
42
CLK1
41
CLK2
40
MS
39
S6B2107
NC
38
VSS
37
(100 TQFP)
SHL
36
NC
35
CR
34
NC
33
R
32
NC
31
C
30
DS2
29
DS1
28
FS
27
DIO1
26
C20
6
64CH COMMON DRIVER FOR DOT MATRIX LCD
S6B0107
PAD DIAGRAM (CHIP LAYOUT FOR THE 100-TQFP)
C19
C18
C17
C16
C15
C14
C13
C12
C11
1
2
3
4
5
6
7
8
9
75 C45
74 C46
73 C47
72 C48
71 C49
70 C50
69 C51
68 C52
67 C53
66 C54
65 C55
64 C56
63 C57
62 C58
61 C59
60 C60
59 C61
58 C62
57 C63
56 C64
Y
C10 10
C9 1 1
C8 12
C7 13
C6 14
C5 15
C4 16
C3 17
C2 18
C1 19
(0, 0)
X
Chip size: 3850 X 100
PAD size: 100 X 100
Unit
: m m
VEE 20
V1L 21
V4L 22
V5L 23
V0L 24
55
VEE
54 V1R
53 V4R
52 V5R
51 V0R
VDD 25
There is the m ark S6B2107 on the center of the chip.
7
S6B0107
64CH COMMON DRIVER FOR DOT MATRIX LCD
PAD CENTER COORDINATES (100-TQFP)
Pad
Pad
Coordinate
Pad
Pad
Coordinate
Pad
Pad
Coordinate
Number Name
Number Name
Number Name
X
Y
X
Y
X
Y
1
2
3
4
5
6
7
8
C19
C18
C17
C16
C15
C14
C13
C12
C11
C10
C9
C8
C7
C6
C5
C4
C3
C2
C1
VEE
V1L
V4L
V5L
V0L
VDD
DIO1
FS
-1697
-1697
-1697
-1697
-1697
-1697
-1697
-1697
-1697
-1697
-1697
-1697
-1697
-1697
-1697
-1697
-1697
-1697
-1697
-1697
-1697
-1697 -1091
-1697 -1216
-1697 -1341
-1697 -1466
-1245 -1821
-1095 -1821
-945
-795
-645
NC
1534
1409
1284
1159
1034
909
784
659
534
409
284
159
34
-91
-216
-341
-466
-591
-716
-841
-966
35
NC
-195
0
NC
195
345
495
NC
645
795
NC
945
1095
NC
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
C51
C50
C49
C48
C47
C46
C45
C44
C43
C42
C41
C40
C39
C38
C37
C36
C35
C34
C33
C32
C31
C30
C29
C28
C27
C26
C25
C24
C23
C22
C21
C20
1697
1697
1697
1697
1697
1697
1697
1500
1375
1250
1125
1000
875
750
625
500
375
250
125
0
-125
-250
-375
-500
-625
-750
-875
-1000
-1125
-1250
-1375
-1500
784
909
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
SHL
VSS
-1821
-1821
1034
1159
1284
1409
1534
1822
1822
1822
1822
1822
1822
1822
1822
1822
1822
1822
1822
1822
1822
1822
1822
1822
1822
1822
1822
1822
1822
1822
1822
1822
MS
CLK2
CLK1
-1821
-1821
-1821
9
FRM
M
-1821
-1821
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
PCLK2
DIO2
-1821
-1821
CL2
1245
NC
-1821
V0R
V5R
V4R
V1R
VEE
C64
C63
C62
C61
C60
C59
C58
C57
C56
C55
C54
C53
C52
1697
1697
1697
1697
1697
1697
1697
1697
1697
1697
1697
1697
1697
1697
1697
1697
1697
1697
-1466
-1341
-1216
-1091
-966
-841
-716
-591
466
-341
-216
-91
34
159
DS1
DS2
C
-1821
-1821
-1821
284
409
534
659
R
-495
NC
-345
-1821
-1821
CR
8
64CH COMMON DRIVER FOR DOT MATRIX LCD
S6B0107
PIN DESCRIPTION
Table 1. Pin Description
I/ O
Pin Number
QFP (TQFP)
Symbol
Description
VDD
VSS
VEE
28(25)
40(37)
23(20), 58(55)
Power
For internal logic circuit (+5V ± 10%)
GND ( = 0 V)
For LCD driver circuit
27(24), 54(51)
24(21), 57(54)
25(22), 56(53)
26(23), 55(52)
V0L, V0R
V1L, V1R
V4L, V4R
V5L, V5R
Power
Bias supply voltage term inals to drive LCD.
Slelect Level
Non-Select Level
V1L (R), V4L (R)
V0L (R), V5L (R)
V0L and V0R (V1L & V1R, V4L & V4R, V5L & V5R) should
be connected by the sam e voltage.
42(39)
MS
Input
Selection of m aster/ slave m ode
- Master m ode (MS = 1)
DIO1, DIO2, CL2 and M is output state.
- Slave m ode (MS = 0)
SHL = 1 ® DIO1 is input state (DIO2 is output state)
SHL = 0 ® DIO2 is input state (DIO1 is output state)
CL2 and M are input state.
39(36)
49(46)
30(27)
SHL
PCLK2
FS
Input
Input
Input
Selection of data shift direction.
SHL
H
Data Shift Direction
DIO1
DIO2
®
®
C1 ...... C64
C64 ...... C1
®
DIO2
DIO1
L
®
Selection of shift clock (CL2) phase.
PCLK2
Shift Clock (CL2) Phase
H
L
Data shift at the rising edge of CL2
Data shift at the falling edge of CL2
Selection of oscillation frequency.
- Master m ode
When the fram e frequency is 70 Hz, the oscillation
frequency
should be
fosc = 430kHz at FS = 1(VDD
)
fosc = 215kHz at FS = 0(VSS
)
- Slave m ode
Connect to VDD
.
9
S6B0107
64CH COMMON DRIVER FOR DOT MATRIX LCD
Table 1. Pin Description (Continued)
Pin Number
Symbol
I/ O
Description
QFP (TQFP)
31(28)
32(29)
DS1
DS2
Input
Selection of display duty.
- Master m ode
DS1
L
DS2
L
Duty
1/ 48
1/ 64
1/ 96
1/ 128
L
H
H
L
H
H
- Slave m ode
Connect to VDD
33(30)
35(32)
37(34)
C
R
CR
RC Oscillator
- Master m ode: Use these term inals as shown below.
S6B0107
S6B0107
R
CR
C
R
CR
C
C
R
f
f
Open
Open
-
Slave m ode: Stop the oscillator as shown below.
44(41)
43(40)
CLK1
CLK2
Output
Output
Operating clock output for the S6B0108
- Master m ode: connection to CLK1 and CLK2 of the
S6B0108
- Slave m ode: open
46(43)
47(44)
FRM
M
Synchronous fram e signal.
- Master m ode: connection to FRM of the S6B0108
- Slave m ode: open
Input/
Output
Alternating signal input for LCD driving.
- Master m ode: output state Connection to M of the
S6B0108
- Slave m ode: input state Connection to the controller
52(49)
CL2
Input /
Output
Data shift clock
- Master m ode: output state Connection to CL of the
S6B0108
- Slave m ode: input state Connection to shift clock
term inal of
the controller.
10
64CH COMMON DRIVER FOR DOT MATRIX LCD
S6B0107
29(26)
50(47)
DIO1
DIO2
Input/
Output
Data input/ output pin of internal shift register.
MS
DS2
H
DIO1
DIO2
Output
Output
Input
Output
Output
Output
Input
H
L
H
L
L
Output
11
S6B0107
64CH COMMON DRIVER FOR DOT MATRIX LCD
Table 1. Pin Description (Continued)
Pin Number
Symbol
I/ O
Description
QFP (TQFP)
22-1(19-1)
100-59(100-
56)
C1-C64
Output
Com m on signal output for LCD driving.
Data
L
M
L
Out
V1
L
H
L
V4
H
V5
H
H
V0
34(31), 36(33)
38(35), 41(38)
45(42), 48(45)
51(48), 53(50)
NC
No connection
MAXIMUM ABSOLUTE LIMIT
Characteristic
Symbol
Value
Unit
Note
(1)
VDD
VEE
Operating voltage
-0.3 to +7.0
VDD-19.0 to VDD+0.3
-0.3 to VDD+0.3
VEE-0.3 to VDD+0.3
-30 to +85
V
(4)
Supply voltage
V
V
(1), (2)
VB
Driver supply voltage
(3), (4)
VLCD
TOPR
TSTG
V
Operating tem perature
Storage tem perature
-
-
°C
°C
-55 to +125
NOTES:
1. Based on V = 0V
SS
2. Applies to input term inals and I/ O term inals at high im pedance. (Except V0L(R), V1L(R), V4L(R) and V5L(R))
3. Applies to V0L(R), V1L(R), V4L(R) and V5L(R).
4. Voltage level: V ³ V0L = V0R ³ V1L = V1R ³ V4L = V4R ³ V5L = V5R ³ V
.
DD
EE
12
64CH COMMON DRIVER FOR DOT MATRIX LCD
S6B0107
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS (VDD = +5V ± 10%, VSS = 0V, | VDD-VEE | =8 - 17V, TA = -30 - +85°C)
Characteristic
Symbol
Condition
Min
Typ
Max
Unit
Note
V
0.7VDD
VDD
(1)
High
-
-
-
-
-
-
V
IH
Input Voltage
V
VSS
VDD-0.4
-
0.3VDD
Low
High
Low
IL
VOH
VOL
ILKG
IOH = -0.4m A
IOL = 0.4m A
(2)
(1)
-
V
Output
voltage
0.4
1.0
V
IN = VDD-VSS
Input leakage current
-1.0
mA
Rf = 47kW ±
2%
fOSC
OSC frequency
315
-
450
-
585
1.5
kHz
Cf = 20pf ± 5%
VDD-VEE = 17V
On resistance (VDIV-
Ci)
RON
KW
Load current =
± 150mA
Master m ode
1/ 128 Duty
IDD1
IDD2
IEE
(3)
(4)
(5)
Operating current
-
-
-
-
-
-
1.0
200
100
mA
Slave m ode
1/ 128 Duty
mA
Master m ode
1/ 128 Duty
Supply current
Master m ode
External clock
fop1
fop2
Operating
Frequency
50
-
-
600
kHz
Slave m ode
0.5
1500
NOTES:
1. Applies to input term inals FS, DS1, DS2, CR, SHL, MS and PCLK2 and I/ O term inals DIO1, DIO2, M and CL2 in
the
input state.
2. Applies to output term inals CLK1, CLK2 and FRM and I/ O term inals DIO1, DIO2, M and CL2 in the output
state.
3. This value is specified at about the current flowing through V . Internal oscillation circuit: Rf = 47kW, Cf =
SS
20pF. Each
term inal of DS1, DS2, FS, SHL and MS is connected to V and out is no load.
DD
4. This value is specified at about the current flowing through V . Each term inal of DS1, DS2, FS, SHL, PCLK2
SS
and CR is
connected to VDD, and MS is connected to V
CL2, M, DIO1 is external clock.
SS.
5. This value is specified at about the current flowing through V . Don’ t connect to V
(V1-V5).
EE
LCD
13
S6B0107
64CH COMMON DRIVER FOR DOT MATRIX LCD
AC CHARACTERISTICS (VDD = 5V ± 10%, TA = -30°C - +85°C)
Master Mode (MS = VDD, PCLK2 = VDD, Cf = 20pF, Rf = 47kW)
tWLC
0.7V
DD
CL2
0.3V
DD
tWHC
tWHC
tsu
tsu
tDH
DIO1 (SHL = V DD
DIO2 (SHL = V SS
)
)
tD
tD
DIO2 (SHL = V DD
DIO1 (SHL = V SS
)
)
tDF
FRM
M
tDM
tDM
0.7V
DD
0.3V
DD
tF
tR
tWH1
CLK1
CLK2
tWL1
tD12
tD21
tWH2
tF
tR
14
64CH COMMON DRIVER FOR DOT MATRIX LCD
Master Mode
S6B0107
Characteristic
Symbol
Min
Typ
Max
Unit
t
Data setup tim e
20
-
-
ms
SU
t
Data hold tim e
40
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DH
t
Data delay tim e
-
D
t
FRM delay tim e
-2
2
DF
t
M delay tim e
-2
2
DM
t
CL2 low level width
CL2 high level width
CLK1 low level width
CLK2 low level width
CLK1 high level width
CLK2 high level width
CLK1-CLK2 phase difference
CLK2-CLK1 phase difference
CLK1, CLK2 rise/ fall tim e
35
-
WLC
t
35
-
WHC
t
700
700
2100
2100
700
700
-
-
ns
WL1
t
-
WL2
t
-
WH1
t
-
WH2
t
-
-
D12
t
D21
t
/ t
R F
150
15
S6B0107
64CH COMMON DRIVER FOR DOT MATRIX LCD
Slave Mode (MS = VSS
)
t
t
t
F
R
WLC1
0.7V
DD
CL2 (PLK2 = VSS
)
0.3V
DD
t
WHC1
t
SU
tWHC2
tWLC
CL2 (PLK2 = VDD
)
t
tD
HCL
t
t
F
R
DIO1 (SHL = VDD
DIO2 (SHL = VSS
Input Data
)
0.7V
DD
)
0.3V
DD
t
H
DIO1 (SHL = VDD
DIO2 (SHL = VSS
)
0.7V
DD
)
0.3V
DD
Onput Data
Characteristics
Symbol
Min
Typ
Max
Unit
Note
tWLC1
PCLK2 = VSS
CL2 low level width
450
150
150
450
100
100
-
-
-
ns
tWHC1
tWLC2
tWHL
tSU
PCLK2 = VSS
PCLK2 = VDD
PCLK2 = VDD
CL2 high level width
CL2 low level width
CL2 high level width
Data setup tim e
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
-
-
-
tDH
Data hold tim e
-
(NOTE)
tD
Data delay tim e
200
-
tH
Output data hold tim e
CL2 rise/ fall tim e
10
tR/ tF
-
30
NOTE: Connect load CL = 30pF
Output
30pF
16
64CH COMMON DRIVER FOR DOT MATRIX LCD
S6B0107
FUNCTIONAL DESCRIPTION
RC Oscillator
The RC Oscillator generates CL2, M, FRM of the S6B0107, and CLK1 and CLK2 of the S6B0108 by the
oscillation resister R and capacitor C. When selecting the m aster/ slave m ode, the oscillation circuit is as
following:
Master Mode: In the m aster m ode, use these term inals as shown below.
S6B0107
S6B0107
CR
R
CR
C
R
C
Cf
Rf
47K
Internal Oscillation
Open
Open
External
Clock
W
20pF
External Clock
Slave Mode: In the slave m ode, stop the oscillator as shown below.
S6B0107
R
CR
C
Open
Open
VDD
Timing Generation Circuit
It generates CL2, M, FRM, CLK1 and CLK2 by the frequency from the oscillation circuit.
Selection of Master/ Slave (M/ S) Mode
- When M/ S is H, it generates CL2, M, FRM, CLK1 and CLK2 internally.
- When M/ S is “L”, it operates by receiving M and CL2 from the m aster device.
Frequency Selection (FS)
To adjust FRM frequency by 70Hz, the oscillation frequency should be as follows:
FS
Oscillation Frequency
fOSC = 430kHz
H
fOSC = 215kHz
L
In the slave m ode, it is connected to VDD
.
17
S6B0107
64CH COMMON DRIVER FOR DOT MATRIX LCD
Duty Selection (DS1, DS2)
It provides various duty selections according to DS1 and DS2.
DS1
DS2
L
DUTY
1/ 48
L
H
1/ 64
H
L
1/ 96
H
1/ 128
Data Shift & Phase Select Control
Phase Selection
It is a circuit to shift data on synchronization or rising edge, or falling edge of the CL2 according to
PCLK2.
PCLK2
Phase Selection
Data shift on rising edge of CL2
Data shift on falling edge of CL2
H
L
Data Shift Direction Selection
When M/ S is connected to VDD, DIO1 and DIO2 term inal is only output.
When M/ S is connected to VSS, it depends on the SHL.
MS
SHL
H
DIO1
Output
Output
Input
DIO2
Output
Output
Output
Input
Direction of Data
H
C1 ® C64
C64 ® C1
L
L
H
DIO1 ® C1 ® C64 ® DIO2
DIO2 ® C64 ® C1 ® DIO1
L
Output
18
64CH COMMON DRIVER FOR DOT MATRIX LCD
S6B0107
TIMING DIAGRAM
1/ 48 DUTY TIMING (MASTER MODE)
Condition: DS1 = L, DS2 = L, SHL = H(L), PCLK2 = H
C
CLK1
1
2
3
63
64
CLK2
3
46 47 48
1
2
3
46 47 48
2
1
CL2
FRM
DIO1 ( DIO2 )
M
V0
V4
V0
V1
V1
V1
V1
C1 ( C48 )
C2 ( C47 )
V4
V4
V5
V4 V0
V1 V5
V0
V1
V1
V1
V1
V4
V4
V4
V4
V4
C47 ( C2 )
V5
V5
V1
V0
C48 ( C1 )
V5
V5
DIO2 ( DIO1 )
Relation of CL2 & DIO1 ( DIO2 )
CLK2
CL2
DIO1 ( DIO2 )
19
S6B0107
64CH COMMON DRIVER FOR DOT MATRIX LCD
1/ 128 DUTY TIMING (MASTER MODE)
Condition: DS1 = H, DS2 = H, SHL = H(L), PCLK2 = H
C
CLK1
1
2
3
23
24
CLK2
3
126 127 128
1
2
3
126 127 128
2
1
CL2
FRM
DIO1 ( DIO2 )
M
V0
V0
V4
V1
V1
V1
V1
V4
V4
C1 ( C128 )
C2 ( C127 )
V5
V4 V0
V1 V5
V0
V4
V1
V5
V1
V1
V1
V4
V4
V4
V4
V5
C127 ( C2 )
V0
C128 ( C1 )
V1 V5
V5
DIO2 ( DIO1 )
Relation of CL2 & DIO1 ( DIO2 )
CLK2
CL2
DIO1 (DIO2)
20
64CH COMMON DRIVER FOR DOT MATRIX LCD
S6B0107
1/ 48 DUTY TIMING (SLAVE MODE)
Condition: PCLK2 = L, SHL = H(L)
1
2
46
47
48
1
2
46
47
48
CL2
M
DIO1 ( DIO2 )
V1
V1
V1
V0
V0
C1 ( C48 )
V4
V5
V1
V0
V1
C2 ( C47 )
V4
V0
V4
V4
V5
V1
V1
V1
V4
V4
V4
V4
V4
C47 ( C2 )
V5
V1
V0
V5
V5
C48 ( C1 )
DIO2 ( DIO1 )
21
S6B0107
64CH COMMON DRIVER FOR DOT MATRIX LCD
POWER DRIVER CIRCUIT
VDD
V0
V1
V2
V3
V4
V5
VDD
V0L/ R
R1
R1
R2
R1
V1L/ R
To
S6B0107
S6B0108
V4L/ R
R1
VR
V5L/ R
VEE
VEE
Relation of Duty & Bias
Duty
1/ 48
1/ 64
1/ 96
1/ 128
Bias
1/ 8
RDIV
R2 = 4R1
R2 = 5R1
R2 = 7R1
R2 = 8R1
1/ 9
1/ 11
1/ 12
When duty factor is 1/ 48, the value of R1 & R2 should satisfy.
R1/ (4R1 + R2) = 1/ 8
R1 + 3kW, R2 = 12kW
22
64CH COMMON DRIVER FOR DOT MATRIX LCD
S6B0107
APPLICATION CIRCUIT
1/ 128 duty Segm ent driver (S6B0108) interface circuit
CS3
CS2B
CS1B
DB0 -DB7
RSTB
E
CS3
CS2B
CS1B
DB0 -DB7
RSTB
E
S6B0108
S6B0108
R/ W
RS
R/ W
RS
VSS
LCD Panel
CS3
CS3
CS2B
CS1B
DB0 -DB7
RSTB
E
CS2B
CS1B
DB0 -DB7
RSTB
E
S6B0108
S6B0108
R/ W
RS
R/ W
RS
V
SS
COM1
COM128
MPU
C
DIO1
DIO2
C1
R1
CR
R
DIO2
CL2
M
CLK2
DS1
DS2
PCLK2
MS
CL2
M
S6B0107
(master)
S6B0107
(slave)
CLK1
FRM
CLK2
2
5
CLK1
FRM
FS
C
CR
R
SHL
VDD
23
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