ENN7944 [SANYO]
Seven-Channel Motor Driver IC for Digital Cameras; 七通道马达驱动器IC数码相机
| 型号： | ENN7944 |
| 厂家： | 
SANYO SEMICON DEVICE |
| 描述： | Seven-Channel Motor Driver IC for Digital Cameras |
| 文件： | 总24页 (文件大小：1152K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : ENN7944
SANYO Semiconductors
DATA SHEET
Bi-CMOS IC
Seven-Channel Motor Driver IC
for Digital Cameras
LV8041FN
Overview
The LV8041FN is a digital camera motor driver IC that integrates seven driver channels on a single chip.
Features
• Two PWM current control microstepping drive stepping motor driver channels
• One constant current forward/reverse motor driver
• Two PWM drive forward/reverse motor driver channels (one channel of which can be switched to function as a
microstepping drive stepping motor driver)
• Stepping motor drivers 1 and 2 support 2-phase, 1-2 phase, 2W1-2 phase, and 4W1-2 phase drive.
• Stepping motor driver 3 operates in fixed 2W1-2 phase drive mode.
• Microstepping drive step advance can be controlled with a single clock input (stepping motor drivers 1, 2, and 3)
• The constant current control chopping frequency can be adjusted with an external resistor (stepping motor drivers
1, 2, and 3)
• Phase detection monitor pins provided (stepping motor drivers 1, 2, and 3)
• The states of all of the drivers can be set up and controlled over an 8-bit serial data interface.
Specifications
Absolute Maximum Ratings at Ta 25qC
Parameter
Supply voltage 1
Symbol
Vmmax
Conditions
Ratings
Unit
V
6
6
Supply voltage 2
V max
CC
V
Peak output current
Continuous output current
I
I
peak
max
1ch/2ch/3ch/4ch/5ch/6ch/7ch
1ch/2ch/3ch/4ch/5ch/6ch/7ch
Independent IC
600
400
0.35
2.2
mA
mA
W
O
O
Pd max1
Pd max2
Topr
Allowable power dissipation
Mounted on a 30 u 50 u 0.8 mm glass epoxy PCB
W
Operating temperature
Storage temperature
ꢀ20 to ꢁ85
qC
qC
Tstg
ꢀ55 to ꢁ150
Allowable Operating Ranges at Ta 25qC
Parameter
Supply voltage range 1
Symbol
VM
Conditions
Ratings
Unit
V
2 to 5.5
Supply voltage range 2
Logic input voltage
Chopping frequency
Clock frequency
V
2.7 to 5.5
V
CC
V
0 to V
ꢁ0.3
V
IN
CC
fchop
fCLK
1ch, 2ch, 3ch, 4ch, 5ch, 6ch
CLK12, CLK34, CLK56
PWM5, PWM6
50 to 200
Up to 64
Up to 100
KHz
KHz
KHz
PWM frequency
fPWM
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control
systems, or other applications whose failure can be reasonably expected to result in serious physical and/or
material damage. Consult with your SANYO representative nearest you before using any SANYO products
described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained herein.
SANYO Electric Co., Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
81004TN (OT) No. 7944-1/24
LV8041FN
Electrical Characteristics at Ta = 25°C, VM = 5 V, VCC = 5 V
Ratings
typ
Parameter
Symbol
Istn
Conditions
Unit
PA
min
max
Standby mode current drain
ST low
ST high
1
IM
50
100
5.5
PA
PWM5 PWM6 IN72 high, No load
ST high
Current drain
I
3.5
4.5
mA
CC
PWM5 PWM6 IN72 high, No load
V
low-voltage cutoff voltage
VthV
2.1
100
4.5
2.35
150
4.7
9
2.6
200
5.0
9.5
0.2
150
170
20
V
mV
V
CC
CC
Low-voltage sensing hysteresis
VG reference voltage
VthHIS
VGL
Charge pump step-up voltage
Charge pump startup time
VGH
8.5
V
tONG
Fchg
TSD
C (VGH) 0.1 PF
R 20 k:
0.1
125
160
10
ms
kHz
qC
qC
Charge pump oscillator frequency
Thermal shutdown temperature
Thermal shutdown hysteresis
100
150
5
Design guarantee value
Design guarantee value
'TSD
Stepping Motor Drivers (Channels 1, 2, 3, and 4)
Ta 25qC, I 400mA,
O
Ronu
0.45
0.45
0.55
0.55
:
:
Upper side on-resistance
Output on-resistance
Ta 25qC, I 400mA,
O
Rond
leak
Lower side on-resistance
Output leakage current
Diode forward voltage
I
1
50
1.2
1.0
70
PA
V
O
VD1
ID ꢀ400mA
0.6
0.9
I
L
IN
V
IN
V
IN
0 V (ST, CLK12, CLK34)
5 V (ST, CLK12, CLK34)
PA
PA
V
Logic pin input current
I
H
IN
50
Logic high-level input voltage
Logic low-level input voltage
V H
IN
ST, CLK12, CLK34
ST, CLK12, CLK34
3.5
V L
IN
1.5
V
Step 16 (Initial state, channel 1 comparator
level)
0.188
0.2
0.218
V
Step 15 (Initial state ꢁ1)
Step 14 (Initial state ꢁ2)
Step 13 (Initial state ꢁ3)
Step 12 (Initial state ꢁ4)
Step 11 (Initial state ꢁ5)
Step 10 (Initial state ꢁ6)
Step 9 (Initial state ꢁ7)
Step 8 (Initial state ꢁ8)
Step 7 (Initial state ꢁ9)
Step 6 (Initial state ꢁ10)
Step 5 (Initial state ꢁ11)
Step 4 (Initial state ꢁ12)
Step 3 (Initial state ꢁ13)
Step 2 (Initial state ꢁ14)
Step 1 (Initial state ꢁ15)
0.188
0.188
0.177
0.170
0.163
0.156
0.148
0.133
0.117
0.100
0.083
0.065
0.050
0.030
0.010
0.188
0.2
0.2
0.218
0.218
0.207
0.200
0.193
0.186
0.178
0.163
0.147
0.130
0.113
0.095
0.077
0.058
0.038
0.218
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
0.192
0.185
0.178
0.171
0.163
0.148
0.132
0.115
0.098
0.080
0.062
0.043
0.023
0.2
4W1-2 phase
drive
Current selection
reference voltage
levels
Step 16 (Initial state, channel 1 comparator
level)
Step 14 (Initial ꢁ1)
Step 12 (Initial ꢁ2)
Step 10 (Initial ꢁ3)
Step 8 (Initial ꢁ4)
Step 6 (Initial ꢁ5)
Step 4 (Initial ꢁ6)
Step 2 (Initial ꢁ7)
0.188
0.170
0.156
0.133
0.100
0.065
0.030
0.2
0.185
0.171
0.148
0.115
0.080
0.043
0.218
0.200
0.186
0.163
0.130
0.095
0.058
V
V
V
V
V
V
V
2W1-2 phase
drive
Step 16 (Initial state, channel 1 comparator
level)
0.188
0.2
0.218
V
1-2 phase
drive
Step 8 (Initial state + 1)
Step 8
0.133
0.188
100
4.5
0.148
0.2
0.163
0.218
150
V
V
2-phase drive
Chopping frequency
Fchop
VMOH
VMOL
R 20 k:
125
4.9
kHz
V
IMO ꢀ50 PA, VM 5V
IMO 50 PA
V
CC
Monitor pin (MO pin) output voltage
0
0.1
0.5
V
Continued on next page
No.7944-2/24
LV8041FN
Continued from preceding page.
Parameter
Symbol
Conditions
Ratings
Unit
H Bridge Drivers (Channels 5 and 6)
Ta 25qC, I 400 mA,
O
Ronu
Rond
0.45
0.45
0.55
0.55
:
:
Upper side on-resistance
Output on-resistance
Ta 25qC, I 400 mA,
O
Lower side on-resistance
Output leakage current
Diode forward voltage 1
I
leak
1
50
1.2
1.0
70
PA
V
O
VD1
ID ꢀ400 mA
0.6
0.9
I
L
IN
V
IN
V
IN
0 V (PWM5, PWM6)
5 V (PWM5, PWM6)
PA
PA
V
Logic pin input current
I
H
IN
50
Logic high-level input voltage
Logic low-level input voltage
V
H
IN
PWM5, PWM6
PWM5, PWM6
3.5
V L
IN
1.5
V
Step 16 (Initial state, channel 5 comparator
level)
0.188
0.2
0.218
V
Step 14 (Initial state +1)
Step 12 (Initial state +2)
Step 10 (Initial state +3)
Step 8 (Initial state +4)
Step 6 (Initial state +5)
Step 4 (Initial state +6)
Step 2 (Initial state +7)
IMO ꢀ50 PA, VM 5 V
IMO 50 PA
0.188
0.170
0.156
0.133
0.100
0.065
0.030
4.5
0.2
0.185
0.171
0.148
0.115
0.080
0.043
4.9
0.218
0.200
0.186
0.163
0.130
0.095
0.058
V
V
V
V
V
V
V
V
V
V
V
V
V
Current selection
2W1-2
reference levels when
phase
microstepping is
drive
selected
VMOH
VMOL
V
CC
Monitor pin (MO56 pin) output
voltage
0
0.1
0.5
0.218
0.149
0.115
0.081
VSEN1
VSEN2
VSEN3
VSEN4
(D7, D6) (0, 0)
0.188
0.119
0.085
0.051
0.2
(D7, D6) (0, 1)
0.134
0.1
Current control reference voltage
(D7, D6) (1, 0)
(D7, D6) (1, 1)
0.066
Constant Current Forward/Reverse Motor Driver (Channel 7)
Ta 25qC, I 400 mA,
O
Ronu
Rond
0.5
0.5
0.6
0.6
:
:
Upper side on-resistance
Output on-resistance
Ta 25qC, I 400 mA,
O
Lower side on-resistance
Output leakage current
Diode forward voltage 1
I
leak
1
50
1.2
1.0
70
PA
V
O
VD1
ID ꢀ400 mA
0.6
3.5
0.9
I
L
IN
V
IN
V
IN
0 V (IN71, IN72)
5 V (IN71, IN72)
PA
PA
V
Logic pin input current
I
H
IN
50
Logic high-level input voltage
Logic low-level input voltage
V
V
H
IN71, IN72
IN
L
IN
IN71, IN72
1.5
V
Rload 3 :, RF 0.5 :,
LIM7 0.2 V
Constant current output
I
384
400
0.2
416
mA
OUT
VREF7 output voltage
VREF7
ILIM7
0.19
0.21
1.0
850
15
V
LIM7 input current
LIM7 0 V
PA
PA
PA
PA
FC7 Rapid charge current
FC7 steady-state charge current
FC7 steady-state discharge current
Serial Data Transfer Pins
Irafc7
500
5
670
10
Ichfc7
Idisfc7
5
10
15
I
L
V
V
0 V (SCLK, DATA, STB)
5 V (SCLK, DATA, STB)
1.0
70
PA
PA
V
IN
IN
Logic pin input current
I
H
50
IN
IN
Logic high-level input voltage
Logic low-level input voltage
Minimum SCLK high-level pulse width
Minimum SCLK low-level pulse width
Stipulated STB time
V
V
H
IN
SCLK, DATA, STB
SCLK, DATA, STB
3.5
L
IN
1.5
V
Tsch
Tscl
Tlat
0.125
0.125
0.125
0.125
0.125
0.125
Ps
Ps
Ps
Ps
Ps
Ps
MHz
Minimum STB pulse width
Data setup time
Tlatw
Tds
Data hold time
Tdh
Maximum CLK frequency
Fclk
4
No.7944-3/24
LV8041FN
Fclk
Tsch Tscl
CLK
Tds
Tdh
D7
Tlat
DATA
D6
D0
D1
D2
SET
Tlatw
Package Dimensions
unit: mm
3305
×
×
SANYO : VQFN52 (7.0 u 7.0)
No.7944-4/24
LV8041FN
Pin Assignment
52
51
50
49
48
47
46
45
44
43
42
41
40
1
2
39
38
37
36
35
34
33
32
31
30
29
28
27
OUT1A
SEN1
CPL1
VM7
OUT1B
VM12
3
OUT7B
SEN7
OUT7A
4
OUT2A
SEN2
5
6
PGND
OUT2B
7
OUT6B
LV8041FN
OUT3A
SEN3
8
SEN6
9
OUT6A
VM56
OUT3B
VM34
10
11
12
13
OUT5B
SEN5
OUT4A
SEN4
OUT5A
14
15
16
17
18
19
20
21
22
23
24
25
26
Top view
40
41
42
43
44
45
46
47
48
49
50
51
52
CPL1
VM7
39
38
37
36
35
34
33
32
31
30
29
28
27
1
OUT1A
SEN1
2
OUT7B
SEN7
OUT1B
VM12
3
4
OUT2A
SEN2
OUT7A
5
PGND
6
OUT6B
OUT2B
7
LV8041FN
SEN6
OUT3A
SEN3
8
9
OUT6A
VM56
OUT3B
VM34
10
11
12
13
OUT5B
SEN5
OUT4A
OUT5A
SEN4
26
25
24
23
22
21
20
19
18
17
16
15
14
Bottom view
No.7944-5/24
LV8041FN
Block Diagram
No.7944-6/24
LV8041FN
Pin Functions
Pin No.
Symbol
Pin description
4
VM12
OUT1A
OUT1B
SEN1
STP 1: Motor power supply
1
STP 1: Channel 1 OUTA output
STP 1: Channel 1 OUTB output
3
2
STP 1: Channel 1 current sensing resistor connection
STP 1: Channel 2 OUTA output
5
OUT2A
OUT2B
SEN2
7
STP 1: Channel 2 OUTB output
6
STP 1: Channel 2 current sensing resistor connection
STP 1: Power system ground
52
51
50
22
20
21
24
11
8
PGND12
CLK12
MO12
SCLK
STP 1: Clock signal input
STP 1: Phase detector monitor
Serial data transfer clock input
DATA
Serial data input
STB
Serial data latch pulse input
R
Oscillator frequency setting resistor connection
STP 2: Motor power supply
VM34
OUT3A
OUT3B
SEN3
STP 2: Channel 3 OUTA output
10
9
STP 2: Channel 3 OUTB output
STP 2: Channel 3 current sensing resistor connection
STP 2: Channel 4 OUTA output
12
15
13
14
16
17
30
27
OUT4A
OUT4B
SEN4
STP 2: Channel 4 OUTB output
STP 2: Channel 4 current sensing resistor connection
STP 2: Power system ground
PGND34
CLK34
MO34
VM56
STP 2: Clock signal input
STP 2: Phase detector monitor
PWM: Channels 5 and 6 motor power supply
OUT5A
PWM: Channel 5 OUTA output
STP 3: Channel 5 OUTA output
29
OUT5B
PWM: Channel 5 OUTB output
STP 3: Channel 5 OUTB output
28
25
SEN5
STP 3: Channel 5 current sensing resistor connection
PWM5/CLK56
PWM: Channel 5 PWM signal input
STP 3: Clock signal input
31
33
OUT6A
OUT6B
PWM: Channel 6 OUTA output
STP 3: Channel 6 OUTA output
PWM: Channel 6 OUTB output
STP 3: Channel 6 OUTB output
32
26
SEN6
STP 3: Channel 6 current sensing resistor connection
PWM6/MO56
PWM: Channel 6 PWM signal input
STP 3: Phase detector monitor
38
45
36
35
37
48
49
34
47
46
39
40
42
43
41
44
18
23
19
VM7
FC7
Constant current drive: Channel 7 motor power supply
Constant current drive: Channel 7 phase compensation capacitor connection
Constant current drive: Channel 7 current sensing resistor connection
Constant current drive: Channel 7 OUTA output
Constant current drive: Channel 7 OUTB output
Constant current drive: Channel 7 logic input 1
Constant current drive: Channel 7 logic input 2
Constant current drive: Channel 7 power system ground
Constant current drive: Channel 7 current control reference voltage output
Constant current drive: Channel 7 constant current setting
Charge pump capacitor connection
SEN7
OUT7A
OUT7B
IN71
IN72
PGND7
VREF7
LIM7
CPL1
CPL2
CPH1
CPH2
VGL
Charge pump capacitor connection
Charge pump capacitor connection
Charge pump capacitor connection
Lower side DMOS gate voltage capacitor connection
Upper side DMOS gate voltage capacitor connection
Chip enable
VGH
ST
V
Logic system power supply
CC
GND
Signal system ground
No.7944-7/24
LV8041FN
Serial Data Input Specifications
x Register (D1, D0): Data transfer target register selection
D1
D0
Mode
Monitor/channels 5 and 6 drive mode settings
STP1 settings
0
0
0
1
1
0
STP2 settings
1
1
PWM/STP3 settings
The D1 and D0 bits in the serial data select the register used to set the motor driver state as shown above.
x Monitor/channel 5 and 6 drive mode settings
Register No.
Data
Symbol
Functions
D0
D1
D2
D3
D4
D5
D6
D7
0
RG_SELECT1
Register selection 1
Register selection 2
0
RG_SELECT2
MO_SELECT1
MO_SELECT2
MO12_MD
1 or 0
1 or 0
1 or 0
1 or 0
1 or 0
1 or 0
MO12 output selection 1
MO12 output selection 2
MO12 output mode setting
MO34 output mode setting
MO56 output mode setting
Channel 5 and 6 drive mode setting
MO34_MD
MO56_MD
PWM/MICRO
x STP1 Settings
Register No.
Data
Symbol
Functions
Register selection 1
Register selection 2
Forward/reverse setting
Microstep selection 1
Microstep selection 2
Step/hold setting
Channel
D0
D1
D2
D3
D4
D5
D6
D7
1
RG_SELECT1
RG_SELECT2
F/R1
0
1 or 0
1 or 0
1 or 0
1 or 0
1 or 0
1 or 0
MS11
MS12
1ch, 2ch
(STP1)
HOLD1
RESET1
Logic reset
OUT ENABLE1
Output enable
x STP2 Settings
Register No.
Data
Symbol
Functions
Register selection 1
Register selection 2
Forward/reverse setting
Microstep selection 1
Microstep selection 2
Step/hold setting
Channel
D0
D1
D2
D3
D4
D5
D6
D7
0
RG_SELECT1
RG_SELECT2
F/R2
1
1 or 0
1 or 0
1 or 0
1 or 0
1 or 0
1 or 0
MS21
MS22
3ch, 4ch
(STP2)
HOLD2
RESET2
Logic reset
OUT ENABLE2
Output enable
x Channel 5 and 6 Driver Settings
Symbol
Functions
Channel 5 and 6 drive mode
setting register D7
Register No.
Data
Channel
PWM mode
STP3 mode
“0”
“1”
D0
D1
D2
1
1
RG_SELECT1
RG_SELECT2
F/R5
Register selection 1
Register selection 2
1 or 0
F/R3
Forward/reverse setting
Forward/reverse setting
Step/hold setting
Logic reset
5ch
Current attenuation mode
setting
PWM
D3
D4
D5
1 or 0
1 or 0
1 or 0
DECAY5
F/R6
HOLD3
5ch/6ch
STP
RESET3
Forward/reverse setting
6ch
OUT
ENABLE3
Current attenuation mode
setting
PWM
DECAY6
Output enable
D6
D7
1 or 0
1 or 0
VSEN1
VSEN2
Current control reference voltage selection 1
Current control reference voltage selection 2
5ch/6ch
STP
No.7944-8/24
LV8041FN
Serial Data Input Settings
ST
DATA
SCLK
STB
D0
D1
D2
D3
D4
D5
D6
D7
State setting data latched
Data is input in order from data bit 0 to data bit 7. The data is transferred on the clock signal rising edge and after all
the data has been transferred, it is latched on the rising edge of the STB signal.
x Timing with which the serial data is reflected in the output
Type 1: For the forward/reverse (FR) and drive mode (MS) settings in STP setting mode, after the data is latched,
after the clock falling edge is detected, the new settings are reflected in the output on the next rising edge
on the clock signal.
Type 2: For the reset and output enable settings, after the data is latched, the new settings are reflected in the output
on the next rising edge on the clock signal.
Type 3: For settings other than those listed above, the new settings are reflected in the output at the same time as
the data is latched with the STB signal.
CLK
STB
CLK
STB
Falling edge detection
Data latch timing
Example: reset
Reflected on the
rising edge
Reflected on the rising edge
Data latch timing
Example: 2-phase drive
F/R (STP)
MS
RESET
ENABLE
Example:
4W1-2 phase drive
Example: Reset cleared
STB signal timing
Cases other
than those shown
at the left or above
No.7944-9/24
LV8041FN
Stepping Motor Drivers (STP1 (channels 1 and 2) and STP2 (channels 3 and 4))
Clock Function (STP1 (Items in parentheses refer to STP2))
Input
Operating mode
Standby mode
Charge pump circuit
Stopped
ST
CLK12 (CLK34)
Low
ꢂ
High
High
Drive step operate
Operating
Drive step hold
STP State Setting Serial Data Truth Table: Six bits (STP1/STP2 settings register)
D7 (OE)
D6 (RES)
D5 (HOLD)
D4 (MS2)
D3 (MS1)
D2 (F/R)
Operating mode
Clockwise (forward)
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
0
1
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
0
1
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
0
1
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
0
0
1
1
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
0
1
0
1
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
0
1
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
Counterclockwise (reverse)
2-phase drive
1-2 phase drive
2W1-2 phase drive
4W1-2 phase drive
Step/hold clear
Step/hold
Counter reset (Drive returns to the initial position)
Counter reset clear
Outputs set to the high-impedance state
Outputs set to the operating state
Note ꢂ: Don’t Care
Initial Drive Position
Drive mode
1ch (3ch)
2ch (4ch)
2-phase
100ꢃ
100ꢃ
100ꢃ
100ꢃ
ꢀ100ꢃ
0ꢃ
1-2 phase
2W1-2 phase
4W1-2
0ꢃ
0ꢃ
Procedure for Calculating the Set Current
IOUT = (reference voltage u set current ratio)/(sense resistor (SEN) value)
Since the reference voltage is 0.2 V, the following output current flows when the set current ratio is 100% and the
sense resistor is 1 :.
IOUT 0.2 V u 100ꢃ/1 :
200 mA
Vary the value of the sense resistor (SEN) to vary the output current.
No.7944-10/24
LV8041FN
Output Current Vector Locus (One step is normalized to 90°)
T15
T16
T14
T13
100
T12
T8 (2-phase)
T11
T10
T9
80
60
40
20
0
T8
T7
T6
T5
T3
T2
T1
T0
0
20
40
60
80
100
Channel 2 (channel 4) phase current ratio (%)
Set Current Ratios in the Various Drive Modes
4W1-2 phase (%)
2W1-2 phase (%)
1ch(3ch) 2ch(4ch)
100
1-2 phase (%)
1ch(3ch) 2ch(4ch)
2 phase (%)
1ch(3ch) 2ch(4ch)
STEP
1ch(3ch) 2ch(4ch)
T0
T1
0
8.69
100
100
0
0
69.56
100
100
69.56
0
T2
17.39
26.08
34.78
43.48
52.17
60.87
69.56
78.26
82.61
86.95
91.3
100
17.39
34.78
52.17
69.56
82.61
91.3
100
91.3
T3
95.65
91.3
T4
T5
86.95
82.61
78.26
69.56
60.87
52.17
43.48
34.78
26.08
17.39
8.69
T6
82.61
69.56
52.17
34.78
17.39
0
T7
T8
100
100
T9
T10
T11
T12
T13
T14
T15
T16
95.65
100
100
100
100
0
100
No.7944-11/24
LV8041FN
2-Phase Drive (D4 = 0, D3 = 0, D2 = 0: clockwise mode)
CLK
MO
(%)
100
0
I1
I2
ꢀ100
(%)
100
0
ꢀ100
1-2 Phase Drive (D4 = 0, D3 = 1, D2 = 0: clockwise mode)
CLK
MO(initial)
MO(quarter)
(%)
100
0
I1
ꢀ100
(%)
100
I2
0
ꢀ100
No.7944-12/24
LV8041FN
2W1-2 Phase Drive (D4 = 1, D3 = 0, D2 = 0: clockwise mode)
CLK
MO(initial)
MO(quarter)
2W1-2 phase drive (channel 1 (channel 3): clockwise)
100
80
60
40
20
0
-20
-40
-60
-80
-100
0
10
20
30
2W1-2 phase drive (channel 2 (channel 4): clockwise)
100
80
60
40
20
0
-20
-40
-60
-80
-100
0
10
20
30
No.7944-13/24
LV8041FN
4W1-2 Phase Drive (D4 = 1, D3 = 1, D2 = 0: clockwise mode)
CLK
MO(initial)
MO(quarter)
100
80
60
40
20
0
0
10
20
30
40
50
60
-20
-40
-60
-80
-100
100
80
60
40
20
0
0
10
20
30
40
50
60
-20
-40
-60
-80
-100
No.7944-14/24
LV8041FN
Set Current Step Switching (CLK pin), Forward/Reverse Switching (D2 (F/R)) Basic Operation
Counter-
clockwise
mode
D2 (F/R)
CLK
Clockwise mode
Clockwise mode
Position
number
j
i
h
g
f
e f g h g f
Channel
1 output
Channel
2 output
The IC internal D/A converter advances by one bit on the rising edge of each input clock pulse.
The clockwise/counterclockwise direction mode is switched by the D2 (F/R) data bit, and the direction in which the
position number advances is changed by switching this mode.
In clockwise mode, the channel 2 current phase is delayed by 90° as seen from the channel 1 current.
In counterclockwise mode, the channel 2 current phase leads by 90° as seen from the channel 1 current.
Output Enable (D7) and Reset (D6) Operational Description
Power saving
Initial mode
OE(D7)
RST(D6)
mode
CLK
CLK
MO
MO
Channel
1 output
Channel
1 output
0%
0%
Channel
2 output
Channel
2 output
The outputs are in the high-impedance state
When OE (D7) is set to 0, the outputs will be turned off on the next clock rising edge and set to the high-impedance
state. However, since the internal logic circuits continue to operate, the position number will advance if the clock signal
is input. Therefore, when OE (D7) is returned to 1, the IC will output levels according to the position number that has
been advanced by the clock input.
When RST (D6) is set to 0, the outputs are set to the initial state at the next clock rising edge, and the MO output goes
to the low level. When RST (D6) is set to one after that, the operation starts from the initial state on the next clock
input, and the position number begins advancing.
No.7944-15/24
LV8041FN
Hold Bit (D5) Operational Description
Internal clock
logic
(External) clock
Internal logic
HOLD(D5)
Step/hold
(1)
Step/hold
release
Step/hold
(2)
Step/hold
release
HOLD (D5)
(External)
clock
Held at the
low level
Internal
clock
Held at the
high level
Channel
1 output
0%
Channel
2 output
Hold state
Hold state
When the HOLD bit (D5) is set to 1, the internal clock signal is held at the state of the external clock at that point.
Since the external clock is low at the timing of the step/hold (1) operation in the figure, the internal clock is then held at
the low level. Similarly, since the external clock is high at the timing of the step/hold (2) operation in the figure, the
internal clock is then held at the high level.
When the HOLD bit (D5) is set to 0, the internal clock is synchronized with the normal (external) clock.
The outputs retain their states at the time the step/hold operation was input, and after the step/hold is released, they
proceed with the timing of the next input clock rising edge.
As long as the IC is in the hold state, the position number will not be advanced even if the external clock signal is input.
No.7944-16/24
LV8041FN
Current Control Operation Specifications
x Sine Wave Increasing Direction
CLK
Set current
Coil current
Set current
fchop
Current
mode
CHARGE
SLOW
FAST
CHARGE
SLOW
FAST
x Sine Wave Decreasing Direction
Each current mode operates with the following sequence.
CLK
Set current
Coil current
Set current
fchop
Current
CHARG E
SLO W
FAST
CHARG E
FAST
CHARG E
SLO W
m ode
x The IC goes to charge mode during chopping oscillation startup. (A period in which the IC forcibly operates in
charge mode exists as 1/8 of a single chopping period regardless of the relationship between the magnitudes of the
coil current (ICOIL) and the set current (IREF).)
x During charge mode, the IC compares the coil current (ICOIL) and the set current (IREF).
If the ICOIL < IREF state occurs during charge mode:
ꢀ Charge mode continues until ICOIL t IREF. After that, the IC switches to slow decay mode and then switches to
fast decay mode for the last 1/8 of a single chopping period.
If the ICOIL < IREF state does not occur during charge mode:
ꢀ The IC switches to fast decay mode and the coil current is attenuated in fast decay mode until the end of the
single chopping period.
The IC repeats the above operation. Normally, in the sine wave increasing direction, the IC operates in slow (+ fast)
decay mode, and in the sine wave decreasing direction, the IC operates in fast decay mode until the current is attenuate
to the set level, and then the IC operates in slow decay mode.
No.7944-17/24
LV8041FN
x Setting the Chopping Frequency (fchop)
When this IC performs constant current control, it uses a chopping operation based on a frequency set by an
external resistor.
The chopping frequency set by the value of the resistor connected to the R pin (pin 24) is set as shown in the figure
below.
300
250
200
150
100
50
0
0
10
20
30
40
50
60
70
80
90
100
Resistance, R (k:)
We recommend that a frequency in the range 50 kHz to 200 kHz be used.
Serial Data Truth Table for Monitor Output Settings (Monitor/channel 5 and 6 drive mode settings
register)
x MO12 Output Setting: 2 bits
D3(MO_SELECT2)
D2(MO_SELECT1)
MO12 output state
The STP1 monitor is output
0
0
1
1
0
1
0
1
The STP2 monitor is output
The STP3 monitor is output (If PWM/MICRO is 1.)
A fixed high level is output
The MO12 pin can be set up to output any of the stepping motor driver states shown in the table above with the monitor
settings register settings shown in that table.
x Monitor Output Mode Setting: 3 bits
D6 (MO56_MD)
D5 (MO34_MD)
D4 (MO12_MD)
0
Monitor output mode state
A low level is output from MO12 in the STP1 initial state
(Only when (D3, D2) (0, 0))
ꢂ
ꢂ
A low level is output from MO12 each STP1 1/4 period
(Only when (D3, D2) (0, 0))
ꢂ
ꢂ
ꢂ
0
ꢂ
0
1
ꢂ
ꢂ
1
ꢂ
ꢂ
ꢂ
ꢂ
A low level is output from MO34 in the STP2 initial state
(When (D3, D2) (0, 1) this is also output from MO12)
A low level is output from MO34 each STP2 1/4 period
(When (D3, D2) (0, 1) this is also output from MO12)
A low level is output from MO56 in the STP3 initial state
(When (D3, D2) (1, 0) this is also output from MO12)
A low level is output from MO56 each STP3 1/4 period
(When (D3, D2) (1, 0) this is also output from MO12)
1
Note ꢂ: Don’t Care
The stepping motor driver monitor outputs can be switched between a mode in which an output is only provided in the
initial position and a mode in which an output is provided each 1/4 period by setting the monitor setting register as
shown in the table above.
No.7944-18/24
LV8041FN
PWM Drive Forward/Reverse Motor Driver (Channels 5 and 6)
Drive Mode Setting Serial Data Truth Table: 1 bit (Monitor/channel 5 and 6 drive mode settings register)
Pin functions
D7(PWM/MICRO)
Operating mode
Pin 25
PWM5
CLK56
Pin 26
PWM6
MO56
Low
PWM: 2 systems
High
One microstep drive STP system
The circuit operating mode can be switched between direct PWM drive H bridge drive operation and 2W1-2 phase
microstep drive stepping motor drive operation by setting the D7 bit (PWM/MAICRO) as shown in the table above.
PWM Drive Mode (Channels 5 and 6 drive mode setting register bit D7 = 0)
x Truth Table (Channels 5 and 6 driver settings register)
Inputs
Outputs
Charge pump
circuit
Operating mode
PWM5
(PWM6)
D2
D3
(D5)
ST
OUTA
OUTB
(D4)
Low
High
High
High
High
ꢂ
ꢂ
ꢂ
ꢂ
OFF
High
Low
OFF
Low
OFF
Low
High
OFF
Low
Standby mode
Stopped
High
High
Low
Low
Low
High
ꢂ
Clockwise (forward)
ꢂ
Counterclockwise (reverse)
Fast decay (output off)
Operating
Low
High
ꢂ
Slow decay (short-circuit braking)
Note ꢂ: Don’t care
x Output Stage Transistor Functions
VM
VM
VM
ON
OFF
U1
OFF
OFF
OFF
U2
ON
U1
U2
U2
U1
OUTA
OUTB
OUTA
OUTB
OUTA
OUTB
L1
L2
L1
L2
L1
L2
ON
OFF
OFF
ON
ON
ON
(Forward)
(Reverse)
(Brake)
x Forward/Reverse Output Operation Timing Chart (D3 = 0)
“H”
D2 data
PW M5
“L”
OFF
OFF
ON
U1
L1
ON
ON
U2
L2
OFF
OFF
ON
High
impedance
High
impedance
High
impedance
Forward
Forward
Reverse
Reverse
No.7944-19/24
LV8041FN
x Brake Mode Output Operation Timing Chart (D3 = 1)
“L”
“H”
D2 data
PWM5
ON
U1
L1
OFF
ON
OFF
U2
L2
OFF
ON
ON
OFF
Forward Brake
Forward
Brake
Reverse
Brake
Reverse
Brake
Microstep Drive Mode (Channels 5 and 6 drive mode setting register bit D7 = 1)
Clock Function (STP3)
Input
Operating mode
Standby mode
Drive step mode
Charge pump circuit
Stopped
ST
CLK56
Low
ꢂ
High
High
Operating
Drive step hold
STP State Setting Serial Data Truth Table: 4 bits (Channels 5 and 6 driver settings register)
D5 (OE3)
D4 (RES3)
D3 (HOLD3)
D2 (F/R3)
Operating mode
Clockwise (forward)
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
0
1
ꢂ
ꢂ
ꢂ
ꢂ
0
1
ꢂ
ꢂ
ꢂ
ꢂ
0
1
ꢂ
ꢂ
ꢂ
ꢂ
0
1
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
Counterclockwise (reverse)
Step/hold clear
Step/hold
Counter reset (Drive goes to the initial position)
Counter reset release
Outputs: high impedance
Output operating state
Note ꢂ: Don’t Care
Initial Drive Position
Initial mode
Drive mode
5ch
100%
6ch
0%
2W1-2 phase drive
Reference Voltage Setting Serial Data: 2 bits (Channels 5 and 6 driver settings register)
D7 (VSEN2)
D6 (VSEN1)
Current control reference voltage (when 100%)
0
0
1
1
0
1
0
1
0.2 V
0.134 V
0.1 V
0.066 V
Set Current Calculation
IOUT (reference voltage u set current ratio)/(sense resistor (SEN) value)
Since the reference voltage can be set to either 0.2, 0.134, 0.1, or 0.066 V with the serial data, the output current
can be set with either the reference voltage or the value of the sense resistor SEN.
No.7944-20/24
LV8041FN
Constant Current Forward/Reverse Motor Driver (Channel 7)
Truth Table
Inputs
IN71
ꢂ
Outputs
Mode
Charge pump circuit
Stopped
ST
IN72
ꢂ
OUT7A
OFF
OFF
High
Low
OUT7B
OFF
OFF
Low
Low
High
High
High
High
Standby mode
Outputs off
Forward
Low
Low
High
High
Low
High
Low
High
Operating
High
Low
Reverse
Low
Brake
Note ꢂ: Don’t care
VM7
OUT7AA
OUT7BA
IN71
IN72
VREF7
Reference
voltage
LIM7
Fast
charge
circuit
SEN7
Fast
discharge
circuit
FC7
IN71
IN72
OFF
ON
U1
L1
OFF
ON
ON
U2
L2
OFF
OFF
ON
ON
High
impedance
High
impedance
Forward
Reverse
Brake
Set Current Calculation
I
OUT = LIM7 voltage/SEN7 resistor
Since the LIM7 voltage is an external input, the reference voltage can be set arbitrarily.
The reference voltage can be set to 0.2 V by using the VREF7 pin and shorting it to the LIM7 pin. If a voltage
created by resistor dividing the VREF7 voltage is input to LIM7, the reference voltage can be made variable (to
voltages under 0.2 V).
No.7944-21/24
LV8041FN
Recommended Application Circuit
The values shown near the various pins are recommended values. See the Allowable Operating Ranges table earlier in
this document for numerical values for the input conditions.
Channels 1 and 2: Microstep drive
Channels 3 and 4: Microstep drive
Channels 5 and 6: Described separately
Channel 7: Constant current drive
(ꢂ3)
5 V
0 V
5 V
0 V
5 V
0 V
0.1 PF
0.1 PF
52
51
50
49
48
47
46
45
44
43
42
41
40
1
2
3
4
5
6
7
8
9
39
38
37
36
35
34
33
32
31
30
29
28
27
OUT1A
SEN1
CPL1
5 V
1 :
VM7
OUT7B
SEN7
M
M
OUT1B
10 PF
5 V
1 :
VM12
OUT2A
SEN2
OUT7A
PGND7
OUT6B
SEN6
10 PF
1 :
LV8041FN
OUT2B
OUT3A
SEN3
1 :
OUT6A
VM56
5 V
10 OUT3B
VM34
5 V
11
12 OUT4A
13
OUT5B
10 PF
SEN5
10 PF
1 :
OUT5A
SEN4
(ꢂ2)
14
15
16
17
18
19
20
21
22
23
24
25
26
5 V
0 V
5 V
0 V
The circuit diagram for
the section enclosed in
the dotted line is
Serial data input
(ꢂ1)
provided separately.
Note ꢂ1: Use a single point ground for the ground lines if at all possible.
ꢂ2: Here, a 1 : resistor is attached for each of the SEN pin resistors. This sets an output of 200 mA when the current ratio is 100%.
ꢂ3: The LIM7 reference voltage can be provided either as an external voltage or by using VREF7: either voltage dividing VREF7 (0.2 V) or simply
shorting LIM7 to VREF7.
No.7944-22/24
LV8041FN
Channels 5 and 6 Recommended Circuit
The channels 5 and 6 systems can be switched between microstep drive and PWM drive.
Set the mode using the serial data as described earlier in this document.
Application 1 ... Microstep Drive Mode (Fixed 2W1-2 phase drive)
33
32
31
30
29
28
27
OUT6B
SEN6
1 :
OUT6A
VM56
OUT5B
1 :
SEN5
M
OUT5A
25
26
(ꢂ4)
5 V
0 V
Note ꢂ4: In microstep drive mode, pin 26 functions as a position detection monitor pin.
Application 2 ... PWM Drive Mode (1)
33
32
31
30
29
28
27
OUT6B
SEN6
(ꢂ5)
OUT6A
VM56
OUT5B
SEN5
OUT5A
25
26
5 V
0 V
5 V
0 V
Note ꢂ5: Since the current limiter does not operate in PWM drive mode, the sense resistor is not needed.
No.7944-23/24
LV8041FN
Application (3) PWM Drive Mode (2) (Doubled output capacity)
33
32
31
30
29
28
27
OUT6B
SEN6
OUT6A
VM56
OUT5B
SEN5
OUT5A
(ꢂ6)
25
26
5 V
0 V
Note ꢂ6: Short the inputs together.
(Also short the outputs together. Do not short the outputs incorrectly: short OUT5A to OUT6A and short OUT5B to OUT6B.)
Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer's
products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer's products or
equipment.
SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could give
rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that
could cause damage to other property. When designing equipment, adopt safety measures so that these
kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits
and error prevention circuits for safe design, redundant design, and structural design.
In the event that any or all SANYO products (including technical data, services) described or contained
herein are controlled under any of applicable local export control laws and regulations, such products
must not be exported without obtaining the export license from the authorities concerned in accordance
with the above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system, of
otherwise, without the prior written permission of SANYO Electric Co., Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for
the SANYO product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no
guarantees are made or implied regarding its use or any infringements of intellectual property rights or
This catalog provides information as of August, 2004. Specifications and information herein are subject to
change without notice.
No.7944-24/24
相关型号：
ENN8036
NPN Triple Diffused Planar Silicon Transistor Color TV Horizontal Deflection Output Applications
SANYO
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