LA75501V_07 [SANYO]
For Use in TV/VTR Applications VIF/SIF Signal Processing IC; 用于TV / VTR应用VIF / SIF信号处理IC
| 型号： | LA75501V_07 |
| 厂家： | 
SANYO SEMICON DEVICE |
| 描述： | For Use in TV/VTR Applications VIF/SIF Signal Processing IC |
| 文件： | 总10页 (文件大小：199K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : ENA0224
Monolithic Linear IC
For Use in TV/VTR Applications
LA75501V
VIF/SIF Signal Processing IC
Overview
The LA75501V is an adjustment free VIF/SIF signal processing IC for PAL TV/VCR. It supports 38MHz, 38.9MHz, and
39.5MHz as the IF frequencies, as well as PAL sound multi-system (M/N,B/G, I, D/K), and contains an on-chip sound
carrier trap and sound carrier BPF. To adjust the VCO circuit, AFT circuit, and sound filter, 4MHz external crystal or
4MHz external signal is needed.
Function
• VIF Block:
VIF Amplifier, PLL Detector, IF AGC, RF AGC, Equalizer, amplifier, Buzz Canceller, SIF Trap,
Digital AFT, FLL, 4MHz X’tal oscillation
• 1st SIF Block: 1st SIF Amplifier, 1st SIF Detector, 1st SIF AGC
• SIF Block:
• Others:
Limiter Amplifier Down Converter, PLL FM Detector SIF PLL SIF VCO, SIF BPF
IF SW (38.9MHz, 38MHz), SIF4 System SW (B/G, I, D/K, M/N), IFAGC 2nd filter
Specifications
Maximum Ratings at Ta = 25°C
Parameter
Maximum Supply voltage
Circuit voltage
Symbol
Conditions
Ratings
Unit
V
V
7
CC
V
V
I
V
V
V
16
CC
V
18
CC
-1
Circuit Current
mA
mA
mA
mA
mW
°C
30
17
I
+0.5
-10
I
6
I
-3
4
Allowable power dissipation
Operating temperature
Storage temperature
Pd max
Topr
Ta≤80°C *
500
-20 to +85
-55 to +150
Tstg
°C
* Mounted on a board : 65×72×1.6mm3,paper phenol board.
Any and all SANYO Semiconductor products described or contained herein do not have specifications
that can handle applications that require extremely high levels of reliability, such as life-support systems,
aircraft's control systems, or other applications whose failure can be reasonably expected to result in
serious physical and/or material damage. Consult with your SANYO Semiconductor representative
nearest you before using any SANYO Semiconductor products described or contained herein in such
applications.
SANYO Semiconductor assumes no responsibility for equipment failures that result from using products
at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor
products described or contained herein.
92706 / 22706 MS OT B8-4910 No.A0224-1/10
LA75501V
Operating Ranges at Ta = 25°C
Parameter
Symbol
Conditions
Ratings
Unit
V
Recommended supply voltage
Operating supply voltage
V
5.0
CC
op
V
4.5 to 6.0
V
CC
Electrical Characteristics at Ta = 25°C, V
= 5V, fp = 38.9MHz
CC
VIF Block
Ratings
typ
Parameter
Symbol
Conditions
Unit
min
max
73.6
Circuit current
I
64.0
9
mA
V
21
Maximum RF AGC voltage
Minimum RF AGC voltage
Input sensitivity
V
H
Collector load 30k VC2 = 9V
8.5
0.0
33
17
V
L
0.3
0.7
45
V
17
vi
39
dBµV
dB
AGC range
GR
58
Maximum allowable input
No-signal video output voltage
Sync. Signal tip voltage
Video output amplitude
Video S/N
Vi max
92
97
3.3
1.2
1.8
52
32
5
dBµV
V
V
6
2.9
0.9
1.5
48
3.7
1.5
2.1
V tip
6
V
V
Vp-p
dB
O
S/N
IC-S
DG
B/G
C-S best
PS = 10dB
26
38
10
10
dB
Differential gain
80dBµ, 87.5% MOD
80dBµ, 87.5% MOD
%
Differential phase
DP
2
°C
Black noise threshold voltage
Black noise clamp voltage
VIF input resistance
VIF input capacitance
Maximum AFT voltage
Minimum AFT voltage
AFT tolerance 1
V
0.7
1.8
2.5
3
V
BTH
V
V
BCL
R
3.0
6
kΩ
i
i
C
PF
V
H
L
4.3
0
4.7
0.2
35
35
55
30
2.0
2.0
2.0
5.0
0.7
70
70
80
60
V
16
V
V
16
dfa1
dfa2
sf
f = 38.9MHz
f = 38.0MHz
KHz
KHz
mV/kHz
MHz
MHz
MHz
MHz
AFT tolerance 2
ATF detection sensitivity
AFT Dead Zone
R
= 100k//100KΩ
30
L
fda
fpu
fpl
APC pull-in range (U)
APC pull-in range (L)
1.5
1.5
1.5
VCO maximum
dfu
variable range (U)
VCO maximum
dfl
1.5
2.0
2.0
MHz
variable range (L)
VCO control sensitivity
β
4.0
-35
-24
-32
-25
-30
-20
-30
60
8.0
kHz/mV
dB
dB
dB
dB
dB
dB
dB
ns
N Trap 1 (4.5M)
NT1
-30
-19
-27
-20
-25
-15
-25
30
N Trap 2 (4.8M)
NT1-1
BT1
B/G Trap 1 (5.5M)
B/G Trap 2 (5.85M)
BT1-1
IT1
I Trap 1 (6.0M)
I Trap 2 (6.55M)
IT1-1
DT1
D/K Trap1 (6.5M)
Group delay 1 NTSC (3.0M)
Group delay 1-1 NTSC (3.5M)
Group delay 2 B/G (4M)
Group delay 2-1 B/G (4.4M)
Group delay 3 I (4M)
Group delay 3-1 I (4.4M)
Group delay 4 D/K (4M)
Group delay 4-1 D/K (4.4M)
ngd1
ngd1-1
bgd2
bgd2-1
bgd3
bgd3-1
bgd4
bgd4-1
90
300
130
300
80
160
70
230
100
230
50
ns
ns
160
20
ns
ns
60
90
120
60
ns
0
30
ns
10
40
70
ns
No.A0224-2/10
LA75501V
1st SIF Block
Ratings
typ
Parameter
Symbol
Conditions
Unit
min
max
Conversion gain
V
fp-5.5MHz,Vi = 500µV
26
32
36
dB
mVrms
dBµV
KΩ
G
SIF carrier output level
1st SIF maximum input
1st SIF input resistance
1st SIF input capacitance
So
Vi = 10mV
So 2dB
100
106
2.0
3
Si max
R s
i
2.4
6
C s
i
PF
SIF Block
Ratings
typ
Parameter
Symbol
Vi (lim)
Conditions
Unit
min
max
Limiting sensitivity
FM detector output voltage
AM rejection ratio
Distortion
f = 5.5MHz
46
52
58
dBµV
mVrms
dB
∆F = 30kHz at 400Hz
V
(FM)
480
50
600
60
0.3
60
100
-3
750
O
AMR
THD
AM = 30% at 400Hz
f = 5.5MHz ∆F = 30kHz
DIN. Audio
1.0
%
FM detector output S/N
BPF 3dB band width
PAL de-emphasis
NTSC de-emphasis
S/N (FM)
BW
55
dB
kHz
dB
Pdeem
Ndeem
GD
fm = 3kHz
fm = 2kHz
-3
dB
PAL/NT Audio voltage gain
difference
6
dB
Others
Ratings
typ
Parameter
Symbol
Conditions
Unit
min
max
Minimum 4MHz level
X MIN
4
Terminal value
80
86
92
dBµ
(at external input)
SIF system SW threshold voltage
V
1.4
V
13
V
14
IF system SW threshold voltage
Split/Inter SW
V
270
KΩ
15
20
V
0.5
V
System Changeover
SW/SIF system SW
The SIF system can be changed over by setting A (pin 13) and B (pin 14) to GND and the open state respectively.
FM DET
A
B
B/G
I
D/K
M/N
O
De-emphasis
LEVEL
6dB
GND
GND
GND
OPEN
GND
75µs
50µs
50µs
50µs
O
0dB
OPEN
OPEN
O
0dB
OPEN
O
0dB
Note: ‘O’ indicates that the system is selected.
IF system SW
The IF frequency is selected 38.9MHz mode with the pin 15 (crystal oscillation) open.
The IF frequency is selected 38MHz mode by adding 220KΩ between the pin 15 and GND.
Inter carrier SW
Inter-carrier is selected by setting the 1st SIF input (pin 20) to GND.
No.A0224-3/10
LA75501V
Package Dimensions
unit : mm
3191B
9.75
30
16
1
15
0.65
0.22
0.15
(0.33)
SANYO : SSOP30(275mil)
Pin Assignment
No.A0224-4/10
LA75501V
Block Diagram and AC Characteristics Test Circuit
Input Impedance Test Circuit
No.A0224-5/10
LA75501V
Test Conditions
V1. Circuit current [I
]
21
(1) External AGC (V = 1.5V)
18
(2) RF AGC VR MAX
(3) Connect an ammeter to the V
and measure the incoming current to pin 17.
CC
V2. V3. Maximum RF AGC voltage, Minimum RF AGC voltage [V H, V L]
17 17
(1) Internal AGC
(2) Input a 38.9MHz, 10mVrms, continuous wave to the VIF input pin.
(3) Adjust the RF AGC VR (resistance max.) and measure the maximum RF AGC voltage.
(4) Adjust the RF AGC VR (resistance min.) and measure the minimum RF AGC voltage.
(3), (4) Measuring point F
V4. Input sensitivity [Vi]
(1) Internal AGC
(2) fp = 38.9MHz 400Hz 40% AM (VIF input)
(3) Turn off the SW1 and put 100kΩ through.
(4) Measure the VIF input level at which the 400Hz detection output level at test point A becomes 0.7Vp-p.
V5.
AGC range [GR]
voltage to the external AGC, If AGC (pin 18).
(1) Apply the V
CC
(2) In the same manner under the same conditions as for V4 (input sensitivity), measure the VIF input level at which
the detection output level becomes 0.7Vp-p. ····· Vil *Vi: Input sensitivity
Vil
Vi
(3) GR = 20log
dB
V6. Maximum allowable input [Vi max]
(1) Internal AGC
(2) fp = 38.9MHz 15kHz 78% AM (VIF input)
(3) VIF input level at which the detection output level at test point A becomes video output (V ) 1dB.
O
V7. No-signal video output voltage [V ]
6
(1) Apply the V
voltage to the external AGC, IF AGC (pin 18).
CC
(2) Measure the DC voltage of VIDEO output (A).
V8. Sync. signal tip voltage [V tip]
6
(1) Internal AGC
(2) Input a 38.9MHz, 10mVrms, continuous wave to the VIF input pin.
(3) Measure the DC voltage of VIDEO output (A).
V9. Video output level [V ]
O
(1) Internal AGC
(2) fp = 38.9MHz 15kHz 78% AM
Vi = 10mVrms (VIF input)
(3) Measure the peak value of the detection output level at test point A. (Vp-p)
V10. Video S/N [S/N]
(1) Internal AGC
(2) fp = 38.9MHz CW = 10mVrms (VIF input)
(3) Measure the noise voltage at test point A in RMS volts through a 10kHz to 4MHz band-pass filter.
····· Noise voltage (N)
Video voltage (Vp-p)
N (Vrms)
1.12Vp-p
N(Vrms)
(4) S/N = 20log
= 20log
(dB)
No.A0224-6/10
LA75501V
V11. C/S beat [Ics]
(1) Apply DC voltage to the external AGC IF AGC (pin 18) and vary it.
(2) fp = 38.9MHz CW;10mVrms
fc = 34.47MHz CW;10mVrms − 10dB
fs = 33.4MHz CW;10mVrms − 10dB
(3) Adjust the IF AGC (pin 18) voltage so that the output level at test point A becomes 1.3Vp-p.
(4) Measure the difference between the levels for 4.43MHz and 1.07MHz components at test point A.
V12.V13. Differential gain, differential phase [DG, DP]
(1) Internal AGC
(2) fp = 38.9MHz APL50% 87.5% Modulation video signal
Vi = 10mVrms
(3) Measure the DG and DP at test point A.
V14.V15. Black noise threshold and clamp voltage [V ]
, V
BTH BCL
(1) Apply DC voltage (1 to 3V) to the external AGC, IF AGC (pin 18) and adjust the voltage.
(2) fp = 38.9MHz 400Hz 40% AM 10mVrms (VIF input)
(3) Adjust the IF AGC (pin 18) voltage to operate the noise canceller.
Measure the V at test point A.
, V
BTH BCL
V16. V17. VIF input resistance, input capacitance [R , C ]
i
i
(1) External AGC (V = 2V)
18
(2) Referring to the Input Impedance Test Circuit, measure R and C with an impedance analyzer.
i
i
No.A0224-7/10
LA75501V
V18. V19. Maximum, minimum AFT voltage, AFT detection sensitivity [V H, V L]
16
16
(1) Internal AGC
(2) fp = 38.9MHz 1.5MHz Vi = 10mVrms (VIF input)
(3) Measure maximum and minimum AFT output voltage (at the measuring point B) by changing the input
frequency.
(4) Maximum voltage: V H, minimum voltage: V L.
16 16
V20.V21.V22.V23. AFT tolerance 1,2,AFT detector sensitivity, AFT Dead Zone [dfa, Sf, fda]
(1) Measure the frequency deviation when the voltage at the measuring point B changes from V1 to V2. ·····∆f
V1−V2
Sf (mV/kHz) =
∆f
(2) Measure the width in which the voltage at the measuring point B does not change.
(3) Calculate as follows:
fda (kHz) = f2 − f1
(4) Calculate as follows:
IF Center frequency: 38.9MHz, 38MHz
f1 + f2
dfa (kHz) = fc−
2
V24.V25. APC pull-in range [fpu, fpl]
(1) Internal AGC
(2) FLL: Free
(3) fp = 33MHz to 44MHz CW;10mVrms
(4) Adjust the SG signal frequency to be higher than fp = 38.9MHz to bring the PLL to unlocked state.
Note; The PLL is taken as in unlocked state when a beat signal appears at test point A.
(5) When the SG signal frequency is lowered, the PLL is brought to locked state again. ····· f1
(6) Lower the SG signal frequency to bring the PLL to unlock state.
(7) When the SG signal frequency is raised, the PLL is brought to locked state again. ····· f2
(8) Calculate as follows:
fpu = f1 − 38.9MHz
fpl = f2 − 38.9MHz
V26.V27. VCO maximum variable range (U, L) [dfu, dfl]
(1) Apply the V
voltage to the external AGC, IF AGC (pin 18).
CC
(2) fl is taken as the frequency when 1V is applied to the APC pin (pin 9). In the same manner,
fu is taken as the frequency when 5V is applied to the APC pin (pin 9).
dpu = fu − 38.9MHz
dfl = fl − 38.9MHz
No.A0224-8/10
LA75501V
V28. VCO control sensitivity [β]
(1) Apply the V voltage to the external AGC, IF AGC (pin 18).
CC
(2) Apply the 3V to the external FLL, FLL (pin 10).
(3) Pick up the VCO oscillation frequency from the VIDEO output (A), GND, etc.
And adjust the VCO coil so that the frequency becomes 38.9MHz.
(4) f1 is taken as the frequency when 2.8V is applied to the APC pin (pin 9).
In the same manner, f2 is taken as the frequency when 3.2V is applied to the APC pin (pin 9).
f1 − f2
400
β = f2−
(kHz/mV)
F1. 1st SIF conversion gain [V ]
G
(1) Internal AGC
(2) fp = 38.9MHz CW;10mV (VIF input)
fs = 33.4MHz CW;500µV (1st SIF input) ····· V1
(3) measure the detection output level at test point C (5.5MHz) ····· V2
V2
V1
(4) V = 20log
dB
G
F2. 5.5MHz output level [So]
(1) Internal AGC
(2) fp = 38.9MHz CW; 10mV (VIF input)
fs = 33.4MHz CW; 10mV (1st SIF input) ····· V1
(3) Measure the detection output level at test point C (5.5MHz). ····· So (mVrms)
F3. 1st maximum input [Si max]
(1) Internal AGC
(2) fp = 38.9MHz CW; 10mV (VIF input)
fs = 33.4MHz CW; Variable (1st SIF input)
(3) Input level at which the detection output (5.5MHz) at test point C becomes So ±2dB. ····· Si max
F4.F5. 1st SIF input resistance, input capacitance [R (SIF1), C (SIF1)]
i
i
(1) Referring to the Input Impedance Test Circuit, measure R and C with an impedance analyzer.
i
i
S1. SIF Limiting sensitivity [V (lim)]
i
(1) Apply the V
voltage to the external AGC, IF AGC (pin 18).
CC
(2) fs = 5.5MHz fm = 400Hz ∆F = 300kHz (SIF input)
(3) Set the SIF input level to 31.6mVrms and measure the level at test point D. ····· V1
(4) Lower the SIF input level and measure the input level which becomes V1. ····· 3dB.
S2.S4. FM detection output voltage, total harmonics distortion [V (FM), THD]
O
(1) Apply the V
voltage to the external AGC, IF AGC (pin 18).
CC
(2) fs = 5.5MHz fm = 400Hz ∆f = 30kHz
(SIF input Vi = 31.6mVrms)
(3) Measure the FM detection output voltage, total harmonics distortion at test point D.
S3. AM rejection ratio [AMR]
(1) External AGC (V =V
)
CC
18
(2) fs = 5.5MHz fm = 400Hz AM = 30%
(SIF input Vi = 31.6mVrms)
(3) Measure the output level at test point D. ····· VAM
V
(DET)
VAM
O
(4) AMR = 20log
dB
S5. SIF S/N [S/N (FM)]
(1) External AGC (V = V
)
15 CC
(2) fs = 5.5MHz NO MOD Vi = 31.6mVrms
(3) Measure the output level at test point D. ····· Vn
V
(DET)
Vn
O
(4) S/N = 20log
dB
No.A0224-9/10
LA75501V
S7.S8. PAL, NT de-emphasis [Pdeem, Ndeem]
(1) External AGC (V = V
)
18 CC
(2) fs = 5.5MHz fm = 3kHz ∆F = 30kHz
(SIF input Vi = 31.6mVrms)
(3) Open system switches (A (pin 13) and B (pin 14)). (BG mode)
(4) Measure the FM detector output voltage at test point D. ····· Vp
(5) Calculate as follows:
Pdeem (dB) = Vp − V (FM)
O
(6) fs = 4.5MHz fm = 2kHz ∆F = 30kHz
(SIF input Vi = 31.6mVrms)
(7) Set system switches [A (pin 13) and B (pin 14)] to GND. (NT mode)
(8) Measure the FM detector output voltage at test point D. ····· Vp
(9) Calculate as follows:
Ndeem (dB) = Vnt − V (FM)
O
S9. PAL/NT Audio voltage gain difference [GD]
(1) External AGC (V =V
)
CC
18
(2) fs = 4.5MHz fm = 400Hz ∆F = 30kHz
(SIF input Vi = 31.6mVrms)
(3) Set system switches [A (pin 13) and B (pin 14)] to GND.
(4) Measure the FM detector output voltage at test point D. ····· Vnt
(5) Calculate as follows:
GD (db) = Vnt − V (FM)
O
Specifications of any and all SANYO Semiconductor products described or contained herein stipulate the
performance, characteristics, and functions of the described products in the independent state, and are
not guarantees of the performance, characteristics, and functions of the described products as mounted
in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an
independent device, the customer should always evaluate and test devices mounted in the customer's
products or equipment.
SANYO Semiconductor Co., Ltd. strives to supply high-quality high-reliability products. However, any
and all semiconductor products fail with some probability. It is possible that these probabilistic failures
could give rise to accidents or events that could endanger human lives, that could give rise to smoke or
fire, or that could cause damage to other property. When designing equipment, adopt safety measures
so that these kinds of accidents or events cannot occur. Such measures include but are not limited to
protective circuits and error prevention circuits for safe design, redundant design, and structural design.
In the event that any or all SANYO Semiconductor products (including technical data,services) described
or contained herein are controlled under any of applicable local export control laws and regulations, such
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Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification"
for the SANYO Semiconductor product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
guaranteed for volume production. SANYO Semiconductor believes information herein is accurate and
reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual
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This catalog provides information as of February, 2006. Specifications and information herein are subject
to change without notice.
PS No.A0224-10/10
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