LC88F52H0A [SANYO]
FROM 128K byte, RAM 6K byte on-chip 16-bit 1-chip Microcontroller; 从128K字节， RAM 6K字节的片上16位单芯片微控制器
| 型号： | LC88F52H0A |
| 厂家： | 
SANYO SEMICON DEVICE |
| 描述： | FROM 128K byte, RAM 6K byte on-chip 16-bit 1-chip Microcontroller |
| 文件： | 总31页 (文件大小：173K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : ENA1951
CMOS LSI
FROM 128K byte, RAM 6K byte on-chip
LC88F58B0A
16-bit 1-chip Microcontroller
Overview
The SANYO LC88F58B0A is a 16-bit microcomputer that, centered around an Xstromy16 CPU, integrates on a single
chip a number of hardware features such as 128K-byte flash ROM (onboard programmable), 6K-byte RAM, six 16-bit
timers, a base timer serving as a time-of-day clock, two synchronous SIO interfaces with automatic transmission
capability, a single master I2C/synchronous SIO interface, two asynchronous SIO (UART) interfaces, a 11-channel 12-bit
resolution AD converter, a motor drive signal generator circuit, two multifrequency 12-bit PWM modules, a watchdog
timer, a system clock frequency divider, a 40-source (24 modules) 16-vector interrupt feature, and on-chip debugger
feature.
Features
Xstromy16 CPU
• 4G-byte address space
• General-purpose registers: 16 bits × 16 registers
Flash ROM
• Capable of onboard programming with a wide range of voltage levels (3.0 to 5.5V).
• Block-erasable in 128 or 1K byte units.
• Data written in 2-byte units.
• 131072 × 8 bits
RAM
• 6144 × 8 bits
* This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by
SANYO Semiconductor Co., Ltd.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer
's products or
equipment.
Ver.1.03
41311HKIM 20080924-S00002 No.A1951-1/31
LC88F58B0A
Minimum Instruction Cycle Time (tCYC)
• 83.3 ns (12MHz)
• 100 ns (10MHz)
• 500 ns (2MHz)
V
DD
V
DD
V
DD
= 4.5 to 5.5V
= 3.0 to 5.5V
= 2.2 to 5.5V
Ports
• Normal withstand voltage I/O ports
Ports whose I/O direction can be designated in 1 bit units : 52 (P0n, P1n, P2n, P30 to P33, P4n, P6n, P70 to P72,
PA0 to PA3, PC2)
• Oscillation/normal withstand voltage I/O ports
• Oscillation dedicated ports
• Reset pins
: 2 (PC0, PC1)
: 2 (CF1, CF2)
: 1 (RESB)
• TEST pins
: 1 (TEST)
• Power pins
: 6 (V 1 to 3, V 1 to 3)
SS DD
Timers
• Timer 0: 16-bit timer that supports PWM/toggle outputs
1) 5-bit prescaler
2) 8-bit PWM × 2, 8-bit timer + 8-bit PWM mode selectable
3) Clock source selectable from system clock, OSC0, OSC1, and internal RC oscillator
• Timer 1: 16-bit timer with capture registers
1) 5-bit prescaler
2) May be divided into 2 channels of 8-bit timer
3) Clock source selectable from system clock, OSC0, OSC1, and internal RC oscillator
• Timer 2: 16-bit timer with capture registers
1) 4-bit prescaler
2) May be divided into 2 channels of 8-bit timer
3) Clock source selectable from system clock, OSC0, OSC1, and external events
• Timer 3: 16-bit timer that supports PWM/toggle outputs
1) 8-bit prescaler
2) 8-bit timer × 2ch or 8-bit timer + 8-bit PWM mode selectable
3) Clock source selectable from system clock, OSC0, OSC1, and external events
• Timer 4: 16-bit timer that supports toggle outputs
1) Clock source selectable from system clock and prescaler 0
• Timer 5: 16-bit timer that supports toggle outputs
1) Clock source selectable from system clock and prescaler 0
• Base timer
1) Clock may be selected from OSC0 (32.768kHz crystal oscillator) and frequency-divided output of system clock.
2) Interrupts can be generated in 7 timing schemes.
No.A1951-2/31
LC88F58B0A
Serial Interfaces
• SIO0: 8-bit synchronous SIO
1) LSB first/MSB first mode selectable
2) Supports data communication with a data length of 8 bits or less (1 to 8 bits specifiable)
3) Built-in 8-bit baudrate generator (4 tCYC to 512 tCYC transfer clocks)
4) Continuous/automatic data transmission (9- to 32768-bit units specifiable)
5) Interval function (intervals specifiable in 0 to 64 tSCK units)
6) Wakeup function
• SIO1: 8-bit synchronous SIO
1) LSB first/MSB first mode selectable
2) Supports data communication with a data length of 8 bits or less (1 to 8 bits specifiable)
3) Built-in 8-bit baudrate generator (4 tCYC to 512 tCYC transfer clocks)
4) Continuous/automatic data transmission (9- to 32768-bit units specifiable)
5) Interval function (intervals specifiable in 0 to 64 tSCK units)
6) Wakeup function
• SMIIC0: Single master I2C/8-bit synchronous SIO
Mode 0: Single-master mode communication
Mode 1: Synchronous 8-bit serial I/O (MSB first)
• UART0
1) Data length
: 8 bits (LSB first)
: 1 bit
2) Start bits
3) Stop bits
: 1 bit
4) Parity bits
5) Transfer rate
: None/even parity/odd parity
: 4/8 cycle
6) Baudrate source clock: P07 input signal used as a 1 cycle signal (T0PWMH can be used as a clock source)
7) Full duplex communication
Note: The “cycle” refers to one period of the baudrate clock source.
• UART2
1) Data length
: 8 bits (LSB first)
: 1 bit
2) Start bits
3) Stop bits
: 1/2 bit
4) Parity bits
5) Transfer rate
: None/even parity/odd parity
: 8 to 4096 cycle
6) Baudrate source clock : System clock/OSC0/OSC1
7) Wakeup function
8) Full duplex communication
Note: The “cycle” refers to one period of the baudrate clock source.
AD Converter
1) 12/8 bits resolution selectable
2) Analog input: 11 channels
3) Comparator mode
4) Automatic reference voltage generation
PWM
• PWM0: Multifrequency 12-bit PWM × 2 channels (PWM0A and PWM0B)
1) 2-channel pairs controlled independently of one another
2) Clock source selectable from system clock or OSC1
3) 8-bit prescaler: TPWMR0=(prescaler value + 1) × clock period
4) 8-bit fundamental wave PWM generator circuit + 4-bit additional pulse generator circuit
5) Fundamental wave PWM mode
Fundamental wave period : 16 TPWMR0 to 256 TPWMR0
High pulse width
: 0 to (Fundamental wave period - TPWMR0)
6) Fundamental wave + additional pulse mode
Fundamental wave period : 16 TPWMR0 to 256 TPWMR0
Overall period
: Fundamental wave period × 16
High pulse width
: 0 to (Fundamental wave period - TPWMR0)
No.A1951-3/31
LC88F58B0A
Watchdog Timer
1) Driven by the base timer + internal watchdog timer dedicated counter
2) Interrupt or reset mode selectable
Motor Drive Signal Generator Circuit
Interrupts (peripheral function)
• 40 sources (24 modules), 16 vector addresses
1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of
the level equal to or lower than the current interrupt are not accepted.
2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level
takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector
address takes precedence.
No.
1
Vector Address
08000H
08004H
08008H
0800CH
08010H
08014H
08018H
0801CH
08020H
08024H
08028H
0802CH
08030H
08034H
08038H
0803CH
Interrupt Module
Watchdog timer (1)
Base timer (2)
Timer 0 (2)
2
3
4
INT0 (1)
5
6
INT1 (1)
7
INT2 (1)/timer 1 (2)/UART2 (4)
INT3 (1)/timer 2 (4)/SMIIC0 (1)
INT4 (1)/timer 3 (2)
INT5 (1)/timer 4 (1)/SIO1 (2)
USM0 (3)
8
9
10
11
12
13
14
15
16
PWM0 (1)
ADC (1)/timer 5 (1)
INT6 (1)
INT7 (1)/SIO0 (2)
Port 0 (3)
• 3 priority levels selectable.
• Of interrupts of the same level, the one with the smallest vector address takes precedence.
• A number enclosed in parentheses denotes the number of sources.
Subroutine Stack: 6K-byte RAM area
• Subroutine calls that automatically save PSW, interrupt vector calls: 6 bytes
• Subroutine calls that do not automatically save PSW: 4 bytes
Multiplication/Division Instructions
• 16 bits × 16 bits (18 tCYC execution time)
• 16 bits ÷ 16 bits (18 to 19 tCYC execution time)
• 32 bits ÷ 16 bits (18 to 19 tCYC execution time)
Oscillator Circuits
• RC oscillator circuit (internal): For system clock
• OSC1 (CF oscillator circuit): For system clock, built-in Rf circuit
• OSC0 (crystal oscillator circut): For low-speed system clock
• SLRC oscillator circuit (internal): For system clock (exception processing time)
System Clock Divider Function
• Can run on low current.
• 1/1 to 1/128 of the system clock frequency can be set.
No.A1951-4/31
LC88F58B0A
Standby Function
• HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation.
1) Oscillation is not stopped automatically.
2) Released by a system reset or occurrence of an interrupt.
• HOLD mode: Suspends instruction execution and the operation of the peripheral circuits.
1) OSC1, RC and OSC0 oscillators automatically stop.
2) There are three ways of releasing the HOLD mode.
(1) Setting the reset pin to the low level
(2) Setting at least one of the INT0, INT1, INT2, INT4, INT5, INT6, and INT7 pins to the specified level
(3) Having an interrupt source established at port 0
(4) Having an interrupt established at SIO0 or SIO1
(5) Having an interrupt established at UART2
• HOLDX mode: Suspends instruction execution and the operation of the peripheral circuits except those which run
on OSC0.
1) OSC1 and RC oscillations automatically stop.
2) OSC0 maintains the state that is established when the HOLDX mode is entered.
3) There are four ways of releasing the HOLDX mode.
(1) Setting the reset pin to the low level
(2) Setting at least one of the INT0, INT1, INT2, INT4, INT5, INT6, and INT7 pins to the specified level
(3) Having an interrupt source established at port 0
(4) Having an interrupt source established at the base timer circuit
(5) Having an interrupt established at SIO0 or SIO1
(6) Having an interrupt established at UART2
On-chip Debugger Function
• Supports software debugging with the IC mounted on the target board.
• Supports source line debugging and tracing functions, and breakpoint setting.
• Single-wire communication
Package Form
• SQFP64 (10×10): Lead-free and halogen-free type
Development Tools
• On-chip debugger: EOCUIF1 + LC88F58B0A
Programming Board
Package
Programming Board
W88F58SQ
SQFP64 (10 × 10)
Flash Programming
Manufacturer
Model Name
AF9708/09/09B/09C
AF9723/23B
Supported Version
Device
Revison : After Rev.03.04
Revison : After Rev.02.29
Revison : After Rev.01.90
Revison : After Rev.01.13
LC88F58B0A
LC88F58B0A
Flash Support Group (Single)
Flash Support Group (Gang)
SANYO
AF9833
LC88F58B0A
SKK/SKK Type-B
No.A1951-5/31
LC88F58B0A
Package Dimensions
unit : mm (typ)
3190A
12.0
10.0
48
33
49
32
17
64
1
16
0.15
0.5
0.18
(1.25)
SANYO : SQFP64(10X10)
Pin Assignment
48 47 46 45 44 43 42 41 40 39 38 37 36 35
34 33
P32/INT2
P31/INT1
P30/INT0
TEST
49
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
P72/AN10
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
P71/AN9
P70/AN8
P17/U2TX
RESB
P16/U2RX
PC0/XT1
PC1/XT2
P15/T3OH
P14/T3OL/U0RX
P13/U0TX
V
1
SS
LC88F58B0A
CF1
CF2
P12/SCK0
P11/SI0/SB0
P10/SO0
V
1
DD
P60/AN0
P61/AN1
P62/AN2
P63/AN3
P64/AN4
P07/T0PWMH/U0BRG
P06/T0PWML
P05/P05INT
P04/P04INT
P03/P0INT
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
Top view
SANYO: SQFP64 (10×10) (Lead-free and halogen-free type)
No.A1951-6/31
LC88F58B0A
System Block Diagram
CF
RC
Base timer
X’tal
Low
speed
RC
Watchdog timer
Timer 0
Xstromy16
CPU
FLASH ROM
RAM
Timer 1
On-chip debugger
Timer 2
Port 0
Port 1
Port 2
Port 3
Port 4
Port 6
Port 7
Port A
Timer 3
Timer 4
Timer 5
SIO0
SIO1
SMIIC0
UART0
UART2
Port C
PWM0
AD
INT0 to INT7
Motor control signal
generator
No.A1951-7/31
LC88F58B0A
Pin Description
Pin Name
I/O
Description
V
V
1, V 2,
-
- Power sources
+ Power sources
SS
SS
3
SS
V
V
1, V 2,
DD
3
-
DD
DD
Port 0
I/O
• 8-bit I/O port
• I/O specifiable in 1-bit units
P00 to P07
• Pull-up resistors can be turned on and off in 1 bit units
• HOLD release input (P00 to P03, P04, P05)
• Port 0 interrupt input (P00 to P03, P04, P05)
• Pin functions
P06: Timer 0L output
P07: Timer 0L output/UART0 clock input
Port 1
I/O
• 8-bit I/O port
• I/O specifiable in 1-bit units
P10 to P17
• Pull-up resistors can be turned on and off in 1 bit units
• Pin functions
P10: SIO0 data output
P11: SIO0 data input/pulse input/output
P12: SIO0 clock input/output
P13: UART0 transmit
P14: Timer 3L output/UART0 receive
P15: Timer 3H output
P16: UART2 receive
P17: UART2 transmit
Port 2
I/O
• 8-bit I/O port
• I/O specifiable in 1-bit units
P20 to P27
• Pull-up resistors can be turned on and off in 1 bit units
• Pin functions
P20: INT4 input/HOLD release input/timer 3 event input/timer 2L capture input/timer 2H capture input
P21: INT5 input/HOLD release input/timer 3 event input/timer 2L capture input/timer 2H capture input
P22: SMIIC0 clock input/output
P23: SMIIC0 bus input/output/data input
P24: SMIIC0 data output (used in 3-wire SIO mode)
P25: Timer 4 output
P26: Timer 5 output
Interrupt acknowledge type
INT4, INT5: H level, L level, H edge, L edge, both edges
Port 3
I/O
• 4-bit I/O port
• I/O specifiable in 1-bit units
P30 to P33
• Pull-up resistors can be turned on and off in 1 bit units
• Pin functions
P30: INT0 input/HOLD release/timer 2L capture input
P31: INT1 input/HOLD release/timer 2H capture input
P32: INT2 input/HOLD release/timer 2 event input/timer 2L capture input
P33: INT3 input/HOLD release/timer 2 event input/timer 2H capture input
Interrupt acknowledge type
INT0 to INT3: H level, L level, H edge, L edge, both edges
Continued on next page.
No.A1951-8/31
LC88F58B0A
Continued from preceding page.
Pin Name
I/O
Description
Port 4
I/O
• 8-bit I/O port
• I/O specifiable in 1-bit units
P40 to P47
• Pull-up resistors can be turned on and off in 1 bit units
• Pin functions
P40: INT6 input/HOLD release input
P41: INT7 input/HOLD release input
P43: SIO1 data output
P44: SIO1 data input/bus input/output
P45: SIO1 clock input/output
P46: PWM00 output
P47: PWM01 output
Interrupt acknowledge type
INT6, INT7: H level, L level, H edge, L edge, both edges
Port 6
I/O
I/O
I/O
• 8-bit I/O port
• I/O specifiable in 1-bit units
• Pull-up resistors can be turned on and off in 1 bit units
• Pin functions
P60 to P67
AN0 (P60) to AN7 (P67): AD converter input port
Port 7
• 3-bit I/O port
• I/O specifiable in 1-bit units
• Pull-up resistors can be turned on and off in 1 bit units
• Pin functions
P70 to P72
AN8 (P70) to AN10 (P72): AD converter input port
Port A
• 4-bit I/O port
• I/O specifiable in 1-bit units
• Pull-up resistors can be turned on and off in 1 bit units
• Multiplexed pin functions
PA0 to PA3
PA0: USM0 output 0
PA1: USM0 output 1
PA2: USM0 output 2
PA3: USM0 output 3
Port C
I/O
I/O
• 3-bit I/O port (on output: Nch-open drain (PC0 to PC1), CMOS (PC2))
• I/O specifiable in 1-bit units
• Pin functions
PC0 to PC2
PC0: 32.768kHz crystal oscillator input
PC1: 32.768kHz crystal oscillator output
PC2: FILT
TEST
• TEST pin
• Used to communicate with on-chip debugger.
• Connects an external 100kΩ pull-down resistor.
RESB
CF1
I
I
Reset pin
Ceramic oscillator input pin
Ceramic oscillator output pin
CF2
O
No.A1951-9/31
LC88F58B0A
Port Output Types
The table below lists the types of port outputs and the presence/absence of a pull-up resistor.
Data can be read into any input port even if it is in the output mode.
Option Selected in
Port Name
Option Type No.
Output Type
Pull-up Resistor
Programmable
Units of
1 bit
P00 to P07
1
CMOS
P10 to P17
P20 to P27
P30 to P33
P40 to P47
P60 to P67
P70 to P72
PA0 to PA3
PC2
2
N-channel open drain
-
-
-
-
CMOS
PC0
PC1
N-channel open drain
None
None
(32.768kHz crystal oscillator input)
N-channel open drain
-
-
(32.768kHz crystal oscillator output)
* Make the following connection to minimize the noise input to the V 1 pin and prolong the backup time.
DD
Be sure to electrically short the V 1, V 2 and V 3 pins.
SS SS SS
Example 1: When data is being backed up in the HOLD mode, the H level signals to the output ports are fed by the
backup capacitors.
LSI
V
1
DD
Power
supply
PC2/FILT
For buckup
1kΩ
V
2
DD
+
-
2.2μF
V
3
DD
1 V 2 V 3
SS
V
SS
SS
Example 2: When data is being backed up in the HOLD mode, the H level output at any ports is not sustained and is
unpredictable.
LSI
V
V
V
1
2
3
DD
DD
DD
Power
supply
PC2/FILT
For buckup
1kΩ
+
-
2.2μF
V
1 V 2 V
SS
3
SS
SS
No.A1951-10/31
LC88F58B0A
Absolute Maximum Ratings at Ta = 25°C, V 1 = V 2 = V 3 = 0V
SS
SS
SS
Specification
typ max
Applicable Pin
/Remarks
Parameter
Symbol
max
Conditions
V
[V]
min
-0.3
unit
DD
Maximum supply
voltage
V
V
1, V 2, V 3
DD
V
1=V 2=V
3
DD
DD
DD
DD DD DD
+6.5
Input voltage
V (1)
CF1, RESB
V
I
DD
-0.3
-0.3
+0.3
V
Input/output
voltage
V
(1)
Ports 0, 1, 2
Ports 3, 4
IO
V
DD
Ports 6, 7
+0.3
Ports A, C
Ports 0, 1, 2
P70 to P72
P40 to P45
PA0 to PA3
P46, P47
Peak output
current
IOPH(1)
CMOS output selected
Per applicable pin
-10
IOPH(2)
IOPH(3)
Per applicable pin
Per applicable pin
-20
-5
Port 6
P30 to P33
PC2
Average
output
IOMH(1)
Ports 0, 1, 2
P70 to P72
P36 to P37
P40 to P45
PA0 to PA3
P46, P47
CMOS output selected
Per applicable pin
current
-7.5
(Note 1-1)
IOMH(2)
IOMH(3)
Per applicable pin
Per applicable pin
-10
-3
Port 6
P30 to P33
PC2
Total output
current
ΣIOAH(1)
ΣIOAH(2)
ΣIOAH(3)
P30 to P33, PC2
Total of currents at
applicable pins
-15
-15
mA
Port 6
Total of currents at
applicable pins
Port 6
Total of currents at
applicable pins
P30 to P33
PC2
-20
ΣIOAH(4)
ΣIOAH(5)
ΣIOAH(6)
ΣIOAH(7)
ΣIOAH(8)
ΣIOAH(9)
Ports 0, 1
P25 to P27
P20 to P24
Total of currents at
applicable pins
-25
-25
-45
-25
-25
Total of currents at
applicable pins
Ports 0, 1, 2
Total of currents at
applicable pins
P40 to P45
PA0 to PA3
P46 to P47
P70 to P72
Port 4
Total of currents at
applicable pins
Total of currents at
applicable pins
Total of currents at
applicable pins
P70 to P72
PA0 to PA3
-45
Note 1-1: Average output current refers to the average of output currents measured for a period of 100ms.
Continued on next page.
No.A1951-11/31
LC88F58B0A
Continued from preceding page.
Specification
typ max
Applicable Pin
/Remarks
Parameter
Symbol
IOPL(1)
Conditions
V
[V]
min
unit
DD
Peak output
current
Ports 0, 1, 4
Per applicable pin
P70 to P72
20
PA0 to PA3
P20, P21, P24 to P27
P22, P23
IOPL(2)
IOPL(3)
Per applicable pin
Per applicable pin
25
10
P30 to P33
Port 6
PC0 to PC2
Ports 0, 1, 4
P70 to P72
PA0 to PA3
P20, P21, P24 to P27
P22, P23
Average
IOML(1)
Per applicable pin
output current
(Note 1-1)
15
IOML(2)
IOML(3)
Per applicable pin
Per applicable pin
20
P30 to P33
Port 6
7.5
PC0 to PC2
P30 to P34
PC0 to PC2
Port 6
Total output
current
ΣIOAL(1)
ΣIOAL(2)
ΣIOAL(3)
Total of currents at
applicable pins
15
15
mA
Total of currents at
applicable pins
Port 6
Total of currents at
applicable pins
P30 to P33
PC0 to PC2
Ports 0, 1
P25 to P27
P20 to P24
20
ΣIOAL(4)
ΣIOAL(5)
ΣIOAL(6)
ΣIOAL(7)
ΣIOAL(8)
ΣIOAL(9)
Total of currents at
applicable pins
45
45
80
45
45
Total of currents at
applicable pins
Ports 0, 1, 2
Total of currents at
applicable pins
P40 to P45
PA0 to PA3
P46 to P47
P70 to P72
Port 4
Total of currents at
applicable pins
Total of currents at
applicable pins
Total of currents at
applicable pins
P70 to P72
PA0 to PA3
SQFP64 (10×10)
80
Allowable power
dissipation
Pd max
Topr
Ta=-40 to +85°C
200
+85
mW
Operating ambient
temperature
-40
°C
Storage ambient
temperature
Tstg
-55
+125
Note 1-1: Average output current refers to the average of output currents measured for a period of 100ms.
No.A1951-12/31
LC88F58B0A
Allowable Operating Conditions at Ta = -40 to +85°C, V 1 = V 2 = V 3 = 0V
SS
SS
SS
Specification
typ max
Applicable Pin
/Remarks
Parameter
Symbol
Conditions
V
[V]
min
4.5
unit
DD
Operating
V
(1)
V
1=V 2=V
3
3
0.081μs≤tCYC≤66μs
0.098μs≤tCYC≤66μs
0.490μs≤tCYC≤66μs
5.5
5.5
5.5
DD
DD
DD
DD
supply voltage
(Note 2-1)
3.0
2.2
Memory
VHD
V
1=V 2=V
DD
RAM and register contents
sustained in HOLD mode
DD
DD
sustaining
supply voltage
High level input
voltage
2.0
5.5
V
V
V
(1)
Ports 0, 1, 2, 3, 4
Port A
0.3V
IH
IH
IH
IH
DD
2.2 to 5.5
2.2 to 5.5
V
V
V
DD
DD
DD
+0.7
(2)
(3)
(4)
Ports 6, 7, PC2
0.3V
DD
+0.7
CF1, RESB
2.2 to 5.5
2.2 to 5.5
4.0 to 5.5
0.75V
DD
PC0, PC1
P22, P23 I2C side
V
V
V
0.7V
V
DD
DD
Low level input
voltage
(1)
(2)
(3)
(4)
(5)
(6)
When ports 1, 2, 3, 4
and port A,
0.1V
IL
IL
IL
IL
IL
IL
DD
V
V
V
V
SS
SS
SS
SS
+0.4
PnFSAn=0
V
V
V
V
V
2.2 to 4.0
4.0 to 5.5
2.2 to 4.0
2.2 to 5.5
0.2V
DD
DD
Ports 0, 6, 7, PC2
When ports 1, 2, 3, 4
and port A,
0.15V
+0.4
PnFSAn=1
0.2V
DD
DD
CF1, RESB
V
V
0.25V
0.3V
SS
PC0, PC1
P22, P23 I2C side
2.2 to 5.5
4.5 to 5.5
3.0 to 5.5
2.2 to 5.5
SS
DD
66
Instruction
cycle time
(Note 2-2)
tCYC
0.081
0.098
0.490
μs
66
66
External
FEXCF(1)
CF1
• CF2 pin open
4.5 to 5.5
3.0 to 5.5
2.2 to 5.5
0.1
0.1
0.1
12
10
2
system clock
frequency
• System clock frequency
division ratio=1/1
• External system clock
DUTY50±5%
MHz
• CF2 pin open
4.5 to 5.5
3.0 to 5.5
2.2 to 5.5
0.2
0.2
0.2
24
20
4
• System clock frequency
division ratio=1/2
Oscillation
frequency
range
FmCF(1)
FmCF(2)
FmCF(3)
CF1, CF2
CF1, CF2
CF1, CF2
12MHz ceramic oscillator
mode
4.5 to 5.5
3.0 to 5.5
2.2 to 5.5
12
See Fig. 1.
(Note 2-3)
10MHz ceramic oscillator
mode
10
4
MHz
See Fig. 1.
4MHz ceramic oscillator
mode
See Fig. 1.
FmRC
Internal RC oscillation
2.2 to 5.5
2.2 to 5.5
0.5
18
1.0
30
2.0
45
FmSLRC
Internal low-speed RC
oscillation
kHz
FsX'tal
XT1, XT2
32.768kHz crystal oscillator
mode
2.2 to 5.5
32.768
See Fig. 2.
Note 2-1: V ≥3.0V must be maintained when making onboard programming into flash ROM.
DD
Note 2-2: Relationship between tCYC and oscillation frequency is 1/FmCF when frequency division ratio is 1/1 and
2/FmCF when the ratio is 1/2.
Note 2-3: See Tables 1 and 2 for oscillator constant values.
No.A1951-13/31
LC88F58B0A
Electrical Characteristics at Ta = -40 to +85°C V 1 = V 2 = V 3 = 0V
SS SS SS
,
Specification
typ max
Applicable Pin
/Remarks
Parameter
Symbol
Conditions
V
[V]
min
unit
DD
High level input
current
I
(1)
IH
Ports 0, 1, 2
Ports 3, 4
Ports 6, 7
Ports A, C
RESB
Output disabled
Pull-up resistor off
V
=V
2.2 to 5.5
2.2 to 5.5
2.2 to 5.5
1
IN DD
(Including output Tr. off leakage
current)
I
I
(2)
IH
CF1
V
=V
15
IN DD
μA
Low level input
current
(1)
IL
Ports 0, 1, 2
Ports 3, 4
Ports 6, 7
Ports A, C
RESB
Output disabled
Pull-up resistor off
V
=V
-1
IN SS
(Including output Tr. off leakage
current)
I
(2)
IL
CF1
V
I
=V
IN SS
2.2 to 5.5
4.5 to 5.5
3.0 to 5.5
2.2 to 5.5
-15
-1
High level output
voltage
V
(1)
Ports 0, 1, 2
PA0 to PA3
P40 to P45
=-1.0mA
V
OH
OH
OH
DD
V
(2)
I
=-0.4mA
V
V
-0.4
OH
DD
V
(3)
I
I
=-0.2mA
-0.4
OH
OH
OH
OH
DD
V
(4)
Port 6
=-0.4mA
3.0 to 5.5
2.2 to 5.5
V
V
-0.4
-0.4
DD
P30 to P33
PC2
V
(5)
I
=-0.2mA
OH
OH
DD
V
V
V
V
(6)
(7)
(8)
P46, P47
I
I
I
I
=-10mA
=-1.6mA
=-1.0mA
4.5 to 5.5
3.0 to 5.5
2.2 to 5.5
V
V
V
-1.5
-0.4
-0.4
OH
OH
OH
OH
OH
OH
DD
DD
DD
V
Low level output
voltage
(1)
Ports 0, 1
Ports 4, 7
P20 to P21,
P24 to P27
PA0 to PA3
P22, P23
=10mA
OL
OL
4.5 to 5.5
3.0 to 5.5
2.2 to 5.5
1.5
0.4
0.4
V
V
(2)
(3)
I
I
=1.6mA
=1.0mA
OL
OL
OL
OL
V
V
V
V
V
(4)
(5)
(6)
(7)
(8)
I
I
I
I
I
=11mA
=3.0mA
=1.3mA
=1.6mA
=1.0mA
=0.9V
4.5 to 5.5
3.0 to 5.5
2.2 to 5.5
3.0 to 5.5
2.2 to 5.5
1.5
0.4
0.4
0.4
0.4
OL
OL
OL
OL
OL
OL
OL
OL
OL
OL
Ports 6, C
P30 to P33
Pull-up resistor
Rpu(1)
Ports 0, 1, 2, 3
Ports 4, 6, 7
Ports A, PC2
RESB
V
OH
DD
4.5 to 5.5
2.2 to 4.5
15
18
35
80
kΩ
Rpu(2)
VHYS
55
150
Hysteresis
voltage
When ports 1, 2, 3,
4, A
2.2 to 5.5
2.2 to 5.5
0.1V
V
DD
PnFSAn=1
All pins
Pin capacitance
CP
Pins other than that under test
=V
V
IN SS
10
pF
f=1MHz
Ta=25°C
No.A1951-14/31
LC88F58B0A
Serial I/O Characteristics at Ta = -40 to +85°C, V 1 = V 2 = V 3 = 0V
SS SS SS
Serial I/O Characteristics (Wakeup Function Disabled) (Note 4-1-1)
Specification
Applicable
Parameter
Symbol
Conditions
• See Fig. 6.
Pin/Remarks
SCK0 (P12)
V
[V]
min
typ
max
unit
DD
Period
tSCK(1)
4
2
2
Low level
tSCKL(1)
pulse width
High level
pulse width
tSCKH(1)
tSCKHA(1)
• Automatic communication
mode
6
2.2 to 5.5
• See Fig. 6.
tCYC
tSCKHBSY(1a)
tSCKHBSY(1b)
• Automatic communication
mode
23
• See Fig. 6.
• Mode other than automatic
communication mode
• See Fig. 6.
4
4
Period
tSCK(2)
SCK0 (P12)
• CMOS output selected
• See Fig. 6.
Low level
tSCKL(2)
tSCKH(2)
tSCKHA(2)
1/2
1/2
pulse width
High level
pulse width
tSCK
• Automatic communication
mode
6
4
2.2 to 5.5
• CMOS output selected
• See Fig. 6.
tSCKHBSY(2a)
• Automatic communication
mode
tCYC
23
• CMOS output selected
• See Fig. 6.
tSCKHBSY(2b)
tsDI(1)
• Mode other than automatic
communication mode
• See Fig. 6.
4
0.03
0.03
Data setup time
Data hold time
SI0 (P11),
SB0 (P11)
• Specified with respect to rising
edge of SIOCLK
• See Fig. 6.
2.2 to 5.5
thDI(1)
Output
tdD0(1)
SO0 (P10),
SB0 (P11)
• (Note 4-1-2)
• (Note 4-1-2)
delay time
1tCYC
+0.05
μs
2.2 to 5.5
tdDO(2)
1tCYC
+0.05
Note 4-1-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-1-2: Specified with respect to the falling edge of SIOCLK. Specified as the interval up to the time an output
change begins in the open drain output mode. See Fig. 6.
No.A1951-15/31
LC88F58B0A
SIO0 Serial Input/Output Characteristics (Wakeup Function Enabled) (Note 4-2-1)
Specification
typ max
Applicable
Parameter
Symbol
Conditions
• See Fig. 6.
Pin/Remarks
SCK0 (P12)
V
[V]
min
unit
DD
Period
tSCK(3)
2
1
Low level
tSCKL(3)
pulse width
High level
pulse width
2.2 to 5.5
tCYC
tSCKH(3)
tSCKHBSY(3)
tsDI(2)
1
2
Data setup time
SI0 (P11),
SB0 (P11)
• Specified with respect to
rising edge of SIOCLK
• See Fig. 6.
0.03
0.03
2.2 to 5.5
Data hold time
thDI(2)
tdD0(3)
μs
Output
SO0 (P10),
SB0 (P11)
• (Note 4-2-2)
delay time
1tCYC
+0.05
2.2 to 5.5
Note 4-2-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-2-2: Specified with respect to the falling edge of SIOCLK. Specified as the interval up to the time an output
change begins in the open drain output mode. See Fig.6.
No.A1951-16/31
LC88F58B0A
SIO1 Serial Input/Output Characteristics (Wakeup Function Disabled) (Note 4-3-1)
Specification
Applicable
Parameter
Symbol
Conditions
• See Fig. 6.
Pin/Remarks
SCK1(P45)
V
[V]
min
typ
max
unit
DD
Period
tSCK(4)
4
2
2
Low level
tSCKL(4)
pulse width
High level
pulse width
tSCKH(4)
tSCKHA(4)
• Automatic communication
mode
6
2.2 to 5.5
• See Fig. 6.
tCYC
tSCKHBSY(4a)
tSCKHBSY(4b)
• Automatic communication
mode
23
• See Fig. 6.
• Mode other than automatic
communication mode
• See Fig. 6.
4
4
Period
tSCK(5)
SCK1(P45)
• CMOS output selected
• See Fig. 6.
Low level
tSCKL(5)
tSCKH(5)
tSCKHA(5)
1/2
1/2
pulse width
High level
pulse width
tSCK
• Automatic communication
mode
6
4
2.2 to 5.5
• CMOS output selected
• See Fig. 6.
tSCKHBSY(5a)
• Automatic communication
mode
tCYC
23
• CMOS output selected
• See Fig. 6.
tSCKHBSY(5b)
tsDI(3)
• Mode other than automatic
communication mode
• See Fig. 6.
4
0.03
0.03
Data setup time
Data hold time
SI1(P44),
SB1(P44)
• Specified with respect to rising
edge of SIOCLK
• See Fig. 6.
2.2 to 5.5
μs
thDI(3)
Output
tdD0(4)
SO1(P43),
SB1(P44)
• (Note 4-3-2)
• (Note 4-3-2)
delay time
1tCYC
+0.05
2.2 to 5.5
μs
tdDO(5)
1tCYC
+0.05
Note 4-3-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-3-2: Specified with respect to the falling edge of SIOCLK. Specified as the interval up to the time an output
change begins in the open drain output mode. See Fig. 6.
No.A1951-17/31
LC88F58B0A
SIO1 Serial Input/Output Characteristics (Wakeup Function Enabled) (Note 4-4-1)
Specification
typ max
Applicable
Parameter
Period
Symbol
tSCK(6)
Conditions
• See Fig. 6.
Pin/Remarks
SCK1(P45)
V
[V]
min
unit
DD
2
1
Low level
tSCKL(6)
2.2 to 5.5
tCYC
pulse width
High level
pulse width
tSCKH(6)
tSCKHBSY(6)
tsDI(4)
1
2
Data setup time
SI1(P44),
SB1(P44)
• Specified with respect to rising
edge of SIOCLK
0.03
0.03
• See Fig. 6.
2.2 to 5.5
Data hold time
thDI(4)
tdD0(6)
μs
Output
SO1(P43),
SB1(P44)
• (Note 4-4-2)
delay time
1tCYC
+0.05
2.2 to 5.5
Note 4-4-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-4-2: Specified with respect to the falling edge of SIOCLK. Specified as the interval up to the time an output
change begins in the open drain output mode. See Fig. 6.
SMIIC0 Simple SIO Mode Input/Output Characteristics
Specification
Applicable
Parameter
Period
Symbol
tSCK(7)
Conditions
Pin/Remarks
V
[V]
min
typ
max
unit
DD
SM0CK(P22)
SM0CK(P22)
SM0DA(P23)
See Fig. 6.
8
4
4
8
Low level
tSCKL(7)
tSCKH(7)
tSCK(8)
tSCKL(8)
tSCKH(8)
tsDI(5)
2.2 to 5.5
2.2 to 5.5
2.2 to 5.5
2.2 to 5.5
pulse width
High level
pulse width
Period
tCYC
• CMOS output selected
• See Fig. 6.
Low level
pulse width
1/2
1/2
tSCK
High level
pulse width
Data setup time
• Specified with respect to rising
edge of SIOCLK
0.03
0.03
• See Fig. 6.
Data hold time
thDI(5)
tdD0(7)
μs
Output delay
time
SM0DO(P24),
SM0DA(P23)
• Specified with respect to falling
edge of SIOCLK
1tCYC
+0.05
• Specified as interval up to time
when output state starts
changing.
• See Fig. 6.
Note 4-5-1: These specifications are theoretical values. Add margin depending on its use.
No.A1951-18/31
LC88F58B0A
SMIIC0 I2C Mode Input/Output Characteristics
Specification
Applicable
Parameter
Period
Symbol
tSCL
Conditions
Pin/Remarks
V
[V]
min
typ
max
unit
Tfilt
DD
SM0CK(P22)
• See Fig. 8.
5
Low level
tSCLL
tSCLH
tSCLx
tSCLLx
tSCLHx
tsp
2.2 to 5.5
2.5
2
pulse width
High level
pulse width
Period
SM0CK(P22)
• Specified as interval up to time
10
when output state starts changing.
Low level
pulse width
2.2 to 5.5
1/2
1/2
tSCL
Tfilt
High level
pulse width
SM0CK and SM0DA
pins input spike
suppression time
Bus release
SM0CK(P22)
SM0DA(P23)
• See Fig. 8.
• See Fig. 8.
1
tBUF
SM0CK(P22)
SM0DA(P23)
time between
start and stop
2.5
Tfilt
2.2 to 5.5
2.2 to 5.5
2.2 to 5.5
tBUFx
SM0CK(P22)
SM0DA(P23)
• Standard clock mode
• Specified as interval up to time
when output state starts changing.
• High-speed clock mode
• Specified as interval up to time
when output state starts changing.
• When SMIIC register control bit,
I2CSHDS=0
5.5
1.6
2.0
2.5
4.1
1.0
μs
Start/restart
condition hold
time
tHD;STA
SM0CK(P22)
SM0DA(P23)
• See Fig. 8.
Tfilt
• When SMIIC register control bit,
I2CSHDS=1
• See Fig. 8.
tHD;STAx
SM0CK(P22)
SM0DA(P23)
• Standard clock mode
• Specified as interval up to time
when output state starts changing.
• High-speed clock mode
• Specified as interval up to time
when output state starts changing.
• See Fig. 8.
μs
Tfilt
μs
Restart
tSU;STA
SM0CK(P22)
SM0DA(P23)
condition setup
time
1.0
tSU;STAx
SM0CK(P22)
SM0DA(P23)
• Standard clock mode
• Specified as interval up to time
when output state starts changing.
• High-speed clock mode
5.5
1.6
• Specified as interval up to time
when output state starts changing.
Continued on next page.
No.A1951-19/31
LC88F58B0A
Continued from preceding page
Specification
typ max
Applicable
Parameter
Symbol
Conditions
Pin/Remarks
V
[V]
min
unit
Tfilt
DD
Stop condition
setup time
tSU;STO
SM0CK(P22)
SM0DA(P23)
• See Fig. 8.
1.0
tSU;STOx
SM0CK(P22)
SM0DA(P23)
• Standard clock mode
2.2 to 5.5
• Specified as interval up to time
when output state starts changing.
• High-speed clock mode
4.9
1.1
μs
• Specified as interval up to time
when output state starts changing.
• See Fig. 8.
Data hold time
tHD;DAT
tHD;DATx
tSU;DAT
tSU;DATx
tF
SM0CK(P22)
SM0DA(P23)
0
1
1
2.2 to 5.5
Tfilt
SM0CK(P22)
SM0DA(P23)
• Specified as interval up to time
when output state starts changing.
1.5
Data setup time
SM0CK(P22)
SM0DA(P23)
• See Fig. 8.
2.2 to 5.5
Tfilt
SM0CK(P22)
SM0DA(P23)
• Specified as interval up to time
when output state starts changing.
1tSCL
-1.5Tfilt
SM0CK and
SM0DA pins fall
time
SM0CK(P22)
SM0DA(P23)
• See Fig. 8.
2.2 to 5.5
300
tF
SM0CK (P22)
SM0DA (P23)
• When SMIIC register control bits,
PSLW=1, P5V=1
20
+0.1Cb
20
5
3
250
250
ns
• When SMIIC register control bits,
PSLW=1, P5V=0
+0.1Cb
• SM0CK, SM0DA port output
FAST mode
3 to 5.5
100
• Cb≤400pF
Note 4-6-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-6-2: The value of Tfilt is determined by the values of the register SMIC0BRG, bits 7 and 6 (BRP1, BRP0) and
the system clock frequency.
BRP1
BRP0
Tfilt
0
0
1
1
0
1
0
1
tCYC×1
tCYC×2
tCYC×3
tCYC×4
Set bits (BPR1, BPR0) so that the value of Tfilt falls between the following range:
250ns ≥ Tfilt >140ns
Note 4-6-3: Cb represents the total loads (in pF) connected to the bus pins. Cb ≤ 400pF
Note 4-6-4: The standard clock mode refers to a mode that is entered by configuring SMIC0BRG as follows:
250ns ≥ Tfilt >140ns
BRDQ (bit5) = 1
SCL frequency setting ≤ 100kHz
The high-speed clock mode refers to a mode that is entered by configuring SMIC0BRG as follows:
250ns ≥ Tfilt >140ns
BRDQ (bit5) = 0
SCL frequency setting ≤ 400kHz
No.A1951-20/31
LC88F58B0A
UART2 Operating Conditions at Ta = -40 to +85°C, V 1 = V 2 = V 3 = 0V
SS SS SS
Specification
typ max
Applicable
Parameter
Symbol
UBR2
Conditions
Pin/Remarks
V
[V]
min
unit
DD
Transfer rate
U2RX(P16),
U2TX(P17)
2.2 to 5.5
8
4096
tBGCYC
Note 4-7: tBGCYC denotes one cycle of the baudrate clock source.
UART0 Operating Conditions at Ta = -40 to +85°C, V 1 = V 2 = V 3 = 0V
SS SS SS
Specification
typ max
Applicable
Parameter
Symbol
UBR0
Conditions
Pin/Remarks
V
[V]
min
unit
DD
Transfer rate
U0RX(P13),
U0TX(P14),
U0BRG(P07)
2.2 to 5.5
4
8
tBGCYC
Note 4-8: tBGCYC denotes one cycle of the baudrate clock source.
Pulse Input Conditions at Ta = -40 to +85°C, V 1 = V 2 = V 3 = 0V
SS
SS
SS
Specification
typ max
Applicable
Parameter
Symbol
Conditions
Pin/Remarks
min
unit
tCYC
μs
V
[V]
DD
High/low level
pulse width
tPIH(1)
tPIL(1)
INT0(P30),
INT1(P31),
INT2(P32),
INT3(P33),
INT4(P20),
INT5(P21),
INT6(P40),
INT7(P41)
RESB
• Interrupt source flag can be set.
• Event inputs for timers 2 and 3
are enabled.
2.2 to 5.5
2.2 to 5.5
2
tPIL(2)
Resetting is enabled.
10
No.A1951-21/31
LC88F58B0A
AD Converter Characteristics at Ta = -40 to +85°C, V 1 = V 2 = V 3 = 0V
SS
SS
SS
12-bit AD Conversion Mode
Specification
typ max
12
Applicable Pin
/Remarks
Parameter
Symbol
Conditions
V
[V]
min
unit
bit
DD
Resolution
NAD
AN0(P60) to
AN7(P67),
2.9 to 5.5
Absolute accuracy
Conversion time
ETAD
(Note 6-1)
2.9 to 5.5
4.7 to 5.5
4.0 to 5.5
2.9 to 5.5
±16
LSB
AN8(P70) to
AN11(P72)
TCAD12
Conversion time calculated
17
209
209
209
μs
27
67
Analog input
voltage range
Analog port
input current
VAIN
2.9 to 5.5
V
V
V
SS
DD
IAINH
IAINL
VAIN=V
DD
2.9 to 5.5
2.9 to 5.5
1
μA
VAIN=V
SS
-1
Conversion time calculation formula: TCAD12= ((52/(AD division ratio))+2) × tCYC
8-bit AD Conversion Mode
Specification
Applicable Pin
Parameter
Symbol
Conditions
/Remarks
V
[V]
min
typ
max
unit
bit
DD
Resolution
NAD
AN0(P60) to
AN7(P67),
2.9 to 5.5
2.9 to 5.5
4.7 to 5.5
4.0 to 5.5
2.9 to 5.5
8
Absolute accuracy
Conversion time
ETAD
(Note 6-1)
±1.5
LSB
AN8(P70) to
AN11(P72)
TCAD8
Conversion time calculated
11
129
129
129
μs
17
42
Analog input
voltage range
Analog port
input current
VAIN
2.9 to 5.5
V
V
V
SS
DD
IAINH
IAINL
VAIN=V
DD
2.9 to 5.5
2.9 to 5.5
1
μA
VAIN=V
SS
-1
Conversion time calculation formula: TCAD8= ((32/(AD division ratio))+2) × tCYC
Note 6-1: The quantization error (±1/2LSB) is excluded from the absolute accuracy.
Note 6-2: The conversion time refers to the interval from the time a conversion starting instruction is issued till the time
the complete digital value against the analog input value is loaded in the result register.
The conversion time is twice the normal value when one of the following conditions occurs:
• The first AD conversion is executed in the 12-bit AD conversion mode after a system reset.
• The first AD conversion is executed after the AD conversion mode is switched from 8-bit to 12-bit AD conversion
mode.
No.A1951-22/31
LC88F58B0A
Consumption Current Characteristics at Ta=-40 to +85°C, V 1=V 2=V 3=0V
SS SS SS
typ: 5.0V (V =4.5V to 5.5V), 3.3V (V =3.0V to 4.5V, 2.2V to 4.5V)
DD
DD
Specification
typ max
Applicable
Parameter
Symbol
Conditions
Pin/Remarks
V
[V]
min
unit
DD
Normal mode
consumption
current
IDDOP(1)
V
1
• FmCF=12MHz ceramic oscillation mode
• FmX'tal=32.768kHz crystal oscillation mode
• System clock set to 12MHz
DD
=V
2
3
DD
DD
=V
4.5 to 5.5
9.3
15.0
(Note 7-1)
• Internal RC oscillation stopped
• 1/1 frequency division mode
IDDOP(2)
• FmCF=10MHz ceramic oscillator mode
• FmX'tal=32.768kHz crystal oscillator mode
• System clock set to 10MHz
4.5 to 5.5
3.0 to 4.5
4.5 to 5.5
2.2 to 4.5
8.5
5.0
3.8
2.5
14.4
8.3
5.6
4.6
IDDOP(3)
IDDOP(4)
• Internal RC oscillation stopped
• 1/1 frequency division mode
mA
• FmCF=4MHz ceramic oscillator mode
• FmX'tal=32.768kHz crystal oscillator mode
• System clock set to 4MHz
IDDOP(5)
• Internal RC oscillation stopped
• 1/2 frequency division mode
IDDOP(6)
IDDOP(7)
• FmCF=0Hz (oscillation stopped)
• FmX'tal=32.768kHz crystal oscillator mode
• System clock set to internal RC oscillation
• 1/1 frequency division mode
4.5 to 5.5
2.2 to 4.5
2.5
1.7
5.6
4.6
IDDOP(8)
IDDOP(9)
IDDOP(10)
• FmCF=0Hz (oscillation stopped)
• FmX'tal=32.768kHz crystal oscillator mode
• System clock set to 32.768kHz
• Internal RC oscillation stopped
• 1/1 frequency division mode
4.5 to 5.5
2.2 to 4.5
63
39
155
102
μA
• FmCF=12MHz ceramic oscillation mode
• FmX'tal=32.768kHz crystal oscillation mode
• System clock set to 12MHz
4.5 to 5.5
11.0
17.5
• Internal RC oscillation stopped
• PLL oscillation mode
• 1/1 frequency division mode
mA
IDDOP(11)
IDDOP(12)
• FmCF=10MHz ceramic oscillation mode
• FmX'tal=32.768kHz crystal oscillation mode
• System clock set to 10MHz
4.5 to 5.5
3.0 to 4.5
10.3
5.9
17.0
13.0
• Internal RC oscillation stopped
• PLL oscillation mode
• 1/1 frequency division mode
Note 7-1: The consumption current value includes none of the currents that flow into the output transistor and internal
pull-up resistors.
Continued on next page.
No.A1951-23/31
LC88F58B0A
Continued from preceding page.
Specification
typ max
Applicable
Parameter
Symbol
Conditions
Pin/Remarks
V
[V]
min
unit
DD
HALT mode
consumption
current
IDDHALT(1)
V
1
• HALT mode
DD
=V
=V
2
3
• FmCF=12MHz ceramic mode
• FmX'tal=32.768kHz crystal oscillation mode
• System clock set to 12MHz
• Internal RC oscillation stopped
• 1/1 frequency division mode
• HALT mode
DD
DD
4.5 to 5.5
2.9
4.4
(Note 7-1)
IDDHALT(2)
• FmCF=10MHz ceramic oscillator mode
• FmX'tal=32.768kHz crystal oscillator mode
• System clock set to 10MHz
• Internal RC oscillation stopped
• 1/1 frequency division mode
• HALT mode
4.5 to 5.5
3.0 to 4.5
4.5 to 5.5
2.2 to 4.5
2.5
1.3
4.2
3.0
1.6
1.1
IDDHALT(3)
IDDHALT(4)
mA
• FmCF=4MHz ceramic oscillator mode
• FmX'tal=32.768kHz crystal oscillator mode
• System clock set to 4MHz
0.90
0.40
IDDHALT(5)
IDDHALT(6)
• Internal RC oscillation stopped
• 1/2 frequency division mode
• HALT mode
4.5 to 5.5
2.2 to 4.5
0.42
0.20
1.25
0.85
• FmCF=0Hz (oscillation stopped)
• FmX'tal=32.768kHz crystal oscillator mode
• System clock set to internal RC oscillation
• 1/1 frequency division mode
• HALT mode
IDDHALT(7)
IDDHALT(8)
• FmCF=0Hz (oscillation stopped)
• FmX'tal=32.768kHz crystal oscillator mode
• System clock set to 32.768kHz
• Internal RC oscillation stopped
• 1/1 frequency division mode
HOLD mode
4.5 to 5.5
2.2 to 4.5
23
10
90
40
μA
μA
IDDHALT(9)
HOLD mode
consumption
current
IDDHOLD(1)
IDDHOLD(2)
IDDHOLD(3)
V
1
DD
4.5 to 5.5
2.2 to 4.5
0.05
0.03
20
15
• CF1=V
DD
or open (external clock mode)
HOLDX
HOLDX mode
• CF1=V or open (external clock mode)
4.5 to 5.5
2.2 to 4.5
15
4
58
35
mode
DD
• FmX'tal=32.768kHz crystal oscillator mode
consumption
current
IDDHOLD(4)
Note 7-1: The consumption current value includes none of the currents that flow into the output transistor and internal
pull-up resistors.
No.A1951-24/31
LC88F58B0A
F-ROM Programming Characteristics at Ta = +10 to +55°C, V 1=V 2=V 3=0V
SS SS SS
Specification
typ max
Applicable
Parameter
Symbol
Conditions
Pin/Remarks
V
[V]
min
unit
mA
DD
Onboard
IDDFW(1)
V
1
• Microcontroller erase current current is
DD
programming
current
excluded.
3.0 to 5.5
5
10
Onboard
programming
time
tFW(1)
tFW(2)
• 128-/1K-byte erase operation
• 2-byte programming operation
3.0 to 5.5
3.0 to 5.5
20
40
30
60
ms
μs
Power Pin Treatment Conditions 1 (V 1, V 1)
DD SS
Connect capacitors that meet the following conditions between the V 1 and V 1 pins:
DD SS
• Connect among the V 1 and V 1 pins and the capacitors C1 and C2 with the shortest possible lead wires,
DD
SS
of the same length (L1=L1', L2=L2') wherever possible.
• Connect a large-capacity capacitor C1 and a small-capacity capacitor C2 in parallel.
The capacitance of C2 should be approximately 0.1μF or larger.
• The V 1 and V 1 traces must be thicker than the other traces.
DD SS
L2
L1
V
1
SS
C1
C2
V
1
DD
L1’
L2’
Power Pin Treatment Conditions 2 (V (2, 3), V (2, 3))
DD SS
Connect capacitors that meet the following condition between the V
DD
(2, 3) and V (2, 3) pins:
SS
• Connect among the V
DD
(2, 3) and V (2, 3) pins and the capacitor C3 with the shortest possible lead wires,
SS
of the same length (L3=L3') wherever possible.
• The capacitance of C3 should be approximately 0.1μF or larger.
• The V
(2, 3) and V (2, 3) traces must be thicker than the other traces.
DD
SS
L3
V
(2, 3)
SS
C3
V
(2, 3)
DD
L3’
No.A1951-25/31
LC88F58B0A
Characteristics of a Sample Main System Clock Oscillation Circuit
Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a
SANYO-designated oscillation characteristics evaluation board and external components with circuit constant values
with which the oscillator vendor confirmed normal and stable oscillation.
Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Resonator
Oscillation
Operating
Circuit Constant
Stabilization
Time
Nominal
Vendor
Name
Voltage
Range
[V]
Resonator
Remarks
Frequency
C3
C4
Rf
Rd2
typ
max
[pF]
[pF]
[Ω]
[Ω]
[ms]
[ms]
C1, C2
integrated type
C1, C2
12MHz
10MHz
CSTCE12M0G52-R0
CSTCE10M0G52-R0
CSTLS10M0G53-B0
CSTCE8M00G52-R0
CSTLS8M00G53-B0
CSTCR4M00G53-R0
CSTLS4M00G53-B0
(10)
(10)
(15)
(10)
(15)
(15)
(15)
(10)
(10)
(15)
(10)
(15)
(15)
(15)
OPEN
OPEN
OPEN
OPEN
OPEN
OPEN
OPEN
220
470
680
470
1k
2.4 to 5.5
2.4 to 5.5
2.6 to 5.5
2.3 to 5.5
2.5 to 5.5
2.2 to 5.5
2.3 to 5.5
0.02
0.02
0.02
0.02
0.02
0.02
0.02
0.2
0.2
0.2
0.2
0.2
0.2
0.2
integrated type
C1, C2
integrated type
C1, C2
MURATA
integrated type
C1, C2
8MHz
integrated type
C1, C2
1.5k
1.5k
integrated type
C1, C2
4MHz
integrated type
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after V
goes above the lower limit level of the operating voltage range (see Figure 4)
DD
Characteristics of a Sample Subsystem Clock Oscillator Circuit
Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a SANYO-
designated oscillation characteristics evaluation board and external components with circuit constant values with which
the oscillator vendor confirmed normal and stable oscillation.
Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Resonator
Operating
Voltage
Range
[V]
Oscillation
Circuit Constant
Nominal
Vendor
Name
Stabilization Time
Oscillator Name
Remarks
Frequency
C3
C4
Rf2
Rd2
typ
[s]
max
[s]
[pF]
[pF]
[Ω]
[Ω]
EPSON
Applicable
32.768kHz
MC-306
10
10
OPEN
0
2.2 to 5.5
0.4
2.0
TOYOCOM
CL value=7.0pF
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the
instruction for starting the subclock oscillator circuit is executed plus the time interval that is required for the oscillation
to get stabilized after the HOLD mode is released (see Figure 4).
Note: The traces to and from the components that are involved in oscillation should be kept as short as possible as the
oscillation characteristics are affected by their trace pattern.
No.A1951-26/31
LC88F58B0A
CF1
CF2
XT1
XT2
Rf1
CF
Rf2
Rd1
C2
Rd2
C4
C1
C3
X’tal
Figure 1 CF Oscillator Circuit
Figure 2 XT Oscillator Circuit
0.5V
DD
Figure 3 AC Timing Measurement Point
No.A1951-27/31
LC88F58B0A
V
DD
Operating V
lower limit
0V
DD
Power
RESB
Reset time
Internal RC
oscillation
tmsCF
CF1, CF2
XT1, XT2
tmsX'tal
Initialization instruction
execution
Operating
mode
Reset
Unpredictable
User instruction execution
Reset Time and Oscillation Stabilization Time
HOLD
release
No HOLD release signal
HOLD release signal valid
Interrupt operation
Internal RC
oscillation
tmsCF
CF1, CF2
tmsX'tal
XT1, XT2
State
HOLD
Instruction execution
HALT
HOLD Release and Oscillation Stabilization Time
Figure 4 Oscillation Stabilization Time Timing Charts
No.A1951-28/31
LC88F58B0A
V
DD
R
C
Note:
RES
Reset signal must be present when power
supply rises.
Determine the value of C
that the reset signal is present for 10μs after the
supply voltage gets stabilized.
RES
and R so
RES
RES
RES
Figure 5 Reset Circuit
tSCKHBSY
tSCKHBSY
RUN:
SIOCLK:
DATAIN:
DI0
DI1
DI6
DI7
DI8
DIx
DATAOUT:
DO0
tdDO
tdDO
DO1
DO6
DO7
DO8
DOx
Data transfer period
(SIO0 and SIO1 only)
tSCK
SIOCLK:
DATAIN:
tSCKL
tSCKH
thDI
tsDI
DATAOUT:
Data transfer period
(SIO0 and SIO1 only)
SIOCLK:
DATAIN:
tSCKL
tSCKHA
thDI
tsDI
DATAOUT:
* Remarks: DIx and DOx denote the last bits communicated; x = 0 to 32768
Figure 6 Serial I/O Waveforms
tPIL
tPIH
Figure 7 Pulse Input Timing Signal Waveform
No.A1951-29/31
LC88F58B0A
P
S
Sr
P
SDA
SCK
tBUF
tHD;STA tR
tF
tHD;STA
tsp
tLOW
tHIGH
tHD;DAT
tSU;DAT
tSU;STO
tSU;STA
S: Start condition
P: Stop condition
Sr: Restart condition
Figure 8 I2C Timing
1kΩ
PC2/FILT
+
-
2.2μF
Cfs
V
1
SS
Cfs=OPEN
Figure 9 Recommended FILT Circuit
* Take at least 50ms to oscillation to stabilize after PLL is started.
No.A1951-30/31
LC88F58B0A
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using
products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd.
products described or contained herein.
SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all
semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or
malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise
to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt
safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not
limited to protective circuits and error prevention circuits for safe design, redundant design, and structural
design.
In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are
controlled under any of applicable local export control laws and regulations, such products may require the
export license from the authorities concerned in accordance with the above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise,
without the prior written consent of SANYO Semiconductor Co.,Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the
SANYO Semiconductor Co.,Ltd. product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed
for volume production.
Upon using the technical information or products described herein, neither warranty nor license shall be granted
with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third
party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's
intellectual property rights which has resulted from the use of the technical information and products mentioned
above.
This catalog provides information as of September, 2008. Specifications and information herein are subject
to change without notice.
PS
No.A1951-31/31
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