LC895194 [SANYO]
CD-ROM Error Correction LSI with On-Chip ATA-PI (IDE) Interface; CD -ROM纠错LSI与片ATA- PI （ IDE ）接口
| 型号： | LC895194 |
| 厂家： | 
SANYO SEMICON DEVICE |
| 描述： | CD-ROM Error Correction LSI with On-Chip ATA-PI (IDE) Interface |
| 文件： | 总7页 (文件大小：87K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : EN*5154B
CMOS LSI
LC895194
CD-ROM Error Correction LSI
with On-Chip ATA-PI (IDE) Interface
Preliminary
Functions
CD-ROM error detection and correction, ATA-PI (IDE)
interface (including the register and other blocks)
Package Dimensions
unit: mm
3214-SQFP144
Features
[LC895194]
• ATA-PI (IDE) interface
• Supports 16×-speed playback (with IORDY): Using 16×
70 ns DRAMs
• 16.6 MB/s transfer rate: Using 16× 70 ns DRAMs
• Supports the use of from 1 M to 32 M of buffer RAM.
(DRAM)
• Allows the user to arbitrarily set the CD main channel
and C2 flag areas in buffer RAM.
• Batch transfer function (function for transferring the CD
main channel and C2 flag data in one operation)
• Multi-transfer function (function for sending multiple
blocks in one operation)
SANYO: SQFP144
Specifications
Absolute Maximum Ratings at V = 0 V
SS
Parameter
Maximum supply voltage
Symbol
Conditions
Ratings
Unit
V
V
max Ta = 25°C
–0.3 to +7.0
DD
I/O voltages
V , V
I
Ta = 25°C
–0.3 to V
+ 0.3
550
V
O
DD
Allowable power dissipation
Operating temperature
Storage temperature
Pd max
Topr
Ta ≤ 70°C
mW
°C
°C
°C
mA
–30 to +75
–55 to +125
235
Tstg
Soldering heat resistances (pins only)
I/O power
10 seconds
I , I
±20*
I
O
Note: * Per cell for basic I/O cells
Allowable Operating Ranges at Ta = –30 to +75°C, V = 0 V
SS
Parameter
Supply voltage
Input voltage range
Symbol
Conditions
min
4.5
0
typ
5.0
max
5.5
Unit
V
V
DD
V
V
V
IN
DD
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
N3097HA(OT) /81095HA (OT) No. 5154-1/7
LC895194
DC Characteristics at V = 0 V, V = 4.5 to 5.5 V, Ta = –30 to +75°C
SS
DD
Parameter
Input high level voltage
Input low level voltage
Input high level voltage
Input low level voltage
Input high level voltage
Input low level voltage
Input high level voltage
Input low level voltage
Input high level voltage
Input low level voltage
Output high level voltage
Output low level voltage
Output high level voltage
Output low level voltage
Output high level voltage
Output low level voltage
Output high level voltage
Output low level voltage
Output low level voltage
Output low level voltage
Input leakage current
Output leakage current
Pull-up resistance
Symbol
Applicable Pins* (See below)
min
typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
80
80
max
Unit
V
V
2.2
—
—
IH
TTL compatible: (1)
V
IL
0.8
—
V
V
2.2
—
V
IH
TTL compatible, with pull-up resistor: (13)
TTL compatible, with pull-down resistor: (2)
TTL compatible, Schmitt: (3), (5), and (14)
COMS compatible, Schmitt: (4)
V
IL
0.8
—
V
V
2.2
—
V
IH
V
IL
0.8
—
V
V
2.4
—
V
IH
V
IL
0.8
—
V
V
0.8 V
V
IH
DD
—
V
IL
0.2 V
V
DD
—
V
I
I
I
I
I
I
I
I
I
I
= –2 mA
= 2 mA
= –8 mA
= 8 mA
= 4 mA
= 24 mA
= –2 mA
= 2 mA
= 2 mA
= 24 mA
V
V
V
V
– 2.1
—
V
OH
OH
OL
OH
OL
OH
OL
OH
OL
OL
OL
DD
DD
DD
DD
(8), (10), and (13)
V
0.4
—
V
OL
V
– 2.1
—
V
OH
(7)
V
0.4
—
V
OL
V
– 2.1
—
V
OH
(9), and (14)
(6)
V
0.4
—
V
OL
V
– 2.1
—
V
OH
V
0.4
0.4
0.4
+10
+10
160
160
V
OL
V
(11)
(12)
—
V
OL
V
—
V
OL
I
V = V , V : (1), (3), (4), (9), and (14)
–10
–10
40
µA
µA
kΩ
kΩ
IL
I
SS DD
I
For high-impedance outputs: (6), (12), and (14)
OZ
R
(13)
UP
Pull-down resistance
R
(2), (5)
40
DN
Input voltage hysteresis
V
HYS
(3), and (14)
0.8
1.0
1.3
mV
Note: * The entries in the “Applicable Pins” column specify the following pin sets.
[Input]
1: CSCTRL, SUA0 to SUA6
2: TEST0 to TEST4
3: DA0 to DA2, ZCS1FX, ZCS3FX, ZDIOR, ZDIOW, ZDMACK, ZHRST, ZRESET, BCK, C2PO, LRCK, SDATA
4: ZCS, ZRD, ZWR
5: WFCK, SCOR
[Output]
6: ZINT1
7: MCK, MCK2
8: ZINT, ZSWAIT
9: DMARQ, HINTRQ
10: RA0 to RA9, ZCAS0, ZCAS1, ZLWE, ZOE, ZRAS0, ZRAS1, ZUWE
11: ZRSTCPU, ZRSTIC
12: IORDY, ZIOCS16
[I/O]
13: D0 to D7, IO0 to IO15
14: DD0 to DD15, ZDASP, ZPDIAG
Note: XTAL, XTALCK
The above pins are not included in the DC characteristics.
Sample Recommended Oscillator Circuit
R1 = 120 kΩ
R2 = 47 kΩ
C1 = 30 pF
For a crystal oscillator frequency of 16.9344 MHz.
Alternatively:
R1 = 3.3 kΩ
R2 = None
C1 = 5 pF
For a crystal oscillator frequency of 33.8688 MHz.
For an oscillator frequency of 33.8688, the third harmonic is used. This means that
precise component values will be influenced by the printed circuit board. Consult
the manufacturer of the crystal to determine the circuit constants for this frequency.
No. 5154-2/7
LC895194
Block Diagram
Each block
register
R0 to R99
Note: 1. WFCK, SCOR
2. BCK, SDATA, LRCK, C2PO
3. DD0 to DD15, ZDASP, ZPDIAG
4. ZCS1FX, ZCS3FX, DA0 to DA2, ZDIOR, ZDIOW, ZDMACK
5. DMARQ, HINTRQ, ZIOCS16, IORDY, ZHRST
6. ZRD, ZWR, SUA0 to SUA6, ZCS, CSCTRL
7. D0 to D7
8. IO0 to IO15
9. RA0 to RA9, ZRAS0, ZRAS1, ZCAS0, ZCAS1, ZOE, ZUWE, ZLWE
Note: HISIDE (WD25C32) is made by WESTERN DIGITAL.
No. 5154-3/7
LC895194
Pin Functions
Type: I: Input pin, O: Output pin, B: Bidirectional pin, P: Power supply pin, NC: No connection pin
Function
Pin No.
1
Symbol
Type
P
V
SS
0
2
ZRAS0
ZRAS1
V
O
O
P
Buffer DRAM RAS signal output 0 (This pin is used normally.)
3
Buffer DRAM RAS signal output 1
4
SS
0
5
ZCAS0
ZCAS1
V
O
O
P
Buffer DRAM CAS signal output 0 (This pin is used normally.)
Buffer DRAM CAS signal output 1
6
7
SS
0
8
ZOE
ZUWE
ZLWE
RA0
O
O
O
O
O
O
O
O
O
O
P
Buffer RAM output enable
9
Buffer RAM upper write enable
Buffer RAM lower write enable
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
RA1
RA2
RA3
RA0 to RA9 are the data buffer DRAM address lines.
RA4
RA5
RA6
V
DD
V
P
SS
0
RA7
RA8
RA9
O
O
O
NC
NC
NC
NC
NC
NC
NC
B
RA0 to RA9 are the data buffer DRAM address lines.
TEST0
TEST1
TEST2
TEST3
Test pins.
IO0
IO1
IO2
IO3
IO4
IO5
V
B
B
Data buffer RAM data I/O
These pins have built-in pull-up resistors.
B
B
B
P
SS
0
V
P
DD
IO6
B
IO7
IO8
B
B
IO9
B
IO10
IO11
IO12
IO13
IO14
IO15
EXCK
WFCK
SBSO
SCOR
B
Data buffer RAM data I/O
These pins have built-in pull-up resistors.
B
B
B
B
B
O
I
SUB-CODE input/out pin
I
I
Note: 1. NC (no connection) pins must be left open.
2. Pin names (signal names) that begin with a Z have negative (inverted) logic.
3. V
is the logic system ground and V
is the IDE interface driver ground.
SS0
SS1
Continued on next page.
No. 5154-4/7
LC895194
Continued from preceding page.
Type: I: Input pin, O: Output pin, B: Bidirectional pin, P: Power supply pin, NC: No connection pin
Function
Pin No.
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Symbol
V
Type
P
P
I
SS
SS
0
0
V
TEST4
V
Test input. This pin must be tied low.
P
P
O
P
P
P
NC
NC
P
I
SS
SS
0
0
V
ZINT1
V
Interrupt request signal output to the microcontroller from the IDE block
SS
SS
SS
0
0
0
V
V
V
SS
0
SDATA
BCK
I
CD-DSP interface
LRCK
C2PO
MCK2
V
I
I
O
P
I
XTALCK 1/1, 1/2, 1/512, and stop output
SS
0
XTALCK
XTAL
V
Crystal oscillator input
Crystal oscillator output
O
P
P
O
P
O
I
SS
0
V
DD
MCK
XTALCK 1/1, 1/2, and stop output
V
SS
0
ZRSTIC
CSCTRL
ZRESET
ZRD
Reset signal to drive reset IC
Selects active high or active low for the microcontroller CS line.
LSI reset
I
I
Microcontroller data read signal input
Microcontroller data write signal input
Input for the register chip select signal from the microcontroller
ZWR
I
ZCS
I
V
P
I
SS
0
SUA0
SUA1
SUA2
SUA3
SUA4
SUA5
SUA6
I
I
I
Microcontroller register select signals
I
I
I
V
P
P
B
B
B
B
B
B
B
B
O
DD
V
SS
0
D0
D1
D2
D3
D4
D5
D6
D7
Microcontroller data signals
These pins have built-in pull-up resistors.
ZINT
Interrupt request signal output to the microcontroller
Note: 1. NC (no connection) pins must be left open.
2. Pin names (signal names) that begin with a Z have negative (inverted) logic.
3. V
is the logic system ground and V
is the IDE interface driver ground.
SS0
SS1
Continued on next page.
No. 5154-5/7
LC895194
Continued from preceding page.
Type: I: Input pin, O: Output pin, B: Bidirectional pin, P: Power supply pin, NC: No connection pin
Function
Pin No.
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
Symbol
ZRSTCPU
ZSWAIT
ZHRST
ZDASP
ZCS3FX
ZCS1FX
DA2
Type
O
O
I
Reset signal to CPU
Wait signal output to the microcontroller
B
I
ATAPI control signals
I
I
V
P
P
I
SS
0
V
DD
DA0
ZPDIAG
DA1
B
I
ATAPI control signals
ZIOCS16
HINTRQ
ZDMACK
V
O
O
I
P
O
I
SS
1
IORDY
ZDIOR
ZDIOW
DMARQ
DD15
V
ATAPI control signals
ATAPI data bus
I
O
B
P
B
B
B
B
P
P
B
B
B
P
B
B
B
P
P
B
B
B
P
B
B
P
SS
1
DD0
DD14
DD1
DD13
V
ATAPI data bus
SS
1
V
DD
DD2
DD12
DD3
V
ATAPI data bus
ATAPI data bus
SS
1
DD11
DD4
DD10
V
SS
1
V
DD
DD5
DD9
DD6
ATAPI data bus
ATAPI data bus
V
SS
1
DD8
DD7
V
DD
Note: 1. NC (no connection) pins must be left open.
2. Pin names (signal names) that begin with a Z have negative (inverted) logic.
3. V
is the logic system ground and V
is the IDE interface driver ground.
SS
1
SS
0
No. 5154-6/7
LC895194
■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace
equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of
which may directly or indirectly cause injury, death or property loss.
■ Anyone purchasing any products described or contained herein for an above-mentioned use shall:
➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and
distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all
damages, cost and expenses associated with such use:
➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on
SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees
jointly or severally.
■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for
volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied
regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of November, 1997. Specifications and information herein are subject to
change without notice.
No. 5154-7/7
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