S1C62N33D [SEIKO]
4-BIT, MROM, 0.032768MHz, MICROCONTROLLER, UUC86, DIE-86;
| 型号： | S1C62N33D |
| 厂家： | 
SEIKO EPSON CORPORATION |
| 描述： | 4-BIT, MROM, 0.032768MHz, MICROCONTROLLER, UUC86, DIE-86 |
| 文件： | 总280页 (文件大小：1603K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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MF633 04
-
CMOS 4 BIT SINGLE CHIP MICROCOMPUTER
S1C62N33
Technical Manual
S1C62N33 Technical Hardware/S1C62N33 Technical Software
NOTICE
No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko
Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any
liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or
circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such
as medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there
is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright
infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic
products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from
the Ministry of International Trade and Industry or other approval from another government agency.
© SEIKO EPSON CORPORATION 2001 All rights reserved.
PREFACE
Th is m an u al is in dividu aly described abou t th e h ardware an d th e software
of th e S1C62N33.
I. S1C62N33 Technical Hardware
Th is part explain s th e fu n ction of th e S1C62N33, th e circu it con figu -
ration s, an d details th e con trollin g m eth od.
II. S1C62N33 Technical Software
Th is part explain s th e program m in g m eth od of th e S1C62N33.
The information of the product number change
Starting April 1, 2001, the product number will be changed as listed below. To order from April 1,
2001 please use the new product number. For further information, please contact Epson sales
representative.
Configuration of product number
Devices
S1
C
60N01
F
0A01
00
00
Packing specification
Specification
Package (D: die form; F: QFP)
Model number
Model name (C: microcomputer, digital products)
Product classification (S1: semiconductor)
Development tools
S5U1
C
60R08 D1
1
Packing specification
2
Version (1: Version 1
)
1
)
Tool type (D1: Development Tool
Corresponding model number (60R08: for S1C60R08)
Tool classification (C: microcomputer use)
Product classification
(S5U1: development tool for semiconductor products)
1: For details about tool types, see the tables below. (In some manuals, tool types are represented by one digit.)
2: Actual versions are not written in the manuals.
Comparison table between new and previous number
S1C60 Family processors
S1C62 Family processors
Previous No.
E0C6001
E0C6002
E0C6003
E0C6004
E0C6005
E0C6006
E0C6007
E0C6008
E0C6009
E0C6011
E0C6013
E0C6014
E0C60R08
New No.
S1C60N01
S1C60N02
S1C60N03
S1C60N04
S1C60N05
S1C60N06
S1C60N07
S1C60N08
S1C60N09
S1C60N11
S1C60N13
S1C60140
S1C60R08
Previous No.
E0C621A
E0C6215
E0C621C
E0C6S27
E0C6S37
E0C623A
E0C623E
E0C6S32
E0C6233
E0C6235
E0C623B
E0C6244
E0C624A
E0C6S46
New No.
S1C621A0
S1C62150
S1C621C0
S1C6S2N7
S1C6S3N7
S1C6N3A0
S1C6N3E0
S1C6S3N2
S1C62N33
S1C62N35
S1C6N3B0
S1C62440
S1C624A0
S1C6S460
Previous No.
E0C6247
E0C6248
E0C6S48
E0C624C
E0C6251
E0C6256
E0C6292
E0C6262
E0C6266
E0C6274
E0C6281
E0C6282
E0C62M2
E0C62T3
New No.
S1C62470
S1C62480
S1C6S480
S1C624C0
S1C62N51
S1C62560
S1C62920
S1C62N62
S1C62660
S1C62740
S1C62N81
S1C62N82
S1C62M20
S1C62T30
Comparison table between new and previous number of development tools
Development tools for the S1C60/62 Family
Previous No.
ASM62
New No.
Previous No.
DEV6262
DEV6266
DEV6274
DEV6292
DEV62M2
DEV6233
DEV6235
DEV6251
DEV6256
DEV6281
DEV6282
DEV6S27
DEV6S32
DEV6S37
EVA6008
EVA6011
EVA621AR
EVA621C
EVA6237
EVA623A
New No.
Previous No.
EVA623B
EVA623E
EVA6247
EVA6248
EVA6251R
EVA6256
EVA6262
EVA6266
EVA6274
EVA6281
EVA6282
EVA62M1
EVA62T3
EVA6S27
EVA6S32R
ICE62R
New No.
S5U1C62000A
S5U1C60N01D
S5U1C60N02D
S5U1C60N03D
S5U1C60N04D
S5U1C60N05D
S5U1C60N06D
S5U1C60N07D
S5U1C60N08D
S5U1C60N09D
S5U1C60N11D
S5U1C60R08D
S5U1C621A0D
S5U1C621C0D
S5U1C623B0D
S5U1C62440D
S5U1C624A0D
S5U1C624C0D
S5U1C62480D
S5U1C62470D
S5U1C62620D
S5U1C62660D
S5U1C62740D
S5U1C62920D
S5U1C62M20D
S5U1C62N33D
S5U1C62N35D
S5U1C62N51D
S5U1C62560D
S5U1C62N81D
S5U1C62N82D
S5U1C6S2N7D
S5U1C6S3N2D
S5U1C6S3N7D
S5U1C60N08E
S5U1C60N11E
S5U1C621A0E2
S5U1C621C0E
S5U1C62N37E
S5U1C623A0E
S5U1C623B0E
S5U1C623E0E
S5U1C62470E
S5U1C62480E
S5U1C62N51E1
S5U1C62N56E
S5U1C62620E
S5U1C62660E
S5U1C62740E
S5U1C62N81E
S5U1C62N82E
S5U1C62M10E
S5U1C62T30E
S5U1C6S2N7E
S5U1C6S3N2E2
S5U1C62000H
S5U1C60N03K
S5U1C60N04K
S5U1C60N07K
DEV6001
DEV6002
DEV6003
DEV6004
DEV6005
DEV6006
DEV6007
DEV6008
DEV6009
DEV6011
DEV60R08
DEV621A
DEV621C
DEV623B
DEV6244
DEV624A
DEV624C
DEV6248
DEV6247
KIT6003
KIT6004
KIT6007
S1C62N33
I. Technical Hardware
CONTENTS
CONTENTS
CHAPTER 1
OVERVIEW........................................................................ I-1
1.1 Configuration .................................................................... I-1
1.2 Features ........................................................................... I-2
1.3 Block Diagram .................................................................. I-3
1.4 Pin Layout Diagram .......................................................... I-4
1.5 Pin Description ................................................................. I-5
CHAPTER 2
POWER SUPPLY AND INITIAL RESET ................................. I-6
2.1 Power Supply ................................................................... I-6
2.2 Initial Reset....................................................................... I-7
Oscillation detection circu it ....................................... I-8
Reset term in al (RESET) ............................................. I-8
Sim u ltan eou s h igh in pu t to in pu t ports (K00–K03) .... I-8
Watch dog tim er ......................................................... I-9
In tern al register at in itial settin g .............................. I-10
2.3 Test Terminal (TEST) ...................................................... I-10
CHAPTER 3
CPU, ROM, RAM ............................................................. I-11
3.1 CPU ................................................................................. I-11
3.2 ROM ................................................................................ I-11
3.3 RAM ................................................................................ I-12
S1C62N33 TECHNICAL HARDWARE
EPSON
I-i
CONTENTS
CHAPTER 4
PERIPHERAL CIRCUITS AND OPERATION ....................... I-13
4.1 Memory Map ................................................................... I-13
4.2 Resetting Watchdog Timer .............................................. I-19
Con figu ration of watch dog tim er ............................... I-19
Mask option ............................................................. I-19
Con trol of watch dog tim er ........................................ I-20
Program m in g n ote .................................................... I-20
4.3 Oscillation Circuit............................................................. I-21
OSC1 oscillation circu it ............................................ I-21
OSC3 oscillation circu it ............................................ I-21
Con figu ration of oscillation circu it ............................ I-23
Con trol of oscillation circu it ..................................... I-24
Program m in g n otes .................................................. I-25
4.4 Input Ports (K00–K03, K10) ............................................ I-26
Con figu ration of in pu t ports ..................................... I-26
Differen tial registers an d in terru pt fu n ction .............. I-27
Mask option ............................................................. I-29
Con trol of in pu t ports ............................................... I-30
Program m in g n otes .................................................. I-32
4.5 Output Ports (R00–R03, R10–R13) ................................ I-34
Con figu ration of ou tpu t ports ................................... I-34
Mask option ............................................................. I-35
Con trol of ou tpu t ports ............................................. I-38
Program m in g n ote .................................................... I-40
4.6 I/O Ports (P00–P03, P10–P13) ....................................... I-41
Con figu ration of I/ O ports ........................................ I-41
I/ O con trol register an d I/ O m ode ............................ I-42
Mask option ............................................................. I-42
Con trol of I/ O ports .................................................. I-43
Program m in g n otes .................................................. I-45
I-ii
EPSON
S1C62N33 TECHNICAL HARDWARE
CONTENTS
4.7 LCD Driver (COM0–COM3, SEG0–SEG39) ................... I-46
Con figu ration of LCD driver ...................................... I-46
Switch in g between dyn am ic an d static drive ............. I-49
Mask option (segm en t allocation ).............................. I-50
Con trol of LCD driver ............................................... I-52
Program m in g n otes .................................................. I-53
4.8 Clock Timer ..................................................................... I-54
Con figu ration of clock tim er ..................................... I-54
In terru pt fu n ction .................................................... I-55
Con trol of clock tim er ............................................... I-56
Program m in g n otes .................................................. I-58
4.9 Stopwatch Counter .......................................................... I-59
Con figu ration of stopwatch cou n ter .......................... I-59
Cou n t-u p pattern ..................................................... I-60
In terru pt fu n ction .................................................... I-61
Con trol of stopwatch cou n ter ................................... I-62
Program m in g n otes .................................................. I-65
4.10 Event Counter ................................................................. I-66
Con figu ration of even t cou n ter ................................. I-66
Operation of even t cou n ter ....................................... I-65
Mask option ............................................................. I-67
Con trol of even t cou n ter ........................................... I-67
Program m in g n ote .................................................... I-68
4.11 Analog Comparator ......................................................... I-69
Con figu ration of an alog com parator .......................... I-69
Operation of an alog com parator ............................... I-69
Con trol of an alog com parator ................................... I-70
Program m in g n otes .................................................. I-70
S1C62N33 TECHNICAL HARDWARE
EPSON
I-iii
CONTENTS
4.12 Supply Voltage Detection (SVD) Circuit
and Heavy Load Protection Function .............................. I-71
Con figu ration of SVD circu it ..................................... I-71
Heavy load protection fu n ction (S1C62L33) .............. I-72
Detection tim in g of SVD circu it ................................ I-73
Con trol of SVD circu it .............................................. I-75
Program in g n otes ..................................................... I-77
4.13 Serial Interface (SIN, SOUT, SCLK, SIOF) ..................... I-78
Con figu ration of serial in terface ................................ I-78
Master m ode an d slave m ode of serial in terface ........ I-79
Data in pu t/ ou tpu t an d in terru pt fu n ction ................ I-81
Mask option ............................................................. I-85
Con trol of serial in terface ......................................... I-86
Program in g n otes ..................................................... I-90
4.14 Interrupt and HALT .......................................................... I-91
In terru pt factors ....................................................... I-93
Specific m asks an d factor flags for in terru pt ............. I-94
In terru pt vectors ...................................................... I-95
Con trol of in terru pt an d HALT .................................. I-96
Program m in g n otes .................................................. I-99
CHAPTER 5
SUMMARY OF NOTES..................................................... I-100
5.1 Notes for Low Current Consumption .............................. I-100
5.2 Summary of Notes by Function ...................................... I-101
CHAPTER 6
DIAGRAM OF BASIC
EXTERNAL CONNECTIONS ............................................ I-108
I-iv
EPSON
S1C62N33 TECHNICAL HARDWARE
CONTENTS
CHAPTER 7
ELECTRICAL CHARACTERISTICS .................................... I-111
7.1 Absolute Maximum Rating ............................................. I-111
7.2 Recommended Operating Conditions ............................ I-112
7.3 DC Characteristics ......................................................... I-113
7.4 Analog Circuit Characteristics
and Consumed Current .................................................. I-115
7.5 Oscillation Characteristics .............................................. I-121
CHAPTER 8
CHAPTER 9
PACKAGE ...................................................................... I-125
8.1 Plastic Package .............................................................. I-125
8.2 Ceramic Package for Test Samples ............................... I-126
PAD LAYOUT .................................................................. I-127
9.1 Diagram of Pad Layout................................................... I-127
9.2 Pad Coordinates............................................................. I-128
S1C62N33 TECHNICAL HARDWARE
EPSON
I-v
CHAPTER 1: OVERVIEW
CHAPTER 1
OVERVIEW
Th e S1C62N33 Series is a sin gle-ch ip m icrocom pu ter m ade
u p of th e 4-bit core CPU S1C6200, ROM (3,072 words, 12
bits to a word), RAM (256 words, 4 bits to a word) LCD
driver circu it, an alog com parator, even t cou n ter, serial
in terface, watch dog tim er, an d two types of tim e base cou n -
ter. Becau se of its low-voltage operation an d low power
con su m ption , th is series is ideal for a wide ran ge of applica-
tion s, an d is especially su itable for battery-driven system s.
1.1 Config ura tion
Th e S1C62N33 Series is con figu red as follows, depen din g on
su pply voltage an d oscillation circu its.
Model
Supply Voltage
Oscillation
Circuits
S1C62N33
3.0 V
S1C62L33
1.5 V
S1C62A33
3.0 V
OSC1 on ly
(Sin gle Clock)
OSC1 on ly
(Sin gle Clock)
OSC1 an d OSC3
(Twin Clock)
S1C62N33 TECHNICAL HARDWARE
EPSON
I-1
CHAPTER 1: OVERVIEW
1.2 Fe a ture s
S1C62N33
S1C62L33
S1C62A33
OSC1 oscillation circu it
OSC3 oscillation circu it
Crystal oscillation circu it 32,768 Hz (Typ.)
No settin g
CR or ceram ic oscillation
circu it (selected by m ask
option ) 500 kHz (Typ.)
In stru ction sets
108 types
In stru ction execu tion tim e
(differs depen din g on in stru ction )
(CLK: CPU operation frequ en cy)
ROM capacity
153 µs, 214 µs, 366 µs (CLK = 32,768 Hz)
10 µs, 14 µs, 24 µs
(CLK = 500 kHz)
3,072 words, 12 bits per word
256 words, 4 bits per word
RAM capacity
In pu t ports
5 bits (pu ll-down resistor can be added th rou gh m ask option )
8 bits (BZ, BZ, FOUT ou tpu ts are available th rou gh m ask option )
8 bits (pu ll-down resistor is added du rin g in pu t data read-ou t)
1 port (serial 8 bits, clock syn ch ron ized)
Ou tpu t ports
In pu t/ ou tpu t ports
Serial in terface
LCD driver
Eith er 40 segm en ts x 4 or 3 com m on (selected th rou gh m ask option )
V-3V 1/ 4 or 1/ 3 du ty (regu lated voltage circu t an d booster voltage circu it bu ilt-in )
Two types (tim er an d stopwatch )
Tim e base cou n ter
Watch dog tim er
Bu ilt-in (can be disabled th rou gh m ask option )
On e 8-bit in pu ts
Even t cou n ter
An alog com parator
Su pply voltage detection circu it (SVD)
Extern al in terru pt
In tern al in terru pt
In verted in pu t x 1, n on in verted in pu t x 1
2.4 V
1.2 V
2.4 V
In pu t port in terru pt; du al system
Tim e base cou n ter in terru pt; du al system
Serial in terface in terru pt; sin gle system
Su pply voltage
3.0 V (1.8–3.5 V)
1.5 V (0.9–1.7 V)
3.0 V (2.2–3.5 V)
2.0 µA
Con su m ed
cu rren t
CLK = 32,768 Hz
(wh en h alted)
1.5 µA
1.0 µA
CLK = 32,768 Hz
(wh en execu ted)
CLK = 500 kHz
(wh en execu ted)
6.0 µA
–
3.0 µA
–
8.0 µA
135 µA
(Typ. valu e)
Form wh en sh ipped
100-pin QFP (plastic) or ch ip
I-2
EPSON
S1C62N33 TECHNICAL HARDWARE
CHAPTER 1: OVERVIEW
1.3 Bloc k Dia g ra m
ROM
System Reset
Control
OSC
3,072 words x 12 bits
Core CPU S1C6200
RAM
256 words x 4 bits
Interrupt
Generator
COM0~3
SEG0~39
K00~03, K10
TEST
LCD Driver
Input Port
I/O Port
P00~03, P10~13
R00~03, R10~13
V
DD
V
L1~3
Power
Controller
Output Port
Comparator
CA~CC
VS1
AMPP
AMPM
VSS
Timer
SVD
Stop Watch
SIN
Event
Counter
SOUT
SCLK
SIOF
Serial Interface
Fig. 1.3
Block diagram
S1C62N33 TECHNICAL HARDWARE
EPSON
I-3
CHAPTER 1: OVERVIEW
1.4 Pin La yout Dia g ra m
80
51
QFP5-100pin
81
50
Index
100
31
1
30
Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name
1
N.C.
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
SEG38
SEG39
N.C.
AMPP
N.C.
AMPM
K10
K03
K02
K01
K00
P03
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
N.C.
N.C.
N.C.
N.C.
R11
R10
R13
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
SIOF
2
N.C.
SCLK
N.C.
3
TEST
4
N.C.
N.C.
5
N.C.
N.C.
6
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SOUT
SIN
7
8
V
SS
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
9
RESET
OSC4
OSC3
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
V
S1
P02
OSC2
OSC1
P01
P00
V
V
V
V
DD
L3
L2
L1
P13
P12
P11
P10
CC
R03
CB
R02
CA
N.C.
R01
COM3
COM2
COM1
COM0
R00
Fig. 1.4
Pin layout diagram
R12
N.C.=No Connection
I-4
EPSON
S1C62N33 TECHNICAL HARDWARE
CHAPTER 1: OVERVIEW
1.5 Pin De sc rip tion
Table 1.5 Pin description
Pin Name Pin Number Input/output
Function
Power source positive terminal
Power source negative terminal
V
V
V
V
V
V
DD
SS
S1
L1
L2
L3
65
(I)
(I)
–
58
62
Constant voltage output terminal for oscillation
Constant voltage output terminal for LCD (approx. -1.05 V)
Booster output terminal for LCD (VL1 × 2)
Booster output terminal for LCD (VL1 × 3)
Booster condenser connector terminal
Crystal oscillator input terminal
Crystal oscillator output terminal
*1
68
–
67
–
66
–
CA–CC
OSC1
OSC2
OSC3
OSC4
K00–10
P00–13
R00–03
R10
69–71
–
64
I
63
O
I
61
60
O
I
*2
32–36
Input terminal
37–44
I/O
O
O
O
O
O
I
Input/output terminal
45, 46, 48, 49
Output terminal
56
57
55
50
29
31
Output terminal (Can output BZ through mask option.)
Output terminal (Can output BZ through mask option.)
Output terminal
R13
R11
R12
Output terminal (Can output FOUT through mask option.)
Analog comparator noninverted input terminal
Analog comparator inverted input terminal
LCD segment output terminal
AMPP
AMPM
I
SEG0–39 6–27, 83–100
O
(DC output available through mask option.)
LCD common output terminal
COM0–3
SIN
72–75
82
O
I
Serial interface input terminal
SOUT
SCLK
SIOF
81
O
I/O
O
I
Serial interface output terminal
Serial interface clock input/output terminal
Serial interface output terminal
Initial setting input terminal
77
76
RESET
TEST
59
3
I
Test input terminal
*1 62N33/ 62L33 : Not con n ected
62A33 : CR or ceram ic oscillation in pu t term in al
(Switch able th rou gh m ask option .)
*2 62N33/ 62L33 : Not con n ected
62A33 :
CR or ceram ic oscillation ou tpu t term in al
(Switch able th rou gh m ask option .)
S1C62N33 TECHNICAL HARDWARE
EPSON
I-5
CHAPTER 2: POWER SUPPLY AND INITIAL RESET
CHAPTER 2
POWER SUPPLY AND
INITIAL RESET
2.1 Powe r Sup p ly
With a sin gle extern al power su pply (*1) su pplied to VDD
th rou gh VSS, th e S1C62N33 Series gen erates th e n ecessary
in tern al voltage with th e regu lated voltage circu it (<VS1> for
oscillators, <VL1> for LCDs) an d th e voltage booster circu it
(<VL2, VL3> for LCDs).
Figu re 2.1 sh ows th e con figu ration of power su pply.
*1 Su pply voltage: 62N33/ 62A33 .. 3 V, 62L33 .. 1.5 V
Note
- External loads cannot be driven by the regulated voltage and
voltage booster circuit's output voltage.
- See "7 ELECTRICAL CHARACTERISTICS" for voltage values.
V
DD
Internal
circuit
V
S1
Oscillation system
regulated voltage
circuit
VS1
Oscillation
circuit
OSC1–4
LCD system regulated
voltage circuit
V
L1
V
L1
V
L1
V
V
CA
CB
CC
L2
L3
LCD system
voltage
booster circuit
COM0–3
SEG0–39
LCD driver
circuit
V
V
L2
L3
External
power
supply
V
SS
Fig. 2.1
Configuration of
power supply
I-6
EPSON
S1C62N33 TECHNICAL HARDWARE
CHAPTER 2: POWER SUPPLY AND INITIAL RESET
2.2 Initia l Re se t
To in itialize th e S1C62N33 Series circu its, in itial reset m u st
be execu ted. Th ere are fou r ways of doin g th is.
(1) In itial reset by th e oscillation detection circu it
(2) Extern al in itial reset by th e RESET term in al
(3) Extern al in itial reset by sim u ltan eou s h igh in pu t to
term in als K00–K03
(4) In itial reset by watch dog tim er
Figu re 2.2 sh ows th e con figu ration of th e in itial reset circu it.
OSC1
OSC1
OSC2
Oscillation
circuit
Oscillation
detection
circuit
K00
K01
K02
K03
Watchdog
Initial
timer
reset
Noise
Vss
rejector
Time
authorize
circuit
RESET
Vss
Fig. 2.2
Configuration of
initial reset circuit
S1C62N33 TECHNICAL HARDWARE
EPSON
I-7
CHAPTER 2: POWER SUPPLY AND INITIAL RESET
Th e oscillation detection circu it ou tpu ts th e in itial reset
Osc illa tion d e te c tion
c irc uit
sign al at power-on u n til th e crystal oscillation circu it (OSC1)
begin s oscillatin g, or wh en th is crystal oscillation circu it
(OSC1) h alts oscillatin g for som e reason .
In itial reset can be execu ted extern ally by settin g th e reset
term in al to th e h igh level. Th is h igh level m u st be m ain -
tain ed for at least 5 m s (wh en oscillatin g frequ en cy is fosc1
= 32 kHz), becau se th e in itial reset circu it con tain s a n oise
rejector circu it. Wh en th e reset term in al goes low th e CPU
begin s to operate.
Re se t te rm ina l
(RESET)
Note
When oscillation is stopped, reset input from the reset terminal
triggered by the noise reject circuit cannot be received. When
oscillation is stopped, initialization of internal circuits is triggered by
the oscillation detection circuit.
An oth er way of execu tin g in itial reset extern ally is to in pu t a
h igh sign al sim u ltan eou sly to th e in pu t ports (K00–K03)
selected with th e m ask option . Th e specified in pu t port
term in als m u st be kept h igh for at least 5 m s (wh en oscillat-
in g frequ en cy is fosc1 = 32 kHz), becau se th e in itial reset
circu it con tain s a n oise rejector circu it. Table 2.2.1 sh ows
th e com bin ation s of in pu t ports (K00–K03) th at can be
selected with th e m ask option .
Sim ulta ne ous hig h
inp ut to inp ut p orts
(K00–K03)
Table 2.2.1
A
B
C
D
Not u sed
Input port combinations
K00*K01
K00*K01*K02
K00*K01*K02*K03
I-8
EPSON
S1C62N33 TECHNICAL HARDWARE
CHAPTER 2: POWER SUPPLY AND INITIAL RESET
Wh en , for in stan ce, m ask option D (K00*K01*K02*K03) is
selected, in itial reset is execu ted wh en th e sign als in pu t to
th e fou r ports K00–K03 are all h igh at th e sam e tim e. Fu r-
th erm ore, in itial reset is also applied wh en key in pu t, wh ich
in clu des th e com bin ation of in pu t ports selected, is per-
form ed.
Fu rth er, wh en th e in pu t tim e of th e sim u ltan eou s HIGH
in pu t is tested an d fou n d to be th e sam e or m ore th an th e
defin ed tim e (1–3 sec), th e tim e test circu it th at perform s
in itial reset can be selected with th e m ask option .
If you u se th is fu n ction , m ake su re th at th e specified ports
do n ot go h igh at th e sam e tim e du rin g ordin ary operation .
Note
When oscillation is stopped, the reset triggered by the noise reject
circuit which would normally take place when the input ports are
simultaneously switched to HIGH cannot be received.
If th e CPU ru n s away for som e reason , th e watch dog tim er
will detect th is situ ation an d ou tpu t an in itial reset sign al.
See "4.2 Resettin g Watch dog Tim er" for details.
Wa tc hd og tim e r
S1C62N33 TECHNICAL HARDWARE
EPSON
I-9
CHAPTER 2: POWER SUPPLY AND INITIAL RESET
In itial reset in itializes th e CPU as sh own in th e table below.
Inte rna l re g iste r a t
initia l se tting
Table 2.2.2
Initial values
CPU Core
Signal Number of Bits Setting Value
Name
Program cou n ter step
Program cou n ter page
New page poin ter
Stack poin ter
PCS
PCP
NPP
SP
IX
IY
RP
A
8
4
4
8
9
9
4
4
4
1
1
1
1
00H
1H
1H
Un defin ed
Un defin ed
Un defin ed
Un defin ed
Un defin ed
Un defin ed
0
In dex register IX
In dex register IY
Register poin ter
Gen eral-pu rpose register A
Gen eral-pu rpose register B
In terru pt flag
B
I
Decim al flag
D
Un defin ed
Un defin ed
Un defin ed
Zero flag
Z
Carry flag
C
Peripheral Circuits
Number of Bits Setting Value
Name
RAM
256 × 4
40 × 4
–
Un defin ed
Un defin ed
*1
Segm en t data
Oth er periph eral circu it
*1 See "4.1 Mem ory Map"
2.3 Te st Te rm ina l (TEST)
Th is term in al is u sed wh en th e IC load is bein g detected.
Du rin g ordin ary operation be certain to con n ect th is term i-
n al to VSS.
I-10
EPSON
S1C62N33 TECHNICAL HARDWARE
CHAPTER 3: CPU, ROM, RAM
CHAPTER 3
CPU, ROM, RAM
3.1
CPU
Th e S1C62N33 Series em ploys th e core CPU S1C6200 for
th e CPU, so th at register con figu ration , in stru ction s an d so
forth are virtu ally iden tical to th ose in oth er fam ily proces-
sors u sin g th e S1C6200.
Refer to "S1C6200/ 6200A Core CPU Man u al" for details
abou t th e S1C6200.
Note th e followin g poin ts with regard to th e S1C62N33
Series:
(1) Th e SLEEP operation is n ot assu m ed, so th e SLP in stru c-
tion can n ot be u sed.
(2) Becau se th e ROM capacity is 3,072 words, ban k bits are
u n n ecessary an d PCB an d NBP are n ot u sed.
(3) Sin ce RAM is set for u p to 1 page, on ly th e su bordin ate 1
bit of th e page section of th e in dex register wh ich speci-
fies address is effective. (Th e 3 su perordin ate bits are
ign ored.)
3.2 ROM
Th e bu ilt-in ROM, a m ask ROM for loadin g th e program , h as
a capacity of 3,072 steps, 12 bits each . Th e program area is
12 pages (0–11), each of 256 steps (00H–FFH). After in itial
reset, th e program begin n in g address is page 1, step 00H.
Th e in terru pt vector is allocated to page 1, steps 01H–0FH.
S1C62N33 TECHNICAL HARDWARE
EPSON
I-11
CHAPTER 3: CPU, ROM, RAM
00H step
01H step
Program start address
Interrupt vector area
0 page
1 page
2 page
3 page
4 page
5 page
6 page
7 page
8 page
9 page
0FH step
10H step
10 page
11 page
FFH step
12 bits
Fig. 3.2
ROM configuration
3.3 RAM
Th e RAM, a data m em ory storin g a variety of data, h as a
capacity of 256 words, each of fou r bits. Wh en program -
m in g, keep th e followin g poin ts in m in d.
(1) Part of th e data m em ory can be u sed as stack area wh en
savin g su brou tin e calls an d registers, so be carefu l n ot to
overlap th e data area an d stack area.
(2) Su brou tin e calls an d in terru pts take u p th ree words of
th e stack area.
(3) Th e data m em ory 000H–00FH is for th e register poin ters
(RP), an d is th e addressable m em ory register area.
(4) Th e data m em ory is split in to th ree areas, 000H–06FH,
080H–09FH an d 100H–16FH, so take care wh en allocat-
in g th e data. (See "4.1 Mem ory Map" for details.)
I-12
EPSON
S1C62N33 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)
CHAPTER 4
PERIPHERAL CIRCUITS AND OPERA-
TION
Periph eral circu its (tim er, I/ O, an d so on ) of th e S1C62N33
Series are m em ory m apped, an d in terfaced with th e CPU.
Th u s, all th e periph eral circu its can be con trolled by u sin g
th e m em ory operation com m an d to access th e I/ O data
m em ory in th e m em ory m ap.
Th e followin g section s describe h ow th e periph eral circu its
operation .
4.1
Me m ory Ma p
Data m em ory of th e S1C62N33 Series h as an address space
of 360 words, of wh ich 48 words are allocated to display
m em ory an d 64 words to I/ O data m em ory.
Figu res 4.1.1 an d 4.1.2 presen t th e overall m em ory m aps of
th e S1C62N33 Series, an d Tables 4.1(a)–(c) th e periph eral
circu its' (I/ O space) m em ory m aps.
Th e I/ O data m em ory in all u n its of th e S1C62N33 Series is
con figu red in th e sam e m an n er at 070H–07FH, 170H–17FH
an d 0F0H–0FFH, 1F0H–1FFH. Th is m akes it possible to
access I/ O data m em ory with ou t switch in g data m em ory
pages.
S1C62N33 TECHNICAL HARDWARE
EPSON
I-13
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)
Address
Page
Low
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
High
0
M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF
1
2
3
RAM (112 words x 4 bits)
R/W
4
5
6
I/O data memory Tables 4.1(a), (b)
7
0
8
RAM (32 words x 4 bits)
R/W
9
A
B
C
D
E
F
Unused area
I/O data memory Table 4.1(c)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
RAM (112 words x 4 bits)
R/W
I/O data memory Tables 4.1(a), (b)
1
Unused area
Fig. 4.1.1
Memory map
I/O data memory Table 4.1(c)
I-14
EPSON
S1C62N33 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)
Address
Page
0
Low
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
High
Fig. 4.1.2
Memory map
4 or C
5 or D
6 or E
Segment data memory (40 words x 4 bits)
40H–6FH = R/W
C0H–EFH = W
(segment area)
Note
(1) The I/O data memory registers of 070H–07FH, 170H–17FH and
0F0H–0FFH, 1F0H–1FFH are each linked. For instance, by
switching the I/O data memory at 074H, data memory at 174H
can by switched simultaneously.
See Tables 4.1(a)–(c) for details of I/O data memory.
(2) The mask option can be used to select whether to assign the
overall area of segment data memory to 040H–06FH or 0C0H–
0EFH.
When 040H–06FH is selected, read/write is enabled.
When 0C0H–0EFH is selected, write only is enabled.
If 040H–06FH is assigned, RAM is used as the segment area
(48 words).
(3) Memory is not mounted in unused area within the memory map
and in memory area not indicated in this chapter. For this
reason, normal operation cannot be assured for programs that
have been prepared with access to these areas.
S1C62N33 TECHNICAL HARDWARE
EPSON
I-15
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)
Table 4.1(a) I/O memory map (70H–77H)
Register
Address
Comment
*1
D3
D2
D1
D0
Name
TM3
Init
0
1
0
*7
Timer data (clock timer 2 Hz)
Timer data (clock timer 4 Hz)
Timer data (clock timer 8 Hz)
Timer data (clock timer 16 Hz)
MSB
TM3
TM2
TM1
TM0
TM2
0
70H
TM1
0
R
R
R
R
TM0
0
SWL3
SWL2
SWL1
SWL0
SWH3
SWH2
SWH1
SWH0
K03
0
SWL3
SWH3
K03
SWL2
SWH2
K02
SWL1
SWH1
K01
SWL0
SWH0
K00
Stopwatch counter
1/100 sec (BCD)
LSB
0
71H
72H
73H
74H
75H
0
0
MSB
0
Stopwatch counter
1/10 sec (BCD)
0
0
LSB
0
High
High
Low
Low
*2
*2
*2
*2
0
Input port
K02
High
Low
(K00–K03)
K01
High
Low
K00
Falling
Falling
Falling
Falling
Enable
Enable
Enable
Enable
Rising
Rising
Rising
Rising
Mask
Mask
Mask
Mask
DFK03
DFK02
DFK01
DFK00
EIK03
EIK02
EIK01
EIK00
HVLD
SVDDT
SVDON
EISWIT1
EISWIT0
SCTRG
SIOF
DFK03
EIK03
DFK02
EIK02
DFK01
DFK00
EIK00
Differential register
(K00–K03)
0
0
R/W
0
0
EIK01
Interrupt mask register
(K00–K03)
0
0
R/W
0
Heavy load Normal Heavy load protection mode register
Low voltage Normal SVD evaluation data (at read-out)
0
SVDDT
SVDON
R
HVLD
R/W
EISWIT1 EISWIT0
R/W
0
On
Off
Mask
Mask
–
SVD ON/OFF (at writing)
Interrupt mask register (stopwatch 1 Hz)
Interrupt mask register (stopwatch 10 Hz)
Serial interface clock trigger
SIOF
76H
77H
0
Enable
Enable
Trigger
Run
0
W
0
–
SCTRG
SIOF
W
EIK10
DFK10
K10
R
Stop
Mask
Rising
Low
0
Enable
Falling
High
Interrupt mask register (K10)
Differential register (K10)
Input port (K10)
EIK10
DFK10
K10
0
0
R/W
R
*2
*1 In itial valu e followin g in itial reset
*2 Not set in th e circu it
*3 Un defin ed
*5 Always "0" wh en bein g read
*6 Refer to m ain m an u al
*7 Page switch in g in I/ O m em ory is
n ot n ecessary
*4 Reset (0) im m ediately after bein g read
I-16
EPSON
S1C62N33 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)
Table 4.1(b) I/O memory map (78H–7FH)
Register
Address
*7
Comment
*1
D3
D2
D1
D0
Name
CSDC
ETI2
ETI8
ETI32
–
Init
0
1
0
Static
Enable
Enable
Enable
Dynamic LCD drive switch
CSDC
ETI2
ETI8
ETI32
Mask
Mask
Mask
Interrupt mask register (clock timer 2 Hz)
Interrupt mask register (clock timer 8 Hz)
Interrupt mask register (clock timer 32 Hz)
Unused *5
0
78H
79H
7AH
7BH
7CH
7DH
7EH
7FH
0
R/W
R
0
*2
0
–
TI2
TI8
TI32
SWIT0
R00
Yes
Yes
No
No
Interrupt factor flag (clock timer 2 Hz) *4
Interrupt factor flag (clock timer 8 Hz) *4
Interrupt factor flag (clock timer 32 Hz) *4
Interrupt factor flag (K10) *4
TI2
TI8
0
Yes
No
TI32
0
Yes
No
IK1
0
IK1
R03
R13
P03
IK0
SWIT1
R01
Yes
No
Interrupt factor flag (K00–K03) *4
Interrupt factor flag (stopwatch 1 Hz) *4
Interrupt factor flag (stopwatch 10 Hz) *4
IK0
0
Yes
No
SWIT1
SWIT0
R03
0
R
Yes
No
0
High
High
High
High
High
High
High
High
High
High
High
High
Reset
Run
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
–
0
R02
R12
P02
Output port
R02
0
(R00–R03)
R01
0
R/W
R/W
R/W
R00
0
Output port (R13, BZ) *6
Output port (R12, FOUT) *6
Output port (R11)
R13
0
R11
P01
R10
R12
0
R11
0
Output port (R10, BZ) *6
R10
0
P03
*2
*2
*2
*2
P00
I/O port (P00–P03)
P02
Output latch reset at time of initial reset
P01
P00
Clock timer reset *5
TMRST
SWRUN
SWRST
IOC0
WDRST
WD2
WD1
WD0
Reset
TMRST SWRUN SWRST
IOC0
R/W
Stop
–
Stopwatch counter RUN/STOP
Stopwatch counter reset *5
0
Reset
Output
Reset
Reset
W
WDRST
W
R/W
W
WD1
R
Input
–
I/O control register 0 (P00–P03)
Watchdog timer reset *5
0
Reset
WD2
WD0
Timer data (watchdog timer 1/4 Hz)
Timer data (watchdog timer 1/2 Hz)
Timer data (watchdog timer 1 Hz)
0
0
0
S1C62N33 TECHNICAL HARDWARE
EPSON
I-17
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)
Table 4.1(c) I/O memory map (F0H–F3H, F6H–F9H, FCH–FEH)
Register
Address
Comment
*1
D3
D2
D1
D0
Name
SD3
SD2
SD1
SD0
SD7
SD6
SD5
SD4
SCS1
SCS0
SE2
EISIO
–
Init
*3
*3
*3
*3
*3
*3
*3
*3
1
1
0
*7
SD3
SD2
SD1
SD0
Serial interface data register
F0H
Low order (SD0–SD3)
R/W
R/W
R/W
R
SD7
SCS1
–
SD6
SCS0
–
SD5
SE2
–
SD4
EISIO
ISIO
–
Serial interface data register
F1H
F2H
F3H
F6H
F7H
F8H
F9H
FCH
FDH
FEH
High order (SD4–SD7)
*6
*6
*6
*6
Clock edge selection register
(SCS0, SCS1)
1
Rising
Enable
Falling
Mask
Clock edge selection register
Interrupt mask register (serial interface)
Unused *5
0
0
*2
*2
*2
0
Unused *5
–
Unused *5
–
Yes
No
Interrupt factor flag (serial interface) *4
Buzzer frequency selection register
Unused *5
ISIO
BZFQ
–
2 kHz
4 kHz
0
BZFQ
R/W
–
–
–
*2
*2
*2
*2
*2
1
Unused *5
–
R
Unused *5
–
Unused *5
–
–
R
AMPDT AMPON
R/W
Unused *5
–
+ > -
- > +
Analog comparator data
Analog comparator ON/OFF
AMPDT
AMPON
EV03
EV02
EV01
EV00
EV07
EV06
EV05
EV04
–
On
Off
0
0
EV03
EV07
EV02
EV01
EV00
Event counter
0
Low order (EV00–EV03)
0
R
R
0
0
EV06
EV05
EV04
Event counter
0
High order (EV04–EV07)
0
0
Unused *5
*2
0
–
R
EVRUN
R/W
–
R
EVRST
W
Run
Stop
Event counter RUN/STOP
Unused *5
EVRUN
–
*2
Reset
*2
*2
*2
*2
*2
0
Reset
High
High
High
High
–
Event counter reset *5
EVRST
P13
Low
Low
Low
Low
P13
P12
P11
P10
I/O port (P10–P13)
P12
Output latch reset at time of initial reset
P11
R/W
P10
Unused *5
–
–
CLKCHG OSCC
R/W
IOC1
OSC3
On
OSC1
Off
CPU clock switch
CLKCHG
OSCC
IOC1
OSC3 oscillator ON/OFF
I/O control register 1 (P10–P13)
0
R
Output
Input
0
I-18
EPSON
S1C62N33 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Resetting Watchdog Timer)
4.2 Re se tting Wa tc hd og Tim e r
Th e S1C62N33 Series in corporates a watch dog tim er as th e
sou rce oscillator for OSC1 (clock tim er 2 Hz sign al). Th e
watch dog tim er m u st be reset cyclically by th e software. If
reset is n ot execu ted in at least 3 or 4 secon ds, th e in itial
reset sign al is ou tpu t au tom atically for th e CPU.
Config ura tion of
wa tc hd og tim e r
Figu re 4.2 is th e block diagram of th e watch dog tim er.
2 Hz
OSC1 demultiplier
(256 Hz)
Clock timer
TM0–TM3
Watchdog timer
WD0–WD2
Initial reset signal
Fig. 4.2
Watchdog timer
block diagram
Watchdog timer reset signal
Th e watch dog tim er, con figu red of a th ree-bit bin ary cou n ter
(WD0–WD2), gen erates th e in itial reset sign al in tern ally by
overflow of th e MSB.
Watch dog tim er reset processin g in th e program 's m ain
rou tin e en ables detection of program overru n , su ch as wh en
th e m ain rou tin e's watch dog tim er processin g is bypassed.
Ordin arily th is rou tin e is in corporated wh ere periodic
processin g takes place, ju st as for th e tim er in terru pt rou -
tin e.
Th e watch dog tim er operates in th e h alt m ode. If th e h alt
statu s con tin u es for 3 or 4 secon ds, th e in itial reset sign al
restarts operation .
You can select wh eth er or n ot to u se th e watch dog tim er
with th e m ask option . Wh en "Not u se" is ch osen , th ere is n o
n eed to reset th e watch dog tim er.
Ma sk op tion
S1C62N33 TECHNICAL HARDWARE
EPSON
I-19
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Resetting Watchdog Timer)
Table 4.2 lists th e watch dog tim er's con trol bits an d th eir
addresses.
Control of
wa tc hd og tim e r
Table 4.2 Control bits of watchdog timer
Register
Address
Comment
*1
D3
D2
D1
D0
Name
SR
1
0
*7
WDRST
WD2
WD1
WD0
WDRST
Reset
Reset
–
Watchdog timer reset *5
W
R
WD2
WD1
WD0
0
0
0
Timer data (watchdog timer 1/4 Hz)
Timer data (watchdog timer 1/2 Hz)
Timer data (watchdog timer 1 Hz)
7FH
*1 In itial valu e followin g in itial reset
*2 Not set in th e circu it
*3 Un defin ed
*5 Always "0" wh en bein g read
*6 Refer to m ain m an u al
*7 Page switch in g in I/ O m em ory is
n ot n ecessary
*4 Reset (0) im m ediately after bein g read
WDRST: Th is is th e bit for resettin g th e watch dog tim er.
Watchdog timer reset
(7FH·D3)
Wh en "1" is written :
Wh en "0" is written :
Read-ou t:
Watch dog tim er is reset
No operation
Always "0"
Wh en "1" is written to WDRST, th e watch dog tim er is reset,
an d th e operation restarts im m ediately after th is. Wh en "0"
is written to WDRST, n o operation resu lts.
Th is bit is dedicated for writin g, an d is always "0" for read-
ou t.
Wh en th e watch dog tim er is bein g u sed, th e software m u st
reset it with in 3-secon d cycles, an d tim er data (WD0–WD2)
can n ot be u sed for tim er application s.
Prog ra m m ing note
I-20
EPSON
S1C62N33 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)
4.3 Osc illa tion Circ uit
Th e S1C62N33 Series h as a bu ilt-in crystal oscillation
circu it. As an extern al elem en t, th e OSC1 oscillation circu it
gen erates th e operatin g clock for th e CPU an d periph eral
circu itry by con n ectin g th e crystal oscillator (Typ. 32.768
kHz) an d trim m er capacitor (5–25 pF).
OSC1 osc illa tion
c irc uit
Figu re 4.3.1 is th e block diagram of th e OSC1 oscillation
circu it.
V
DD
C
GX
OSC1
OSC2
To CPU and
peripheral circuits
V
DD
C
DX
Fig. 4.3.1
OSC1 oscillation circuit
S1C62N33 Series
As Figu re 4.3.1 in dicates, th e crystal oscillation circu it can
be con figu red sim ply by con n ectin g th e crystal oscillator
(X'tal) between term in als OSC1 an d OSC2 to th e trim m er
capacitor (CGX) between term in als OSC1 an d VDD.
In th e S1C62N33 Series, th e S1C62A33 h as twin clock
specification . Th e m ask option en ables selection of eith er
th e CR or ceram ic oscillation circu it (OSC3 oscillation
circu it) as th e CPU's su bclock. Becau se th e oscillation
circu it itself is bu ilt-in , it provides th e resistan ce as an
extern al elem en t wh en CR oscillation is selected, bu t wh en
ceram ic oscillation is selected both th e ceram ic oscillator
an d two capacitors (gate an d drain capacitan ce) are
requ ired.
OSC3 osc illa tion
c irc uit
Figu re 4.3.2 is th e block diagram of th e OSC3 oscillation
circu it.
S1C62N33 TECHNICAL HARDWARE
EPSON
I-21
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)
C
CR
OSC3
OSC4
To CPU (SIO)
Oscillation circuit
control signal
S1C62A33
V
DD
C
GC
OSC3
OSC4
To CPU (SIO)
Oscillation circuit
control signal
R
DC
C
DC
Fig. 4.3.2
S1C62A33
OSC3 oscillation circuit
As in dicated in Figu re 4.3.2, th e CR oscillation circu it can be
con figu red sim ply by con n ectin g th e resistor (RCR) between
term in als OSC3 an d OSC4 wh en CR oscillation is selected.
Wh en 82 kΩ is u sed for RCR, th e oscillation frequ en cy is
abou t 430 kHz. Wh en ceram ic oscillation is selected, th e
ceram ic oscillation circu it can be con figu red by con n ectin g
th e ceram ic oscillator (Typ. 500 kHz) between term in als
OSC3 an d OSC4 to th e two capacitors (CGC an d CDC) located
between term in als OSC3 an d OSC4 an d VDD. For both CGC
an d CDC, con n ect capacitors th at are abou t 100 pF. To lower
cu rren t con su m ption of th e OSC3 oscillation circu it, oscilla-
tion can be stopped th rou gh th e software.
For th e S1C62N33 an d 62L33 (sin gle clock specification ), do
n ot con n ect an yth in g to term in als OSC3 an d OSC4.
I-22
EPSON
S1C62N33 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)
Th e S1C62N33 an d 62L33 h ave on e oscillation circu it
(OSC1), an d th e S1C62A33 h as two oscillation circu its
(OSC1 an d OSC3). OSC1 is a crystal oscillation circu it th at
su pplies th e operatin g clock th e CPU an d periph eral cir-
cu its. OSC3 is eith er a CR or ceram ic oscillation circu it.
Wh en processin g with th e S1C62A33 requ ires h igh -speed
operation , th e CPU operatin g clock can be switch ed from
OSC1 to OSC3.
Config ura tion of
osc illa tion c irc uit
Figu re 4.3.3 is th e block diagram of th is oscillation system .
OSC1
oscillation
circuit
To peripheral circuit
Clock
OSC3
oscillation
circuit
To CPU (SIO)
switch
CPU clock selection signal
Fig. 4.3.3
Oscillation system
Oscillation circuit control signal
For S1C62A33, selection of eith er OSC1 or OSC3 for th e
CPU's operatin g clock can be m ade th rou gh th e software.
S1C62N33 TECHNICAL HARDWARE
EPSON
I-23
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)
Table 4.3 lists th e con trol bits an d th eir addresses for th e
oscillation circu it.
Control of osc illa tion
c irc uit
Table 4.3 Control bits of oscillation circuit and prescaler
Register
Address
Comment
*1
D3
D2
D1
D0
Name
SR
1
0
*7
*2
–
CLKCHG OSCC
R/W
IOC1
–
Unused *5
CLKCHG
OSCC
IOC1
0
0
0
OSC3
ON
OSC1
OFF
CPU clock switch
R
FEH
OSC3 oscillator ON/OFF
Output
Input
I/O control register 1 (P10–P13)
*1 In itial valu e followin g in itial reset
*2 Not set in th e circu it
*3 Un defin ed
*5 Always "0" wh en bein g read
*6 Refer to m ain m an u al
*7 Page switch in g in I/ O m em ory is
n ot n ecessary
*4 Reset (0) im m ediately after bein g read
OSCC: Con trols oscillation ON/ OFF for th e OSC3 oscillation circu it.
OSC3 oscillation control (S1C62A33 on ly.)
(FEH·D1)
Wh en "1" is written :
Wh en "0" is written :
Read-ou t:
Th e OSC3 oscillation ON
Th e OSC3 oscillation OFF
Valid
Wh en it is n ecessary to operate th e CPU of th e S1C62A33 at
h igh speed, set OSCC to "1". At oth er tim es, set it to "0" to
lessen th e cu rren t con su m ption .
For th e S1C62N33 an d 62L33, keep OSCC set to "0".
At in itial reset, OSCC is set to "0".
I-24
EPSON
S1C62N33 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)
CLKCHG: Th e CPU's operation clock is selected with th is register.
The CPU's clock switch (S1C62A33 on ly.)
(FEH·D2)
Wh en "1" is written :
Wh en "0" is written :
Read-ou t:
OSC3 clock is selected
OSC1 clock is selected
Valid
Wh en th e S1C62N33's CPU clock is to be OSC3, set
CLKCHG to "1"; for OSC1, set CLKCHG to "0". Th is register
can n ot be con trolled for th e S1C62N33 an d 62L33, so th at
OSC1 is selected n o m atter wh at th e set valu e.
At in itial reset, CLKCHG is set to "0".
(1) It takes at least 5 m s from th e tim e th e OSC3 oscillation
circu it goes ON u n til th e oscillation stabilizes. Con se-
qu en tly, wh en switch in g th e CPU operation clock from
OSC1 to OSC3, do th is after a m in im u m of 5 m s h ave
elapsed sin ce th e OSC3 oscillation wen t ON.
Fu rth er, th e oscillation stabilization tim e varies depen d-
in g on th e extern al oscillator ch aracteristics an d con di-
tion s of u se, so allow am ple m argin wh en settin g th e wait
tim e.
Prog ra m m ing note s
(2) Wh en switch in g th e clock form OSC3 to OSC1, u se a
separate in stru ction for switch in g th e OSC3 oscillation
OFF. An error in th e CPU operation can resu lt if th is
processin g is perform ed at th e sam e tim e by th e on e
in stru ction .
S1C62N33 TECHNICAL HARDWARE
EPSON
I-25
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)
4.4 Inp ut Ports (K00–K03, K10)
Th e S1C62N33 Series h as five bits gen eral-pu rpose in pu t
Config ura tion of
inp ut p orts
ports. Each of th e in pu t port term in als (K00–K03, K10)
provides in tern al pu ll-down resistor. Pu ll-down resistor can
be selected for each bit with th e m ask option .
Figu re 4.4.1 sh ows th e con figu ration of in pu t port.
VDD
Interrupt
request
K
Fig. 4.4.1
Address
Vss
Configuration of
input port
Mask option
Selection of "pu ll-down resistan ce en abled" with th e m ask
option su its in pu t from th e pu sh switch , key m atrix, an d so
forth . Wh en "pu ll-down resistan ce disabled" is selected, th e
port can be u sed for slide switch in pu t an d in terfacin g with
oth er LSIs.
Fu rth er, th e in pu t port term in al K10 is u sed as th e in pu t
term in als for th e even t cou n ter. (See "4.10 Even t Cou n ter"
for details.)
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EPSON
S1C62N33 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)
All five bits of th e in pu t ports (K00–K03, K10) provide th e
in terru pt fu n ction . Th e con dition s for issu in g an in terru pt
can be set by th e software. Fu rth er, wh eth er to m ask th e
in terru pt fu n ction can be selected in dividu ally for all five
bits by th e software.
Diffe re ntia l re g iste rs
a nd inte rrup t func -
tion
Figu re 4.4.2 sh ows th e con figu ration of K00–K03 an d K10.
K
One for each terminal series
Address
Differential
register (DFK)
Interrupt factor
flag (IK)
Interrupt
request
Noise
rejector
Address
Address
Mask option
(K00–K03, K10)
Interrupt mask
register (EIK)
Fig. 4.4.2
Input interrupt circuit
configuration
Address
(K00–K03, K10)
Th e in pu t in terru pt tim in g for K00–K03 an d K10 depen ds on
th e valu e set for th e differen tial registers (DFK00–DFK03
an d DFK10). In terru pt can be selected to occu r at th e risin g
or fallin g edge of th e in pu t.
Th e in terru pt m ask registers (EIK00–EIK03, EIK10) en ables
th e in terru pt m ask to be selected in dividu ally for K00–K03
an d K10. However, wh ereas th e in terru pt fu n ction is en a-
bled in side K00–K03, th e in terru pt occu rs wh en th e con -
ten ts ch an ge from m atch in g th ose of th e differen tial register
to n on -m atch in g con ten ts. In terru pt for K10 can be gen er-
ated by settin g th e sam e con dition s in dividu ally.
Wh en th e in terru pt is gen erated, th e in terru pt factor flag
(IK0 an d IK1) is set to "1".
Figu re 4.4.3 sh ows an exam ple of an in terru pt for K00–K03.
Writing to the interrupt mask registers (EIK00–EIK03, EIK10) can
Note
be done only in the DI status (interrupt flag = "0").
S1C62N33 TECHNICAL HARDWARE
EPSON
I-27
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)
Interrupt mask register
Differential register
EIK03 EIK02 EIK01 EIK00 DFK03 DFK02 DFK01 DFK00
1
1
1
0
1
0
1
0
With th e above settin g, th e in terru pt for K00–K03 occu rs in
th e followin g con dition s.
Input port
(1) K03
1
K02
0
K01
1
K00
0
(In itial valu e)
↓
↓
(2) K03
1
K02
0
K01
1
K00
1
(3) K03
0
K02
0
K01
1
K00
1
→ In terru pt gen erated
K00 is m asked, so th e th ree bits
of K01–K03 cease m atch in g
th ose of th e differen tial register
DFK01–DFK03, an d an in ter-
ru pt occu rs.
↓
(4) K03
0
K02
1
K01
1
K00
1
Fig. 4.4.3
Example of interrupt of
K00–K03
K00 is m asked by th e in terru pt m ask register (EIK00), so
th at an in terru pt does n ot occu r at (2). At (3), K03 ch an ges
to "0"; th e data of th e term in al th at is in terru pt en abled n o
lon ger m atch es th e data of th e differen tial register, so th at
in terru pt occu rs. As already explain ed, th e con dition for th e
in terru pt to occu r is th e ch an ge in th e port data an d con -
ten ts of th e differen tial register from m atch in g to
n on m atch in g. Hen ce, in (4), wh en th e n on m atch in g statu s
ch an ges to an oth er n on m atch in g statu s, an in terru pt does
n ot occu r. Fu rth er, term in als th at h ave been m asked for
in terru pt do n ot affect th e con dition s for in terru pt gen era-
tion .
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EPSON
S1C62N33 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)
Th e con ten ts th at can be selected with th e in pu t port m ask
option are as follows:
Ma sk op tion
(1) In tern al pu ll-down resistor can be selected for each of th e
five bits of th e in pu t ports (K00–K03, K10).
Wh en you h ave selected "pu ll-down resistor disabled",
take care th at th e floatin g statu s does n ot occu r for th e
in pu t. Select "pu ll-down resistor en abled" for in pu t ports
th at are n ot bein g u sed.
(2) Th e in pu t in terru pt circu it con tain s a n oise rejector for
preven tin g in terru pt occu rrin g th rou gh n oise. Th e m ask
option en ables selection of wh eth er to u se th e n oise
rejector for each separate term in al series.
Wh en "Use" is selected, a m axim u m delay of 1 m s occu rs
from th e tim e in terru pt con dition is establish ed u n til th e
in terru pt factor flag (IK) is set to "1".
S1C62N33 TECHNICAL HARDWARE
EPSON
I-29
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)
Table 4.4 list th e in pu t ports con trol bits an d th eir ad-
Control of inp ut p orts
dresses.
Table 4.4 Input port control bits
Register
Address
Comment
*1
D3
D2
D1
D0
Name
K03
SR
1
0
*7
K03
K02
K01
K00
*2
High
Low
R
Input port
K02
K01
*2
*2
High
High
Low
Low
(K00–K03)
73H
K00
*2
High
Low
DFK03
DFK02
DFK01
DFK00
DFK03
0
Falling
Rising
R/W
DFK02
DFK01
DFK00
EIK03
EIK02
EIK01
EIK00
0
0
0
0
0
0
0
Falling
Falling
Falling
Enable
Enable
Enable
Enable
Rising
Rising
Rising
Mask
Mask
Mask
Mask
Differential register
(K00–K03)
74H
EIK03
EIK02
EIK10
IK0
EIK01
EIK00
Interrupt mask register
(K00–K03)
R/W
75H
Serial interface clock trigger
SIOF
SCTRG
SIOF
–
0
Trigger
Run
–
SCTRG
SIOF
DFK10
K10
R
Stop
W
R
Interrupt mask register (K10)
Differential register (K10)
EIK10
0
0
Mask
Enable
Falling
R/W
77H
DFK10
Rising
Input port (K10)
K10
IK1
*2
0
Low
No
High
Yes
Interrupt factor flag (K10) *4
Interrupt factor flag (K00–K03) *4
Interrupt factor flag (stopwatch 1 Hz) *4
Interrupt factor flag (stopwatch 10 Hz) *4
IK1
SWIT1
SWIT0
R
IK0
0
Yes
Yes
Yes
No
No
No
7AH
SWIT1
SWIT0
0
0
*1 In itial valu e followin g in itial reset
*2 Not set in th e circu it
*3 Un defin ed
*5 Always "0" wh en bein g read
*6 Refer to m ain m an u al
*7 Page switch in g in I/ O m em ory is
n ot n ecessary
*4 Reset (0) im m ediately after bein g read
I-30
EPSON
S1C62N33 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)
K00–K03, K10: In pu t data of th e in pu t port term in als can be read ou t with
Input port data th ese registers.
(73H, 77H·D0)
Wh en "1" is read ou t: High level
Wh en "0" is read ou t: Low level
Writin g:
In valid
Th e read-ou t is "1" wh en th e term in al voltage of th e five bits
of th e in pu t ports (K00–K03, K10) goes h igh (VDD), an d "0"
wh en th e voltage goes low (VSS).
Th ese bits are dedicated for read-ou t, so writin g can n ot be
don e.
In terru pt con dition s can be set with th ese registers.
DFK00–DFK03, DFK10:
Differential registers
(74H, 77H·D1)
Wh en read ou t is "1": Fallin g edge
Wh en read ou t is "0": Risin g edge
Read-ou t:
Valid
Th e in terru pt con dition s can be set for th e risin g or fallin g
edge of in pu t for each of th e five bits (K00–K03 an d K10),
th rou gh th e differen tial registers (DFK00–DFK03 an d
DFK10).
At in itial reset, th ese registers are set to "0".
EIK00–EIK03, EIK10:
Interrupt mask registers
(75H, 77H·D2)
Maskin g th e in terru pt of th e in pu t port term in als can be
selected with th ese registers.
Wh en "1" is written :
Wh en "0" is written :
Read-ou t:
En able
Mask
Valid
With th ese registers, m askin g of th e in pu t port bits can be
selected for each of th e five bits.
Writin g to th e in terru pt m ask registers can be don e on ly in
th e DI statu s (in terru pt flag = "0").
At in itial reset, th ese registers are all set to "0".
IK0, IK1: Th ese flags in dicate th e occu rren ce of in pu t in terru pt.
Interrupt factor flags
Wh en "1" is read ou t: In terru pt h as occu rred
Wh en "0" is read ou t: In terru pt h as n ot occu rred
(7AH·D2 and D3)
Writin g:
In valid
Th e in terru pt factor flags IK0 an d IK1 are associated with
K00–K03 an d K10, respectively.
S1C62N33 TECHNICAL HARDWARE
EPSON
I-31
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)
From th e statu s of th ese flags, th e software can decide
wh eth er an in pu t in terru pt h as occu rred.
Th ese flags are reset wh en th e software reads th em . Read-
ou t can be don e on ly in th e DI statu s (in terru pt flag = "0").
At in itial reset, th ese flags are set to "0".
(1) Wh en in pu t ports are ch an ged from h igh to low by pu ll-
down resistan ce, th e fall of th e waveform is delayed on
accou n t of th e tim e con stan t of th e pu ll-down resistan ce
an d in pu t gate capacitan ce. Hen ce, wh en fetch in g in pu t
ports, set an appropriate wait tim e.
Prog ra m m ing note s
Particu lar care n eeds to be taken of th e key scan du rin g
key m atrix con figu ration . Aim for a wait tim e of abou t 1
m s.
(2) Wh en "n oise rejector circu it en able" is selected with th e
m ask option , a m axim u m delay of 1 m s occu rs from tim e
th e in terru pt con dition s are establish ed u n til th e in ter-
ru pt factor flag (IK) is set to "1" (u n til th e in terru pt is
actu ally gen erated).
Hen ce, pay atten tion to th e tim in g wh en readin g ou t
(resettin g) th e in terru pt factor flag.
For exam ple, wh en perform in g a key scan with th e key
m atrix, th e key scan ch an ges th e in pu t statu s to set th e
in terru pt factor flag, so it h as to be read ou t to reset it.
However, if th e in terru pt factor flag is read ou t im m edi-
ately after key scan n in g, th e delay will cau se th e flag to
be set after read-ou t, so th at it will n ot be reset.
(3) In pu t in terru pt program in g related precau tion s
Port K input
Active status
Active status
Differential register
Falling edge interrupt
Rising edge interrupt
Mask register
➀
Factor flag set Not set
➀
Factor flag set
When the content of the mask register is rewritten, while the port K
input is in the active status. The input interrupt factor flags are set at
➀ and ➀, ➀ being the interrupt due to the falling edge and ➀ the
interrupt due to the rising edge.
Fig. 4.4.4
Input interrupt timing
I-32
EPSON
S1C62N33 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)
Wh en u sin g an in pu t in terru pt, if you rewrite th e con ten t
of th e m ask register, wh en th e valu e of th e in pu t term in al
wh ich becom es th e in terru pt in pu t is in th e active statu s,
th e factor flag for in pu t in terru pt m ay be set. Th erefore,
wh en u sin g th e in pu t in terru pt, th e active statu s of th e
in pu t term in al im plies
in pu t term in al = low statu s, wh en th e fallin g edge
in terru pt is effected an d
in pu t term in al = h igh statu s, wh en th e risin g edge
in terru pt is effected.
Wh en an in terru pt is triggered at th e fallin g edge of an
in pu t term in al, a factor flag is set with th e tim in g of ➀
sh own in Figu re 4.4.4. However, wh en clearin g th e con -
ten t of th e m ask register with th e in pu t term in al kept in
th e low statu s an d th en settin g it, th e factor flag of th e
in pu t in terru pt is again set at th e tim in g th at h as been
set. Con sequ en tly, wh en th e in pu t term in al is in th e
active statu s (low statu s), do n ot rewrite th e m ask regis-
ter (clearin g, th en settin g th e m ask register), so th at a
factor flag will on ly set at th e fallin g edge in th is case.
Wh en clearin g, th en settin g th e m ask register, set th e
m ask register, wh en th e in pu t term in al is n ot in th e
active statu s (h igh statu s).
Wh en an in terru pt is triggered at th e risin g edge of th e
in pu t term in al, a factor flag will be set at th e tim in g of ➀
sh own in Figu re 4.4.4. In th is case, wh en th e m ask
registers cleared, th en set, you sh ou ld set th e m ask
register, wh en th e in pu t term in al is in th e low statu s.
In addition , wh en th e m ask register = "1" an d th e con ten t
of th e differen tial register is rewritten in th e in pu t term i-
n al active statu s, an in pu t in terru pt factor flag m ay be
set. Th u s, you sh ou ld rewrite th e con ten t of th e differen -
tial register in th e m ask register = "0" statu s.
(4) Read-ou t th e in terru pt factor flag (IK) on ly in th e DI
statu s (in terru pt flag = "0"). Read-ou t du rin g EI statu s
will cau se m alfu n ction .
(5) Writin g to th e in terru pt m ask registers (EIK) can be don e
on ly in th e DI statu s (in terru pt flag = "0").
Writin g du rin g EI statu s will cau se m alfu n ction .
S1C62N33 TECHNICAL HARDWARE
EPSON
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)
4.5 Outp ut Ports (R00–R03, R10–R13)
Th e S1C62N33 Series h as gen eral ou tpu t ports (4 bits x 2).
Ou tpu t specification s of th e ou tpu t ports can be selected
in dividu ally with th e m ask option . Two kin ds of ou tpu t
specification s are available: com plem en tary ou tpu t an d Pch
open drain ou tpu t.
Config ura tion of
outp ut p orts
Fu rth er, th e m ask option en ables th e ou tpu t ports R10,
R12, an d R13 to be u sed as special ou tpu t ports.
Figu re 4.5.1 sh ows th e con figu ration of th e ou tpu t ports.
V
DD
Register
R
Address
V
SS
Fig. 4.5.1
Configuration of output ports
Mask option
I-34
EPSON
S1C62N33 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)
Th e m ask option en ables th e followin g ou tpu t port selection .
Ma sk op tion
(1) Ou tpu t specification s of ou tpu t ports
Ou tpu t specification s for th e ou tpu t ports (R00–R03,
R10–R13) en able selection of eith er com plem en tary
ou tpu t or Pch open drain ou tpu t for each of th e eigh t
bits.
However, even wh en Pch open drain ou tpu t is selected,
voltage exceedin g sou rce voltage m u st n ot be applied to
th e ou tpu t port.
(2) Special ou tpu t
In addition to th e regu lar DC ou tpu t, special ou tpu t can
be selected for th e ou tpu t ports R10, R12, an d R13 as
sh own in Table 4.5.1. Figu re 4.5.2 sh ows th e stru ctu re of
th e ou tpu t ports R10–R13.
Table 4.5.1
Pin Name
R10
When Special Output Selected
Special output
BZ
R13
BZ (On ly wh en R10 = BZ ou tpu t is selected)
FOUT
R12
S1C62N33 TECHNICAL HARDWARE
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)
BZ
Register
(R10)
R10
Register
(R13)
R13
(Without SW)
Register
(R11)
R11
FOUT
R12
Register
(R12)
Address
(7CH)
Mask option
Fig. 4.5.2
Structure of output port
R10–R13
I-36
EPSON
S1C62N33 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)
BZ, BZ BZ an d BZ are th e bu zzer sign al ou tpu t for drivin g th e
(R10, R13) piezoelectric bu zzer. Th e bu zzer sign al frequ en cy of 2 kHz or
4 kHz can be selected by software.
Note
When the BZ and BZ output signals are turned ON or OFF, a
hazard can result.
When DC output is set for the output port R10, the output port R13
cannot be set for BZ output.
Figu re 4.5.3 sh ows th e ou tpu t waveform for BZ an d BZ.
0
1
0
Register
"H"
BZ output
(R10 terminal)
"L"
Fig. 4.5.3
Output waveform of
BZ and BZ
"H"
BZ output
(R13 terminal)
"L"
FOUT Wh en th e ou tpu t port R12 is set for FOUT ou tpu t, it ou tpu ts
(R12) th e clock of fosc1 or th e dem u ltiplied fosc1. Th e clock fre-
qu en cy is selectable with th e m ask option s, from th e fre-
qu en cies listed in Table 4.5.2.
Table 4.5.2
Clock Frequency (Hz)
fosc1 = 32,768
32,768
Setting Value
FOUT clock frequency
fosc1 /
fosc1 /
fosc1 /
fosc1 /
1
2
4
8
16,384
8,192
4,096
fosc1 / 16
fosc1 / 32
fosc1 / 64
fosc1 / 128
2,048
1,024
512
256
Note
A hazard may occur when the FOUT signal is turned ON or OFF.
S1C62N33 TECHNICAL HARDWARE
EPSON
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)
Table 4.5.3 lists th e ou tpu t ports' con trol bits an d th eir
addresses.
Control of outp ut
p orts
Table 4.5.3 Control bits of output ports
Register
Address
Comment
*1
D3
D2
D1
D0
Name
R03
SR
0
1
0
*7
R03
R02
R01
R00
High
Low
R02
R01
R00
R13
R12
R11
0
0
0
0
0
0
High
High
High
High
High
High
Low
Low
Low
Low
Low
Low
R/W
7BH
Output port (R00–R03)
R13
R12
R11
R10
Output port (R13, BZ) *6
Output port (R12, FOUT) *6
Output port (R11)
R/W
7CH
R10
0
0
High
Low
Output port (R10, BZ) *6
Buzzer frequency selection register
Unused *5
BZFQ
R/W
–
–
–
BZFQ
2 kHz
4 kHz
*2
–
–
–
R
F6H
*2
*2
Unused *5
Unused *5
*1 In itial valu e followin g in itial reset
*2 Not set in th e circu it
*3 Un defin ed
*5 Always "0" wh en bein g read
*6 Refer to m ain m an u al
*7 Page switch in g in I/ O m em ory is
n ot n ecessary
*4 Reset (0) im m ediately after bein g read
I-38
EPSON
S1C62N33 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)
R00–R03, R10–R13 Sets th e ou tpu t data for th e ou tpu t ports.
(when DC output):
Output port data
(7BH, 7CH)
Wh en "1" is written :
Wh en "0" is written :
Read-ou t:
High ou tpu t
Low ou tpu t
Valid
Th e ou tpu t port term in als ou tpu t th e data written in th e
correspon din g registers (R00–R03, R10–R13) with ou t ch an g-
in g it. Wh en "1" is written in th e register, th e ou tpu t port
term in al goes h igh (VDD), an d wh en "0" is written , th e ou tpu t
port term in al goes low (VSS).
At in itial reset, all registers are set to "0".
Th ese bits con trol th e ou tpu t of th e bu zzer sign als (BZ, BZ).
R10, R13 (when BZ and
BZ output is selected):
Special output port data
(7CH·D0 and D3)
Wh en "1" is written :
Wh en "0" is written :
Read-ou t:
Bu zzer sign al is ou tpu t
Low level (DC) is ou tpu t
Valid
BZ is ou tpu t from term in al R13. With th e m ask option ,
selection can be m ade perform th is ou tpu t con trol by R13,
or to perform ou tpu t con trol sim u ltan eou sly with BZ by
R10.
• When R13 controls BZ output
BZ ou tpu t an d BZ ou tpu t can be con trolled in depen den tly.
BZ ou tpu t is con trolled by writin g data to R10, an d BZ
ou tpu t is con trolled by writin g data to R13.
• When R10 controls BZ output
BZ ou tpu t an d BZ ou tpu t can be con trolled sim u ltan e-
ou sly by writin g data to R10 on ly. For th is case, R13 can
be u sed as a on e-bit gen eral register h avin g both read an d
write fu n ction s, an d data of th is register exerts n o affect
on BZ ou tpu t (ou tpu t from th e R13 pin ).
At in itial reset, registers R10 an d R13 are set to "0".
S1C62N33 TECHNICAL HARDWARE
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)
BZFQ: Selects th e frequ en cy of th e bu zzer sign al.
Buzzer frequency
selection register
(F6H·D3)
Wh en "1" is written :
Wh en "0" is written :
Read-ou t:
2 kHz
4 kHz
Valid
Wh en "1" is written to register BZFQ, th e frequ en cy of th e
bu zzer sign al is set in 2 kHz, an d in 4 kHz wh en "0" is
written .
At in itial reset, BZFQ is set to "0" (4 kHz).
R12 Con trols th e FOUT (clock) ou tpu t.
(when FOUT is selected):
Wh en "1" is written :
Wh en "0" is written :
Read-ou t:
Clock ou tpu t
Low level (DC) ou tpu t
Valid
Special output port data
(7CH·D2)
FOUT ou tpu t can be con trolled by writin g data to R12.
At in itial reset, th is register is set to "0".
Wh en BZ, BZ an d FOUT are selected with th e m ask option ,
a h azard m ay be observed in th e ou tpu t waveform wh en th e
data of th e ou tpu t register ch an ges.
Prog ra m m ing note
I-40
EPSON
S1C62N33 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)
4.6 I/ O Ports (P00–P03, P10–P13)
Th e S1C62N33 Series h as gen eral-pu rpose I/ O ports (4 bits
x 2). Figu re 4.6 sh ows th e con figu ration of th e I/ O ports.
Th e fou r bits of each of th e I/ O ports P00–P03 an d P10–P13
can be set to eith er in pu t m ode or ou tpu t m ode. Modes can
be set by writin g data to th e I/ O con trol register.
Config ura tion of
I/ O p orts
Input
control
Register
P
Address
I/O control
register
V
ss
Fig. 4.6
Address
Configuration of I/O ports
S1C62N33 TECHNICAL HARDWARE
EPSON
I-41
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)
In pu t or ou tpu t m ode can be set for th e fou r bits of I/ O port
I/ O c ontrol re g iste r
a nd I/ O m od e
P00–P03 an d I/ O port P10–P13 by writin g data in to th e
correspon din g I/ O con trol register IOC0 an d IOC1.
To set th e in pu t m ode, "0" is written to th e I/ O con trol
register. Wh en an I/ O port is set to in pu t m ode, it becom es
h igh im pedan ce statu s an d works as an in pu t port. How-
ever, th e in pu t lin e is pu lled down wh en in pu t data is read.
Th e ou tpu t m ode is set wh en "1" is written to th e I/ O con trol
register. Wh en an I/ O port set to ou tpu t m ode works as an
ou tpu t port, it ou tpu ts a h igh sign al (VDD) wh en th e port
ou tpu t data is "1", an d a low sign al (VSS) wh en th e port
ou tpu t data is "0".
At in itial reset, th e I/ O con trol registers are set to "0", an d
th e I/ O port en ters th e in pu t m ode.
Th e ou tpu t specification du rin g ou tpu t m ode (IOC = "1") of
th ese I/ O ports can be set with th e m ask option for eith er
com plem en tary ou tpu t or Pch open drain ou tpu t. Th is
settin g can be perform ed for each bit of each port.
However, wh en Pch open drain ou tpu t h as been selected,
voltage in excess of th e power voltage m u st n ot be applied to
th e port.
Ma sk op tion
I-42
EPSON
S1C62N33 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)
Table 4.6 lists th e I/ O ports' con trol bits an d th eir ad-
dresses.
Control of I/ O p orts
Table 4.6 I/O port control bits
Register
Address
Comment
*1
D3
D2
D1
D0
Name
P03
SR
1
0
*7
P03
P02
P01
P00
*2
High
Low
R/W
*2
*2
*2
I/O port (P00–P03)
P02
P01
High
High
Low
Low
Output latch reset at time of initial reset
7DH
P00
High
Low
–
TMRST SWRUN SWRST
IOC0
R/W
Reset
TMRST
Reset
0
Clock timer reset *5
W
R/W
W
RUN
Reset
Output
High
STOP
–
SWRUN
SWRST
IOC0
P13
Stopwatch counter RUN/STOP
Stopwatch counter reset *5
I/O control register 0 (P00–P03)
7EH
FDH
FEH
Reset
0
Input
Low
Low
Low
Low
*2
P13
P12
P11
P10
*2
P12
High
I/O port (P10–P13)
R/W
Output latch reset at time of initial reset
*2
P11
High
*2
P10
High
*2
0
–
CLKCHG OSCC
R/W
IOC1
–
Unused *5
CLKCHG
OSCC
IOC1
OSC3
ON
OSC1
OFF
CPU clock switch
R
0
OSC3 oscillator ON/OFF
I/O control register 1 (P10–P13)
0
Output
Input
*1 In itial valu e followin g in itial reset
*2 Not set in th e circu it
*3 Un defin ed
*5 Always "0" wh en bein g read
*6 Refer to m ain m an u al
*7 Page switch in g in I/ O m em ory is
n ot n ecessary
*4 Reset (0) im m ediately after bein g read
S1C62N33 TECHNICAL HARDWARE
EPSON
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)
I/ O port data can be read an d ou tpu t data can be set
P00–P03, P10–P13:
I/O port data
th rou gh th ese ports.
(7DH, FDH)
• When writing data
Wh en "1" is written :
Wh en "0" is written :
High level
Low level
Wh en an I/ O port is set to th e ou tpu t m ode, th e written data
is ou tpu t u n ch an ged from th e I/ O port term in al. Wh en "1" is
written as th e port data, th e port term in al goes h igh (VDD),
an d wh en "0" is written , th e level goes low (VSS).
Port data can be written also in th e in pu t m ode.
• When reading data out
Wh en "1" is read ou t: High level
Wh en "0" is read ou t: Low level
Th e term in al voltage level of th e I/ O port is read ou t. Wh en
th e I/ O port is in th e in pu t m ode th e voltage level bein g
in pu t to th e port term in al can be read ou t; in th e ou tpu t
m ode th e ou tpu t voltage level can be read. Wh en th e term i-
n al voltage is h igh (VDD) th e port data th at can be read is "1",
an d wh en th e term in al voltage is low (VSS) th e data is "0".
Fu rth er, th e bu ilt-in pu ll-down resistan ce goes ON du rin g
read-ou t, so th at th e I/ O port term in al is pu lled down .
In tern al pu ll down resistors are on ly ON du rin g readou t an d
gate floatin g by m ean s of an in pu t con trol sign al can n ot
occu r even at tim es oth er th an readou t.
Note
- When the I/O port is set to the output mode and a low-impedance
load is connected to the port terminal, the data written to the
register may differ from the data read out.
- When the I/O port is set to the input mode and a low-level voltage
(VSS) is input, erroneous input results if the time constant of the
capacitive load of the input line and the built-in pull-down resis-
tance load is greater than the read-out time.
I-44
EPSON
S1C62N33 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)
When the input data is being read out, the time that the input line
is pulled down is equivalent to 1.5 cycles of the CPU system
clock. However, the electric potential of the terminals must be
settled within 0.5 cycles. If this condition cannot be fulfilled, some
measure must be devised such as arranging pull-down resis-
tance externally, or performing multiple read-outs.
IOC0, IOC1:
I/O control registers
(7EH·D0, FEH·D0)
Th e in pu t an d ou tpu t m odes of th e I/ O ports can be set
with th ese registers.
Wh en "1" is written :
Wh en "0" is written :
Read-ou t:
Ou tpu t m ode
In pu t m ode
Valid
Th e in pu t an d ou tpu t m odes of th e I/ O ports are set in u n its
of fou r bits. IOC0 sets th e m ode for P00–P03, an d IOC1 sets
th e m ode for P10–P13.
Writin g "1" to th e I/ O con trol register m akes th e correspon d-
in g I/ O port en ter th e ou tpu t m ode, an d writin g "0" in du ces
th e in pu t m ode.
At in itial reset, th ese two registers are set to "0", so th e I/ O
ports are in th e in pu t m ode.
(1) Wh en th e I/ O port is bein g read ou t, th e bu ilt-in pu ll-
down resistan ce of th e I/ O port goes ON. Con sequ en tly, if
data is read ou t wh ile th e CPU is ru n n in g in th e OSC3
oscillation circu it, data m u st be read ou t con tin u ou sly for
abou t 500 µs.
Prog ra m m ing note s
(2) Wh en th e I/ O port is set to th e ou tpu t m ode an d th e data
register h as been read, th e term in al data in stead of th e
register data can be read ou t. Becau se of th is, if a low-
im pedan ce load is con n ected an d read-ou t perform ed, th e
valu e of th e register an d th e read-ou t resu lt m ay differ.
S1C62N33 TECHNICAL HARDWARE
EPSON
I-45
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)
4.7 LCD Drive r (COM0–COM3, SEG0–SEG39)
Th e S1C62N33 Series h as fou r com m on term in als an d 40
segm en t term in als, so th at it can drive an LCD with a m axi-
m u m of 160 (40 x 4) segm en ts.
Config ura tion of LCD
d rive r
Th e power for drivin g th e LCD is gen erated by th e CPU
in tern al circu it so th at th ere is n o n eed to apply power
especially from ou tside.
Th e drivin g m eth od is 1/ 4 du ty (or 1/ 3 du ty with th e m ask
option ) dyn am ic drive depen din g on th e fou r types of poten -
tial, VDD, VL1, VL2 an d VL3. Th e fram e frequ en cy is fosc1/
1,024 Hz for 1/ 4 du ty, an d fosc1/ 768 Hz for 1/ 3 du ty.
Figu re 4.7.1 sh ows th e drive waveform for 1/ 4 du ty, an d
Figu re 4.7.2 sh ows th e drive waveform for 1/ 3 du ty.
Note Fosc1 indicates the oscillation frequency of the OSC1 oscillation
circuit.
I-46
EPSON
S1C62N33 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)
LCD lighting status
COM0
-VDD
-VL1
COM0
-VL2
-VL3
COM1
COM2
COM3
COM1
COM2
COM3
SEG0–39
Not lit
Lit
-VDD
-VL1
-VL2
-VL3
SEG
0–39
Frame frequency
Fig. 4.7.1
Drive waveform for 1/4 duty
S1C62N33 TECHNICAL HARDWARE
EPSON
I-47
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)
COM0
-VDD
-VL1
-VL2
-VL3
LCD lighting status
COM0
COM1
COM2
COM1
COM2
COM3
SEG0–39
Not lit
Lit
-VDD
-VL1
-VL2
-VL3
SEG
0–39
Frame frequency
Fig. 4.7.2
Drive waveform for 1/3 duty
I-48
EPSON
S1C62N33 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)
Th e S1C62N33 Series provides software settin g of th e LCD
static drive. Th is fu n ction en ables easy adju stm en t (caden ce
adju stm en t) of th e oscillation frequ en cy of th e OSC1 oscilla-
tion circu it (crystal oscillation circu it).
Switc hing b e twe e n
d yna m ic a nd sta tic
d rive
Th e procedu re for execu tin g static drive of th e LCD is as
follows:
➀ Write "1" to register CSDC at address 78H·D3.
➀ Write th e sam e valu e to all registers correspon din g to
COM0–COM3 of th e segm en t m em ory.
- Even when 1/3 duty is selected, COM3 is valid for static drive.
However, the output frequency is the same as for the frame
frequency.
Note
- For cadence adjustment, set the segment data so that all the
LCDs light.
Figu re 4.7.3 sh ows th e drive waveform for static drive.
LCD lighting status
COM0
COM1
COM2
COM3
–VDD
–VL1
–VL2
–VL3
COM
0–3
SEG0–39
Not lit
Frame frequency
Lit
–VDD
–VL1
–VL2
–VL3
SEG
0–39
–VDD
–VL1
–VL2
–VL3
Fig. 4.7.3
LCD static drive waveform
S1C62N33 TECHNICAL HARDWARE
EPSON
I-49
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)
(1) Segment allocation
Ma sk op tion
(se g m e nt a lloc a tion)
As sh own in Figu re 4.1.2, segm en t data of th e S1C62N33
Series is decided depen din g on display data written to th e
segm en t data m em ory (write-on ly) at address 40H–6FH or
C0H–EFH.
➀ Th e m ask option en ables th e segm en t data m em ory to
be allocated en tirely to eith er 40H–6FH or C0H–EFH.
➀ Th e address an d bits of th e segm en t data m em ory can
be m ade to correspon d to th e segm en t pin s (SEG0–
SEG39) in an y form th rou gh th e m ask option . Th is
m akes design easy by in creasin g th e degree of freedom
with wh ich th e liqu id crystal pan el can be design ed.
Figu re 4.7.4 sh ows an exam ple of th e relation sh ip be-
tween th e LCD segm en ts (on th e pan el) an d th e segm en t
data m em ory (wh en 40H–6FH is selected) for th e case of
1/ 3 du ty.
Data
D2
Common 0 Common 1 Common 2
Address
D3
d
D1
b
D0
a
SEG10
SEG11
SEG12
6A, D0 6B, D1 6B, D0
(a)
6A, D1 6B, D2 6A, D3
(b) (g) (d)
6D, D1 6A, D2 6B, D3
(f' ) (c) (p)
(f)
(e)
6AH
6BH
6CH
6DH
c
g
→
p
f
e
d'
p'
c'
g'
b'
f'
a'
e'
Segment data memory allocation
Pin address allocation
↑
a
a'
g'
b'
c'
b
f'
f
g
e
c
e'
p'
p
d'
d
SEG10 SEG11 SEG12
Common 0
Common 1
Common 2
Fig. 4.7.4
Segment allocation
Example of LCD panel
I-50
EPSON
S1C62N33 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)
(2) Drive duty
With th e m ask option , eith er 1/ 4 or 1/ 3 du ty can be
selected for th e LCD drive du ty.
Table 4.7.1 sh ows th e differen ces in th e n u m ber of seg-
m en ts depen din g on th e selected du ty.
Table 4.7.1 Differences depending on selected duty
Duty Pins Used in Common Maximum Number of Segments Frame Frequency (when fosc1 = 32 kHz)
1/ 4
1/ 3
COM0–COM3
COM0–COM2
160 (40 x 4)
120 (40 x 3)
fosc1/ 1,024 (32 Hz)
fosc1/ 768 (42.7 Hz)
(3) Output specification
➀ Th e segm en t pin s (SEG0–SEG39) are selected with th e
m ask option in pairs for eith er segm en t sign al ou tpu t
or DC ou tpu t (VDD an d VSS bin ary ou tpu t).
Wh en DC ou tpu t is selected, th e data correspon din g to
COM0 of each segm en t pin is ou tpu t.
➀ Wh en DC ou tpu t is selected, eith er com plem en tary
ou tpu t or Pch open drain ou tpu t can be selected for
each pin with th e m ask option .
Note
The pin pairs are the combination of SEG2*n and SEG2*n + 1
(where n is an integer from 0 to 18).
S1C62N33 TECHNICAL HARDWARE
EPSON
I-51
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)
Table 4.7.2 sh ows th e LCD driver's con trol bits an d th eir
Control of LCD d rive r
addresses. Figu re 4.7.5 sh ows th e segm en t data m em ory
m ap.
Table 4.7.2 Control bits of LCD driver
Register
Address
Comment
*1
D3
D2
D1
D0
Name
CSDC
SR
0
1
0
*7
CSDC
ETI2
ETI8
ETI32
LCD drive switch
Static
Dynamic
R/W
ETI2
ETI8
0
0
0
Enable
Enable
Enable
Mask
Mask
Mask
Interrupt mask register (clock timer 2 Hz)
Interrupt mask register (clock timer 8 Hz)
Interrupt mask register (clock timer 32 Hz)
78H
ETI32
*1 In itial valu e followin g in itial reset
*2 Not set in th e circu it
*3 Un defin ed
*5 Always "0" wh en bein g read
*6 Refer to m ain m an u al
*7 Page switch in g in I/ O m em ory is
n ot n ecessary
*4 Reset (0) im m ediately after bein g read
Address
Low
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Page
0
High
4 or C
5 or D
6 or E
Segment data memory (40 words x 4 bits)
40H–6FH = R/W
C0H–EFH = W
Fig. 4.7.5
Segment data memory map
I-52
EPSON
S1C62N33 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)
CSDC: Th e LCD drive form at can be selected with th is switch .
LCD drive switch
Wh en "1" is written :
Wh en "0" is written :
Read-ou t:
Static drive
Dyn am ic drive
Valid
(78H·D3)
At in itial reset, dyn am ic drive (CSDC = "0") is selected.
Segment data memory
Th e LCD segm en ts are lit or tu rn ed off depen din g on th is
data.
(40H–6FH or C0H–EFH)
Wh en "1" is written :
Wh en "0" is written :
Read-ou t:
Lit
Not lit
Valid for 40H–6FH
Un defin ed C0H–EFH
By writin g data in to th e segm en t data m em ory allocated to
th e LCD segm en t (on th e pan el), th e segm en t can be lit or
pu t ou t.
At in itial reset, th e con ten ts of th e segm en t data m em ory are
u n defin ed.
(1) Wh en 40H–6FH is selected for th e segm en t data m em ory,
th e m em ory data an d th e display will n ot m atch u n til th e
area is in itialized (th rou gh , for in stan ce, m em ory clear
processin g by th e CPU). In itialize th e segm en t data m em -
ory by execu tin g in itial processin g.
Prog ra m m ing note s
(2) Wh en C0H–EFH is selected for th e segm en t data m em ory,
th at area becom es write-on ly. Con sequ en tly, data can n ot
be rewritten by arith m etic operation s (su ch as AND, OR,
ADD, SUB).
S1C62N33 TECHNICAL HARDWARE
EPSON
I-53
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)
4.8 Cloc k Tim e r
Th e S1C62N33 Series h as a bu ilt-in clock tim er as th e
Config ura tion of
c loc k tim e r
sou rce oscillator for OSC1 (crystal oscillator). Th e clock
tim er is con figu red of a seven -bit bin ary cou n ter th at serves
as th e in pu t clock, a 256 kHz sign al ou tpu t by th e prescaler.
Data of th e fou r h igh -order bits (16 Hz–2 Hz) can be read ou t
by th e software.
Figu re 4.8.1 is th e block diagram for th e clock tim er.
Data bus
OSC1
oscillation
circuit
256 Hz
128 Hz–32 Hz
16 Hz–2 Hz
32 Hz, 8 Hz, 2 Hz
Clock timer reset signal
Fig. 4.8.1
Block diagram of clock timer
Interrupt
control
Interrupt request
Ordin arily, th is clock tim er is u sed for all types of tim in g
fu n ction s su ch as clocks.
I-54
EPSON
S1C62N33 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)
Th e clock tim er can cau se in terru pts at th e fallin g edge of 32
Hz, 8 Hz an d 2 Hz sign als. Software can set wh eth er to m ask
an y of th ese frequ en cies.
Inte rrup t func tion
Figu re 4.8.2 is th e tim in g ch art of th e clock tim er.
Address Register Frequency
Clock timer timing chart
D0
D1
D2
D3
16 Hz
8 Hz
4 Hz
2 Hz
70H
32 Hz interrupt request
8 Hz interrupt request
2 Hz interrupt request
Fig. 4.8.2
Timing chart of
clock timer
As sh own in Figu re 4.8.2, in terru pt is gen erated at th e
fallin g edge of th e frequ en cies (32 Hz, 8 Hz, 2 Hz). At th is
tim e, th e correspon din g in terru pt factor flag (TI32, TI8, TI2)
is set to "1". Selection of wh eth er to m ask th e separate
in terru pts can be m ade with th e in terru pt m ask registers
(ETI32, ETI8, ETI2). However, regardless of th e in terru pt
m ask register settin g, th e in terru pt factor flag is set to "1" at
th e fallin g edge of th e correspon din g sign al.
Note Perform writing to the interrupt mask registers (ETI32, ETI8, ETI2)
and readout from the interrupt factor flags (TI32, TI8, TI2) only in
the DI status (interrupt flag = "0").
S1C62N33 TECHNICAL HARDWARE
EPSON
I-55
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)
Table 4.8 sh ows th e clock tim er con trol bits an d th eir ad-
dresses.
Control of c loc k
tim e r
Table 4.8 Control bits of clock timer
Register
Address
Comment
Timer data (clock timer 2 Hz)
Timer data (clock timer 4 Hz)
Timer data (clock timer 8 Hz)
Timer data (clock timer 16 Hz)
*1
D3
D2
D1
D0
Name
TM3
SR
0
1
0
*7
TM3
TM2
TM1
TM0
R
TM2
TM1
TM0
0
0
0
70H
CSDC
ETI2
ETI8
ETI32
LCD drive switch
CSDC
ETI2
0
0
Static
Enable
Enable
Enable
Dynamic
Mask
R/W
Interrupt mask register (clock timer 2 Hz)
Interrupt mask register (clock timer 8 Hz)
Interrupt mask register (clock timer 32 Hz)
Unused *5
78H
79H
7EH
ETI8
0
Mask
ETI32
0
Mask
–
TI2
TI8
TI32
–
*2
0
R
TI2
TI8
Yes
Yes
No
No
Interrupt factor flag (clock timer 2 Hz) *4
Interrupt factor flag (clock timer 8 Hz) *4
Interrupt factor flag (clock timer 32 Hz) *4
Clock timer reset *5
0
TI32
0
Yes
No
TMRST SWRUN SWRST
IOC0
R/W
Reset
RUN
Reset
Output
–
TMRST
SWRUN
SWRST
IOC0
Reset
0
W
R/W
W
STOP
–
Stopwatch counter RUN/STOP
Stopwatch counter reset *5
Reset
0
Input
I/O control register 0 (P00–P03)
*1 In itial valu e followin g in itial reset
*2 Not set in th e circu it
*3 Un defin ed
*5 Always "0" wh en bein g read
*6 Refer to m ain m an u al
*7 Page switch in g in I/ O m em ory is
n ot n ecessary
*4 Reset (0) im m ediately after bein g read
I-56
EPSON
S1C62N33 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)
TM0–TM3: Th e 16 Hz–2 Hz tim er data of th e clock tim er can be read
Timer data ou t with th is register. Th ese fou r bits are read-ou t on ly, an d
(70H) writin g operation s are in valid.
At in itial reset, th e tim er data is in itialized to "0H".
ETI32, ETI8, ETI2: Th ese registers are u sed to select wh eth er to m ask th e clock
Interrupt mask registers tim er in terru pt.
(78H·D0–D2)
Wh en "1" is written :
Wh en "0" is written :
Read-ou t:
En abled
Masked
Valid
Th e in terru pt m ask registers (ETI32, ETI8, ETI2) are u sed to
select wh eth er to m ask th e in terru pt to th e separate fre-
qu en cies (32 Hz, 8 Hz, 2 Hz).
Writin g to th e in terru pt m ask registers can be don e on ly in
th e DI statu s (in terru pt flag = "0").
At in itial reset, th ese registers are all set to "0".
Th ese flags in dicate th e statu s of th e clock tim er in terru pt.
TI32, TI8, TI2:
Interrupt factor flags
(79H·D0–D2)
Wh en "1" is read ou t: In terru pt h as occu rred
Wh en "0" is read ou t: In terru pt h as n ot occu rred
Writin g:
In valid
Th e in terru pt factor flags (TI32, TI8, TI2) correspon d to th e
clock tim er in terru pts of th e respective frequ en cies (32 Hz, 8
Hz, 2 Hz). Th e software can ju dge from th ese flags wh eth er
th ere is a clock tim er in terru pt. However, even if th e in ter-
ru pt is m asked, th e flags are set to "1" at th e fallin g edge of
th e sign al.
Th ese flags can be reset th rou gh bein g read ou t by th e
software. Also, th e flags can be read ou t on ly in th e DI
statu s (in terru pt flag = "0").
At in itial reset, th ese flags are set to "0".
S1C62N33 TECHNICAL HARDWARE
EPSON
I-57
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)
TMRST: Th is bit resets th e clock tim er.
Clock timer reset
Wh en "1" is written :
Wh en "0" is written :
Read-ou t:
Clock tim er reset
(7EH·D3)
No operation
Always "0"
Th e clock tim er is reset by writin g "1" to TMRST. Th e clock
tim er starts im m ediately after th is. No operation resu lts
wh en "0" is written to TMRST.
Th is bit is write-on ly, an d so is always "0" at read-ou t.
(1) Wh en th e clock tim er h as been reset, th e in terru pt factor
flag (TI) m ay som etim es be set to "1". Con sequ en tly,
perform flag read-ou t (reset th e flag) as n ecessary at
reset.
Prog ra m m ing note s
(2) Th e in pu t clock of th e watch dog tim er is th e 2 Hz sign al
of th e clock tim er, so th at th e watch dog tim er m ay be
cou n ted u p at tim er reset.
(3) Read-ou t th e in terru pt factor flag (TI) on ly du rin g th e DI
statu s (in terru pt flag = "0"). Read-ou t du rin g EI statu s
will cau se m alfu n ction .
(4) Writin g to th e in terru pt m ask register (ETI) can be don e
on ly in th e DI statu s (in terru pt flag = "0").
Writin g du rin g EI statu s will cau se m alfu n ction .
I-58
EPSON
S1C62N33 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Counter)
4.9 Stop wa tc h Counte r
Th e S1C62N33 Series in corporates a 1/ 100 sec an d 1/ 10
sec stopwatch cou n ter. Th e stopwatch cou n ter is con figu red
Config ura tion of
stop wa tc h c ounte r
of a two-stage, fou r-bit BCD cou n ter servin g as th e in pu t
clock of an approxim ately 100 Hz sign al (sign al obtain ed by
approxim ately dem u ltiplyin g th e 256 Hz sign al ou tpu t by
th e prescaler). Data can be read ou t fou r bits at a tim e by
th e software.
Figu re 4.9.1 is th e block diagram of th e stopwatch cou n ter.
Data bus
OSC1
oscillation
circuit
10 Hz
256 Hz
SWL counter
SWH counter
10 Hz, 1 Hz
Fig. 4.9.1
Block diagram of
stopwatch counter
Stopwatch counter reset signal
Stopwatch counter RUN/STOP signal
Interrupt
control
Interrupt request
Th e stopwatch cou n ter can be u sed as a separate tim er from
th e clock tim er. In particu lar, digital watch stopwatch fu n c-
tion s can be realized easily with software.
S1C62N33 TECHNICAL HARDWARE
EPSON
I-59
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Counter)
Th e stopwatch cou n ter is con figu red of fou r-bit BCD cou n t-
Count-up p a tte rn
ers SWL an d SWH.
Th e cou n ter SWL, at th e stage precedin g th e stopwatch
cou n ter, h as an approxim ated 100 Hz sign al for th e in pu t
clock. It cou n ts u p every 1/ 100 sec, an d gen erates an
approxim ated 10 Hz sign al. Th e cou n ter SWH h as an ap-
proxim ated 10 Hz sign al gen erated by th e cou n ter SWL for
th e in pu t clock. It cou n t-u p every 1/ 10 sec, an d gen erated 1
Hz sign al.
Figu re 4.9.2 sh ows th e cou n t-u p pattern of th e stopwatch
cou n ter.
SWH count up pattern
SWH count value
0
1
2
3
4
5
6
7
8
9
0
1 Hz
signal
26
26 25 25 26
26 25 25 26 26
Count time (S)
256 256 256 256 256 256 256 256 256 256
generation
26
256
25
256
x 4 = 1 (S)
x 6 +
SWL count up pattern 1
SWL count value
0
1
2
3
3
4
2
5
6
7
8
9
0
Approximate
10 Hz
signal
3
2
3
2
3
2
3
2
Count time (S)
256 256 256 256 256 256 256 256 256 256
generation
25
256
(S)
SWL count up pattern 2
SWL count value
0
1
2
3
4
5
6
7
8
9
0
Approximate
10 Hz
signal
3
3
3
2
3
2
3
2
3
2
Count time (S)
256 256 256 256 256 256 256 256 256 256
generation
26
(S)
256
Fig. 4.9.2
Count-up pattern of
stopwatch counter
SWL gen erates an approxim ated 10 Hz sign al from th e basic
256 Hz sign al. Th e cou n t-u p in tervals are 2/ 256 sec an d 3/
256 sec, so th at fin ally two pattern s are gen erated: 25/ 256
sec an d 26/ 256 sec in tervals. Con sequ en tly, th ese pattern s
do n ot am ou n t to an accu rate 1/ 100 sec.
SWH cou n ts th e approxim ated 10 Hz sign als gen erated by
th e 25/ 256 sec an d 26/ 256 sec in tervals in th e ratio of 4:6,
to gen erate a 1 Hz sign al. Th e cou n t-u p in tervals are 25/
256 sec an d 26/ 256 sec, wh ich do n ot am ou n t to an
accu rate 1/ 10 sec.
I-60
EPSON
S1C62N33 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Counter)
Th e 10 Hz (approxim ate 10 Hz) an d 1 Hz in terru pts can be
gen erated th rou gh th e overflow of stopwatch cou n ters SWL
an d SWH respectively. Also, software can set wh eth er to
separately m ask th e frequ en cies described earlier.
Inte rrup t func tion
Figu re 4.9.3 is th e tim in g ch art for th e stopwatch cou n ter.
Stopwatch counter (SWL) timing chart
Address
Register
D0
D1
71H
(1/100 sec BCD)
D2
D3
10 Hz interrupt request
Address
Register
D0
Stopwatch counter (SWH) timing chart
D1
72H
(1/10 sec BCD)
D2
Fig. 4.9.3
Timing chart for
D3
1 Hz interrupt request
stopwatch counter
As sh own in Figu re 4.9.3, th e in terru pts are gen erated by
th e overflow of th eir respective cou n ters ("9" ch an gin g to
"0"). Also, at th is tim e th e correspon din g in terru pt factor
flags (SWIT0, SWIT1) are set to "1".
Th e respective in terru pts can be m asked separately th rou gh
th e in terru pt m ask registers (EISWIT0, EISWIT1). However,
regardless of th e settin g of th e in terru pt m ask registers, th e
in terru pt factor flags are set to "1" by th e overflow of th eir
correspon din g cou n ters.
Note
Perform writing to the interrupt mask registers (EISWIT0, EISWIT1)
and readout from the interrupt factor flags (SWIT0, SWIT1) only in
the DI status (interrupt flag = "0").
S1C62N33 TECHNICAL HARDWARE
EPSON
I-61
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Counter)
Table 4.9.1 list th e stopwatch cou n ter con trol bits an d th eir
addresses.
Control of stop wa tc h
c ounte r
Table 4.9.1 Stopwatch counter control bits
Register
Address
Comment
*1
D3
D2
D1
D0
Name
SWL3
SR
0
1
0
*7
SWL3
SWL2
SWL1
SWL0
MSB
SWL2
SWL1
SWL0
SWH3
SWH2
SWH1
0
0
0
0
0
0
Stopwatch counter
1/100 sec (BCD)
R
71H
LSB
SWH3
SWH2
SWH1
SWH0
MSB
Stopwatch counter
1/10 sec (BCD)
R
72H
76H
SWH0
HVLD
0
0
LSB
SVDDT
SVDON
R
Heavy
load
HVLD
R/W
EISWIT1 EISWIT0
R/W
Normal Heavy load protection mode register
SVD evaluation data (at read-out)
Low voltage
ON
SVDDT
SVDON
0
0
Normal
SVD ON/OFF (at writing)
Interrupt mask register
(stopwatch 1 Hz)
W
OFF
EISWIT1
EISWIT0
IK1
0
0
0
0
0
0
Enable
Enable
Mask
Interrupt mask register
(stopwatch 10 Hz)
Mask
Interrupt factor flag (K10) *4
Interrupt factor flag (K00–K03) *4
Interrupt factor flag (stopwatch 1 Hz) *4
Interrupt factor flag (stopwatch 10 Hz) *4
Clock timer reset *5
IK1
IK0
SWIT1
SWIT0
Yes
Yes
No
No
R
IK0
7AH
7EH
SWIT1
SWIT0
TMRST
SWRUN
SWRST
IOC0
Yes
No
Yes
No
TMRST SWRUN SWRST
IOC0
R/W
Reset
RUN
Reset
Output
–
Reset
0
W
R/W
W
STOP
–
Stopwatch counter RUN/STOP
Stopwatch counter reset *5
Reset
0
Input
I/O control register 0 (P00–P03)
*1 In itial valu e followin g in itial reset
*2 Not set in th e circu it
*3 Un defin ed
*5 Always "0" wh en bein g read
*6 Refer to m ain m an u al
*7 Page switch in g in I/ O m em ory is
n ot n ecessary
*4 Reset (0) im m ediately after bein g read
I-62
EPSON
S1C62N33 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Counter)
SWL0–SWL3: Data (BCD) of th e 1/ 100 sec colu m n of th e stopwatch cou n -
Stopwatch counter ter can be read ou t. Th ese fou r bits are read-on ly, an d
1/100 sec (71H) can n ot be u sed for writin g operation s.
At in itial reset, th e cou n ter data is set to "0H".
Data (BCD) of th e 1/ 10 sec colu m n of th e stopwatch cou n ter
can be read ou t. Th ese fou r bits are read-on ly, an d can n ot
be u sed for writin g operation s.
SWH0–SWH3:
Stopwatch counter
1/10 sec (72H)
At in itial reset, th e cou n ter data is set to "0H".
EISWIT0, EISWIT1: Th ese registers are u sed to select wh eth er to m ask th e
Interrupt mask register stopwatch cou n ter in terru pt.
(76H·D0 and D1)
Wh en "1" is written :
Wh en "0" is written :
Read-ou t:
En abled
Masked
Valid
Th e in terru pt m ask registers (EISWIT0, EISWIT1) are u sed
to separately select wh eth er to m ask th e 10 Hz an d 1 Hz
in terru pts.
Writin g to th e in terru pt m ask registers can be don e on ly in
th e DI statu s (in terru pt flag = "0").
At in itial reset, th ese registers are both set to "0".
SWIT0, SWIT1:
Interrupt factor flag
(7AH·D0 and D1)
Th ese flags in dicate th e statu s of th e stopwatch cou n ter
in terru pt.
Wh en "1" is read ou t: In terru pt h as occu rred
Wh en "0" is read ou t: In terru pt h as n ot occu rred
Writin g:
In valid
Th e in terru pt factor flags (SWIT0, SWIT1) correspon d to th e
10 Hz an d 1 Hz in terru pts respectively. With th ese flags, th e
software can ju dge wh eth er a stopwatch cou n ter in terru pt
h as occu rred. However, regardless of th e in terru pt m ask
register settin g, th ese flags are set to "1" by th e cou n ter
overflow.
Th ese flags are reset wh en read ou t by th e software. Also,
read-ou t is on ly possible in th e DI statu s (in terru pt flag =
"0").
At in itial reset, th ese flags are set to "0".
S1C62N33 TECHNICAL HARDWARE
EPSON
I-63
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Counter)
SWRST: Th is bit resets th e stopwatch cou n ter.
Stopwatch counter reset
Wh en "1" is written :
Wh en "0" is written :
Read-ou t:
Stopwatch cou n ter reset
(7EH·D1)
No operation
Always "0"
Th e stopwatch cou n ter is reset wh en "1" is written to
SWRST. Wh en th e stopwatch cou n ter is reset in th e RUN
statu s, operation restarts im m ediately. Also, in th e STOP
statu s th e reset data is m ain tain ed.
Th is bit is write-on ly, an d is always "0" at read-ou t.
SWRUN:
Stopwatch counter
RUN/STOP
Th is bit con trols RUN/ STOP of th e stopwatch cou n ter.
Wh en "1" is written :
Wh en "0" is written :
Read-ou t:
RUN
STOP
Valid
(7EH·D2)
Th e stopwatch cou n ter en ters th e RUN statu s wh en "1" is
written to SWRUN, an d th e STOP statu s wh en "0" is written .
In th e STOP statu s, th e cou n ter data is m ain tain ed u n til th e
n ext RUN statu s or resets cou n ter. Also, wh en th e STOP
statu s ch an ges to th e RUN statu s, th e data th at was m ain -
tain ed can be u sed for resu m in g th e cou n t.
Wh en th e cou n ter data is read ou t in th e RUN statu s, cor-
rect read-ou t m ay be im possible becau se of th e carry from
th e low-order bit (SWL) to th e h igh -order bit (SWH). Th is
occu rs wh en read-ou t h as exten ded over th e SWL an d SWH
bits wh en th e carry occu rs. To preven t th is, perform read
ou t after en terin g th e STOP statu s, an d th en retu rn to th e
RUN statu s. Also, th e du ration of th e STOP statu s m u st be
with in 976 µs (256 Hz 1/ 4 cycle).
At in itial reset, th is register is set to "0".
I-64
EPSON
S1C62N33 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Counter)
(1) If cou n ter data is read ou t in th e RUN statu s, th e cou n ter
m u st be m ade in to th e STOP statu s, an d after data is
read ou t th e RUN statu s can be restored. If data is read
ou t wh en a carry occu rs, th e data can n ot be read cor-
rectly.
Prog ra m m ing note s
Also, th e processin g above m u st be perform ed with in th e
STOP in terval of 976 µs (256 Hz 1/ 4 cycle).
(2) Read-ou t of th e in terru pt factor flag (SWIT) m u st be don e
on ly in th e DI statu s (in terru pt flag = "0").
Read-ou t du rin g EI statu s will cau se m alfu n ction .
(3) Writin g to th e in terru pt m ask registers (EISWIT) can be
don e on ly in th e DI statu s (in terru pt flag = "0").
Writin g du rin g EI statu s will cau se m alfu n ction .
S1C62N33 TECHNICAL HARDWARE
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Event Counter)
4.10 Eve nt Counte r
Th e S1C62N33 Series h as an even t cou n ter th at cou n ts th e
Config ura tion of
e ve nt c ounte r
clock sign als in pu t from ou tside.
Th e even t cou n ter is con figu red of eigh t-bit bin ary cou n ters
(UP cou n ters). Th e clock pu lses are in pu t th rou gh pin s K02
an d K03 of th e in pu t port.
Figu re 4.10.1 sh ows th e con figu ration of th e even t cou n ter.
Input port
K10
Interrupt request
Noise rejector
circuit
Event counter
[EV00–EV07]
Fig. 4.10.1
Configuration of
event counter
Event counter RUN/STOP
Event counter reset
Th e clock sign al in pu t from term in al K10 is in pu t to th e
even t cou n ter via th e n oise rejector.
Op e ra tion of e ve nt
c ounte r
Th e even t cou n ter in crem en ts wh en th e clock sign al is
in pu t, an d th e in crem en ted data can be read ou t th rou gh
th e software.
RUN an d STOP of th e even t cou n ter are perform ed by m ak-
in g th e clock of th e n oise rejector ON an d OFF. Th is is
con trolled by writin g data to th e EVRUN register.
Figu re 4.10.2 is th e tim in g ch art for th e even t cou n ter.
Noise
Input of K10 terminal
T
ON
T
OFF
T
ON2
TN
EVRUN
Input of event counter
Defined time
STOP
RUN
TSTP
T
T
T
T
T
ON ≥ 1.5 T CH
OFF ≥ 1.0 T CH
< 0.5 T CH
STP ≥ 0.5 T CH
CH
T = 1/fCH
Through the mask option, fCH
selects fosc 1/16 or fosc 1/128
for the clock frequency of the
noise rejector
Fig. 4.10.2
N
Timing chart of
event counter
ON2 ≥ 1.5 T CH + TSTP (Execution time)
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S1C62N33 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Event Counter)
Th e clock frequ en cy of th e n oise rejector can be selected as
fosc1/ 16 or fosc1/ 128.
Ma sk op tion
Table 4.10.1 lists th e defin ed tim e depen din g on th e fre-
qu en cy selected.
Table 4.10.1
Selection
TON
fosc1/16
0.74
fosc1/128
5.86
Defined time depending
on frequency selected
TOFF
0.49
3.91
TN
0.24
1.95
TSTP
0.25
1.96
fosc1 = 32,768 Hz
(Un it: m s)
TN :
Max valu e
Oth ers : Min valu e
Table 4.10.2 sh ows th e even t cou n ter con trol bits an d th eir
addresses.
Control of e ve nt
c ounte r
Table 4.10.2 Event counter control bits
Register
Address
*7
Comment
*1
D3
D2
D1
D0
Name
EV03
SR
0
1
0
EV03
EV02
EV01
EV00
R
Event counter
EV02
EV01
0
0
low order (EV00–EV03)
F8H
F9H
EV00
EV07
0
0
EV07
EV06
EV05
EV04
R
EV06
EV05
EV04
–
0
0
Event counter
high order (EV04–EV07)
0
*2
0
–
EVRUN
R/W
–
EVRST
W
Unused *5
R
R
EVRUN
–
RUN
STOP
Event counter RUN/STOP
Unused *5
FCH
*2
EVRST
Reset
Reset
–
Event counter reset *5
*1 In itial valu e followin g in itial reset
*2 Not set in th e circu it
*3 Un defin ed
*5 Always "0" wh en bein g read
*6 Refer to m ain m an u al
*7 Page switch in g in I/ O m em ory is
n ot n ecessary
*4 Reset (0) im m ediately after bein g read
S1C62N33 TECHNICAL HARDWARE
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Event Counter)
EV00–EV03: Th e fou r low-order data bits of even t cou n ter are read ou t.
Event counter Low-order Th ese fou r bits are read-on ly, an d can n ot be u sed for writ-
(F8H) in g.
At in itial reset, even t cou n ter is set to "00H".
EV04–EV07: Th e fou r h igh -order data bits of even t cou n ter are read ou t.
Event counter High-order Th ese fou r bits are read-on ly, an d can n ot be u sed for writ-
(F9H) in g.
At in itial reset, even t cou n ter is set to "00H".
EVRST:
Event counter reset
(FCH·D0)
Th is is th e register for resettin g even t cou n ter.
Wh en "1" is written :
Wh en "0" is written :
Read-ou t:
Even t cou n ter reset
No operation
Always "0"
Wh en "1" is written , even t cou n ter is reset an d th e data
becom es "00H". Wh en "0" is written , n o operation is exe-
cu ted.
Th is is a write-on ly bit, an d is always "0" at read-ou t.
EVRUN: Th is register con trols th e even t cou n ter RUN/ STOP statu s.
Event counter RUN/STOP
Wh en "1" is written :
Wh en "0" is written :
Read-ou t:
RUN
STOP
Valid
(FCH·D2)
Wh en "1" is written , th e even t cou n ter en ters th e RUN
statu s an d starts receivin g th e clock sign al in pu t.
Wh en "0" is written , th e even t cou n ter en ters th e STOP
statu s an d th e clock sign al in pu t is ign ored. (However, in pu t
to th e in pu t port is valid.)
At in itial reset, th is register is set to "0".
To preven t erron eou s readin g of th e even t cou n ter data, read
ou t th e cou n ter data several tim es, com pare it, an d u se th e
m atch in g data as th e resu lt.
Prog ra m m ing note
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S1C62N33 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Analog Comparator)
4.11 Ana log Com p a ra tor
Th e S1C62N33 Series in corporates an MOS in pu t an alog
com parator. Th is an alog com parator, wh ich h as two differ-
Config ura tion of
a na log c om p a ra tor
en tial in pu t term in als (in verted in pu t term in al AMPM,
n on in verted in pu t term in al AMPP), can be u sed for gen eral
pu rposes.
Figu re 4.11 sh ows th e con figu ration of th e an alog com para-
tor.
VDD
AMPP
AMPM
+
–
AMPDT
Input control
Power source
control
AMPON
Fig. 4.11
Configuration of
VSS
analog comparator
Address
Th e an alog com parator is ON wh en th e AMPON register is
"1", an d com pares th e in pu t levels of th e AMPP an d AMPM
term in als. Th e resu lt of th e com parison is read from th e
AMPDT register. It is "1" wh en AMPP (+) > AMPM (-) an d "0"
wh en AMPP (+) < AMPM (-).
Op e ra tion of a na log
c om p a ra tor
After th e an alog com parator goes ON it takes a m axim u m of
3 m s u n til th e ou tpu t stabilizes.
S1C62N33 TECHNICAL HARDWARE
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Analog Comparator)
Table 4.11 lists th e an alog com parator con trol bits an d th eir
addresses.
Control of a na log
c om p a ra tor
Table 4.11 Analog comparator control bits
Register
Address
Comment
*1
D3
D2
D1
D0
Name
SR
1
0
*7
*2
–
–
AMPDT AMPON
R/W
–
Unused *5
Unused *5
*2
1
–
R
F7H
+ > -
- > +
AMPDT
AMPON
Analog comparator data
0
ON
OFF
Analog comparator ON/OFF
*1 In itial valu e followin g in itial reset
*2 Not set in th e circu it
*3 Un defin ed
*5 Always "0" wh en bein g read
*6 Refer to m ain m an u al
*7 Page switch in g in I/ O m em ory is
n ot n ecessary
*4 Reset (0) im m ediately after bein g read
AMPON: Switch es th e an alog com parator ON an d OFF.
Analog comparator
Wh en "1" is written :
Wh en "0" is written :
Read-ou t:
Th e an alog com parator goes ON
Th e an alog com parator goes OFF
Valid
ON/OFF (F7H·D0)
Th e an alog com parator goes ON wh en "1" is written to
AMPON, an d OFF wh en "0" is written .
At in itial reset, AMPON is set to "0".
Reads ou t th e ou tpu t from th e an alog com parator.
AMPDT:
Analog comparator data
(F7H·D1)
Wh en "1" is read ou t: AMPP (+) > AMPM (-)
Wh en "0" is read ou t: AMPP (+) < AMPM (-)
Writin g:
In valid
AMPDT is "0" wh en th e in pu t level of th e in verted in pu t
term in al (AMPM) is greater th an th e in pu t level of th e
n on in verted in pu t term in al (AMPP); an d "1" wh en sm aller.
At in itial reset, AMPDT is set to "1".
(1) To redu ce cu rren t con su m ption , set th e an alog com para-
tor to OFF wh en it is n ot n ecessary.
Prog ra m m ing note s
(2) After settin g AMPON to "1", wait at least 3 m s for th e
operation of th e an alog com parator to stabilize before
readin g th e ou tpu t data of th e an alog cpm parator from
AMPDT.
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S1C62N33 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function)
4.12 Sup p ly Volta g e De te c tion (SVD) Circ uit
a nd He a vy Loa d Prote c tion Func tion
Th e S1C62N33 Series h as a bu ilt-in su pply voltage detection
Config ura tion of
SVD c irc uit
(SVD) circu it, so th at th e software can fin d wh en th e sou rce
voltage lowers. Th e con figu ration of th e SVD circu it is sh own
in Figu re 4.12.
Tu rn in g th e SVD operation ON/ OFF is con trolled th rou gh
th e software (HVLD, SVDON). Moreover, wh en a drop in
sou rce voltage (SVDDT = "1") is detected, SVD operation is
periodically perform ed by th e h ardware u n til th e sou rce
voltage is recovered (SVDDT = "0").
Becau se th e power cu rren t con su m ption of th e IC becom es
big wh en th e SVD operation is tu rn ed ON, set th e SVD
operation to OFF u n less oth erwise n ecessary.
See "7 ELECTRICAL CHARACTERISTICS" for th e evalu ation
voltage accu racy.
VDD
SVD circuit
Address 76H
HVLD
SVD
sampling
control
Address 76H
SVDON
Fig. 4.12
SVDDT
Configuration of SVD circuit
Detection output
VSS
S1C62N33 TECHNICAL HARDWARE
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function)
Note th at th e h eavy load protection fu n ction on th e
He a vy loa d p rote c -
S1C62L33 is differen t from th e S1C62N33.
tion func tion
(1) In case of S1C62L33
(S1C62L33)
Th e S1C62L33 h as th e h eavy load protection fu n ction for
wh en th e battery load becom es h eavy an d th e sou rce
voltage drops, su ch as wh en an extern al bu zzer sou n ds
or an extern al lam p ligh ts. Th e state wh ere th e h eavy
load protection fu n ction is in effect is called th e h eavy
load protection m ode. In th is m ode, operation with a
lower voltage th an n orm al is possible.
Th e n orm al m ode ch an ges to th e h eavy load protection
m ode in th e followin g two cases:
➀ Wh en th e software ch an ges th e m ode to th e h eavy load
protection m ode (HVLD = "1")
➀ Wh en su pply voltage drop (SVDDT = "1") in th e SVD
circu it is detected, th e m ode will au tom atically sh ift to
th e h eavy load protection m ode u n til th e su pply volt-
age is recovered (SVDDT = "0")
In th e h eavy load protection m ode, th e in tern ally regu -
lated voltage is gen erated by th e liqu id crystal driver
sou rce ou tpu t VL2 so as to operate th e in tern al circu it.
Con sequ en tly, m ore cu rren t is con su m ed in th e h eavy
load protection m ode th an in th e n orm al m ode. Un less it
is n ecessary, be carefu l n ot to set th e h eavy load protec-
tion m ode with th e software. Also, wh en th e SVD is to be
tu rn ed on du rin g operation in th e h eavy load protection
m ode, lim it th e ON tim e to 10 m s per secon d of operation
tim e.
(2) In case of S1C62N33/ 62A33
Th e S1C62N33/ 62A33 h as th e h eavy load protection
fu n ction for wh en th e battery load becom es h eavy an d
th e sou rce voltage ch an ges, su ch as wh en an extern al
bu zzer sou n ds or an extern al lam p ligh ts. Th e state
wh ere th e h eavy load protection fu n ction is in effect is
called th e h eavy load protection m ode. Com pared with
th e n orm al operation m ode, th is m ode can redu ce th e
ou tpu t voltage variation of th e con stan t voltage/ booster
voltage circu it of th e LCD system .
Th e n orm al m ode ch an ges to th e h eavy load protection
m ode in th e followin g case:
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S1C62N33 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function)
➀ Wh en th e software ch an ges th e m ode to th e h eavy load
protection m ode (HVLD = "1")
Th e h eavy load protection m ode switch es th e con stan t
voltage circu it of th e LCD system to th e h igh -stability
m ode from th e low cu rren t con su m ption m ode. Con se-
qu en tly, m ore cu rren t is con su m ed in th e h eavy load
protection m ode th an in th e n orm al m ode. Un less it is
n ecessary, be carefu l n ot to set th e h eavy load protection
m ode with th e software.
Th is section explain s th e tim in g for wh en th e SVD circu it
De te c tion tim ing of
writes th e resu lt of th e sou rce voltage detection to th e
SVD c irc uit
SVDDT latch .
Tu rn in g th e SVD operation ON/ OFF is con trolled th rou gh
th e software (HVLD, SVDON). Moreover, wh en a drop in
sou rce voltage (SVDON = "1") is detected, SVD operation is
periodically perform ed by th e h ardware u n til th e sou rce
voltage is recovered (SVDON = "0").
Th e resu lt of th e sou rce voltage detection is written to th e
SVDDT latch by th e SVD circu it, an d th is data can be read
ou t by th e software to fin d th e statu s of th e sou rce voltage.
Th ere are th ree m eth ods, explain ed below, for execu tin g th e
detection operation of th e SVD circu it.
(1) Sam plin g with HVLD set to "1"
Wh en HVLD is set to "1" an d SVD sam plin g execu ted, th e
detection resu lts can be written to th e SVDDT latch in
th e followin g two tim in gs.
➀ Im m ediately after th e tim e for on e in stru ction cycle
h as en ded im m ediately after HVLD = "1"
➀ Im m ediately after sam plin g in th e 2 Hz cycle ou tpu t by
th e clock tim er wh ile HVLD = "1"
Con sequ en tly, th e SVDDT latch data is loaded im m edi-
ately after HVLD h as been set to "1", an d at th e sam e
tim e th e n ew detection resu lt is written in 2 Hz cycles.
To obtain a stable SVD detection resu lt, th e SVD circu it
m u st be set to ON with at least 100 µs. Con sequ en tly,
wh en th e CPU system clock is fosc3 in S1C62A33, th e
detection resu lt at th e tim in g in ➀ above m ay be in valid
or in correct. (Wh en perform in g SVD detection u sin g th e
tim in g in ➀, be su re th at th e CPU system clock is fosc1.)
S1C62N33 TECHNICAL HARDWARE
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function)
(2) Sam plin g with SVDON set to "1"
Wh en SVDON is set to "1", SVD detection is execu ted. As
soon as SVDON is reset to "0" th e detection resu lt is
loaded to th e SVDDT latch . To obtain a stable SVD detec-
tion resu lt, th e SVD circu it m u st be set to ON with at
least 100 µs. Hen ce, to obtain th e SVD detection resu lt,
follow th e program m in g sequ en ce below.
0. Set HVLD to "1" (on ly wh en th e CPU system clock is
fosc3 in S1C62A33)
1. Set SVDON to "1"
2. Main tain at 100 µs m in im u m
3. Set SVDON to "0"
4. Read ou t SVDDT
5. Set HVLD to "0" (on ly wh en th e CPU system clock is
fosc3 in S1C62A33)
However, wh en a crystal oscillation clock (fosc1) is se-
lected for th e CPU system clock in S1C62N33, S1C62L33,
an d S1C62A33, th e in stru ction cycles are lon g en ou gh ,
so th at th ere is n o n eed for con cern abou t m ain tain in g
100 µs for th e SVDON = "1" with th e software.
(3) Sam plin g by h ardware wh en SVDDT latch is set to "1"
Wh en SVDDT latch is set to "1", th e detection resu lts can
be written to th e SVDDT latch in th e followin g two tim -
in gs (sam e as th at sam plin g with HVLD set to "1").
➀ Im m ediately after th e tim e for on e in stru ction cycle
h as en ded im m ediately after SVDDT = "1"
➀ Im m ediately after sam plin g in th e 2 Hz cycle ou tpu t by
th e clock tim er wh ile SVDDT = "1"
Con sequ en tly, th e SVDDT latch data is loaded im m edi-
ately after SVDDT latch h as been set to "1", an d at th e
sam e tim e th e n ew detection resu lt is written in 2 Hz
cycles.
To obtain a stable SVD detection resu lt, th e SVD circu it
m u st be set to ON with at least 100 µs.
Wh en th e CPU system clock is fosc3 in S1C62A33, th e
detection resu lt at th e tim in g in ➀ above m ay be in valid
or in correct.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function)
Table 4.12 sh ows th e SVD circu it's con trol bits an d th eir
Control of SVD c ir-
addresses.
c uit
Table 4.12 Control bits of SVD circuit
Register
Address
Comment
*1
D3
D2
SVDDT
SVDON
R
D1
D0
Name
HVLD
SR
0
1
0
*7
Heavy
load
HVLD
EISWIT1 EISWIT0
Normal Heavy load protection mode register
SVD evaluation data (at read-out)
Low voltage
ON
SVDDT
SVDON
0
0
Normal
R/W
R/W
SVD ON/OFF (at writing)
Interrupt mask register
(stopwatch 1 Hz)
W
OFF
76H
EISWIT1
EISWIT0
0
0
Enable
Enable
Mask
Interrupt mask register
(stopwatch 10 Hz)
Mask
*1 In itial valu e followin g in itial reset
*2 Not set in th e circu it
*3 Un defin ed
*5 Always "0" wh en bein g read
*6 Refer to m ain m an u al
*7 Page switch in g in I/ O m em ory is
n ot n ecessary
*4 Reset (0) im m ediately after bein g read
HVLD:
Heavy load protection
mode (76H·D3)
Wh en "1" is written :
Wh en "0" is written :
Heavy load protection m ode is set
Heavy load protection m ode
is released
Read-ou t:
Valid
Wh en HVLD is set to "1", th e IC operatin g statu s en ters th e
h eavy load protection m ode an d at th e sam e tim e th e su pply
voltage detection of th e SVD circu it is con trolled (ON/ OFF).
Wh en HVLD is set to "1", sam plin g con trol is execu ted for
th e SVD circu it ON tim e. Th ere are two types of sam plin g
tim e, as follows:
(1) Th e tim e of on e in stru ction cycle im m ediately after HVLD
= "1"
(2) Sam plin g at cycles of 2 Hz ou tpu t by th e clock tim er
wh ile HVLD = "1"
Th e SVD circu it m u st be m ade ON with at least 100 µs for
th e SVD circu it to respon d. Hen ce, wh en th e CPU system
clock is fosc3 in S1C62A33, th e detection resu lt at th e
tim in g in (1) above m ay be in valid or in correct. (Wh en per-
form in g SVD detection u sin g th e tim in g in (1), be su re th at
th e CPU system clock is fosc1.)
S1C62N33 TECHNICAL HARDWARE
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function)
Wh en SVD sam plin g is don e with HVLD set to "1", th e
resu lts are written to th e SVDDT latch in th e tim in g as
follows:
(1) As soon as th e tim e h as elapsed for on e in stru ction cycle
im m ediately followin g HVLD = "1"
(2) Im m ediately on com pletion of sam plin g at cycles of 2 Hz
ou tpu t by th e clock tim er wh ile HVLD = "1"
Con sequ en tly, th e SVDDT latch data is written im m ediately
after HVLD is set to "1", an d at th e sam e tim e th e n ew
detection resu lt is written in 2 Hz cycles.
SVDON/SVDDT:
SVD detection/SVD data
(76H·D2)
Wh en "0" is written :
Wh en "1" is written :
SVD detection OFF
SVD detection ON
Wh en "0" is read ou t: Sou rce voltage (VDD–VSS)
is h igh er th an SVD set valu e
Wh en "1" is read ou t: Sou rce voltage (VDD–VSS)
is lower th an SVD set valu e
Note th at th e fu n ction of th is bit wh en written is differen t to
wh en read ou t.
Wh en th is bit is written to, ON/ OFF of th e SVD detection
operation is con trolled; wh en th is bit is read ou t, th e resu lt of
th e SVD detection (con ten ts of SVDDT latch ) is obtain ed.
Appreciable cu rren t is con su m ed du rin g operation of SVD
detection , so keep SVD detection OFF except wh en n ecessary.
Wh en SVDON is set to "1", SVD detection is execu ted. As
soon as SVDON is reset to "0" th e detection resu lt is loaded
to th e SVDDT latch . To obtain a stable SVD detection resu lt,
th e SVD circu it m u st be set to ON with at least 100 µs.
Hen ce, to obtain th e SVD detection resu lt, follow th e pro-
gram m in g sequ en ce below.
0. Set HVLD to "1" (on ly wh en th e CPU system clock is
fosc3 in S1C62A33)
1. Set SVDON to "1"
2. Main tain at 100 µs m in im u m
3. Set SVDON to "0"
4. Read ou t SVDDT
5. Set HVLD to "0" (on ly wh en th e CPU system clock is
fosc3 in S1C62A33)
However, wh en a crystal oscillation clock (fosc1) is selected
for th e CPU system clock in S1C62N33, S1C62L33, an d
S1C62A33, th e in stru ction cycles are lon g en ou gh , so th at
th ere is n o n eed for con cern abou t m ain tain in g 100 µs for
th e SVDON = "1" with th e software.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function)
(1) It takes 100 µs from th e tim e th e SVD circu it goes ON
Prog ra m m ing note s
u n til a stable resu lt is obtain ed. For th is reason , keep th e
followin g software n otes in m in d:
➀ Wh en th e CPU system clock is fosc1
1. Wh en detection is don e at HVLD
After writin g "1" on HVLD, read th e SVDDT after 1
in stru ction h as passed.
2. Wh en detection is don e at SVDON
After writin g "1" on SVDON, write "0" after at least
100 µs h as lapsed (possible with th e n ext in stru c-
tion ) an d th en read th e SVDDT.
➀ Wh en th e CPU system clock is fosc3 (in case of
S1C62A33 on ly)
1. Wh en detection is don e at HVLD
After writin g "1" on HVLD, read th e SVDDT after 0.6
sec h as passed. (HVLD h olds "1" for at least 0.6 sec)
2. Wh en detection is don e at SVDON
Before writin g "1" on SVDON, write "1" on HVLD
first; after at least 100 µs h as lapsed after writin g
"1" on SVDON, write "0" on SVDON an d th en read
th e SVDDT.
(2) SVDON resides in th e sam e bit at th e sam e address as
SVDDT, an d on e or th e oth er is selected by write or read
operation . Wh en writin g a "1" to SVDON u se th e OR
com m an d, an d wh en writin g a "0" u se th e AND com m an d.
No oth er com m an ds sh ou ld be u sed for th is pu rpose.
(3) Select on e of th e followin g software processin g to retu rn
to th e n orm al m ode after a h eavy load h as been driven in
th e h eavy load protection m ode (S1C62L33).
➀ After h eavy load drive is com pleted, retu rn to th e
n orm al m ode after at least on e secon d h as elapsed.
➀ After h eavy load drive is com pleted, switch SVD ON
an d OFF (at least 100 µs is n ecessary for th e ON
statu s) an d th en retu rn to th e n orm al m ode.
Th e S1C62N33/ 62A33 retu rn s to th e n orm al m ode after
drivin g a h eavy load with ou t special software processin g.
(4) Wh en th e SVD is to be tu rn ed on du rin g operation in th e
h eavy load protection m ode, lim it th e ON tim e to 10 m s
per secon d of operation tim e.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
4.13 Se ria l Inte rfa c e (SIN, SOUT, SCLK, SIOF)
Th e S1C62N33 h as a syn ch ron ou s clock type 8 bits serial
in terface bu ilt-in .
Config ura tion of
se ria l inte rfa c e
Th e con figu ration of th e serial in terface is sh own in Figu re
4.13.1.
Th e CPU, via th e 8 bits sh ift register, can read th e serial
in pu t data from th e SIN term in al. Moreover, via th e sam e 8
bits sh ift register, it can con vert parallel data to serial data
an d ou tpu t it to th e SOUT term in al.
Th e syn ch ron ou s clock for serial data in pu t/ ou tpu t m ay be
set by selectin g by software an y on e of 3 types of m aster
m ode (in tern al clock m ode: wh en th e S1C62N33 is to be th e
m aster for serial in pu t/ ou tpu t) an d a type of slave m ode
(extern al clock m ode: wh en th e S1C62N33 is to be th e slave
for serial in pu t/ ou tpu t).
Also, wh en th e serial in terface is u sed at slave m ode, SIOF
sign al wh ich in dicates wh eth er or n ot th e serial in terface is
available to tran sm it or receive ou tpu t to ou tpu t port SIOF.
SD0–SD7
SOUT
SIN
Shift register (8 bits)
Output
latch
SCS0 SCS1
SEN
Serial clock
selector
Serial clock
counter
Serial interface
interrupt control circuit
ISIO
SCLK
Serial clock
generator
System clock
EISIO
Serial interface
activating circuit
Fig. 4.13.1
Configuration of
serial interface
SIOF
SCTRG
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
Th e serial in terface of th e S1C62N33 h as two types of opera-
tion m ode: m aster m ode an d slave m ode.
Ma ste r m od e a nd
sla ve m od e of
se ria l inte rfa c e
In th e m aster m ode, it u ses an in tern al clock as syn ch ro-
n ou s clock of th e bu ilt-in sh ift register, gen erates th is
in tern al clock at th e SCLK term in al an d con trols th e exter-
n al (slave side) serial device.
In th e slave m ode, th e syn ch ron ou s clock ou tpu t from th e
extern al (m aster side) serial device is in pu t from th e SCLK
term in al an d u ses it as th e syn ch ron ou s clock to th e bu ilt-
in sh ift register.
Th e m aster m ode an d slave m ode are selected by writin g
data to registers SCS1 an d SCS0 (address F2H·D2, D3).
Wh en th e m aster m ode is selected, a syn ch ron ou s clock
m ay be selected from am on g 3 types as sh own in Table
4.13.1.
Table 4.13.1
Synchronous clock selection
SCS1
SCS0
Mode
Synchronous Clock
CLK
0
0
1
1
0
1
0
1
Master mode
Slave mode
CLK/2
CLK/4
External clock
CLK: system clock
At in itial reset, th e slave m ode (extern al clock m ode) is
selected.
Moreover, th e syn ch ron ou s clock, alon g with th e in pu t
/ ou tpu t of th e 8 bits serial data, is con trolled as follows:
• At m aster m ode, after ou tpu t of 8 clocks from th e SCLK
term in al, clock ou tpu t is au tom atically su spen ded an d
SCLK term in al is fixed at low level.
• At slave m ode, after in pu t of 8 clocks to th e SCLK term i-
n al, su bsequ en t clock in pu ts are m asked.
Note When using the serial interface in the master mode, CPU system
clock is used as the synchronous clock. Accordingly, when the
serial interface is operating, system clock switching (fosc1 ↔ fosc3)
should not be performed.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
A sam ple basic serial in pu t/ ou tpu t portion con n ection is
sh own in Figu re 4.13.2.
S1C62N33
SCLK
External serial
device
CLK
SOUT
SOUT
SIN
SIN
Input terminal
READY
a. Master m ode
S1C62N33
SCLK
External serial
device
CLK
SOUT
SIN
SOUT
SIN
Fig. 4.13.2
Sample basic connection of
serial input/output section
SIOF
Input terminal
b. Slave m ode
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Th e serial in terface of S1C62N33 can in pu t/ ou tpu t data via
th e in tern al 8 bits sh ift register. Th e sh ift register operates
by syn ch ron izin g with eith er th e syn ch ron ou s clock ou tpu t
from SCLK term in al (m aster m ode), or th e syn ch ron ou s
clock in pu t to SCLK (slave m ode).
Da ta inp ut/ outp ut
a nd inte rrup t func -
tion
Th e serial in terface gen erates in terru pt on com pletion of th e
8 bits serial data in pu t/ ou tpu t. Detection of serial data
in pu t/ ou tpu t is don e by th e cou n tin g of th e syn ch ron ou s
clock (SCLK); th e clock com pletes in pu t/ ou tpu t operation
wh en 8 cou n ts (equ ivalen t to 8 cycles) h ave been m ade an d
th en gen erates in terru pt.
Th e serial data in pu t/ ou tpu t procedu re data is explain ed
below:
(1) Serial data output procedure and interrupt
Th e S1C62N33 serial in terface is capable of ou tpu ttin g
parallel data as serial data, in u n its of 8 bits.
By settin g th e parallel data to 4 bits registers SD0–SD3
(address F0H) an d SD4–SD7 (address F1H) in dividu ally
an d writin g "1" to SCTRG bit (address 77H·D3), it syn -
ch ron izes with th e syn ch ron ou s clock an d serial data is
ou tpu t at th e SOUT term in al. Th e syn ch ron ou s clock
u sed h ere is as follows: in th e m aster m ode, in tern al
clock wh ich is ou tpu t to th e SCLK term in al wh ile in th e
slave m ode, extern al clock wh ich is in pu t from th e SCLK
term in al. Th e serial ou tpu t of th e SOUT term in a ch an ges
with th e risin g edge of th e clock th at is in pu t or ou tpu t
from th e SCLK term in al.
Th e serial data to th e bu ilt-in sh ift register is sh ifted with
th e risin g edge of th e SCLK sign al wh en SE2 bit (address
F2H·D1) is "1" an d is sh ifted with th e fallin g edge of th e
SCLK sign al wh en SE2 bit (address F2H·D1) is "0".
Wh en th e ou tpu t of th e 8 bits data from SD0 to SD7 is
com pleted, th e in terru pt factor flag ISIO (address
F3H·D0) is set to "1" an d in terru pt is gen erated. Moreo-
ver, th e in terru pt can be m asked by th e in terru pt m ask
register EISIO (address F2H·D0).
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(2) Serial data input procedure and interrupt
Th e S1C62N33 serial in terface is capable of in pu ttin g
serial data as parallel data, in u n its of 8 bits.
Th e serial data is in pu t from th e SIN term in al, syn ch ro-
n izes with th e syn ch ron ou s clock, an d is sequ en tially
read in th e 8 bits sh ift register. As in th e above item (1),
th e syn ch ron ou s clock u sed h ere is as follows: in th e
m aster m ode, in tern al clock wh ich is ou tpu t to th e SCLK
term in al wh ile in th e slave m ode, extern al clock wh ich is
in pu t from th e SCLK term in al.
Th e serial data to th e bu ilt-in sh ift register is read with
th e risin g edge of th e SCLK sign al wh en SE2 bit is "1"
an d is read with th e fallin g edge of th e SCLK sign al wh en
SE2 bit is "0". Moreover, th e sh ift register is sequ en tially
sh ifted as th e data is fetch ed.
Wh en th e in pu t of th e 8 bits data from SD0 to SD7 is
com pleted, th e in terru pt factor flag ISIO is set to "1" an d
in terru pt is gen erated. Moreover, th e in terru pt can be
m asked by th e in terru pt m ask register EISIO. Note,
h owever, th at regardless of th e settin g of th e in terru pt
m ask register, th e in terru pt factor flag is set to "1" after
in pu t of th e 8 bits data.
Th e data in pu t in th e sh ift register can be read from data
registers SD0–SD7 by software.
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(3) Serial data input/output permutation
S1C62N33 allows th e in pu t/ ou tpu t perm u tation of serial
data to be selected by m ask option as to eith er LSB first
or MSB first. Th e block diagram sh owin g in pu t/ ou tpu t
perm u tation in case of LSB first an d MSB first is provided
in Figu re 4.13.3.
Address F1H
Address F0H
SIN
SIN
SD7 SD6 SD5 SD4
SD3 SD2 SD1 SD0
Output
latch
SOUT
(In case of LSB first)
Address F0H
Address F1H
Fig. 4.13.3
Serial data input/output
permutation
SD4 SD5 SD6 SD7
Output
latch
SD0 SD1 SD2 SD3
SOUT
(In case of MSB first)
(4) SIOF signal
Wh en th e S1C62N33 serial in terface is u sed in th e slave
m ode (extern al clock m ode), SIOF is u sed to in dicate
wh eth er th e in tern al serial in terface is available to tran s-
m it or receive data for th e m aster side (extern al) serial
device.
SIOF sign al becom es "1" (h igh ) wh en th e S1C62N33 serial
in terface becom es available to tran sm it or receive data;
n orm ally, it is at "0" (low).
SIOF sign al ch an ges from "0" to "1" im m ediately after "1"
is written to SCTRG an d retu rn s from "1" to "0" wh en
eigh t syn ch ron ou s clock h as been cou n ted.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
(5) Timing chart
Th e S1C62N33 serial in terface tim in g ch art is sh own in
Figu re 4.13.4.
SCTRG
SCLK
SIN
8-BIT SHIFT REGISTER
SOUT
ISIO
SIOF
a. Tim in g ch art, SE2 = "1"
SCTRG
SCLK
SIN
8-BIT SHIFT REGISTER
SOUT
ISIO
SIOF
b. Tim in g ch art, SE2 = "0"
Fig. 4.13.4
Serial interface timing chart
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Th e serial in terface m ay be selected for th e followin g by
m ask option .
Ma sk op tion
(1) Wh eth er or n ot th e SIN term in al will u se bu ilt-in pu ll
down resistor m ay be selected.
If th e u se of n o pu ll down resistor is selected, take care
th at floatin g state does n ot occu r at th e SIN term in al.
Wh en th e SIN term in al is n ot u sed, th e u se of pu ll down
resistor sh ou ld be selected.
(2) Eith er com plem en tary ou tpu t or P ch an n el (Pch ) open
drain as ou tpu t specification for th e SOUT term in al m ay
be selected.
However, even if Pch open drain h as been selected, appli-
cation of voltage exceedin g power sou rce voltage to th e
SOUT term in al will be proh ibited.
(3) Wh eth er or n ot th e SCLK term in al will u se pu ll down
resistor wh ich is tu rn ed ON du rin g in pu t m ode (extern al
clock) m ay be selected.
If th e u se of n o pu ll down resistor is selected, take care
th at floatin g state does n ot occu r at th e SCLK term in al
du rin g in pu t m ode.
Norm ally, th e u se of pu ll down resistor sh ou ld be se-
lected.
(4) As ou tpu t specification du rin g ou tpu t m ode, eith er com -
plem en tary ou tpu t or P ch an n el (Pch ) open drain ou tpu t
m ay be selected for th e SCLK term in al.
(5) Positive or n egative logic can be selected for th e sign al
logic of th e SCLK pin (SCLK or SCLK).
However, keep in m in d th at on ly pu ll-down resistan ce
can be set for th e in pu t m ode (pu ll-u p resistan ce is n ot
bu ilt-in ).
(6) LSB first or MSB first as in pu t/ ou tpu t perm u tation of
serial data m ay be selected.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
Table 4.13.2 lists th e serial in terface con trol bits an d th eir
addresses.
Control of se ria l
inte rfa c e
Table 4.13.2 Control registers of serial interface
Register
Address
Comment
*1
D3
D2
D1
D0
Name
SD3
SR
1
0
*7
*3
SD3
SD2
SD1
SD0
×
*3
*3
*3
*3
*3
*3
*3
R/W
R/W
R/W
SD2
SD1
SD0
SD7
SD6
SD5
SD4
×
×
×
×
×
×
×
1
Serial interface data regsiter
Low order (SD0–SD3)
F0H
SD7
SD6
SD5
SD4
Serial interface data regsiter
High order (SD4–SD7)
F1H
*6
*6
*6
*6
SCS1
SCS0
SE2
EISIO
SCS1
SCS0
SE2
Clock mode selection register
(SCS0, SCS1)
1
F2H
Rising
Enable
Falling
Mask
Clock edge selection register
0
EISIO
0
Interrupt mask register (serial interface)
Unused *5
–
–
–
ISIO
–
–
*2
*2
*2
0
R
Unused *5
F3H
Unused *5
–
Interrupt factor flag (serial interface) *4
ISIO
Yes
No
Serial interface clock trigger
SIOF
SCTRG
SIOF
–
Trigger
RUN
–
SCTRG
SIOF
EIK10
DFK10
K10
R
0
STOP
W
R
R/W
EIK10
DFK10
K10
0
0
Enable
Falling
High
Mask
Rising
Low
Interrupt mask register (K10)
Input comparison register (K10)
Input port (K10)
77H
*2
*1 In itial valu e followin g in itial reset
*2 Not set in th e circu it
*3 Un defin ed
*5 Always "0" wh en bein g read
*6 Refer to m ain m an u al
*7 Page switch in g in I/ O m em ory is
n ot n ecessary
*4 Reset (0) im m ediately after bein g read
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
SD0–SD3, SD4–SD7: Th ese registers are u sed for writin g an d readin g serial data.
Serial interface data
• During writing operation
registers
(F0H, F1H)
Wh en "1" is written :
Wh en "0" is written :
High level
Low level
Writes serial data will be ou tpu t to SOUT term in al. From th e
SOUT term in al, th e data con verted to serial data as h igh
(VDD) level bit for bits set at "1" an d as low (VSS) level bit for
bits set at "0".
• During reading operation
Wh en "1" is read ou t: High level
Wh en "0" is read ou t: Low level
Th e serial data in pu t from th e SIN term in al can be read by
th is register.
Th e data con verted to parallel data, as h igh (VDD) level bit "1"
an d as low (VSS) level bit "0" in pu t from SIN term in al. Per-
form data readin g on ly wh ile th e serial in terface is h alted
(i.e., th e syn ch ron ou s clock is n eith er bein g in pu t or ou tpu t).
At in itial reset, th ese registers will be u n defin ed.
SCS1, SCS0:
Clock mode selection
register
Selects th e syn ch ron ou s clock for th e serial in terface
(SCLK).
(F2H·D3, D2)
SCS1
SCS0
Mode
Synchronous Clock
CLK
Table 4.13.3
0
0
1
1
0
1
0
1
Synchronous clock selection
Master mode
Slave mode
CLK/2
CLK/4
External clock
CLK: system clock
Syn ch ron ou s clock (SCLK) is selected from am on g th e above
4 types: 3 types of in tern al clock an d extern al clock.
At in itial reset, extern al clock is selected.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
SE2: Selects th e tim in g for readin g in th e serial data in pu t.
Clock edge selection
register
Wh en "1" is written :
Wh en "0" is written :
Read-ou t:
Risin g edge of SCLK
Fallin g edge of SCLK
Valid
(F2H·D1)
Selects wh eth er th e fetch in g for th e serial in pu t data to
registers (SD0–SD7) at th e risin g edge (at "1" writin g) or
fallin g edge (at "0" writin g) of th e SCLK sign al.
Pay atten tion if th e syn ch ton ou s clock goes in to reverse
ph ase (SCLK → SCLK) th rou gh th e m ask option .
SCLK risin g = SCLK fallin g, SCLK fallin g = SCLK risin g
Wh en th e in tern al clock is selected as th e syn ch ron ou s
clock (SCLK), a h azard occu rs in th e syn ch ron ou s clock
(SCLK) wh en data is written to register SE2.
Th e in pu t data fetch in g tim in g m ay be selected bu t ou tpu t
tim in g for ou tpu t data is fixed at SCLK risin g edge.
At in itial reset, fallin g edge of SCLK (SE2 = "0") is selected.
Th is is th e in terru pt m ask register of th e serial in terface.
EISIO:
Interrupt mask register
(F2H·D0)
Wh en "1" is written :
Wh en "0" is written :
Read-ou t:
En abled
Masked
Valid
At in itial reset, th is register is set to "0" (m ask).
ISIO: Th is is th e in terru pt factor flag of th e serial in terface.
Interrupt factor flag
(F3H·D0)
Wh en "1" is read ou t: In terru pt h as occu rred
Wh en "0" is read ou t: In terru pt h as n ot occu rred
Writin g:
In valid
From th e statu s of th is flag, th e software can decide wh eth er
th e serial in terface in terru pt.
Th e in terru pt factor flag is reset wh en it h as been read ou t.
Note, h owever, th at even if th e in terru pt is m asked, th is flag
will be set to "1" after th e 8 bits data in pu t/ ou tpu t.
Be su re th at th e in terru pt factor flag readin g is don e with
th e in terru pt in th e DI statu s (in terru pt flag = "0").
At in itial reset, th is flag is set to "0".
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SCTRG: Th is is a trigger to start in pu t/ ou tpu t of syn ch ron ou s clock.
Clock trigger
Wh en "1" is written :
Wh en "0" is written :
Read-ou t:
Trigger
(77H·D3)
No operation
SIOF
Wh en th is trigger is su pplied to th e serial in terface activat-
in g circu it, th e syn ch ron ou s clock (SCLK) in pu t/ ou tpu t is
started.
As a trigger con dition , it is requ ired th at data writin g or
readin g on data registers SD0–SD7 be perform ed prior to
writin g "1" to SCTRG. (Th e in tern al circu it of th e serial
in terface is in itiated th rou gh data writin g/ readin g on data
registers SD0–SD7.)
Su pply trigger on ly on ce every tim e th e serial in terface is
placed in th e RUN state. Refrain from perfom in g trigger
in pu t m u ltiple tim es, as leads to m alfu n ction in g.
Moreover, wh en th e syn ch ron ou s clock SCLK is extern al
clock, start to in pu t th e extern al clock after th e trigger.
SCTRG resides in th e sam e bit at th e sam e address as SIOF,
an d on e or th e oth er is selected by write or read operation .
Wh en writin g a "1" to SCTRG u se th e OR com m an d, an d
wh en writin g a "0" u se th e AND com m an d. No oth er com -
m an ds sh ou ld be u sed for th is pu rpose.
In dicates th e ru n n in g statu s of th e serial in terface.
SIOF:
Serial interface running
status
Wh en "1" is read ou t: RUN statu s
Wh en "0" is read ou t: STOP statu s
(77H·D3)
Writin g:
SCTRG
Th e RUN statu s is in dicated from im m ediatery after "1" is
written to SCTRG bit th rou gh to th e en d of serial data in -
pu t/ ou tpu t.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
(1) If th e bit data of SE2 ch an ges wh ile SCLK is in th e m as-
Prog ra m m ing note s
ter m ode, a h azard will be ou tpu t to th e SCLK pin . If th is
poses a problem for th e system , be su re to set th e SCLK
to th e extern al clock if th e bit data of SE2 is to be
ch an ged.
(2) Be su re th at read-ou t of th e in terru pt factor flag (ISIO) is
don e on ly wh en th e serial port is in th e STOP statu s
(SIOF = "0") an d th e DI statu s (in terru pt flag = "0"). If
read-ou t is perform ed wh ile th e serial data is in th e RUN
statu s (du rin g in pu t or ou tpu t), th e data in pu t or ou tpu t
will be su spen ded an d th e in itial statu s resu m ed. Read-
ou t du rin g th e EI statu s (in terru pt flag = "1") cau ses
m alfu n ction in g.
(3) Wh en u sin g th e serial in terface in th e m aster m ode, th e
syn ch ron ou s clock u ses th e CPU system clock. Accord-
in gly, do n ot ch an ge th e system clock (fosc1 ↔ fosc3)
wh ile th e serial in terface is operatin g.
(4) Perform data writin g/ readin g to data registers SD0–SD7
on ly wh ile th e serial in terface is h alted (i.e., th e syn ch ro-
n ou s clock is n eith er bein g in pu t or ou tpu t).
(5) As a trigger con dition , it is requ ired th at data writin g or
readin g on data registers SD0–SD7 be perform ed prior to
writin g "1" to SCTRG. (Th e in tern al circu it of th e serial
in terface is in itiated th rou gh data writin g/ readin g on
data registers SD0–SD7.) Su pply trigger on ly on ce every
tim e th e serial in terface is placed in th e RUN state. More-
over, wh en th e syn ch ron ou s clock SCLK is extern al clock,
start to in pu t th e extern al clock after th e trigger.
(6) Writin g to th e in terru pt m ask registers can be don e on ly
in th e DI statu s (in terru pt flag = "0").
Writin g du rin g EI statu s will cau se m alfu n ction .
(7) SCTRG resides in th e sam e bit at th e sam e address as
SIOF, an d on e or th e oth er is selected by write or read
operation . Wh en writin g a "1" to SCTRG u se th e OR
com m an d, an d wh en writin g a "0" u se th e AND com -
m an d. No oth er com m an ds sh ou ld be u sed for th is pu r-
pose.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)
4.14 Inte rrup t a nd HALT
Th e S1C62N33 Series provides th e followin g in terru pt set-
tin gs, each of wh ich is m askable.
Extern al in terru pt:
In tern al in terru pt:
In pu t in terru pt (two)
Tim er in terru pt (th ree)
Stopwatch in terru pt (two)
Serial in terface in terru pt (on e)
To au th orize in terru pt, th e in terru pt flag m u st be set to "1"
(EI) an d th e n ecessary related in terru pt m ask registers m u st
be set to "1" (en able).
Wh en an in terru pt occu rs th e in terru pt flag is au tom atically
reset to "0" (DI), an d in terru pts after th at are in h ibited.
Wh en a HALT in stru ction is in pu t th e CPU operatin g clock
stops, an d th e CPU en ters th e HALT statu s.
Th e CPU is reactivated from th e HALT statu s wh en an in ter-
ru pt requ est occu rs.
If reactivation is n ot cau sed by an in terru pt requ est, in itial
reset by th e watch dog tim er cau ses reactivates th e CPU
(wh en th e watch dog tim er is en abled).
Figu re 4.14 sh ows th e con figu ration of th e in terru pt circu it.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)
SWIT1
EISWIT1
SWIT0
EISWIT0
Interrupt vector
TI2
ETI2
(MSB)
TI8
Program counter
(four low-order bits)
ETI8
TI32
ETI32
(LSB)
K00
DFK00
EIK00
EIK01
EIK02
EIK03
INT
K01
(interrupt request)
DFK01
IK0
K02
DFK02
K03
DFK03
K10
Interrupt factor flag
DFK10
IK1
EIK10
Interrupt mask register
Differential register
ISIO
EISIO
Fig. 4.14
Configuration of
interrupt circuit
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)
Table 4.14.1 sh ows th e factors for gen eratin g in terru pt
requ ests.
Inte rrup t fa c tors
Th e in terru pt flags are set to "1" depen din g on th e corre-
spon din g in terru pt factors.
Th e CPU operation is in terru pted wh en an y of th e con dition s
below set an in terru pt factor flag to "1".
• Th e correspon din g m ask register is "1" (en abled)
• Th e in terru pt flag is "1" (EI)
Th e in terru pt factor flag is a read-on ly register, bu t can be
reset to "0" wh en th e register data is read ou t.
At in itial reset, th e in terru pt factor flags are reset to "0".
Note Read the interrupt factor flags only in the DI status (interrupt flag =
"0").
A malfunction could result from read-out during the EI status
(interrupt flag = "1").
Table 4.14.1
Interrupt Factor
Clock timer 2 Hz falling edge
Clock timer 8 Hz falling edge
Clock timer 32 Hz falling edge
Stopwatch counter
Interrupt Factor Flag
Interrupt factors
(79H D2)
(79H D1)
(79H D0)
(7AH D1)
TI2
TI8
TI32
SWIT1
1 Hz falling edge
(7AH D0)
(7AH D2)
(7AH D3)
(F3H D0)
Stopwatch counter
SWIT0
IK0
10 Hz falling edge
Input data (K00–K03)
Rising or falling edge
Input data (K10)
IK1
Rising or falling edge
Serial interface
ISIO
Data (8 bits) input/output has completed
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)
Th e in terru pt factor flags can be m asked by th e correspon d-
Sp e c ific m a sks a nd
fa c tor fla g s for inte r-
rup t
in g in terru pt m ask registers.
Th e in terru pt m ask registers are read/ write registers. Th ey
are en abled (in terru pt au th orized) wh en "1" is written to
th em , an d m asked (in terru pt in h ibited) wh en "0" is written
to th em .
At in itial reset, th e in terru pt m ask register is set to "0".
Table 4.14.2 sh ows th e correspon den ce between in terru pt
m ask registers an d in terru pt factor flags.
Note Writing to the interrupt mask registers can be done only in the DI
status (interrupt flag = "0").
A malfunction could result from writing during the EI status.
Table 4.14.2
Interrupt mask registers and
interrupt factor flags
Interrupt Mask Register
Interrupt Factor Flag
ETI2
(78H D2)
(78H D1)
(78H D0)
(76H D1)
(76H D0)
(F2H D0)
(75H D3)
(75H D2)
(75H D1)
(75H D0)
(77H D2)
TI2
(79H D2)
(79H D1)
(79H D0)
(7AH D1)
(7AH D0)
(F3H D0)
ETI8
TI8
ETI32
EISWIT1
EISWIT0
EISIO
EIK03
EIK02
EIK01
EIK00
EIK10
TI32
SWIT1
SWIT0
ISIO
IK0
IK1
(7AH D2)
(7AH D3)
* Th ere is an in terru pt m ask register for each pin
of th e in pu t ports.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)
Wh en an in terru pt requ est is in pu t to th e CPU, th e CPU
begin s in terru pt processin g. After th e program bein g exe-
cu ted is term in ated, th e in terru pt processin g is execu ted in
th e followin g order.
Inte rrup t ve c tors
➀ Th e address data (valu e of program cou n ter) of th e pro-
gram to be execu ted n ext is saved in th e stack area
(RAM).
➀ Th e in terru pt requ est cau ses th e valu e of th e in terru pt
vector (page 1, 01H–0FH) to be set in th e program cou n -
ter.
➀ Th e program at th e specified address is execu ted (execu -
tion of in terru pt processin g rou tin e by software).
Table 4.14.3 sh ows th e correspon den ce of in terru pt requ ests
an d in terru pt vectors.
The processing in ➀ and ➀ above take 12 cycles of the CPU
Note
system clock.
Table 4.14.3
Interrupt request and
interrupt vectors
PC
Value
Interrupt Request
Stopwatch interrupt
PCS3
1
0
1
0
1
0
1
0
Enabled
Masked
Enabled
Masked
Enabled
Masked
Enabled
Masked
Stopwatch interrupt
PCS2
PCS1
PCS0
Timer interrupt
Timer interrupt
Input (K00–K03, K10) interrupt
Input (K00–K03, K10) interrupt
Serial interface interrupt
Serial interface interrupt
Th e fou r low-order bits of th e program cou n ter are in directly
addressed th rou gh th e in terru pt requ est.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)
Tables 4.14.4(a) an d (b) sh ow th e in terru pt con trol bits an d
th eir addresses.
Control of inte rrup t
a nd HALT
Table 4.14.4(a) Interrupt control bits (1)
Register
Address
Comment
*1
D3
D2
D1
D0
Name
DFK03
SR
0
1
0
*7
DFK03
DFK02
DFK01
DFK00
Falling
Rising
R/W
DFK02
DFK01
DFK00
EIK03
EIK02
EIK01
EIK00
HVLD
0
0
0
0
0
0
0
0
Falling
Falling
Falling
Enable
Enable
Enable
Enable
Rising
Rising
Rising
Mask
Mask
Mask
Mask
Differential register
74H
(K00–K03)
EIK03
EIK02
EIK01
EIK00
Interrupt mask register
(K00–K03)
R/W
75H
76H
SVDDT
SVDON
R
Heavy
load
HVLD
R/W
EISWIT1 EISWIT0
R/W
Normal Heavy load protection mode register
SVD evaluation data (at read-out)
Low voltage
ON
SVDDT
SVDON
0
0
Normal
SVD ON/OFF (at writing)
Interrupt mask register
(stopwatch 1 Hz)
W
OFF
EISWIT1
EISWIT0
0
0
Enable
Enable
Mask
Interrupt mask register
(stopwatch 10 Hz)
Serial interface clock trigger
SIOF
Mask
Trigger
Run
SCTRG
SIOF
–
0
–
SCTRG
SIOF
W
EIK10
DFK10
K10
R
Stop
EIK10
DFK10
K10
0
0
Enable
Falling
High
Mask
Rising
Low
Interrupt mask register (K10)
Differential register (K10)
Input port (K10)
R/W
R
77H
*2
*1 In itial valu e followin g in itial reset
*2 Not set in th e circu it
*3 Un defin ed
*5 Always "0" wh en bein g read
*6 Refer to m ain m an u al
*7 Page switch in g in I/ O m em ory is
n ot n ecessary
*4 Reset (0) im m ediately after bein g read
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)
Table 4.14.4(b) Interrupt control bits (2)
Register
Address
*7
Comment
*1
D3
D2
D1
D0
Name
CSDC
SR
0
1
0
CSDC
ETI2
ETI8
ETI32
Static
Dynamic LCD drive switch
R/W
Interrupt mask register (clock timer 2 Hz)
Interrupt mask register (clock timer 8 Hz)
Interrupt mask register (clock timer 32 Hz)
Unused *5
ETI2
ETI8
ETI32
–
0
0
Enable
Enable
Enable
Mask
Mask
Mask
78H
79H
7AH
F2H
F3H
0
*2
0
–
IK1
SCS1
–
TI2
TI8
TI32
SWIT0
EISIO
ISIO
R
TI2
Yes
Yes
No
No
Interrupt factor flag (clock timer 2 Hz) *4
Interrupt factor flag (clock timer 8 Hz) *4
Interrupt factor flag (clock timer 32 Hz) *4
Interrupt factor flag (K10) *4
TI8
0
TI32
0
Yes
No
IK0
SWIT1
IK1
IK0
0
Yes
No
Interrupt factor flag (K00–K03) *4
Interrupt factor flag (stopwatch 1 Hz) *4
Interrupt factor flag (stopwatch 10 Hz) *4
R
0
Yes
No
SWIT1
SWIT0
SCS1
SCS0
SE2
EISIO
–
0
Yes
No
0
Yes
No
SCS0
SE2
1
1
*6
*6
Clock edge selection register
(SCS0, SCS1)
R/W
*6
*6
Clock edge selection register
Interrupt mask register (serial interface)
Unused *5
0
Rising
Enable
Falling
Mask
0
–
–
*2
*2
*2
0
R
–
Unused *5
–
Unused *5
ISIO
Yes
No
Interrupt factor flag (serial interface) *4
*1 In itial valu e followin g in itial reset
*2 Not set in th e circu it
*3 Un defin ed
*5 Always "0" wh en bein g read
*6 Refer to m ain m an u al
*7 Page switch in g in I/ O m em ory is
n ot n ecessary
*4 Reset (0) im m ediately after bein g read
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)
– ETI32, ETI8, ETI2: Interrupt mask registers (78H·D0–D2)
– TI32, TI8, TI2: Interrupt factor flags (79H·D0–D2)
See "Con trol of clock tim er".
– EISWIT0, EISWIT1: Interrupt mask registers (76H·D0, D1)
– SWIT0, SWIT1: Interrupt factor flags (7AH·D0, D1)
See "Con trol of stopwatch cou n ter".
– EISIO: Interrupt mask register (F2H·D0)
– ISIO: Interrupt factor flag (F3H·D0)
See "Con trol of serial in terface".
– DFK00–DFK03: Differential registers (74H)
– EIK00–EIK03: Interrupt mask registers (75H)
– IK0: Interrupt factor flag (7AH·D2)
See "Con trol of in pu t ports".
– DFK10: Differential register (77H·D1)
– EIK10: Interrupt mask register (77H·D2)
– IK1: Interrupt factor flag (7AH·D3)
See "Con trol of in pu t ports".
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)
(1) Wh en th e in terru pt m ask register (EIK) is set to "0", th e
in terru pt factor flag (IK) of th e in pu t port can n ot be set
even th ou gh th e pin statu s of th e in pu t port h as ch an ged.
Prog ra m m ing note s
(2) Th e in terru pt factor flags of th e clock tim er an d stop-
watch cou n ter (TI, SWIT) are set wh en th e tim in g con di-
tion is establish ed, even if th e in terru pt m ask registers
(ETI, EISWIT) are set to "0".
(3) Read ou t th e in terru pt factor flags on ly in th e DI statu s
(in terru pt flag = "0"). If read-ou t is perform ed in th e EI
statu s a m alfu n ction will resu lt.
(4) Writin g to th e in terru pt m ask registers can be don e on ly
in th e DI statu s (in terru pt flag = "0").
Writin g du rin g EI statu s will cau se m alfu n ction .
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CHAPTER 5: SUMMARY OF NOTES
CHAPTER 5
SUMMARY OF NOTES
5.1 Note s for Low Curre nt Consum p tion
Th e S1C62N33 Series con tain s con trol registers for each of
th e circu its so th at cu rren t con su m ption can be lowered.
Th ese con trol registers lower th e cu rren t con su m ption
th rou gh program s th at operate th e circu its at th e m in im u m
levels.
Th e followin g text explain s th e circu its th at can con trol
operation an d th eir con trol registers. Refer to th ese wh en
pu ttin g program s togeth er.
Table 5.1 Circuits and control registers
Circuits (and Items)
CPU
Control Registers
Order of Consumed Current
HALT instruction See electrical characteristics (Chapter 7)
CLKCHG, OSCC See electrical characteristics (Chapter 7)
CPU operation frequency
(SMC62A33)
Heavy load protection mode HVLD
See electrical characteristics (Chapter 7)
Several tens µA
SVD circuit
HVLD, SVDON
AMPON
Analog comparator
Several tens µA
Below are th e circu it statu ses at in itial reset.
CPU:
Operatin g statu s
CPU operatin g frequ en cy:
Low speed side (CLKCHG = "0"),
OSC3 oscillation circu it stop
statu s (OSCC = "0")
Heavy load protection m ode: Norm al operatin g m ode
(HVLD = "0")
SVD circu it:
OFF statu s (HVLD = "0", SVDON = "0")
OFF statu s (AMPON = "0")
An alog com parator:
Also, be carefu l abou t pan el selection becau se th e cu rren t
con su m ption can differ by th e order of several µA on ac-
cou n t of th e LCD pan el ch aracteristics.
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CHAPTER 5: SUMMARY OF NOTES
5.2 Sum m a ry of Note s b y Func tion
Here, th e cau tion ary n otes are su m m ed u p by fu n ction
category. Keep th ese n otes well in m in d wh en program m in g.
Mem ory is n ot m ou n ted in u n u sed area with in th e m em ory
m ap an d in m em ory area n ot in dicated in th is m an u al. For
th is reason , n orm al operation can n ot be assu red for pro-
gram s th at h ave been prepared with access to th ese areas.
Memory
Reset terminal
Watchdog timer
Wh en oscillation is stopped, reset in pu t from th e reset
term in al triggered by th e n oise reject circu it can n ot be
received. Wh en oscillation is stopped, in itialization of in ter-
n al circu its is triggered by th e oscillation detection circu it.
Wh en th e watch dog tim er is bein g u sed, th e software m u st
reset it with in 3-secon d cycles, an d tim er data (WD0–WD2)
can n ot be u sed for tim er application s.
Oscillation circuit (1) It takes at least 5 m s from th e tim e th e OSC3 oscillation
circu it starts operatin g u n til th e oscillation stabilizes.
Con sequ en tly, wh en switch in g th e CPU operation clock
from OSC1 to OSC3, do th is after a m in im u m of 5 m s
h ave elapsed sin ce th e OSC3 oscillation wen t ON. Fu r-
th er, th e oscillation stabilization tim e varies depen din g on
th e extern al oscillator ch aracteristics an d con dition s of
u se, so allow am ple m argin wh en settin g th e wait tim e.
and prescaler
(2) Wh en switch in g th e clock from OSC3 to OSC1, u se a
separate in stru ction for switch in g th e OSC3 oscillation
OFF. An error in th e CPU operation can resu lt if th is
processin g is perform ed at th e sam e tim e by th e on e
in stru ction .
(1) Wh en in pu t ports are ch an ged from h igh to low by pu ll-
down resistan ce, th e fall of th e waveform is delayed on
accou n t of th e tim e con stan t of th e pu ll-down resistan ce
an d in pu t gate capacitan ce. Hen ce, wh en fetch in g in pu t
ports, set an appropriate wait tim e. Particu lar care n eeds
to be taken of th e key scan du rin g key m atrix con figu ra-
tion . Aim for a wait tim e of abou t 1 m s.
Input port
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CHAPTER 5: SUMMARY OF NOTES
(2) Wh en "n oise rejector circu it en able" is selected with th e
m ask option , a m axim u m delay of 1 m s occu rs from th e
tim e th e in terru pt con dition s are establish ed u n til th e
in terru pt factor flag (IK) is set to "1" (u n til th e in terru pt is
actu ally gen erated). Hen ce, pay atten tion to th e tim in g
wh en readin g ou t (resettin g) th e in terru pt factor flag. For
exam ple, im m ediately after perform in g a key scan with
th e key m atrix, th e flag will n ot be reset becau se th e
delay in th e in terru pt factor flag read-ou t m ean s th e flag
is set after read-ou t. (Th e key scan ch an ges th e in pu t
statu s an d th e in terru pt factor flag is set, n ecessitatin g
read-ou t to reset th e flag.)
(3) In pu t in terru pt program in g related precau tion s
Port K input
Differential register
Mask register
Active status
Active status
Falling edge interrupt
Rising edge interrupt
➀
Factor flag set Not set
➀
Factor flag set
When the content of the mask register is rewritten, while the port K
input is in the active status. The input interrupt factor flags are set
at ➀ and ➀, ➀ being the interrupt due to the falling edge and ➀ the
interrupt due to the rising edge.
Fig. 5.2.1
Input interrupt timing
Wh en u sin g an in pu t in terru pt, if you rewrite th e con ten t
of th e m ask register, wh en th e valu e of th e in pu t term in al
wh ich becom es th e in terru pt in pu t is in th e active statu s,
th e factor flag for in pu t in terru pt m ay be set. Th erefore,
wh en u sin g th e in pu t in terru pt, th e active statu s of th e
in pu t term in al im plies
in pu t term in al = low statu s, wh en th e fallin g edge
in terru pt is effected an d
in pu t term in al = h igh statu s, wh en th e risin g edge
in terru pt is effected.
Wh en an in terru pt is triggered at th e fallin g edge of an
in pu t term in al, a factor flag is set with th e tim in g of ➀
sh own in Figu re 5.2.1. However, wh en clearin g th e con -
ten t of th e m ask register with th e in pu t term in al kept in
th e low statu s an d th en settin g it, th e factor flag of th e
in pu t in terru pt is again set at th e tim in g th at h as been
set.
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Con sequ en tly, wh en th e in pu t term in al is in th e active
statu s (low statu s), do n ot rewrite th e m ask register
(clearin g, th en settin g th e m ask register), so th at a factor
flag will on ly set at th e fallin g edge in th is case. Wh en
clearin g, th en settin g th e m ask register, set th e m ask
register, wh en th e in pu t term in al is n ot in th e active
statu s (h igh statu s).
Wh en an in terru pt is triggered at th e risin g edge of th e
in pu t term in al, a factor flag will be set at th e tim in g of ➀
sh own in Figu re 5.2.1. In th is case, wh en th e m ask
registers cleared, th en set, you sh ou ld set th e m ask
register, wh en th e in pu t term in al is in th e low statu s.
In addition , wh en th e m ask register = "1" an d th e con ten t
of th e differen tial register is rewritten in th e in pu t term i-
n al active statu s, an in pu t in terru pt factor flag m ay be
set. Th u s, you sh ou ld rewrite th e con ten t of th e differen -
tial register in th e m ask register = "0" statu s.
(4) Read-ou t th e in terru pt factor flag (IK) on ly in th e DI
statu s (in terru pt flag = "0"). Read-ou t du rin g EI statu s
will cau se m alfu n ction .
(5) Writin g to th e in terru pt m ask registers (EIK) can be don e
on ly in th e DI statu s (in terru pt flag = "0"). Writin g du rin g
EI statu s will cau se m alfu n ction .
(6) Wh en oscillation is stopped, th e reset triggered by th e
n oise reject circu it wh ich wou ld n orm ally take place
wh en th e in pu t ports are sim u ltan eou sly switch ed to
HIGH can n ot be received.
Wh en BZ, BZ an d FOUT are selected with th e m ask option ,
a h azard m ay be observed in th e ou tpu t waveform wh en th e
data of th e ou tpu t register ch an ges.
Output port
I/O port
(1) Wh en th e I/ O port is bein g read ou t, th e in -bu ilt pu ll-
down resistan ce of th e I/ O port goes ON. Con sequ en tly, if
data is read ou t wh ile th e CPU is ru n n in g in th e OSC3
oscillation circu it, data m u st be read ou t con tin u ou sly for
abou t 500 µs.
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CHAPTER 5: SUMMARY OF NOTES
(2) Wh en th e I/ O port is set to th e ou tpu t m ode an d th e data
register h as been read, th e term in al data in stead of th e
register data can be read ou t. Becau se of th is, if a low-
im pedan ce load is con n ected an d read-ou t perform ed, th e
valu e of th e register an d th e read-ou t resu lt m ay differ.
(1) Wh en 40H–6FH is selected for th e segm en t data m em ory,
th e m em ory data an d th e display will n ot m atch u n til th e
area is in itialized (th rou gh , for in stan ce, m em ory clear
processin g by th e CPU). In itialize th e segm en t data m em -
ory by execu tin g in itial processin g.
LCD driver
(2) Wh en C0H–EFH is selected for th e segm en t data m em ory,
th at area becom es write-on ly. Con sequ en tly, data can n ot
be rewritten by arith m etic operation s (su ch as AND, OR,
ADD, SUB).
(1) Wh en th e clock tim er h as been reset, th e in terru pt factor
flag (TI) m ay som etim es be set to "1". Con sequ en tly,
perform flag read-ou t (reset th e flag) as n ecessary at
reset.
Clock timer
(2) Th e in pu t clock of th e watch dog tim er is th e 2 Hz sign al
of th e clock tim er, so th at th e watch dog tim er m ay be
cou n ted u p at tim er reset.
(3) Read-ou t th e in terru pt factor flag (TI) on ly du rin g th e DI
statu s (in terru pt flag = "0"). Read-ou t du rin g EI statu s
will cau se m alfu n ction .
(4) Writin g to th e in terru pt m ask registers (ETI) can be don e
on ly in th e DI statu s (in terru pt flag = "0"). Writin g du rin g
EI statu s will cau se m alfu n ction .
Stopwatch counter (1) If cou n ter data is read ou t in th e RUN statu s, th e cou n ter
m u st be m ade in to th e STOP statu s, an d after data is
read ou t th e RUN statu s can be restored. If data is read
ou t wh en a carry occu rs, th e data can n ot be read cor-
rectly.
Also, th e processin g above m u st be perform ed with in th e
STOP in terval of 976 µs (256 Hz 1/ 4 cycle).
(2) Read-ou t of th e in terru pt factor flag (SWIT) m u st be don e
on ly in th e DI statu s (in terru pt flag = "0"). Read-ou t
du rin g EI statu s will cau se m alfu n ction .
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S1C62N33 TECHNICAL HARDWARE
CHAPTER 5: SUMMARY OF NOTES
(3) Writin g to th e in terru pt m ask registers (EISWIT) can be
don e on ly in th e DI statu s (in terru pt flag = "0"). Writin g
du rin g EI statu s will cau se m alfu n ction .
To preven t erron eou s readin g of th e even t cou n ter data, read
ou t th e cou n ter data several tim es, com pare it, an d u se th e
m atch in g data as th e resu lt.
Event counter
(1) To redu ce cu rren t con su m ption , set th e an alog com para-
tor to OFF wh en it is n ot n ecessary.
Analog comparator
(2) After settin g AMPON to "1", wait at least 3 m s for th e
operation of th e an alog com parator to stabilize before
readin g th e ou tpu t data of th e an alog cpm parator from
AMPDT.
(1) It takes 100 µs from th e tim e th e SVD circu it goes ON
u n til a stable resu lt is obtain ed. For th is reason , keep th e
followin g software n otes in m in d:
Supply voltage detection
(SVD) circuit and heavy
load protection function
➀ Wh en th e CPU system clock is fosc1
1. Wh en detection is don e at HVLD
After writin g "1" on HVLD, read th e SVDDT after 1
in stru ction h as passed.
2. Wh en detection is don e at SVDON
After writin g "1" on SVDON, write "0" after at least
100 µs h as lapsed (possible with th e n ext in stru c-
tion ) an d th en read th e SVDDT.
➀ Wh en th e CPU system clock is fosc3 (in case of
S1C62A33 on ly)
1. Wh en detection is don e at HVLD
After writin g "1" on HVLD, read th e SVDDT after 0.6
sec h as passed. (HVLD h olds "1" for at least 0.6 sec)
2. Wh en detection is don e at SVDON
Before writin g "1" on SVDON, write "1" on HVLD
first; after at least 100 µs h as lapsed after writin g
"1" on SVDON, write "0" on SVDON an d th en read
th e SVDDT.
S1C62N33 TECHNICAL HARDWARE
EPSON
I-105
CHAPTER 5: SUMMARY OF NOTES
(2) SVDON resides in th e sam e bit at th e sam e address as
SVDDT, an d on e or th e oth er is selected by write or read
operation . Th is m ean s th at arith m etic operation s (AND,
OR, ADD, SUB an d so forth ) can n ot be u sed for SVDON
con trol.
(3) Select on e of th e followin g software processin g to retu rn
to th e n orm al m ode after a h eavy load h as been driven in
th e h eavy load protection m ode.
➀ After h eavy load drive is com pleted, retu rn to th e
n orm al m ode after at least on e secon d h as elapsed.
➀ After h eavy load drive is com pleted, switch SVD ON
an d OFF (at least 100 µs is n ecessary for th e ON
statu s) an d th en retu rn to th e n orm al m ode.
(4) Wh en th e SVD is to be tu rn ed on du rin g operation in th e
h eavy load protection m ode, lim it th e ON tim e to 10 m s
per secon d of operation tim e.
(1) If th e bit data of SE2 ch an ges wh ile SCLK is in th e m as-
ter m ode, a h azard will be ou tpu t to th e SCLK pin . If th is
poses a problem for th e system , be su re to set th e SCLK
to th e extern al clock if th e bit data of SE2 is to be
ch an ged.
Serial interface
(2) Be su re th at read-ou t of th e in terru pt factor flag (ISIO) is
don e on ly wh en th e serial port is in th e STOP statu s
(SIOF = "0") an d th e DI statu s (in terru pt flag = "0"). If
read-ou t is perform ed wh ile th e serial data is in th e RUN
statu s (du rin g in pu t or ou tpu t), th e data in pu t or ou tpu t
will be su spen ded an d th e in itial statu s resu m ed. Read-
ou t du rin g th e EI statu s (in terru pt flag = "1") cau ses
m alfu n ction in g.
(3) Wh en u sin g th e serial in terface in th e m aster m ode, th e
syn ch ron ou s clock u ses th e CPU system clock. Accord-
in gly, do n ot ch an ge th e system clock (fosc1 ↔ fosc3)
wh ile th e serial in terface is operatin g.
(4) Perform data writin g/ readin g to data registers SD0–SD7
on ly wh ile th e serial in terface is h alted (i.e., th e syn ch ro-
n ou s clock is n eith er bein g in pu t or ou tpu t).
I-106
EPSON
S1C62N33 TECHNICAL HARDWARE
CHAPTER 5: SUMMARY OF NOTES
(5) As a trigger con dition , it is requ ired th at data writin g or
readin g on data registers SD0–SD7 be perform ed prior to
writin g "1" to SCTRG. (Th e in tern al circu it of th e serial
in terface is in itiated th rou gh data writin g/ readin g on
data registers SD0–SD7.) Su pply trigger on ly on ce every
tim e th e serial in terface is placed in th e RUN state. More-
over, wh en th e syn ch ron ou s clock SCLK is extern al clock,
start to in pu t th e extern al clock after th e trigger.
(6) Writin g to th e in terru pt m ask registers can be don e on ly
in th e DI statu s (in terru pt flag = "0").
Writin g du rin g EI statu s will cau se m alfu n ction .
(7) SCTRG resides in th e sam e bit at th e sam e address as
SIOF, an d on e or th e oth er is selected by write or read
operation . Wh en writin g a "1" to SCTRG u se th e OR
com m an d, an d wh en writin g a "0" u se th e AND com -
m an d. No oth er com m an ds sh ou ld be u sed for th is pu r-
pose.
(1) Wh en th e in terru pt m ask register (EIK) is set to "0", th e
in terru pt factor flag (IK) of th e in pu t port can n ot be set
even th ou gh th e pin statu s of th e in pu t port h as ch an ged.
Interrupt and HALT
(2) Th e in terru pt factor flags of th e clock tim er an d stop-
watch cou n ter (TI, SWIT) are set wh en th e tim in g con di-
tion is establish ed, even if th e in terru pt m ask registers
(ETI, EISWIT) are set to "0".
(3) Read-ou t th e in terru pt factor flags on ly in th e DI statu s
(in terru pt flag = "0"). If read-ou t is perform ed in th e EI
statu s a m alfu n ction will resu lt.
(4) Writin g to th e in terru pt m ask registers can be don e on ly
in th e DI statu s (in terru pt flag = "0").
Writin g du rin g EI statu s will cau se m alfu n ction .
S1C62N33 TECHNICAL HARDWARE
EPSON
I-107
CHAPTER 6: DIAGRAM OF BASIC EXTERNAL CONNECTIONS
DIAGRAM OF BASIC EXTERNAL
CHAPTER 6
CONNECTIONS
S1C62N33 and S1C62L33
LCD
panel
C1
C2
• K 1 0
• K 0 3
↓
• CC
• CB
• CA
• VL1
• VL2
• VL3
I
• K 0 0
C3
• P 1 3
C4
C5
↓
• P 1 0
• P 0 3
↓
I/O
• VDD
• OSC1
C
GX
• P 0 0
X'tal
S1C
1.5V
(S1C62L33)
or
3.0V
(S1C62N33)
• OSC2
• VS1
• OSC3
• S I O F
62N33/62L33
C6
N.C
N.C
• S I N
• S C L K
• S O U T
• OSC4
• RESET
• A M P M
• A M P P
+
• TEST
• VSS
CP
• R 0 3
↓
O
• R 0 0
X'tal
CGX
C1
C2
C3
C4
C5
C6
CP
Crystal oscillator
Trim m er capacitor
32,768 Hz, CI (MAX) = 35 kΩ
5–25pF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
3.3 µF
Note The above table is simply an example, and is not guaranteed to work.
I-108
EPSON
S1C62N33 TECHNICAL HARDWARE
CHAPTER 6: DIAGRAM OF BASIC EXTERNAL CONNECTIONS
S1C62A33
LCD
panel
K 1 • 0
K 0 • 3
C1
C2
•
•
•
•
•
•
•
•
CC
CB
CA
↓
I
K 0 • 0
P 1 • 3
C3
VL1
VL2
VL3
VDD
↓
C4
C5
P 1 • 0
P 0 • 3
I/O
↓
C
GX
P 0 • 0
OSC1
X'tal
C6
S1C62A33
S I • O F
S I • N
•
•
OSC2
S1
V
S C • L K
S O • U T
R
CR
C
GC
•
OSC3
3.0V
*2
CR *1
A M • P M
A M • P P
CDC
•
•
OSC4
RESET
R 0 • 3
+
↓
R 0 • 0
•
•
TEST
SS
V
O
CP
*1 Ceramic oscillation
*2 CR oscillation
X'tal Crystal oscillator
32,768 Hz, CI (MAX)=35 kΩ
CGX
CR
CGC
CDC
RCR
C1
C2
C3
C4
C5
Trim m er capacitor
Ceram ic oscillator
Gate capacitan ce
Drain capacitan ce
Resistan ce for CR oscillation
5–25 pF
500 kHz
100 pF
100 pF
82 kΩ
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
3.3 µF
C6
CP
Note The above table is simply an example, and is not guaranteed to work.
S1C62N33 TECHNICAL HARDWARE
EPSON
I-109
CHAPTER 6: DIAGRAM OF BASIC EXTERNAL CONNECTIONS
Wh en th e piezoelectric bu zzer is driven directly
S1C62N33 Series
R10
(BZ)
R13
(BZ)
RA1
RA2
Piezo
RA1
RA2
Protection resistan ce 100 Ω
Protection resistan ce 100 Ω
I-110
EPSON
S1C62N33 TECHNICAL HARDWARE
CHAPTER 7: ELECTRICAL CHARACTERISTICS
CHAPTER 7
ELECTRICAL CHARACTERISTICS
7.1 Ab solute Ma xim um Ra ting
S1C62N33 and S1C62A33
(VDD = 0 V)
Item
Supply voltage
Code
VSS
Rated Value
-5.0 to 0.5
Unit
V
Input voltage (1)
Input voltage (2)
VI
VSS-0.3 to 0.5
VS1-0.3 to 0.5
10
V
VIOSC
ΣIVSS
Topr
Tstg
Tsol
PD
V
*2
Permissible total output current
Operating temperature
Storage temperature
mA
°C
°C
–
-20 to 70
-65 to 150
Soldered temperature, time
Permitted loss *1
260°C, 10 sec (lead section)
250
mW
S1C62L33
(VDD = 0 V)
Item
Supply voltage
Code
VSS
Rated Value
-2.0 to 0.5
Unit
V
Input voltage (1)
Input voltage (2)
VI
VSS-0.3 to 0.5
VS1-0.3 to 0.5
10
V
VIOSC
ΣIVSS
Topr
Tstg
Tsol
PD
V
*2
Permissible total output current
Operating temperature
Storage temperature
mA
°C
°C
–
-20 to 70
-65 to 150
Soldered temperature, time
Permitted loss *1
260°C, 10 sec (lead section)
250
mW
*1 For 100-pin plastic package
*2 The permissible total output current is the sum total of the current (average
current) that simultaneously flows from the output pins (or is drawn in).
S1C62N33 TECHNICAL HARDWARE
EPSON
I-111
CHAPTER 7: ELECTRICAL CHARACTERISTICS
7.2 Re c om m e nd e d Op e ra ting Cond itions
S1C62N33
(Ta = -20–70°C)
Item
Supply voltage
Code
VSS
Condition
Min.
-3.5
–
Typ.
-3.0
Max.
-1.8
–
Unit
V
VDD = 0V
Oscillation frequency
fosc1
32,768
Hz
S1C62L33
(Ta = -20–70°C)
Item
Code
Condition
Min.
Typ.
Max.
Unit
Supply voltage
VSS
VDD = 0V
-1.7
-1.5
-1.1
V
VDD = 0V
software
controllable*1
-1.7
-1.5
-0.9*2
V
VDD = 0V When
use the analog
comparator
-1.7
–
-1.5
-1.2
–
V
Oscillation frequency
fosc1
32,768
Hz
S1C62A33
(Ta = -20–70°C)
Item
Code
VSS
Condition
Min.
-3.5
–
Typ.
-3.0
Max.
-2.2
–
Unit
V
Supply voltage
VDD = 0V
Oscillation frequency (1)
Oscillation frequency (2)
fosc1
32,768
500
Hz
fosc3 duty 50 5ꢀ 50
600
kHz
*1 When switching to heavy load protection mode. (See Section 4.12 for details.)
Note, however, that the ON time for SVD in the heavy load protection must be limited
to 10 ms per second of operation time.
*2 The possibility of LCD panel display differs depending on the characteristics of the
LCD panel.
I-112
EPSON
S1C62N33 TECHNICAL HARDWARE
CHAPTER 7: ELECTRICAL CHARACTERISTICS
7.3 DC Cha ra c te ristic s
S1C62N33 and S1C62A33
(VDD=0V, VSS=-3V, fosc1=32,768Hz, Ta=25°C, VS1, VL1, VL2, VL3 are internal voltage, C1=C2=C3=C4=C5=C6=0.1µF)
Item
High-level
Code
Condition
Min. Typ. Max. Unit
K00–03·10
VIH1
0.2·
VSS
0.1·
VSS
VSS
0
V
SIN, SCLK
input voltage (1)
High-level
P00–03·10–13
VIH2
0
V
input voltage (2)
Low-level
RESET, TEST
K00–03·10
VIL1
0.8·
VSS
0.9·
VSS
0.5
V
input voltage (1)
Low-level
P00–03·10–13
VIL2
VSS
V
input voltage (2)
High-level
RESET, TEST
K00–03·10
IIH1 VIH = 0V
0
µA
input current (1)
SIN, SCLK
P00–03·10–13
AMPP, AMPM
K00–03·10
No pull-down
resistance
High-level
IIH2 VIH = 0V
4
25
16
100
0
µA
µA
µA
Has pull-down
input current (2)
High-level
resistance
IIH3 VIH = 0V
P00–03·10–13
RESET, TEST
K00–03·10,
Has pull-down
resistance
input current (3)
Low-level
IIL
VIL = VSS
SIN -0.5
input current
P00–03·10–13, SCLK
AMPP, AMPM
RESET, TEST
R10
High-level
IOH1 VOH1 = 0.1·VSS
-1.8 mA
output current (1)
R11
R13
R00–03·12
High-level
IOH2 VOH2 = 0.1·VSS
IOL1 VOL1 = 0.9·VSS
-0.9 mA
mA
SOUT, SIOF
output current (2)
Low-level
P00–03·10–13, SCLK
R10
R11
R13
6.0
3.0
output current (1)
R00–03·12
Low-level
IOL2 VOL2 = 0.9·VSS
mA
SOUT, SIOF
output current (2)
Common
P00–03·10–13, SCLK
IOH3 VOH3 = -0.05V
COM0–3
SEG0–39
SEG0–39
-3
-3
µA
µA
µA
µA
output current
IOL3 VOL3 = VL3+0.05V
3
3
Segment output current IOH4 VOH4 = -0.05V
(at LCD output) IOL4 VOL4 = VL3+0.05V
Segment output current IOH5 VOH5 = 0.1·VSS
(at DC output) IOL5 VOL5 = 0.9·VSS
-200 µA
µA
200
S1C62N33 TECHNICAL HARDWARE
EPSON
I-113
CHAPTER 7: ELECTRICAL CHARACTERISTICS
S1C62L33
(VDD=0V, VSS=-1.5V, fosc1=32,768Hz, Ta=25°C, VS1, VL1, VL2, VL3 are internal voltage, C1=C2=C3=C4=C5=C6=0.1µF)
Item
High-level
Code
Condition
Min. Typ. Max. Unit
K00–03·10
VIH1
0.2·
VSS
0.1·
VSS
VSS
0
V
SIN, SCLK
input voltage (1)
High-level
P00–03·10–13
VIH2
0
V
input voltage (2)
Low-level
RESET, TEST
K00–03·10
VIL1
0.8·
VSS
0.9·
VSS
0.5
V
input voltage (1)
Low-level
P00–03·10–13
VIL2
VSS
V
input voltage (2)
High-level
RESET, TEST
K00–03·10
IIH1 VIH = 0V
0
µA
input current (1)
SIN, SCLK
P00–03·10–13
AMPP, AMPM
K00–03·10
No pull-down
resistance
High-level
IIH2 VIH = 0V
2
12
10
60
0
µA
µA
µA
Has pull-down
resistance
input current (2)
High-level
IIH3 VIH = 0V
P00–03·10–13
RESET, TEST
K00–03·10,
Has pull-down
resistance
input current (3)
Low-level
IIL
VIL = VSS
SIN -0.5
input current
P00–03·10–13, SCLK
AMPP, AMPM
RESET, TEST
R10
High-level
IOH1 VOH1 = 0.1·VSS
-300 µA
output current (1)
R11
R13
R00–03·12
High-level
IOH2 VOH2 = 0.1·VSS
IOL1 VOL1 = 0.9·VSS
-150 µA
µA
SOUT, SIOF
output current (2)
Low-level
P00–03·10–13, SCLK
R10
R11
R13
1,400
700
output current (1)
R00–03·12
Low-level
IOL2 VOL2 = 0.9·VSS
µA
SOUT, SIOF
output current (2)
Common
P00–03·10–13, SCLK
IOH3 VOH3 = -0.05V
COM0–3
SEG0–39
SEG0–39
-3
-3
µA
µA
µA
µA
output current
IOL3 VOL3 = VL3+0.05V
3
3
Segment output current IOH4 VOH4 = -0.05V
(at LCD output) IOL4 VOL4 = VL3+0.05V
Segment output current IOH5 VOH5 = 0.1·VSS
(at DC output) IOL5 VOL5 = 0.9·VSS
-100 µA
µA
100
I-114
EPSON
S1C62N33 TECHNICAL HARDWARE
CHAPTER 7: ELECTRICAL CHARACTERISTICS
7.4 Ana log Circ uit Cha ra c te ristic s a nd Consum e d Curre nt
S1C62N33 (Always in operating mode)
(VDD=0V, VSS=-3V, fosc1=32,768Hz, CG=25pF, Ta=25°C, VS1, VL1, VL2, VL3 are internal
voltage, C1=C2=C3=C4=C5=C6=0.1µF)
Item
Code
Condition
Min.
Typ.
Max.
Unit
Internal voltage
VL1 Connects a 1MΩ load resistance
between VDD and VL1 (No panel load)
VL2 Connects a 1MΩ load resistance
-1.15
-1.05
-0.95
V
2·VL1
2·VL1
× 0.9
V
V
between VDD and VL2 (No panel load) -0.1
VL3 Connects a 1MΩ load resistance 3·VL1
3·VL1
× 0.9
between VDD and VL3 (No panel load) -0.1
SVD voltage
VSVD
-2.55
-2.40
-2.25
100
V
µs
V
SVD circuit response time TSVD
Analog comparator
input voltage
VIP
Noninverted input (AMPP)
VSS+0.3
VDD-0.9
VIM Inverted input (AMPM)
VOF
Analog comparator
offset voltage
10
3
mV
ms
Analog comparator
response time
TAMP VIP = -1.5V
VIM = VIP 15mV
Consumed current
IOP
During HALT
During operation
No panel load
1.5
6.0
4.0
µA
µA
*1
10.0
*1 The SVD circuit and analog comparator are in the OFF status.
S1C62N33 TECHNICAL HARDWARE
EPSON
I-115
CHAPTER 7: ELECTRICAL CHARACTERISTICS
S1C62N33 (Heavy load protection mode)
(VDD=0V, VSS=-3V, fosc1=32,768Hz, CG=25pF, Ta=25°C, VS1, VL1, VL2, VL3 are internal
voltage, C1=C2=C3=C4=C5=C6=0.1µF)
Item
Code
Condition
Min.
Typ.
Max.
Unit
Internal voltage
VL1 Connects a 1MΩ load resistance
between VDD and VL1 (No panel load)
VL2 Connects a 1MΩ load resistance
-1.15
-1.05
-0.95
V
2·VL1
2·VL1
× 0.9
V
V
between VDD and VL2 (No panel load) -0.1
VL3 Connects a 1MΩ load resistance 3·VL1
3·VL1
× 0.9
between VDD and VL3 (No panel load) -0.1
SVD voltage
VSVD
-2.55
-2.40
-2.25
100
V
µs
V
SVD circuit response time TSVD
Analog comparator
input voltage
VIP
Noninverted input (AMPP)
VSS+0.3
VDD-0.9
VIM Inverted input (AMPM)
VOF
Analog comparator
offset voltage
10
3
mV
ms
Analog comparator
response time
TAMP VIP = -1.5V
VIM = VIP 15mV
Consumed current
IOP
During HALT
During operation
No panel load
11.2
14.5
34.0
40.0
µA
µA
*1
*1 The SVD circuit is on status (HVLD = "1", SVDON = "0"). The analog comparator
is in the OFF status.
I-116
EPSON
S1C62N33 TECHNICAL HARDWARE
CHAPTER 7: ELECTRICAL CHARACTERISTICS
S1C62L33 (Always in operating mode)
(VDD=0V, VSS=-1.5V, fosc1=32,768Hz, CG=25pF, Ta=25°C, VS1, VL1, VL2, VL3 are internal
voltage, C1=C2=C3=C4=C5=C6=0.1µF)
Item
Code
Condition
Min.
Typ.
Max.
Unit
Internal voltage
VL1 Connects a 1MΩ load resistance
between VDD and VL1 (No panel load)
VL2 Connects a 1MΩ load resistance
-1.15
-1.05
-0.95
V
2·VL1
2·VL1
× 0.9
V
V
between VDD and VL2 (No panel load) -0.1
VL3 Connects a 1MΩ load resistance 3·VL1
3·VL1
× 0.9
between VDD and VL3 (No panel load) -0.1
SVD voltage
VSVD
-1.30
-1.20
-1.10
100
V
µs
V
SVD circuit response time TSVD
Analog comparator
input voltage
VIP
Noninverted input (AMPP)
VSS+0.3
VDD-0.9
VIM Inverted input (AMPM)
VOF
Analog comparator
offset voltage
20
3
mV
ms
Analog comparator
response time
TAMP VIP = -1.1V
VIM = VIP 30mV
Consumed current
IOP
During HALT
No panel load
1.0
3.0
3.0
8.0
µA
µA
*1
During operation
*1 The SVD circuit and analog comparator are in the OFF status.
S1C62N33 TECHNICAL HARDWARE
EPSON
I-117
CHAPTER 7: ELECTRICAL CHARACTERISTICS
S1C62L33 (Heavy load protection mode)
(VDD=0V, VSS=-1.5V, fosc1=32,768Hz, CG=25pF, Ta=25°C, VS1, VL1, VL2, VL3 are internal
voltage, C1=C2=C3=C4=C5=C6=0.1µF)
Item
Code
Condition
Min.
Typ.
Max.
Unit
Internal voltage
VL1 Connects a 1MΩ load resistance
between VDD and VL1 (No panel load)
VL2 Connects a 1MΩ load resistance
-1.15
-1.05
-0.95
V
2·VL1
2·VL1
× 0.85
3·VL1
V
V
between VDD and VL2 (No panel load) -0.1
VL3 Connects a 1MΩ load resistance 3·VL1
between VDD and VL3 (No panel load) -0.1
× 0.85
-1.10
SVD voltage
VSVD
-1.30
-1.20
V
µs
V
SVD circuit response time TSVD
100
Analog comparator
input voltage
VIP
Noninverted input (AMPP)
VSS+0.3
VDD-0.9
VIM Inverted input (AMPM)
VOF
Analog comparator
offset voltage
20
3
mV
ms
Analog comparator
response time
TAMP VIP = -1.1V
VIM = VIP 30mV
*1
Consumed current
IOP
During HALT
No panel load
2.0
8.0
7.0
µA
µA
*1
During operation
18.0
*1 The SVD circuit is on status (HVLD = "1", SVDON = "0"). The analog comparator
is in the OFF status.
I-118
EPSON
S1C62N33 TECHNICAL HARDWARE
CHAPTER 7: ELECTRICAL CHARACTERISTICS
S1C62A33 (Always in operating mode)
(VDD=0V, VSS=-3V, fosc1=32,768Hz, CG=25pF, Ta=25°C, VS1, VL1, VL2, VL3 are internal
voltage, C1=C2=C3=C4=C5=C6=0.1µF)
Item
Code
Condition
Min.
Typ.
Max.
Unit
Internal voltage
VL1 Connects a 1MΩ load resistance
between VDD and VL1 (No panel load)
VL2 Connects a 1MΩ load resistance
-1.15
-1.05
-0.95
V
2·VL1
2·VL1
× 0.9
V
V
between VDD and VL2 (No panel load) -0.1
VL3 Connects a 1MΩ load resistance 3·VL1
3·VL1
× 0.9
between VDD and VL3 (No panel load) -0.1
SVD voltage
VSVD
-2.55
-2.40
-2.25
100
V
µs
V
SVD circuit response time TSVD
Analog comparator
input voltage
VIP
Noninverted input (AMPP)
VSS+0.3
VDD-0.9
VIM Inverted input (AMPM)
VOF
Analog comparator
offset voltage
10
3
mV
ms
Analog comparator
response time
TAMP VIP = -1.5V
VIM = VIP 15mV
*1
Consumed current
IOP
During HALT
No panel load
OSCC = "0"
No panel load
2.0
8.0
135
5.0
15.0
300
µA
µA
µA
During operation
During operation
*1
at 500 kHz
*1 The SVD circuit and analog comparator are in the OFF status.
S1C62N33 TECHNICAL HARDWARE
EPSON
I-119
CHAPTER 7: ELECTRICAL CHARACTERISTICS
S1C62A33 (Heavy load protection mode)
(VDD=0V, VSS=-3V, fosc1=32,768Hz, CG=25pF, Ta=25°C, VS1, VL1, VL2, VL3 are internal
voltage, C1=C2=C3=C4=C5=C6=0.1µF)
Item
Code
Condition
Min.
Typ.
Max.
Unit
Internal voltage
VL1 Connects a 1MΩ load resistance
between VDD and VL1 (No panel load)
VL2 Connects a 1MΩ load resistance
-1.15
-1.05
-0.95
V
2·VL1
2·VL1
× 0.9
V
V
between VDD and VL2 (No panel load) -0.1
VL3 Connects a 1MΩ load resistance 3·VL1
3·VL1
× 0.9
between VDD and VL3 (No panel load) -0.1
SVD voltage
VSVD
-2.55
-2.40
-2.25
100
V
µs
V
SVD circuit response time TSVD
Analog comparator
input voltage
VIP
Noninverted input (AMPP)
VSS+0.3
VDD-0.9
VIM Inverted input (AMPM)
VOF
Analog comparator
offset voltage
10
3
mV
ms
Analog comparator
response time
TAMP VIP = -1.5V
VIM = VIP 15mV
*1
Consumed current
IOP
During HALT
No panel load
OSCC = "0"
No panel load
11.5
16.0
130
35.0
45.0
330
µA
µA
µA
During operation
During operation
*1
at 500 kHz
*1 The SVD circuit is on status (HVLD = "1", SVDON = "0"). The analog comparator
is in the OFF status.
I-120
EPSON
S1C62N33 TECHNICAL HARDWARE
CHAPTER 7: ELECTRICAL CHARACTERISTICS
7.5 Osc illa tion Cha ra c te ristic s
The oscillation characteristics change depending on the conditions (components
used, board pattern, etc.). Use the following characteristics as reference values.
S1C62N33
If no special requirement
VDD=0V, VSS=-3.0V, Crystal: Q13MC146, CG=25pF, CD=built-in,
Ta=25°C
Item
Oscillation start
voltage
Code
Condition
Min.
Typ.
Max.
Unit
Vsta Tsta 5sec
(VSS)
-1.8
V
Oscillation stop
voltage
Vstp Tstp 10sec
(VSS)
-1.8
V
Built-in capacitance
(drain)
Frequency/voltage
deviation
Frequency/IC
deviation
Frequency adjustment f/CG CG = 5 to 25pF
range
CD
f/V
f/IC
Including incidental
18
pF
capacitance inside IC
VSS = -1.8 to -3.5V
5
ppm
ppm
ppm
V
-10
35
10
45
Harmonic oscillation
start voltage
Vhho
(VSS)
-3.5
Permitted leak
resistance
Rleak Between OSC1
and VDD, VSS
200
MΩ
S1C62N33 TECHNICAL HARDWARE
EPSON
I-121
CHAPTER 7: ELECTRICAL CHARACTERISTICS
S1C62L33
If no special requirement
VDD=0V, VSS=-1.5V, Crystal: Q13MC146, CG=25pF, CD=built-in, Ta=25°C
*1 Parentheses indicate value for operation in heavy load protection mode.
Item
Oscillation start
voltage
Code
Condition
Min.
Typ.
Max.
Unit
Vsta Tsta 5sec
(VSS)
-1.1
V
Oscillation stop
voltage
Vstp Tstp 10sec
(VSS)
-1.1
V
(-0.9)*1
Built-in capacitance
(drain)
Frequency/voltage
deviation
Frequency/IC
deviation
Frequency adjustment f/CG CG = 5 to 25pF
range
CD
f/V
f/IC
Including incidental
18
pF
capacitance inside IC
VSS = -1.1 to -1.7V
(-0.9)*1
5
ppm
ppm
ppm
V
-10
35
10
45
Harmonic oscillation
start voltage
Vhho
(VSS)
-1.7
Permitted leak
resistance
Rleak Between OSC1
and VDD, VSS
200
MΩ
Note, however, that the ON time for SVD must be limited to 10 ms per second
of operation time.
I-122
EPSON
S1C62N33 TECHNICAL HARDWARE
CHAPTER 7: ELECTRICAL CHARACTERISTICS
S1C62A33
OSC1, 2
If no special requirement
VDD=0V, VSS=-3.0V, Crystal: Q13MC146, CG=25pF, CD=built-in,
Ta=25°C
Item
Oscillation start
voltage
Code
Condition
Min.
Typ.
Max.
Unit
Vsta Tsta 5sec
(VSS)
-2.2
V
Oscillation stop
voltage
Vstp Tstp 10sec
(VSS)
-2.2
V
Built-in capacitance
(drain)
Frequency/voltage
deviation
Frequency/IC
deviation
Frequency adjustment f/CG CG = 5 to 25pF
range
CD
f/V
f/IC
Including incidental
18
pF
capacitance inside IC
VSS = -2.2 to -3.5V
5
ppm
ppm
ppm
V
-10
35
10
45
Harmonic oscillation
start voltage
Vhho
(VSS)
-3.5
Permitted leak
resistance
Rleak Between OSC1
and VDD, VSS
200
MΩ
S1C62N33 TECHNICAL HARDWARE
EPSON
I-123
CHAPTER 7: ELECTRICAL CHARACTERISTICS
OSC3, OSC4 (for CR oscillation circuit)
If no special requirement
VDD=0V, VSS=-3.0V, RCR=82kΩ, Ta=25°C
Item
Code
fosc3
Vsta
Condition
Min.
-30
Typ.
Max.
Unit
ꢀ
Oscillation frequency
Oscillation start voltage
Oscillation start time
Oscillation stop voltage
430 kHz
30
-2.2
V
Tsta VSS = -2.2 to -3.5V
Vstp
3
ms
V
-2.2
OSC3, OSC4 (for ceramic oscillation circuit)
If no special requirement
VDD=0V, VSS=-3.0V, ceramic oscillation: 500kHz
CGC=CDC=100pF, Ta=25°C
Item
Code
Condition
Min.
Typ.
Max.
Unit
V
Oscillation start voltage
Oscillation start time
Oscillation stop voltage
Vsta
-2.2
Tsta VSS = -2.2 to -3.5V
Vstp
5
ms
V
-2.2
I-124
EPSON
S1C62N33 TECHNICAL HARDWARE
CHAPTER 8: PACKAGE
CHAPTER 8
PACKAGE
8.1
Pla stic Pa c ka g e
QFP5-100pin
(Un it: m m )
25.6 ± 0.4
20.0 ± 0.1
80
51
81
50
Index
100
31
1
30
± 0.1
0.65
0.30 ± 0.1
2.8
S1C62N33 TECHNICAL HARDWARE
EPSON
I-125
CHAPTER 8: PACKAGE
8.2 Ce ra m ic Pa c ka g e for Te st Sa m p le s
(Un it: m m )
26.8
20.0
80
51
81
50
100
31
1
30
0.65
0.30
Grass
Note The ceramic package is fixed in this form regardless selecting of the
plastic package form.
I-126
EPSON
S1C62N33 TECHNICAL HARDWARE
CHAPTER 9: PAD LAYOUT
CHAPTER 9
PAD LAYOUT
Dia g ra m of Pa d La yout
9.1
20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
86
85
84
83
21
22
23
24
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
25
26
27
28
29
30
31
32
33
34
35
36
37
Y
X
(0, 0)
38
39
40
41
42
43
64
44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
DIE No.
4.31 mm
Ch ip th ickn ess: 400µm
Pad open in g: 95µm
S1C62N33 TECHNICAL HARDWARE
EPSON
I-127
CHAPTER 9: PAD LAYOUT
9.2 Pa d Coord ina te s
(Un it : µm )
Pad No. Pad Name
X
Y
Pad No. Pad Name
X
Y
Pad No. Pad Name
X
Y
1
AMPP
AMPM
K10
K03
K02
K01
K00
P03
1,990
1,765
1,560
1,400
1,240
1,080
920
2,220
2,220
2,220
2,220
2,220
2,220
2,220
2,220
2,220
2,220
2,220
2,220
2,220
2,220
2,220
2,220
2,220
2,220
2,220
2,220
1,780
1,620
1,460
1,291
1,036
876
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
V
V
V
V
DD
L3
L2
L1
-1,990
-1,990
-1,990
-1,990
-1,990
-1,990
-1,990
76
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
SEG15
SEG16
SEG17
TEST
1,198 -2,220
1,358 -2,220
1,518 -2,220
1,990 -2,005
1,990 -1,559
1,990 -1,399
1,990 -1,239
1,990 -1,079
2
-84
-244
-404
-564
-724
-884
3
4
5
CC
CB
CA
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
6
7
8
630
COM3 -1,990 -1,070
COM2 -1,990 -1,230
COM1 -1,990 -1,390
COM0 -1,990 -1,590
9
P02
470
1,990
1,990
1,990
1,990
1,990
1,990
1,990
1,990
1,990
1,990
1,990
1,990
1,990
1,990
1,990
1,990
1,990
1,990
-919
-759
-599
-439
-279
-119
41
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
P01
310
P00
150
P13
-50
SIOF
-1,990 -1,750
-1,990 -2,010
-1,589 -2,220
-1,428 -2,220
-1,202 -2,220
-1,042 -2,220
-882 -2,220
-722 -2,220
-562 -2,220
-402 -2,220
-242 -2,220
-82 -2,220
P12
-210
SCLK
SOUT
SIN
P11
-370
P10
-530
R03
R02
R01
R00
R12
R11
R10
R13
-738
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
201
-898
361
-1,058
-1,218
-1,426
-1,990
-1,990
-1,990
-1,990
521
681
841
1,001
1,161
1,377
1,537
1,697
1,857
V
SS
78 -2,220
RESET -1,990
238 -2,220
398 -2,220
558 -2,220
718 -2,220
878 -2,220
1,038 -2,220
OSC4
OSC3
-1,990
-1,990
-1,990
-1,990
-1,990
716
V
S1
556
OSC2
OSC1
396
236
Ch ip size X : 4.31 (m m )
Y : 4.77 (m m )
I-128
EPSON
S1C62N33 TECHNICAL HARDWARE
S1C62N33
II. Technical Software
CONTENTS
CONTENTS
CHAPTER 1
CHAPTER 2
BLOCK DIAGRAM .......................................................... II-1
PROGRAM MEMORY ..................................................... II-2
2.1 Program Memory Map.................................................... II-2
2.2 Programming Notes ....................................................... II-3
CHAPTER 3
DATA MEMORY .............................................................. II-4
3.1 Data Memory Map .......................................................... II-4
3.2 RAM Map ....................................................................... II-6
3.3 Programming Notes ....................................................... II-6
3.4 I/O Memory Map............................................................. II-7
CHAPTER 4
INTERRUPT AND HALT .................................................... II-10
4.1 Control of Interrupt and HALT ....................................... II-10
4.2 Generation of Interrupt .................................................. II-13
4.3 Example of Main Routine: Entering HALT
and waiting for reactivation by interrupt......................... II-14
4.4 Interrupt Vector Map...................................................... II-15
4.5 Example of Interrupt Vector Processing ........................ II-16
4.6 Programming Notes ...................................................... II-19
CHAPTER 5
PERIPHERAL CIRCUITS ................................................... II-20
5.1 Watchdog Timer ............................................................ II-20
Watch dog tim er m em ory m ap ................................. II-20
Exam ple of reset processin g for watch dog tim er ..... II-21
Program m in g n ote .................................................. II-22
S1C62N33 TECHNICAL SOFTWARE
EPSON
II-i
CONTENTS
5.2 OSC3............................................................................. II-23
OSC3 m em ory m ap ................................................ II-23
Exam ple of u sin g OSC3 .......................................... II-24
Program m in g n otes ................................................ II-25
5.3 Supply Voltage Detection (SVD) Circuit
and Heavy Load Protection Function ............................ II-26
SVD circu it m em ory m ap ....................................... II-26
Exam ple of fin din g su pply voltage u sin g SVD circu it II-26
Exam ple of u sin g h eavy load protection fu n ction .... II-31
Program m in g n otes ................................................ II-36
5.4 Output Ports (R00–R03, R10–R13) .............................. II-38
Ou tpu t port m em ory m ap ....................................... II-38
Exam ple of u sin g ou tpu t ports ............................... II-40
Program m in g n ote .................................................. II-46
5.5 LCD Driver..................................................................... II-47
Segm en t data m em ory m ap .................................... II-47
Exam ple of con trol program
for LCD segm en t ou tpu t ......................................... II-48
LCD driver m em ory m ap ........................................ II-55
Exam ple of switch in g LCD drive ............................. II-55
Program m in g n otes ................................................ II-57
5.6 Clock Timer ................................................................... II-58
Clock tim er m em ory m ap ....................................... II-58
Exam ple of u sin g clock tim er ................................. II-59
Tim er in terru pt m em ory m ap ................................. II-62
Clock tim er tim in g ch art ........................................ II-63
Exam ple of u sin g tim er in terru pt ............................ II-63
Program m in g n otes ................................................ II-68
5.7 Input Ports (K00–K03, K10) .......................................... II-69
In pu t port m em ory m ap ......................................... II-69
Exam ple of u sin g in pu t ports ................................. II-71
Program m in g n otes ................................................ II-80
5.8 I/O Ports ........................................................................ II-82
I/ O port m em ory m ap ............................................ II-82
Exam ple of program for I/ O ports ........................... II-83
Program m in g n otes ................................................ II-86
II-ii
EPSON
S1C62N33 TECHNICAL SOFTWARE
CONTENTS
5.9 Stopwatch Counter ........................................................ II-87
Stopwatch cou n ter m em ory m ap ............................ II-87
Exam ple of program for stopwatch cou n ter ............ II-88
Stopwatch in terru pt m em ory m ap .......................... II-90
Stopwatch cou n ter tim in g ch art ............................. II-91
Exam ple of program for stopwatch in terru pt .......... II-92
Program m in g n otes ................................................ II-96
5.10 Event Counter ............................................................... II-97
Even t cou n ter m em ory m ap ................................... II-97
Exam ple of program for even t cou n ter .................... II-98
Program m in g n ote .................................................. II-99
5.11 Analog Comparator ...................................................... II-100
An alog com parator m em ory m ap ........................... II-100
Exam ple of program for an alog com parator ........... II-100
Program m in g n otes ............................................... II-101
5.12 Serial Interface (SIN, SOUT, SCLK, SIOF) .................. II-102
Serial in terface m em ory m ap ................................. II-102
Exam ple of program for serial in terface ................. II-106
Program m in g n otes ............................................... II-109
CHAPTER 6
INITIAL RESET ................................................................ II-110
6.1 Internal Status at Initial Reset ...................................... II-110
6.2 Example of Initialize Program....................................... II-111
CHAPTER 7
CHAPTER 8
SUMMARY OF NOTES................................................... II-113
CPU............................................................................... II-121
8.1 S1C62N33 Restrictions ................................................ II-121
8.2 Instruction Set .............................................................. II-121
APPENDIX
• Table of cross assem bler pseu do-in stru ction s .................. II-127
• Table of ICE com m an ds ................................................... II-128
S1C62N33 TECHNICAL SOFTWARE
EPSON
II-iii
CHAPTER 1: BLOCK DIAGRAM
CHAPTER 1
BLOCK DIAGRAM
ROM
System Reset
Control
OSC
3,072 words x 12 bits
Core CPU S1C6200
RAM
256 words x 4 bits
Interrupt
Generator
COM0~3
SEG0~39
K00~03, K10
TEST
LCD Driver
Input Port
I/O Port
P00~03, P10~13
R00~03, R10~13
V
DD
V
L1~3
Power
Controller
Output Port
Comparator
CA~CC
VS1
AMPP
AMPM
VSS
Timer
SVD
Stop Watch
SIN
Event
Counter
SOUT
SCLK
SIOF
Serial Interface
Fig. 1
Block diagram
S1C62N33 TECHNICAL SOFTWARE
EPSON
II-1
CHAPTER 2: PROGRAM MEMORY
CHAPTER 2
PROGRAM MEMORY
Th e S1C62N33 Series h as a m ask ROM of 3,072 steps × 12
bits, for storin g program s. Address space for program
m em ory is con figu red of on e ban k of 12 pages × 256 steps.
2.1
Prog ra m Me m ory Ma p
00H step
01H step
Program start address
Interrupt vector area
0 page
1 page
2 page
3 page
4 page
5 page
6 page
7 page
8 page
9 page
0FH step
10H step
10 page
11 page
FFH step
12 bits
Fig. 2.1
Program memory map
After in itial reset, th e program start address is page 1, step
00H; in terru pt vectors can be allocated to page 1, steps
01H–0FH.
II-2
EPSON
S1C62N33 TECHNICAL SOFTWARE
CHAPTER 2: PROGRAM MEMORY
2.2 Prog ra m m ing Note s
(1) To u se a bran ch in stru ction su ch as "J P" to bran ch
ou tside th e page of th at in stru ction , th e page to bran ch
to m u st first be set with th e "PSET" in stru ction ; th en th e
bran ch in stru ction can be execu ted. Be su re to execu te
th e bran ch in stru ction as th e step im m ediately followin g
"PSET".
(2) Im m ediately after th e "PSET" in stru ction m en tion ed in
above item (1), it will au tom atically be DI state u n til
execu tion of th e bran ch in stru ction is com pleted.
(3) Wh en m ovin g from th e last step of on e page to th e top
step of th e n ext page, th ere is n o n eed to execu te bran ch
in stru ction s su ch as "PSET" an d "J P".
(4) With ju st th e on e in stru ction "CALZ", su brou tin es on
page 0 can be called from an y page with ou t u sin g "PSET".
Program m in g can be don e efficien tly if u n iversal su brou -
tin es are located on page 0.
(5) If th e "PSET" in stru ction is execu ted im m ediately before
"CALZ", "CALZ" will h ave priority an d data set with
"PSET" will be ign ored.
(6) Th e program m em ory can be u sed as a data table
th rou gh th e table look-u p in stru ction .
For details of th e in stru ction s, refer to "S1C6200/ 6200A
Core CPU Man u al".
S1C62N33 TECHNICAL SOFTWARE
EPSON
II-3
CHAPTER 3: DATA MEMORY
CHAPTER 3
DATA MEMORY
Th e S1C62N33 Series h as a gen eral-pu rpose RAM (256 words
× 4 bits ), I/ O m em ory for con trollin g th e in tern al periph eral
circu its (64 words × 4 bits), an d th e option ally selectable
segm en t m em ory (48 words × 4 bits). All th ese are allocated
to th e data m em ory addresses on page 0 an d page 1.
3.1
Da ta Me m ory Ma p
Data m em ory of th e S1C62N33 Series h as an address space
of 360 words, of wh ich 48 words are allocated to display
m em ory an d 64 words to I/ O data m em ory.
Figu re 3.1 presen t th e overall m em ory m aps of th e
S1C62N33 Series, an d Tables 3.4 (a)–(c) th e periph eral
circu its' (I/ O space) m em ory m aps.
Th e I/ O data m em ory in all u n its of th e S1C62N33 Series is
con figu red in th e sam e m an n er at 070H–07FH, 170H–17FH
an d 0F0H–0FFH, 1F0H–1FFH. Th is m akes it possible to
access I/ O data m em ory with ou t switch in g data m em ory
pages.
II-4
EPSON
S1C62N33 TECHNICAL SOFTWARE
CHAPTER 3: DATA MEMORY
Address
Page
Low
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
High
0
M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF
1
2
3
RAM (112 words x 4 bits)
R/W
4
5
6
I/O data memory Tables 3.4(a), (b)
7
0
8
RAM (32 words x 4 bits)
R/W
9
A
B
C
D
E
F
Unused area
I/O data memory Table 3.4(c)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
RAM (112 words x 4 bits)
R/W
I/O data memory Tables 3.4(a), (b)
1
Unused area
Fig. 3.1
I/O data memory Table 3.4(c)
Data memory map
Note
(1) The I/O data memory registers of 070H–07FH, 170H–17FH and
0F0H–0FFH, 1F0H–1FFH are each linked. For instance, by
switching the I/O data memory at 074H, data memory at 174H
can by switched simultaneously.
See Tables 3.4(a)–(c) for details of I/O data memory.
(2) The mask option can be used to select whether to assign the
overall area of segment data memory to 040H–06FH or 0C0H–
0EFH.
When 040H–06FH is selected, read/write is enabled.
When 0C0H–0EFH is selected, write only is enabled.
If 040H–06FH is assigned, RAM is used as the segment area
(48 words).
(3) Memory is not mounted in unused area within the memory map
and in memory area not indicated in this chapter. For this
reason, normal operation cannot be assured for programs that
have been prepared with access to these areas.
S1C62N33 TECHNICAL SOFTWARE
EPSON
II-5
CHAPTER 3: DATA MEMORY
3.2 RAM Ma p
Address
Page
Low
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
High
0
1
2
3
4
5
6
M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF
0
8
9
0
1
0
1
2
3
4
5
6
Fig. 3.2
RAM map
Addresses 000H–00FH are th e m em ory register area th at
can be addressed with th e register poin ter (RP).
Note
Addresses 040H–06FH can be allocated to segment memory by
option selection. With this selection, 48 words of RAM can be
used as segment area.
3.3
Prog ra m m ing Note s
(1) Part of th e data m em ory is u sed as stack area for su brou -
tin e calls an d register storage, so be carefu l n ot to overlap
th e data area an d stack area.
(2) Su brou tin e calls an d in terru pts take u p th ree words of
th e stack area.
(3) Wh en addresses 040H–06FH h ave been allocated as
segm en t m em ory by option selection , 48 words of RAM
can be u sed as segm en t area.
II-6
EPSON
S1C62N33 TECHNICAL SOFTWARE
CHAPTER 3: DATA MEMORY
3.4 I/ O Me m ory Ma p
Table 3.4(a) I/O data memory map (70H–77H)
Register
Address
Comment
*1
D3
D2
D1
D0
Name
TM3
Init
0
1
0
*7
Timer data (clock timer 2 Hz)
TM3
TM2
TM1
TM0
Timer data (clock timer 4 Hz)
Timer data (clock timer 8 Hz)
Timer data (clock timer 16 Hz)
MSB
TM2
0
70H
TM1
0
R
R
R
R
TM0
0
SWL3
SWL2
SWL1
SWL0
SWH3
SWH2
SWH1
SWH0
K03
0
SWL3
SWH3
K03
SWL2
SWH2
K02
SWL1
SWH1
K01
SWL0
SWH0
K00
Stopwatch counter
1/100 sec (BCD)
LSB
0
71H
72H
73H
74H
75H
0
0
MSB
0
Stopwatch counter
1/10 sec (BCD)
LSB
0
0
0
High
High
Low
Low
*2
*2
*2
*2
0
Input port
K02
High
Low
(K00–K03)
K01
High
Low
K00
Falling
Falling
Falling
Falling
Enable
Enable
Enable
Enable
Rising
Rising
Rising
Rising
Mask
Mask
Mask
Mask
DFK03
DFK02
DFK01
DFK00
EIK03
EIK02
EIK01
EIK00
HVLD
SVDDT
SVDON
EISWIT1
EISWIT0
SCTRG
SIOF
DFK03
EIK03
DFK02
EIK02
DFK01
DFK00
EIK00
Differential register
(K00–K03)
0
0
R/W
0
0
EIK01
Interrupt mask register
(K00–K03)
0
0
R/W
0
Heavy load Normal Heavy load protection mode register
Low voltage Normal SVD evaluation data (at read-out)
0
SVDDT
SVDON
R
HVLD
R/W
EISWIT1 EISWIT0
R/W
0
On
Off
Mask
Mask
–
SVD ON/OFF (at writing)
Interrupt mask register (stopwatch 1 Hz)
Interrupt mask register (stopwatch 10 Hz)
Serial interface clock trigger
SIOF
76H
77H
0
Enable
Enable
Trigger
Run
0
W
0
–
SCTRG
SIOF
W
EIK10
DFK10
K10
R
Stop
Mask
Rising
Low
0
Enable
Falling
High
Interrupt mask register (K10)
Differential register (K10)
Input port (K10)
EIK10
DFK10
K10
0
0
R/W
R
*2
*1 In itial valu e followin g in itial reset
*2 Not set in th e circu it
*3 Un defin ed
*5 Always "0" wh en bein g read
*6 Refer to m ain m an u al
*7 Page switch in g in I/ O m em ory is
n ot n ecessary
*4 Reset (0) im m ediately after bein g read
S1C62N33 TECHNICAL SOFTWARE
EPSON
II-7
CHAPTER 3: DATA MEMORY
Table 3.4(b) I/O data memory map (78H–7FH)
Register
Address
Comment
*1
D3
D2
D1
D0
Name
CSDC
ETI2
ETI8
ETI32
–
Init
0
1
0
*7
Static
Enable
Enable
Enable
Dynamic LCD drive switch
CSDC
ETI2
ETI8
ETI32
Mask
Mask
Mask
Interrupt mask register (clock timer 2 Hz)
Interrupt mask register (clock timer 8 Hz)
Interrupt mask register (clock timer 32 Hz)
Unused *5
0
78H
0
R/W
0
*2
0
–
TI2
IK0
TI8
TI32
SWIT0
R00
Yes
Yes
No
No
Interrupt factor flag (clock timer 2 Hz) *4
Interrupt factor flag (clock timer 8 Hz) *4
Interrupt factor flag (clock timer 32 Hz) *4
Interrupt factor flag (K10) *4
TI2
79H
7AH
7BH
7CH
7DH
7EH
7FH
TI8
0
R
Yes
No
TI32
0
Yes
No
IK1
0
IK1
R03
R13
P03
SWIT1
R01
Yes
No
Interrupt factor flag (K00–K03) *4
Interrupt factor flag (stopwatch 1 Hz) *4
Interrupt factor flag (stopwatch 10 Hz) *4
IK0
0
Yes
No
SWIT1
SWIT0
R03
0
R
Yes
No
0
High
High
High
High
High
High
High
High
High
High
High
High
Reset
Run
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
–
0
R02
R12
P02
Output port
R02
0
(R00–R03)
R01
0
R/W
R/W
R/W
R00
0
Output port (R13, BZ) *6
Output port (R12, FOUT) *6
Output port (R11)
R13
0
R11
P01
R10
R12
0
R11
0
Output port (R10, BZ) *6
R10
0
P03
*2
*2
*2
*2
P00
I/O port (P00–P03)
P02
Output latch reset at time of initial reset
P01
P00
Clock timer reset *5
TMRST
SWRUN
SWRST
IOC0
WDRST
WD2
WD1
WD0
Reset
TMRST SWRUN SWRST
IOC0
R/W
Stop
–
Stopwatch counter RUN/STOP
Stopwatch counter reset *5
0
Reset
Output
Reset
Reset
W
WDRST
W
R/W
W
WD1
R
Input
–
I/O control register 0 (P00–P03)
Watchdog timer reset *5
0
Reset
WD2
WD0
Timer data (watchdog timer 1/4 Hz)
Timer data (watchdog timer 1/2 Hz)
Timer data (watchdog timer 1 Hz)
0
0
0
II-8
EPSON
S1C62N33 TECHNICAL SOFTWARE
CHAPTER 3: DATA MEMORY
Table 3.4(c) I/O data memory map (F0H–F3H, F6H–F9H, FCH–FEH)
Register
Address
Comment
*1
D3
D2
D1
D0
Name
SD3
SD2
SD1
SD0
SD7
SD6
SD5
SD4
SCS1
SCS0
SE2
EISIO
–
Init
*3
*3
*3
*3
*3
*3
*3
*3
1
1
0
*7
SD3
SD2
SD1
SD0
Serial interface data register
F0H
Low order (SD0–SD3)
R/W
R/W
R/W
R
SD7
SCS1
–
SD6
SCS0
–
SD5
SE2
–
SD4
EISIO
ISIO
–
Serial interface data register
F1H
F2H
F3H
F6H
F7H
F8H
F9H
FCH
FDH
FEH
High order (SD4–SD7)
*6
*6
*6
*6
Clock edge selection register
(SCS0, SCS1)
1
Rising
Enable
Falling
Mask
Clock edge selection register
Interrupt mask register (serial interface)
Unused *5
0
0
*2
*2
*2
0
Unused *5
–
Unused *5
–
Yes
No
Interrupt factor flag (serial interface) *4
Buzzer frequency selection register
Unused *5
ISIO
BZFQ
–
2 kHz
4 kHz
0
BZFQ
R/W
–
–
–
*2
*2
*2
*2
*2
1
Unused *5
–
R
Unused *5
–
Unused *5
–
–
R
AMPDT AMPON
R/W
Unused *5
–
+ > -
- > +
Analog comparator data
Analog comparator ON/OFF
AMPDT
AMPON
EV03
EV02
EV01
EV00
EV07
EV06
EV05
EV04
–
On
Off
0
0
EV03
EV07
EV02
EV01
EV00
Event counter
0
Low order (EV00–EV03)
0
R
R
0
0
EV06
EV05
EV04
Event counter
0
High order (EV04–EV07)
0
0
Unused *5
*2
0
–
R
EVRUN
R/W
–
R
EVRST
W
Run
Stop
Event counter RUN/STOP
Unused *5
EVRUN
–
*2
Reset
*2
*2
*2
*2
*2
0
Reset
High
High
High
High
–
Event counter reset *5
EVRST
P13
Low
Low
Low
Low
P13
P12
P11
P10
I/O port (P10–P13)
P12
Output latch reset at time of initial reset
P11
R/W
P10
Unused *5
–
–
CLKCHG OSCC
R/W
IOC1
OSC3
On
OSC1
Off
CPU clock switch
CLKCHG
OSCC
IOC1
OSC3 oscillator ON/OFF
I/O control register 1 (P10–P13)
0
R
Output
Input
0
S1C62N33 TECHNICAL SOFTWARE
EPSON
II-9
CHAPTER 4: INTERRUPT AND HALT
CHAPTER 4
INTERRUPT AND HALT
Th e S1C62N33 Series provides th e followin g in terru pt set-
tin gs, each of wh ich is m askable.
Extern al in terru pts:
In tern al in terru pts:
In pu t in terru pts (two)
Tim er in terru pt (th ree)
Stopwatch in terru pt (two)
Serial in terface in terru pt (on e)
Wh en a HALT in stru ction is in pu t th e CPU operatin g clock
stops, an d th e CPU en ters th e HALT statu s.
Th e CPU is reactivated from th e HALT statu s wh en an
in terru pt requ est occu rs.
II-10
EPSON
S1C62N33 TECHNICAL SOFTWARE
CHAPTER 4: INTERRUPT AND HALT
4.1
Control of Inte rrup t a nd HALT
Table 4.1(a) I/O data memory map (interrupt 1)
Register
Address
Comment
*1
D3
D2
D1
D0
Name
DFK03
SR
0
1
0
*7
DFK03
DFK02
DFK01
DFK00
Falling
Rising
R/W
DFK02
DFK01
DFK00
EIK03
EIK02
EIK01
EIK00
HVLD
0
0
0
0
0
0
0
0
Falling
Falling
Falling
Enable
Enable
Enable
Enable
Rising
Rising
Rising
Mask
Mask
Mask
Mask
Differential register
(K00–K03)
74H
EIK03
EIK02
EIK01
EIK00
Interrupt mask register
(K00–K03)
R/W
75H
76H
SVDDT
SVDON
R
Heavy
load
HVLD
R/W
EISWIT1 EISWIT0
R/W
Normal Heavy load protection mode register
SVD evaluation data (at read-out)
Low voltage
ON
SVDDT
SVDON
0
0
Normal
SVD ON/OFF (at writing)
Interrupt mask register
(stopwatch 1 Hz)
W
OFF
EISWIT1
EISWIT0
0
0
Enable
Enable
Mask
Interrupt mask register
(stopwatch 10 Hz)
Serial interface clock trigger
SIOF
Mask
Trigger
Run
SCTRG
SIOF
–
0
–
SCTRG
SIOF
W
EIK10
DFK10
K10
R
Stop
EIK10
DFK10
K10
0
0
Enable
Falling
High
Mask
Rising
Low
Interrupt mask register (K10)
Differential register (K10)
Input port (K10)
R/W
R
77H
*2
*1 In itial valu e followin g in itial reset
*2 Not set in th e circu it
*3 Un defin ed
*5 Always "0" wh en bein g read
*6 Refer to m ain m an u al
*7 Page switch in g in I/ O m em ory is
n ot n ecessary
*4 Reset (0) im m ediately after bein g read
S1C62N33 TECHNICAL SOFTWARE
EPSON
II-11
CHAPTER 4: INTERRUPT AND HALT
Table 4.1(b) I/O data memory map (interrupt 2)
Register
Address
Comment
*1
D3
D2
D1
D0
Name
CSDC
SR
0
1
0
*7
CSDC
ETI2
ETI8
ETI32
Static
Dynamic LCD drive switch
R/W
Interrupt mask register (clock timer 2 Hz)
Interrupt mask register (clock timer 8 Hz)
Interrupt mask register (clock timer 32 Hz)
Unused *5
ETI2
ETI8
ETI32
–
0
0
Enable
Enable
Enable
Mask
Mask
Mask
78H
0
*2
0
–
IK1
SCS1
–
TI2
TI8
TI32
SWIT0
EISIO
ISIO
R
TI2
Yes
Yes
No
No
Interrupt factor flag (clock timer 2 Hz) *4
Interrupt factor flag (clock timer 8 Hz) *4
Interrupt factor flag (clock timer 32 Hz) *4
Interrupt factor flag (K10) *4
79H
7AH
F2H
F3H
TI8
0
TI32
0
Yes
No
IK0
SWIT1
IK1
IK0
0
Yes
No
Interrupt factor flag (K00–K03) *4
Interrupt factor flag (stopwatch 1 Hz) *4
Interrupt factor flag (stopwatch 10 Hz) *4
R
0
Yes
No
SWIT1
SWIT0
SCS1
SCS0
SE2
EISIO
–
0
Yes
No
0
Yes
No
SCS0
SE2
1
1
*6
*6
Clock edge selection register
(SCS0, SCS1)
R/W
*6
*6
Clock edge selection register
Interrupt mask register (serial interface)
Unused *5
0
Rising
Enable
Falling
Mask
0
–
–
*2
*2
*2
0
R
–
Unused *5
–
Unused *5
ISIO
Yes
No
Interrupt factor flag (serial interface) *4
*1 In itial valu e followin g in itial reset
*2 Not set in th e circu it
*3 Un defin ed
*5 Always "0" wh en bein g read
*6 Refer to m ain m an u al
*7 Page switch in g in I/ O m em ory is
n ot n ecessary
*4 Reset (0) im m ediately after bein g read
II-12
EPSON
S1C62N33 TECHNICAL SOFTWARE
CHAPTER 4: INTERRUPT AND HALT
4.2 Ge ne ra tion of Inte rrup t
Interrupt Mask
Register
Interrupt
Factor Flag
Table 4.2
Interrupt Factor
Interrupt factors
Clock timer 2 Hz falling edge
Clock timer 8 Hz falling edge
T2Hz
T8Hz
ETI2
ETI8
ETI32
(78H•D2) TI2
(78H•D1) TI8
(79H•D2)
(79H•D1)
Clock timer 32 Hz falling edge T32Hz
(78H•D0) TI32 (79H•D0)
Stopwatch counter
1 Hz falling edge
Stopwatch counter
10 Hz falling edge
Serial interface
SWT1Hz
EISWIT1 (76H•D1) SWIT1 (7AH•D1)
SWT10Hz EISWIT0 (76H•D0) SWIT0 (7AH•D0)
SIO
EISIO
(F2H•D0) ISIO (F3H•D0)
Data (8 bits) input/output has completed
Input data (K00–K03)
Change from match to mismatch
of differential register data
and port register data
K0
EIK03
EIK02
EIK01
EIK00
EIK10
(75H•D3) IK0
(75H•D2)
(7AH•D2)
(7AH•D3)
(75H•D1)
(75H•D0)
Input data (K10)
K1
(77H•D2) IK1
Rising or falling edge
Th e CPU operation is in terru pted wh en an y of th e con dition s
below sets an in terru pt factor flag to "1".
• Th e correspon din g in terru pt m ask register is "1" (en abled)
• Th e in terru pt flag is "1" (EI)
Th e in terru pt flag is set to "1" depen din g on th e correspon d-
in g in terru pt factor.
Th e in terru pt factor flag is a read-on ly register, an d is reset
to "0" wh en th e register data is read ou t.
- Write to the interrupt mask registers only in the DI status (inter-
rupt flag = "0").
Note
An error could result from writing during the EI status.
- Even when the interrupt mask registers (ETI, EISWIT) are set to
"0", the interrupt factor flags (TI, SWIT) of the clock timer and
stopwatch counter can be set when the timing conditions are
established.
- Read the interrupt factor flags only in the DI status (interrupt flag
= "0").
An error could result from reading out during the EI status.
S1C62N33 TECHNICAL SOFTWARE
EPSON
II-13
CHAPTER 4: INTERRUPT AND HALT
4.3 Exa m p le of Ma in Routine : Ente ring HALT
a nd wa iting for re a c tiva tion b y inte rrup t
Specifications
Th is m ain rou tin e en ables K00–K03 in pu t in terru pt an d 2
Hz tim er in terru pt, after wh ich it en ters th e HALT statu s to
wait for reactivation by in terru pts.
At every loop, th e EI in stru ction en ables an in terru pt after
execu tion of th e display rou tin e "DS" (of th e watch or wh at-
ever th e application h appen s to be).
Program
LD
X,75H
;Enable K00–K03 input interrupt
LD
LD
LD
MX,1111B
X,78H
;
;Enable 2 Hz timer interrupt
MX,0100B
;
;
MAINLP: CALL
DS
;Execute display processing "DS"
;Enable interrupts
EI
HALT
JP
;Enter HALT
MAINLP
;Interrupts' return address: Back to "MAINLP"
Th is rou tin e assu m es th at "DS" h as been prepared sepa-
rately.
1. Th is program exam ple is on e to follow th e in itialize
program . Even with ou t execu tin g th e DI in stru ction ,
writin g to in terru pt m ask registers is don e in th e DI
statu s.
Notes
2. Wh en an in terru pt is gen erated, th e DI statu s (in terru pt
flag = "0") com es in to effect au tom atically, so th e EI
in stru ction is n ecessary for each loop.
II-14
EPSON
S1C62N33 TECHNICAL SOFTWARE
CHAPTER 4: INTERRUPT AND HALT
4.4 Inte rrup t Ve c tor Ma p
Table 4.4
Page Step
Interrupt Vector
Interrupt vector map
Initial reset
00H
01H
02H
03H
04H
05H
06H
Generation of Serial interface interrupt (ISIO)
Generation of input port interrupt (INTK0 or INTK1)
Generation of ISIO and (INTK0 or INTK1)
Generation of timer interrupt (TINT)
Generation of ISIO and TINT
Generation of (INTK0 or INTK1) and TINT
Generation of ISIO, (INTK0 or INTK1) and TINT
Generation of stopwatch interrupt (SWINTT)
Generation of ISIO and SWINTT
07H
1
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
Generation of (INTK0 or INTK1) and SWINTT
Generation of ISIO, (INTK0 or INTK1) and SWINTT
Generation of TINT and SWINTT
Generation of ISIO, TINT and SWINTT
Generation of (INTK0 or INTK1), TINT and SWINTT
Generation of all interrupts
Addresses (start addresses of in terru pt processin g rou tin es)
to ju m p to are written in to th e addresses available for in ter-
ru pt vector allocation .
S1C62N33 TECHNICAL SOFTWARE
EPSON
II-15
CHAPTER 4: INTERRUPT AND HALT
4.5 Exa m p le of Inte rrup t Ve c tor Proc e ssing
Specifications
Wh en in terru pts h avin g differen t vectors occu r sim u ltan e-
ou sly, th ey are processed in th e specified order of priority.
Becau se of th is, it is con ven ien t to process all in terru pts
with th e on e in terru pt rou tin e "IN".
Interrupt vectors
ORG
101H
;Vector leading address
;
JP
JP
JP
JP
JP
JP
JP
JP
JP
JP
JP
JP
JP
JP
JP
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
;Generation of Serial interface interrupt (ISIO)
;Generation of input port interrupt (INTK0 or INTK1)
;Generation of ISIO and (INTK0 or INTK1)
;Generation of timer interrupt (TINT)
;Generation of ISIO and TINT
;Generation of (INTK0 or INTK1) and TINT
;Generation of ISIO, (INTK0 or INTK1) and TINT
;Generation of stopwatch interrupt (SWINTT)
;Generation of ISIO and SWINTT
;Generation of (INTK0 or INTK1) and SWINTT
;Generation of ISIO, (INTK0 or INTK1) and SWINTT
;Generation of TINT and SWINTT
;Generation of ISIO, TINT and SWINTT
;Generation of (INTK0 or INTK1), TINT and SWINTT
;Generation of all interrupts
Interrupt routine
Table 4.5 lists th e order of priority for processin g in terru pts.
Valu es of registers X, Y, A, B an d F are retain ed in stack.
Table 4.5
Priority
Interrupt Factor
Stopwatch
1
2
3
4
5
6
7
8
10 Hz
1 Hz
Order of interrupt priority in
program example
Stopwatch
Serial interface
K00–K03 input ports
K10 input port
Clock timer
32 Hz
8 Hz
2 Hz
Clock timer
Clock timer
II-16
EPSON
S1C62N33 TECHNICAL SOFTWARE
CHAPTER 4: INTERRUPT AND HALT
YIKSTB
EQU
EQU
●●H
●●H
;Buffer address for factor flags of input interrupts
;and stopwatch interrupts
;Buffer address for timer interrupt factor flags
YTIB
;
;
IN:
PUSH
PUSH
PUSH
PUSH
PUSH
PUSH
PUSH
PUSH
PUSH
XH
XL
XP
YH
YL
YP
A
;Store the value of X register to stack
;
;
;Store the value of Y register to stack
;
;
;Store the value of A register to stack
;Store the value of B register to stack
;Store the value of F register to stack
B
F
;
LD
LD
LD
LD
LD
OR
AND
X,7AH
Y,YIKSTB
MY,MX
X,76H
A,MX
;Reset and store
;input interrupt and stopwatch interrupt factor flags
;in the buffer
;Mask the stopwatch interrupt factor flags
;
;
A,1100B
MY,A
;by the value of the stopwatch interrupt mask register
;
;
FAN
JP
CALL
MY,0001B
Z,INSIT1
STI0
;If the ST10Hz interrupt factor flag is set
;and enabled
;then execute ST10Hz interrupt processing "SIT0"
INSIT1: LD
FAN
Y,YIKSTB
MY,0010B
Z,INSIO
SIT1
;If the ST1Hz interrupt factor flag is set
;and enabled
;
JP
CALL
;then execute ST1Hz interrupt processing "SIT1"
;
INSIO:
LD
LD
FAN
JP
CALL
Y,0F3H
A,MX
A,0001B
Z,INK0
ISIO
;Reset and store
;serial interface interrupt factor flag in the A register
;If the serial interface interrupt factor flag is set
;
;then execute serial interface interrupt processing "ISIO"
;
INK0:
LD
FAN
JP
Y,YIKSTB
MY,0100B
Z,INK1
IK0
;If the K0 interrupt factor flag is set
;
;
CALL
;then execute K0 interrupt processing "IK0"
S1C62N33 TECHNICAL SOFTWARE
EPSON
II-17
CHAPTER 4: INTERRUPT AND HALT
;
INK1:
LD
FAN
JP
Y,YIKSTB
MY,1000B
Z,INTI
IK1
;If the K1 interrupt factor flag is set
;
;
CALL
;then execute K1 interrupt processing "IK1"
;
INTI:
LD
LD
LD
LD
X,79H
Y,YETI
MY,MX
X,78H
MY,MX
;Reset and store
;the timer interrupt factor flags
;in the buffer
;Mask the timer interrupt factor flag
;by the value of the timer interrupt mask register
AND
;
FAN
JP
CALL
MY,0001B
Z,INTI8
TI32
;If the T32Hz interrupt factor flag is set
;and enabled
;then execute T32Hz interrupt processing "TI32"
;
INTI8:
LD
FAN
JP
Y,YTIB
MY,0010B
Z,INTI2
TI8
;If the T8Hz interrupt factor flag is set
;and enabled
;
CALL
;then execute T8Hz interrupt processing "TI8"
;
INTI2:
LD
FAN
JP
Y,YTIB
MY,0100B
Z,INRT
TI2
;If the TI2Hz interrupt factor flag is set
;and enabled
;
CALL
;then execute T2Hz interrupt processing "TI2"
;
INRT:
POP
POP
POP
POP
POP
POP
POP
POP
POP
RET
F
B
A
YP
YL
YH
XP
XL
XH
;Return the value of F register from stack
;Return the value of B register from stack
;Return the value of A register from stack
;Return the value of Y register from stack
;
;
;Return the value of X register from stack
;
;
;
Return to parent routine
Addresses of bu ffers IKSTB an d TIB can be set an ywh ere in
RAM.
Th is rou tin e assu m es th at processin g rou tin es "SIT0",
"SIT1", "ISIO", "IK0", "IK1", "TI32", "TI8" an d "TI2" h ave been
prepared separately for each of th e in terru pts.
II-18
EPSON
S1C62N33 TECHNICAL SOFTWARE
CHAPTER 4: INTERRUPT AND HALT
4.6 Prog ra m m ing Note s
(1) Write to th e in terru pt m ask registers on ly in th e DI statu s
(in terru pt flag = "0"). Writin g in th e EI statu s can cau se
an error.
(2) Even wh en th e in terru pt m ask registers (ETI, EISWIT) are
set to "0", th e in terru pt factor flags (TI, SWIT) of th e clock
tim er an d stopwatch cou n ter can be set wh en th e tim in g
con dition s are establish ed.
(3) Wh en an in terru pt is gen erated, th ree words of RAM are
u sed; also, it takes 12 cycles of th e CPU system clock
u n til th e valu e of th e in terru pt vector is set in th e pro-
gram cou n ter.
(4) Wh en an in terru pt occu rs, th e DI statu s (in terru pt flag =
"0") com es in to effect au tom atically.
(5) Read th e in terru pt factor flags on ly in th e DI statu s
(in terru pt flag = "0"). Readin g ou t in th e EI statu s can
cau se an error.
S1C62N33 TECHNICAL SOFTWARE
EPSON
II-19
CHAPTER 5: PERIPHERAL CIRCUITS (Watchdog Timer)
CHAPTER 5
PERIPHERAL CIRCUITS
Periph eral circu its of th e S1C62N33 Series, su ch as th e tim er
an d I/ O, are in terfaced with th e CPU by m em ory m apped I/ O
form at. Th is m ean s th at all periph eral circu its can be
con trolled by accessin g th e m em ory m ap's I/ O m em ory or
segm en t m em ory with m em ory operation in stru ction s.
Th is ch apter details h ow to con trol th e periph eral circu its.
5.1
Wa tc hd og Tim e r
Th e S1C62N33 Series in corporates a watch dog tim er.
If th e watch dog tim er reset is n ot execu ted by th e software
in at least 3–4 secon ds, th e in itial reset sign al is ou tpu t
au tom atically for th e CPU.
You can select wh eth er or n ot to u se th e watch dog tim er
with th e m ask option . Wh en "Not u se" is ch osen , th ere is n o
n eed to reset th e watch dog tim er.
Wa tc hd og tim e r
m e m ory m a p
Table 5.1 I/O data memory map (watchdog timer)
Register
Address
Comment
*1
D3
D2
D1
D0
Name
SR
1
0
–
*7
WDRST
WD2
WD1
WD0
WDRST
Reset
Reset
Watchdog timer reset *5
W
R
WD2
WD1
WD0
0
0
0
Timer data (watchdog timer 1/4 Hz)
Timer data (watchdog timer 1/2 Hz)
Timer data (watchdog timer 1 Hz)
7FH
*1 In itial valu e followin g in itial reset
*2 Not set in th e circu it
*3 Un defin ed
*5 Always "0" wh en bein g read
*6 Refer to m ain m an u al
*7 Page switch in g in I/ O m em ory is
n ot n ecessary
*4 Reset (0) im m ediately after bein g read
II-20
EPSON
S1C62N33 TECHNICAL SOFTWARE
CHAPTER 5: PERIPHERAL CIRCUITS (WATCHDOG TIMER)
WDRST: Th is is th e bit for resettin g th e watch dog tim er.
Watchdog timer reset
(7FH.D3)
Wh en "1" is written : Watch dog tim er is reset.
Wh en "0" is written : No operation
Read-ou t: Always "0"
Wh en th e watch dog tim er is u sed for th e reset fu n ction , th e
software m u st reset th e watch dog tim er with in 3 secon ds.
Operation restarts im m ediately after th e watch dog tim er is
reset.
Exa m p le of re se t
p roc e ssing for
wa tc hd og tim e r
Ordin arily, th is rou tin e is in corporated wh ere periodic
processin g takes place, su ch as in th e tim er in terru pt rou -
tin e, to detect program overru n , for in stan ce wh en th e
watch dog tim er processin g is bypassed.
Note In this case, timer data (WD0–WD2) cannot be used for timer
applications.
Th e watch dog tim er operates in th e h alt m ode. If th e h alt
statu s con tin u es for 3–4 secon ds, th e in itial reset sign al
restarts operation .
Specifications
Wh en th e tim in g flag ("0.5 sec flag") is set in th e T2Hz in ter-
ru pt processin g rou tin e "TI2", th e watch dog tim er will be
reset every secon d.
Wh en th e rou tin e "basic tim er 'CK'" for th e tim er is execu ted
every secon d on th e secon d, th e watch dog tim er will be reset
every secon d on th e h alf-secon d.
n sec
n.5 sec
(n+1) sec (n+1).5 sec
Time
"CK" is executed
"CK" is executed
Fig. 5.1
Watchdog timer
is reset
Watchdog timer
is reset
Timing chart
S1C62N33 TECHNICAL SOFTWARE
EPSON
II-21
CHAPTER 5: PERIPHERAL CIRCUITS (Watchdog Timer)
Program
XTISF EQU
0001B
;0.5 sec flag (TISF)
YFTM
;
EQU
◆◆H
;Address for timing flag set
;
TI2:
LD
X,YFTM
;TISF = "0" or "1"?
FAN
JP
MX,XTISF
NZ,TI21
;
;
;
OR
LD
LD
RET
MX,XTISF
X,7FH
MX,0001B
;TISF = "0": Set the TIS flag
;
;
;
Reset the watchdog timer
Returns to parent routine
TI21: AND
CALL
MX,XTISF XOR 0FH ;TISF = "1": Reset the TIS flag
CK Execute the basic timer "CK"
;
;
RET
;Returns to parent routine
Th e address for th e tim in g flag set FTM can be set an ywh ere
in RAM.
Fu rth er, th is rou tin e assu m es th at a tim er su brou tin e h as
been prepared separately to m ake 1 secon d th e u n it for th e
rou tin e "basic tim er 'CK'".
(See page 63, "Exam ple of u sin g tim er in terru pt" for h ow to
m ake "basic tim er 'CK'".)
Wh en th e watch dog tim er is u sed for th e reset fu n ction , th e
software m u st reset th e watch dog tim er with in 3 secon ds.
In th is case, tim er data (WD0–WD2) can n ot be u sed for
tim er application s.
Prog ra m m ing note
II-22
EPSON
S1C62N33 TECHNICAL SOFTWARE
CHAPTER 5: PERIPHERAL CIRCUITS (OSC3)
5.2 OSC3
S1C62A33 h as two bu ilt-in oscillation circu its (OSC1 an d
OSC3).
Wh en processin g of S1C63A33 requ ires h igh -speed opera-
tion s, th e CPU's operatin g clock sh ou ld be switch ed from
OSC1 to OSC3.
OSC3 m e m ory m a p
Table 5.2 I/O data memory map (OSC3)
Register
Address
Comment
*1
D3
D2
D1
D0
Name
–
SR
1
0
*7
*2
–
CLKCHG OSCC
R/W
IOC1
Unused *5
CLKCHG
OSCC
IOC1
0
0
0
OSC3
ON
OSC1
OFF
CPU clock switch *6
R
FEH
OSC3 oscillator ON/OFF
I/O control register 1 (P10–P13)
Output
Input
*1 In itial valu e followin g in itial reset
*2 Not set in th e circu it
*3 Un defin ed
*5 Always "0" wh en bein g read
*6 Refer to m ain m an u al
*7 Page switch in g in I/ O m em ory is
n ot n ecessary
*4 Reset (0) im m ediately after bein g read
CLKCHG: Th e CPU's operation clock is selected with th is register
The CPU's clock switch (S1C62N33 on ly).
(FEH.D2)
Wh en "1" is written : OSC3 is selected
Wh en "0" is written : OSC1 is selected
Read-ou t: Available
Th is register can n ot be con trolled for S1C62N33/ 62L33, so
th at OSC1 is selected regardless of th e set valu e.
S1C62N33 TECHNICAL SOFTWARE
EPSON
II-23
CHAPTER 5: PERIPHERAL CIRCUITS (OSC3)
Exa m p le of using
OSC3
Note To lessen current consumption, keep OSC3 oscillation OFF except
when the CPU must be run at high speed. Also, with S1C62N33/
62L33, keep OSCC fixed to "0".
(1 ) Swit ch in g from OSC1 t o OSC3
Th is su brou tin e first sets OSC3 to ON, an d th en , after abou t
5 m s, switch es th e CPU clock to OSC3.
Specifications
Program
OS3:
LD
OR
X,0FEH
MX,0010B
;Set OSC3 to ON
;
LD
A,0EH
;Delay of 5.28 ms: preparation
OS3DLLP: ADD
A,0FH
NZ,OS3DLLP
;
;
Loop for delay
JP
;
OR
RET
MX,0100B
;Switche the CPU clock to OSC3
;Return to parent routine
Note
A 5.28 m s delay is specified before switch in g to OSC3, to
allow tim e for th e oscillation circu it to stabilize.
II-24
EPSON
S1C62N33 TECHNICAL SOFTWARE
CHAPTER 5: PERIPHERAL CIRCUITS (OSC3)
(2 ) Swit ch in g from OSC3 t o OSC1
Specifications
Program
Th is su brou tin e switch es th e CPU clock to OSC1, an d th en
sets OSC3 to OFF.
OS1:
;
LD
AND
X,0FEH
MX,1011B
;Switche the CPU clock to OSC1
;
AND
RET
MX,1101B
;Set OSC3 to OFF
;Return to parent routine
Note
To preven t an error, first switch OSC1, an d th en set OSC3
to OFF in th e n ext step.
(1) It takes at least 5 m s from th e tim e th e OSC3 oscillation
circu it goes ON u n til th e oscillation stabilizes. Con se-
qu en tly, wh en switch in g th e CPU operation clock from
OSC1 to OSC3, do th is after a m in im u m of 5 m s h ave
elapsed sin ce th e OSC3 oscillation wen t ON.
Prog ra m m ing note s
Fu rth er, th e oscillation stabilization tim e varies depen d-
in g on th e extern al oscillator ch aracteristics an d con di-
tion s of u se, so allow am ple m argin wh en settin g th e wait
tim e.
(2) Wh en switch in g th e clock from OSC3 to OSC1, u se a
separate in stru ction for switch in g th e OSC3 oscillation
OFF.
(3) To lessen cu rren t con su m ption , keep OSC3 oscillation
OFF except wh en th e CPU m u st be ru n at h igh speed.
Also, with S1C62N33/ 62L33, keep OSCC fixed to "0".
S1C62N33 TECHNICAL SOFTWARE
EPSON
II-25
CHAPTER 5: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function)
5.3 Sup p ly Volta g e De te c tion (SVD) Circ uit a nd
He a vy Loa d Prote c tion Func tion
Th e S1C62N33 Series h as a bu ilt-in su pply voltage detection
(SVD) circu it, so th at th e software can fin d wh en th e sou rce
voltage lowers.
S1C62L33 h as a h eavy load protection fu n ction for wh en th e
battery load becom es h eavy an d th e sou rce voltage drops.
*1 In itial valu e followin g in itial reset
*5 Always
SVD c irc uit m e m ory
m a p
Table 5.3 I/O data memory map (SVD circuit and heavy load protection function)
Register
Address
Comment
*1
D3
D2
SVDDT
SVDON
R
D1
D0
Name
HVLD
SR
0
1
0
*7
Heavy
load
HVLD
EISWIT1 EISWIT0
Normal Heavy load protection mode register
SVD evaluation data (at read-out)
Low voltage
ON
SVDDT
SVDON
0
0
Normal
R/W
R/W
SVD ON/OFF (at writing)
Interrupt mask register
(stopwatch 1 Hz)
W
OFF
76H
EISWIT1
EISWIT0
0
0
Enable
Enable
Mask
Interrupt mask register
(stopwatch 10 Hz)
Mask
"0" wh en bein g read
*2 Not set in th e circu it
*3 Un defin ed
*6 Refer to m ain m an u al
*7 Page switch in g in I/ O m em ory is
n ot n ecessary
*4 Reset (0) im m ediately after bein g read
To obtain th e SVD detection resu lt, follow th e program m in g
sequ en ce below.
Exa m p le of find ing
sup p ly volta g e using
SVD c irc uit
0. Set HVLD to "1" (on ly wh en th e CPU system clock is
fosc3 in S1C62A33)
1. Set SVDON to "1"
2. Main tain at 100 µs m in im u m
3. Set SVDON to "0"
4. Read ou t SVDDT
5. Set HVLD to "0" (on ly wh en th e CPU system clock is
fosc3 in S1C62A33)
II-26
EPSON
S1C62N33 TECHNICAL SOFTWARE
CHAPTER 5: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function)
Wh en HVLD is set to "1" or low voltage is detected by th e
SVD, th e HVLD circu it is tu rn ed ON. At th e sam e tim e th e
SVD circu it is switch ed ON an d OFF.
At th is tim e, sam plin g con trol is execu ted for th e SVD cir-
cu it ON tim e. Th ere are two types of sam plin g tim e, as
follows:
➀ Th e tim e of on e in stru ction cycle im m ediately after th e
HVLD circu it is tu rn ed ON.
➀ Sam plin g at cycles of 2 Hz ou tpu t by th e clock tim er
wh ile HVLD circu it ON tim e.
Wh en th e CPU system clock is fosc3 in S1C62A33, th e
detection resu lt at th e tim in g in ➀ above m ay be in valid or
in correct. Wh en perform in g SVD detection u sin g th e tim in g
in ➀, be su re th at th e CPU system clock is fosc1.
Appreciable current is consumed during operation of SVD detec-
tion, so keep SVD detection OFF except when necessary.
Note
(1 ) For OSC1 u sin g SVDON
Specifications Wh en th e CPU clock is OSC1, th e tim in g flag ("0.5 sec flag")
is set in th e T2Hz in terru pt processin g rou tin e "TI2", so th at
th e su pply voltage is detected every secon d.
Every secon d on th e secon d th e tim er rou tin e "basic tim er
'CK'" is execu ted, to tu rn SVD ON or OFF every secon d on
th e h alf secon d.
If th e detection resu lt in dicates th at th e voltage is low, th e
separately prepared low voltage display rou tin e "DSSVD" is
execu ted.
n sec
n.5 sec
(n+1) sec (n+1).5 sec
Time
"CK" is executed
"CK" is executed
Fig. 5.3.1
Supply voltage
is detected
Supply voltage
is detected
Timing chart
S1C62N33 TECHNICAL SOFTWARE
EPSON
II-27
CHAPTER 5: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function)
Program
0.5 sec flag (TISF)
XTISF EQU
0001B
➀➀H
;
;
Address for timing flag set
YFTM
;
EQU
;
TISF = "0" or "1"?
TI2:
LD
FAN
JP
X,YFTM
MX,XTISF
NZ,TI21
;
;
;
;
TISF = "0": Set the TIS flag
Detect: SVD ON
OR
LD
OR
AND
FAN
JP
MX,XTISF
X,76H
;
;
;
;
;
;
;
MX,0100B
MX,1011B
MX,0100B
Z,TI2RT
DSSVD
SVD OFF
If result is "1" (low voltage)
then execute display routine "DSSVD"
CALL
;
Return to parent routine
TISF = "1": Reset the TIS flag
Execute the basic timer "CK"
TI2RT: RET
TI21: AND
;
MX,XTISF XOR 0FH ;
CALL
CK
;
;
Return to parent routine
RET
;
Th e address for th e tim in g flag set FTM can be set an ywh ere
in RAM.
Th is rou tin e assu m es th at a tim er su brou tin e h as been
prepared separately to m ake 1 secon d th e u n it for th e rou -
tin e "basic tim er 'CK'".
(See page 63, "Exam ple of u sin g tim er in terru pt" for h ow to
m ake "basic tim er 'CK'".)
Timing chart of SVD operation
Criteria voltage
(1.2 V)
Source voltage
1 sec
SVDON register
SVDDT register
HVLD circuit
0.5 sec
Fig. 5.3.2
Timing chart of
SVD operation
SVD circuit
II-28
EPSON
S1C62N33 TECHNICAL SOFTWARE
CHAPTER 5: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function)
(2 ) For OSC3 u sin g HVLD
Specifications
Wh en th e CPU clock is OSC3, th e su pply voltage is detected
every secon d, ju st as for (1). However, th e m eth od of detec-
tion is th rou gh th e ON an d OFF statu s of HVLD.
Program
Wh en th e CPU clock is OSC3, detection m u st be perform ed
after switch in g th e CPU clock to OSC1.
XTISF EQU
0001B
➀➀H
;0.5 sec flag (TISF)
;Address for timing flag set
YFTM
;
EQU
;
TI2:
LD
X,YFTM
;TISF = "0" or "1"?
FAN
JP
MX,XTISF
NZ,TI21
;
;
;
OR
LD
LD
AND
OR
AND
OR
FAN
JP
MX,XTISF
X,76H
Y,0FEH
MY,1011B
MX,1000B
MX,0011B
MY,0100B
MX,0100B
Z,TI2RT
DSSVD
;TISF = "0": Set the TIS flag
;
;
;
;
;
;
;
;
;
Detect: Preparation
Switch the CPU's operating clock OSC1
HVLD ON
HVLD OFF
Return the CPU's operating clock to OSC3
If the result is "1" (low voltage)
CALL
then execute display routine "DSSVD"
Return to parent routine
;
TI2RT: RET
TI21: AND
;
MX,XTISF XOR 0FH ;TISF = "1": Reset the TIS flag
CK
Execute the basic timer "CK"
CALL
;
;
RET
;Return to parent routine
Note
SVDON is fixed to "0" wh en th e HVLD is tu rn d OFF, becau se
SVDON risides in th e sam e bits at th e sam e address as
SVDDT, an d on e or th e oth er is selected by write or read
operation .
S1C62N33 TECHNICAL SOFTWARE
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CHAPTER 5: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function)
(3 ) For S1 C6 2 L3 3 u sin g HVLD
Specifications
S1C62L33 u ses HVLD to detect su pply voltage. Th e oth er
con dition s are th e sam e as for (1) an d (2). However, th e
CPU of S1C62L33 does n ot u se OSC3 for th e clock.
Program
S1C62L33 h as a h eavy load protection fu n ction , so do n ot
u se HVLD to detect su pply voltage in th e h eavy load protec-
tion m ode.
(See th e followin g section s for th e h eavy load protection
fu n ction .)
XTISF
YFTM
;
EQU
EQU
0001B
➀➀H
;0.5 sec flag (TISF)
;Address for timing flag set
;
TI2:
LD
X,YFTM
;TISF = "0" or "1"?
FAN
JP
MX,XTISF
NZ,TI21
;
;
;
;
OR
LD
FAN
JP
MX,XTISF
X,76H
MX,1000B
NZ,TI2DSB
;TISF = "0": Set the TIS flag
;
;
;
If HVLD is OFF
OR
AND
TI2DSB: FAN
JP
MX,1000B
MX,0011B
MX,0100B
Z,TI2RT
;
;
;
;
;
then detect: HVLD ON
HVLD OFF
If the result is "1" (low voltage)
CALL DSSVD
then execute display routine "DSSVD"
Return to parent routine
;
TI2RT: RET
;
TI21:
AND
MX,XTISF XOR 0FH ;TISF = "1": Reset the TIS flag
CALL CK
;
Execute the basic timer "CK"
;
RET
;Return to parent routine
Note
Wh en th e HVLD is tu rn ed OFF, SVDON is fixed to "0".
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S1C62N33 TECHNICAL SOFTWARE
CHAPTER 5: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function)
Note th at th e h eavy load protection fu n ction on th e
S1C62L33 is differen t from th e S1C62N33.
Exa m p le of using
he a vy loa d p rote c -
tion func tion
(1) In case of S1C62L33
Th e S1C62L33 h as th e h eavy load protection fu n ction for
wh en th e battery load becom es h eavy an d th e sou rce
voltage drops, su ch as wh en an extern al bu zzer sou n ds
or an extern al lam p ligh ts. Th e state wh ere th e h eavy
load protection fu n ction is in effect is called th e h eavy
load protection m ode. In th is m ode, operation with a
lower voltage th an n orm al is possible.
Th e n orm al m ode ch an ges to th e h eavy load protection
m ode in th e followin g two cases:
➀ Wh en th e software ch an ges th e m ode to th e h eavy load
protection m ode (HVLD = "1")
➀ Wh en su pply voltage drop (SVDDT = "1") in th e SVD
circu it is detected, th e m ode will au tom atically sh ift to
th e h eavy load protection m ode u n til th e su pply volt-
age is recovered (SVDDT = "0")
In th e h eavy load protection m ode, th e in tern ally regu -
lated voltage is gen erated by th e liqu id crystal driver
sou rce ou tpu t VL2 so as to operate th e in tern al circu it.
Con sequ en tly, m ore cu rren t is con su m ed in th e h eavy
load protection m ode th an in th e n orm al m ode. Un less it
is n ecessary, be carefu l n ot to set th e h eavy load protec-
tion m ode with th e software. Also, wh en th e SVD is to be
tu rn ed on du rin g operation in th e h eavy load protection
m ode, lim it th e ON tim e to 10 m s per secon d of operation
tim e.
(2) In case of S1C62N33/ 62A33
Th is fu n ction can be u sed wh en th e "Use" is selected by
th e m ask option for th e h eavy load protection fu n ction .
Th e S1C62N33/ 62A33 h as th e h eavy load protection
fu n ction for wh en th e battery load becom es h eavy an d
th e sou rce voltage ch an ges, su ch as wh en an extern al
bu zzer sou n ds or an extern al lam p ligh ts. Th e state
wh ere th e h eavy load protection fu n ction is in effect is
called th e h eavy load protection m ode. Com pared with
th e n orm al operation m ode, th is m ode can redu ce th e
ou tpu t voltage variation of th e con stan t voltage/ booster
voltage circu it of th e LCD system .
S1C62N33 TECHNICAL SOFTWARE
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CHAPTER 5: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function)
Th e n orm al m ode ch an ges to th e h eavy load protection
m ode in th e followin g case:
➀ Wh en th e software ch an ges th e m ode to th e h eavy load
protection m ode (HVLD = "1")
Th e h eavy load protection m ode switch es th e con stan t
voltage circu it of th e LCD system to th e h igh -stability
m ode from th e low cu rren t con su m ption m ode. Con se-
qu en tly, m ore cu rren t is con su m ed in th e h eavy load
protection m ode th an in th e n orm al m ode. Un less it is
n ecessary, be carefu l n ot to set th e h eavy load protection
m ode with th e software.
(1 ) Con t rol of h eavy load prot ect ion fu n ct ion u sin g flag (S1 C6 2 L3 3 )
Specifications
Wh en h eavy load protection m ode is set, th is will be rou tin e
"HLONBZ" wh ich switch es BZ ON, rou tin e "BZOF" wh ich
switch es BZ OFF, an d 2 Hz in terru pt rou tin e "TI2" wh ich
con trols 1-secon d waitin g release.
Th is rou tin e em ploys th e h eavy load protection m ode release
flag HLOFF, wh ich recogn izes term in ation of h eavy load
drive, an d th e h eavy load protection m ode release delay flag
HLOFDLF, wh ich takes th e tim in g of a 1-secon d wait.
Setting heavy load protection mode
XHLOF
XHLOFDL EQU
XNOTHL
YFHL
EQU
1000B
0100B
0011B
➀➀H
;Heavy load protection mode release flag
;Heavy load protection mode release delay flag
;
EQU
EQU
;Address of heavy load protection function related flag set
;
;
HLONBZ: LD
X,76H
;Set heavy load protection mode
OR
LD
MX,1000B
X,YFHL
;
;Reset flags related to heavy load protection
AND
LD
MX,XNOTHL
X,7CH
;
;Switch BZ ON
OR
MX,0001B
;
RET
;Return to parent routine
Th is rou tin e assu m es th at th e addresses of th e flag set
related to h eavy load protection fu n ction s togeth er with th e
0.5 sec flag are allocated su itably in RAM as th e addresses
of th e tim in g flag set.
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S1C62N33 TECHNICAL SOFTWARE
CHAPTER 5: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function)
Release of heavy load protection mode
Wh en th e h eavy load drive term in ates, th e h eavy load
protection m ode release flag is set, th e h eavy load protection
m ode delay flag is set an d reset with th e 1-secon d tim er
du rin g th e T2Hz in terru pt processin g rou tin e, th e h eavy
load protection m ode is released.
n sec
n.5 sec
(n+1) sec
(n+1).5 sec
Time
"CK" is executed
"CK" is executed
HLOFDL
flag is set
Heavy load protection
mode is released
(Two flags are reset)
Heavy load
drive terminates
(HLOF flag is set)
Fig. 5.3.3
Timing chart
XTISF
XHLOFF
XHLOFDL EQU
XNOTHL
YFTM
YFHL
;
EQU
EQU
0001B
1000B
0100B
1100B
➀➀H
;0.5 sec flag (TISF)
;High load protection mode release flag (HLOFF)
;High load protection mode release delay flag (HLOFDLF)
;
;Address of timing flag set
;Address of heavy load protection flag set
EQU
EQU
EQU
➀➀H
;
BZOF:
LD
X,7CH
;Stop BZ
AND
LD
OR
MX,1110B
X,YFHL
MX,XHLOF
;
;Set the HLOF flag
;
RET
;Return to parent routine
;
;
TI2:
LD
X,YFTM
;TISF = "0" or "1"?
FAN
JP
MX,XTISF
NZ,TI21
;
;
;
OR
MX,XTISF
;TISF = "0": Set the TIS flag
FAN
JP
FAN
JP
MX,XHLOFDL
Z,TI2RT
MX,XHLOFDL
NZ,TI2HLO
;
;
;
;
If the HLOF flag is set
then HLOFDLF = "0" or "1"?
;
OR
RET
MX,XHLOFDL
;
;
HLOFDLF = "0": Set the HLOFDL flag
Return to parent routine
S1C62N33 TECHNICAL SOFTWARE
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CHAPTER 5: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function)
TI2HLO: AND
MX,XNOTHL
;HLOFDLF = "1": Reset heavy load protection
;
;
;
flag set
LD
AND
X,76H
MX,0011B
Release heavy load protection mode
and fix SVDON to "0"
;
TI2RT:
TI21:
RET
AND
;Return to parent routine
MX,XTISF XOR 0FH ;TISF = "1": Reset the TIS flag
CALL
CK
;Execute basic timer "CK"
;
RET
;Return to parent routine
See page 40, "Exam ple of u sin g ou tpu t ports" for details on
BZ con trol.
Notes
1. Wh en th e h eavy load protection m ode is set, th e h eavy
load protection flags m u st be reset.
2. SVD is fixed to "0" wh en th e h eavy load protection m ode
is released, becau se th e SVDON resu lt is n ot fed back to
SVDON th rou gh th e AND in stru ction .
(2 ) Met h od wit h ou t u sin g flags (S1 C6 2 L3 3 )
Specifications
Wh en h eavy load protection m ode is set, th is will be rou tin e
"HLONBZ" wh ich switch es BZ ON an d rou tin e "BZHLOF"
wh ich stop BZ th en releases th e h eavy load protection m ode.
Note, h owever, th at u n like item (1) above, it does n ot u se
flags.
SVDON is u sed to release th e h eavy load protection m ode
with ou t u sin g flags. After th e h eavy load drive term in ates,
th e SVD is set ON an d OFF, an d th en th e h eavy load protec-
tion m ode is released.
Program
HLONBZ: LD
X,76H
;Set the heavy load protection mode
OR
LD
MX,1000B
X,7CH
;
;Switch BZ ON
OR
MX,0001B
;
RET
;Return to parent routine
;
;
BZHLOF: LD
X,7CH
MX,1110B
X,76H
;Stop BZ
;
;SVD ON
AND
LD
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S1C62N33 TECHNICAL SOFTWARE
CHAPTER 5: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function)
OR
AND
AND
MX,0100B
MX,1011B
MX,0011B
;
;
OFF
;Release the heavy load protection mode
;and fix SVDON to "0"
RET
;Return to parent routine
Note
SVD is fixed to "0" wh en th e h eavy load protection m ode is
released, becau se th e SVDON resu lt is n ot fed back to
SVDON th rou gh th e AND in stru ction .
Timing chart of heavy load protection mode operation
Criteria voltage
(1.2 V)
Source voltage
HVLD register
HVLD circuit
BZ output
SVDON register
0.5 sec
Fig. 5.3.4
Timing chart
SVD circuit
SVDDT register
of HVLD operation
(3 ) Con t rol of h eavy load prot ect ion (for S1 C6 2 N3 3 / 6 2 A3 3 )
Specifications
Wh en th e h eavy load protection fu n ction is selected for th e
S1C62N33 or S1C62A33 by th e m ask option settin g, th e
"HLBZ10" rou tin e sets th e h eavy load protection m ode an d
ou tpu ts th e BZ sign al for 10 m s, th en , it releases th e h eavy
load protection m ode.
However, th e OSC1 clock (32.768 kHz) m u st be set for th e
CPU operatin g clock.
10 ms
BZ
Fig. 5.3.5
HVLD
Timing chart
S1C62N33 TECHNICAL SOFTWARE
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II-35
CHAPTER 5: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function)
Program
HLBZ10: LD
X,76H
;Set the heavy losd protection mode
OR
LD
MX,1000B
Y,7CH
;
;Switch BZ ON
OR
MY,1000B
;
;
CALL ST10MS
;10 ms soft timer call
;
AND
AND
MY,0111B
MX,0111B
;Switch BZ OFF
;Release the heavy load protection mode
;
;
ST10MS: LD
RDF
A,0H
;10 ms soft timer subroutine
;Reset the decimal flag
ST10MS1: NOP7
;Loop for 10 ms
ADD
JP
RET
A,0FH
NZ,ST10MS1
;(7+7+5) clock × 16
;
;
Note
Th e h eavy load protection m ode can be released im m ediately
after drivin g th e h eavy load (BZ ou tpu t).
To redu ce cu rren t con su m ption , release th e h eavy load
protection m ode u n less oth erwise n ecessary.
(1) It takes 100 µs from th e tim e th e SVD circu it goes ON
u n til a stable resu lt is obtain ed. For th is reason , keep
th e followin g software n otes in m in d:
Prog ra m m ing note s
➀ Wh en th e CPU system clock is fosc1
1. Wh en detection is don e at HVLD
After writin g "1" on HVLD, read th e SVDDT after 1
in stru ction h as passed.
2. Wh en detection is don e at SVDON
After writin g "1" on SVDON, write "0" after at least
100 µs h as lapsed (possible with th e n ext in stru c-
tion ) an d th en read th e SVDDT.
➀ Wh en th e CPU system clock is fosc3 (in case of
S1C62A33 on ly)
1. Wh en detection is don e at HVLD
After writin g "1" on HVLD, read th e SVDDT after 0.6
sec h as passed. (HVLD h olds "1" for at least 0.6 sec)
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S1C62N33 TECHNICAL SOFTWARE
CHAPTER 5: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function)
2. Wh en detection is don e at SVDON
Before writin g "1" on SVDON, write "1" on HVLD
first; after at least 100 µs h as lapsed after writin g
"1" on SVDON, write "0" on SVDON an d th en read
th e SVDDT.
(2) To redu ce cu rren t con su m ption , set th e SVD operation to
OFF u n less oth erwise n ecessary.
(3) SVDON resides in th e sam e bit at th e sam e address as
SVDDT, an d on e or th e oth er is selected by write or read
operation . Wh en writin g a "1" to SVDON u se th e OR
com m an d, an d wh en writin g a "0" u se th e AND com -
m an d. No oth er com m an ds sh ou ld be u sed for th is
pu rpose.
(4) Select on e of th e followin g software processin g to retu rn
to th e n orm al m ode after a h eavy load h as been driven in
th e h eavy load protection m ode (S1C62L33).
➀ After h eavy load drive is com pleted, retu rn to th e
n orm al m ode after at least on e secon d h as elapsed.
➀ After h eavy load drive is com pleted, switch SVD ON
an d OFF (at least 100 µs is n ecessary for th e ON
statu s) an d th en retu rn to th e n orm al m ode.
Th e S1C62N33/ 62A33 retu rn s to th e n orm al m ode after
drivin g a h eavy load with ou t special software processin g.
(5) To redu ce cu rren t con su m ption , be carefu l n ot to set th e
h eavy load protection m ode with th e software u n less
oth erwise n ecessary.
(6) Wh en th e SVD is to be tu rn ed on du rin g operation in th e
h eavy load protection m ode, lim it th e ON tim e to 10 m s
per secon d of operation tim e.
S1C62N33 TECHNICAL SOFTWARE
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II-37
CHAPTER 5: PERIPHERAL CIRCUITS (Output Ports)
5.4 Outp ut Ports (R00–R03, R10–R13)
Th e S1C62N33 Series reserves eigh t bits (4 bits × 2) for
gen eral ou tpu t ports. Th e ou tpu t ports R10–R13 can be
u sed as special ou tpu t ports.
Outp ut p ort m e m ory
m a p
Table 5.4 I/O data memory map (output ports)
Register
Address
Comment
*1
D3
D2
D1
D0
Name
R03
SR
0
1
0
*7
R03
R02
R01
R00
High
Low
R02
R01
R00
R13
R12
R11
0
0
0
0
0
0
High
High
High
High
High
High
Low
Low
Low
Low
Low
Low
R/W
7BH
Output port (R00–R03)
R13
R12
R11
R10
Output port (R13, BZ) *6
Output port (R12, FOUT) *6
Output port (R11)
R/W
7CH
R10
0
0
High
Low
Output port (R10, BZ) *6
Buzzer frequency selection register
Unused *5
BZFQ
R/W
–
–
–
BZFQ
2 kHz
4 kHz
*2
–
–
–
R
F6H
*2
*2
Unused *5
Unused *5
*1 In itial valu e followin g in itial reset
*2 Not set in th e circu it
*3 Un defin ed
*5 Always "0" wh en bein g read
*6 Refer to m ain m an u al
*7 Page switch in g in I/ O m em ory is
n ot n ecessary
*4 Reset (0) im m ediately after bein g read
II-38
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S1C62N33 TECHNICAL SOFTWARE
CHAPTER 5: PERIPHERAL CIRCUITS (Output Ports)
Th e followin g explan ation s cover th e con trol registers wh en
special ou tpu t h as been selected for R10, R12, an d R13.
R10, R13
(when BZ and BZ output is
selected):
Th ese bits con trol th e ou tpu t of th e bu zzer sign als (BZ, BZ).
Wh en "1" is written : Bu zzer sign al is ou tpu t
Wh en "0" is written : Low level (DC) is ou tpu t
Read-ou t: Available
Special output ports
data
(7CH.D0 and D3)
BZ is ou tpu t from pin R13. Th e m ask option su pports
selection of ou tpu t con trol by R13, or ou tpu t con trol by R10
sim u ltan eou sly with BZ.
• Wh en R13 con trols BZ ou tpu t
BZ ou tpu t an d BZ ou tpu t can be con trolled in depen d-
en tly. BZ ou tpu t is con trolled by writin g data to R10,
an d BZ ou tpu t is con trolled by writin g data to R13.
• Wh en R10 con trols BZ ou tpu t
BZ ou tpu t an d BZ ou tpu t can be con trolled sim u ltan e-
ou sly by writin g data to R10 on ly. For th is case, R13 can
be u sed as a on e-bit gen eral register h avin g both read
an d write fu n ction s, an d data of th is register exerts n o
affect on BZ ou tpu t (ou tpu t from pin R13).
R12
(when FOUT is selected):
Special output port
data
Con trols th e FOUT (clock) ou tpu t.
Wh en "1" is written : Clock ou tpu t
Wh en "0" is written : Low level (DC) ou tpu t
Read-ou t: Available
(7CH.D2)
S1C62N33 TECHNICAL SOFTWARE
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II-39
CHAPTER 5: PERIPHERAL CIRCUITS (Output Ports)
Exa m p le of using
outp ut p orts
(1 ) Writ in g an d readin g t o ou t pu t port s
Specifications
Register R13 con trol for pin R13 h as been selected by m ask
option .
First, th e im m ediate valu e "0010B" is ou tpu t to th e ou tpu t
ports R00–R03.
Th e valu e of RAM, OUTB is ou tpu t to ou tpu t ports R10–R13.
Figu re 5.4.1 in dicates th e correspon den ce of write data an d
ou tpu t ports.
RAM, OUTB
D3 D2 D1 D0
Immediate value
0
0
1
0
R13 register
R12 register
R11 register
R10 register
R13
R12
R11
R10
R03 register
R02 register
R01 register
R00 register
R03: Becomes low output
R02: Becomes low output
R01: Becomes high output
R00: Becomes low output
Fig. 5.4.1
Correspondence
of write data and
output ports
Th en , th e statu s of th e (ou tpu ttin g) pin s of ou tpu t ports
R00–R03 is read in to B register, an d th e statu s of th e pin s of
ou tpu t ports R10–R13 is read in to RAM, DTB.
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S1C62N33 TECHNICAL SOFTWARE
CHAPTER 5: PERIPHERAL CIRCUITS (Output Ports)
Program
YOUTB EQU
●●H
●●H
;Buffer address of data to be output to R10–R13
;Buffer address of data
YDTB
EQU
;
;
LD
LD
X,7BH
MX,0010B ;
;Output (write) the immediate value "0010B" to R00–R03
;
LD
LD
LD
X,7CH
Y,YOUTB
MY,MX
;Output (write) the value of RAM, OUTB to R10–R13
;
;
;
LD
LD
X,7BH
B,MX
;Read the value of R00–R03 (being output) to B register
;
LD
LD
LD
X,7CH
Y,YDTB
MY,MX
;Read the value of R10–R13 (being output) to RAM, DTB
;
;
Addresses for RAM, OUTB an d DTB are allocated appropri-
ately.
S1C62N33 TECHNICAL SOFTWARE
EPSON
II-41
CHAPTER 5: PERIPHERAL CIRCUITS (Output Ports)
(2 ) Operat ion of ou t pu t port s by separat e bit s
Specifications
Th is rou tin e u ses th e read-ou t capability of th e ou tpu t port
con trol registers, to con trol ou tpu t for separate bits with th e
m em ory arith m etic in stru ction s.
First, "1" is written to registers R00 an d R03 by th e OR
in stru ction , an d th en "0" is written to register R01 by th e
AND in stru ction .
Th e resu lt of th e ou tpu t to ports R00–R03 is sh own in
Figu re 5.4.2.
I/O memory
R03 R02 R01 R00
Set to "1"
No change
Set to "0"
Set to "1"
R03: Becomes high output
R02: No change
R01: Becomes low output
R00: Becomes high output
Fig. 5.4.2
Output result
LD
X,7BH
;Make R00 and R03 outputs high
Program
OR
AND
MX,1001B
MX,1101B
;
;Make R01 output low
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S1C62N33 TECHNICAL SOFTWARE
CHAPTER 5: PERIPHERAL CIRCUITS (Output Ports)
(3 ) Scan n in g for k ey in pu t by port s R0 0 –R0 3
Specifications
Th e key m atrix is sh own in Figu re 5.4.3. Th is is th e scan -
n in g su brou tin e, "KYSC", to specify th e key th at h as been
m ade h igh in pu t.
Kxx
R03
R02
R01
R00
Fig. 5.4.3
Key matrix (Kxx × R00–R03)
Program
"KYSC" first brin gs R00 to h igh ou tpu t an d th e oth er ports
to low ou tpu t, an d th en execu tes "KYIN" to ju dge wh eth er an
en try h as been m ade to th e key con n ected to R00.
Regardless of th e resu lt of evalu ation , th e h igh ou tpu t pin is
sh ifted to th e left an d th e key con n ected to th e n ext pin is
evalu ated.
Th is processin g is repeated u p to R03.
KYSC:
;
LD
LD
X,7BH
MX,0001B ;
;Make R00 only high output
KYSCLP: CALL KYIN
;Scanning loop: Execute key input evaluation processing "KYIN"
LD
ADD
JP
X,7BH
MX,MX
NZ,KYSCLP;
;
;
Shift high output to left
Continue until R00–R03 are all low
RET
;Return to parent routine
Th is rou tin e assu m es th at th e key in pu t evalu ation process-
in g rou tin e "KYIN" h as been prepared separately.
S1C62N33 TECHNICAL SOFTWARE
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CHAPTER 5: PERIPHERAL CIRCUITS (Output Ports)
(4 ) Con t rol of BZ (wh en R1 3 is R1 0 con t rol)
Specifications
Th is is th e su brou tin e to switch BZ an d BZ ON an d OFF
wh en R13 h as becom e R10 con trol.
In su brou tin e "BZ4", BZ ou tpu t is switch ed ON after th e BZ
frequ en cy is set to 4 kHz.
In su brou tin e "BZ2", BZ ou tpu t is switch ed ON after th e BZ
frequ en cy is set to 2 kHz.
In su brou tin e "BZOF", BZ ou tpu t is switch ed OFF.
Program
BZ4:
BZ2:
LD
LD
LD
OR
X,0F6H
MX,0000B
X,7CH
;Set BZ frequency to 4 kHz
;
;Make R10 and R13 high output
;
MX,0001B
RET
;Return to parent routine
LD
LD
LD
OR
X,0F6H
MX,1000B
X,7CH
;Set BZ frequency to 2 kHz
;
;Make R10 and R13 high output
;
MX,0001B
RET
;Returns to parent routine
BZOF: LD
AND
RET
X,7CH
MX,1110B
;Make R10 and R13 low output
;
;Return to parent routine
Non e of th ese rou tin es affects registers R11–R13 (ou tpu t
pin s R11 an d R12).
Note
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S1C62N33 TECHNICAL SOFTWARE
CHAPTER 5: PERIPHERAL CIRCUITS (Output Ports)
(5 ) Con t rol of BZ frequ en cy (wh en R1 3 is R1 0 con t rol)
Specifications
Th is su brou tin e, "BZ", u ses th e BZ frequ en cy con trol to
sou n d BZ at 4 kHz wh en th e valu e of th e secon d cou n ter is
im plem en ted in even tim e, an d at 2 kHz for odd tim e.
Th e secon d cou n ter is th e secon ds colu m n BCD data in th e
tim er program . Th is rou tin e assu m es th at th e start address
of th e secon ds data (th at is, th e m em ory address of th e 1-
secon d colu m n BCD data) is defin ed in "YCKS", th e sym bol
in dicatin g th e address. (In th e program exam ple, " 0H".)
Program
Th e valu e of th e secon d cou n ter is ju dged to be even tim e
(th at is, even secon ds) or odd tim e (th at is, odd secon ds)
depen din g on wh eth er th e D0 data in th e BCD data is "0" or
"1". Bran ch in g is don e depen din g on th is evalu ation , an d
th e BZ is sou n ded after "0" or "1" is written to th e BZFQ
register.
Start address of second counter
YCKS
;
EQU
0H
;
;
Store the I/O memory BZFQ in the X register
Is the value of the second counter even or odd?
BZ:
LD
LD
FAN
JP
X,0F6H
Y,YCKS
MY,0001B
NZ,BZ0D
;
;
;
;
;
Even: Make BZFQ = "0"
Odd: Make BZFQ = "1"
Output BZ
LD
JP
MX,0000B
BZON
MX,1000B
;
;
;
BZ0D: LD
;
BZON: LD
OR
X,7CH
MX,0001B
;
;
;
Return to parent routine
RET
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CHAPTER 5: PERIPHERAL CIRCUITS (Output Ports)
Note
In th is program exam ple, th e BZ frequ en cy is ch an ged
(accordin g to even secon ds or odd secon ds) on ly wh en "BZ"
is called an d execu ted.
For in stan ce, if "BZ" is execu ted at even secon ds an d th e BZ
frequ en cy is set to 4 kHz, th en th e BZ frequ en cy will still be
4 kHz, even if th e secon d cou n ter advan ces an d becom es
odd secon ds. As lon g as "BZ" is n ot execu ted again , th e
frequ en cy will n ot ch an ge to 2 kHz.
Wh en BZ h as been selected by th e ou tpu t application for pin
R13, th e m ask option decides wh eth er ou tpu t is con trolled
by register R13, or by register R10 sim u ltan eou sly with BZ.
Prog ra m m ing note
In particu lar, wh en BZ ou tpu t is u n der R10 con trol, register
R13 can be u sed as a 1-bit gen eral register for read/ write.
Data in th is register h as n o affect on BZ ou tpu t (ou tpu t of
pin R13).
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S1C62N33 TECHNICAL SOFTWARE
CHAPTER 5: PERIPHERAL CIRCUITS (LCD Driver)
5.5 LCD Drive r
Th e S1C62N33 Series h as fou r com m on pin s an d 40
segm en t pin s, so th at it can drive an LCD with u p to 160 (40
× 4) segm en ts.
Th e drivin g m eth od is 1/ 4 du ty (or 1/ 3 du ty with th e m ask
option ) dyn am ic drive.
Fu rth er, th e S1C62N33 Series provides software settin g of
th e LCD static drive.
Se g m e nt d a ta m e m -
ory m a p
Address
Page
0
Low
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
High
4 or C
5 or D
6 or E
Segment data memory (40 words x 4 bits)
40H–6FH = R/W
Fig. 5.5.1
Segment data memory map
C0H–EFH = W
Segment data memory Th e LCD segm en ts are lit or tu rn ed off depen din g on th is
(40H–6FH or C0H–EFH) data.
Wh en "1" is written : Lit
Wh en "0" is written : Not lit
Read-ou t: Available for 40H–6FH
Un defin ed for C0H–EFH
At in itial reset, th e con ten ts of th e segm en t data m em ory are
u n defin ed.
Note - When 40H–6FH is selected for the segment data memory, the
memory data and the display will not match until the area is
initialized (through, for instance, memory clear processing by the
CPU). Initialize the segment data memory by executing initial
processing.
- When C0H–EFH is selected for the segment data memory, that
area becomes write-only. Consequently, data cannot be rewrit-
ten by arithmetic operations (such as AND, OR, ADD, SUB).
- Data output from segment pins selected as DC output will be the
data corresponding to the COM0 pins.
S1C62N33 TECHNICAL SOFTWARE
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CHAPTER 5: PERIPHERAL CIRCUITS (LCD Driver)
Exa m p le of c ontrol
p rog ra m for LCD
se g m e nt outp ut
(1 ) Gen erat ion of 1 6 -segm en t ch aract er
Specifications
Th is is th e su brou tin e "DSCG", wh ich u ses th e table looku p
in stru ction to gen erate ch aracters correspon din g to th e
valu es of A an d B registers, by writin g to th e A an d B regis-
ters.
Segment data memory assignment table
Data
Address
D3
–
D2
c
D1
b
D0
a
(n+0)H
(n+1)H
(n+2)H
(n+3)H
h
g
f
e
l
k
j
i
–
o
n
m
↓
Pin address assignment table
Common 0 Common 1 Common 2 Common 3
SEG(0+4•n)
SEG(1+4•n)
SEG(2+4•n)
SEG(3+4•n)
(b)
(g)
(h)
(d)
(a)
(f)
(i)
(o)
(e)
(j)
(p)
(l)
(k)
(n)
(c)
(m)
↑
SEG SEG
(2+4•n) (0+4•n)
d
b
h
g
f
l
c
a
o
Common0
Common1
Common2
Common3
i
e
j
k
m
n
p
Fig. 5.5.2
Example of LCD panel
SEG SEG
(3+4•n)(1+4•n)
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S1C62N33 TECHNICAL SOFTWARE
CHAPTER 5: PERIPHERAL CIRCUITS (LCD Driver)
Th e m ask option s are selected as below for th e segm en t
assign m en t to correspon d with th e LCD pan el sh own in
Figu re 5.5.2.
• Th e drive du ty is m ade 1/ 4 du ty.
• Of th e 40 segm en t pin s, on e con secu tive grou p of fou r pin s
(SEG0 + 4·n th rou gh SEG3 + 4·n , wh ere n is 0 to 9) ligh ts
on e LCD figu re (16 segm en ts). (See th e pin address as-
sign m en t table.)
As a resu lt, a grou p of fou r con secu tive words in th e seg-
m en t m em ory address can con trol on e LCD figu re. (See th e
segm en t data m em ory assign m en t table.)
Th e segm en t data m em ory area can be eith er 40H–6FH or
C0H–EFH. In th e two assign m en t tables, th e addresses of
on e set of fou r words begin from th e lowest valu e, as (n + 0),
(n + 1), (n + 2), (n + 3).
Th e relation sh ip between th e valu es of th e A an d B registers
an d th e ch aracters gen erated is as follows:
• Wh en th e B register is "0", th e valu e (h exadecim al) of th e A
register correspon ds to a n u m eral from "0" th rou gh "F"
(h exadecim al).
• Wh en th e B register is "1" an d A register is "0", th is corre-
spon ds to " " (sin gle-figu re space). Wh en th e table is
expan ded, it correspon ds to th e ch aracter added to th e A
register in h exadecim al order.
B=0
Value of A
0
1
2
3
4
5
6
7
8
Character
B=1
Value of A
Character
9
A
B
C
D
E
F
Value of A
0
Character
Fig. 5.5.3
Diagram of characters
S1C62N33 TECHNICAL SOFTWARE
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CHAPTER 5: PERIPHERAL CIRCUITS (LCD Driver)
Table look-up
"DSCG" con verts th e address of th e steps for writin g in to
segm en t data m em ory th e ch aracters in th e data table th at
correspon d to th e valu es of registers A an d B (wh ich h ave
been set by th e paren t rou tin e). Th en it ju m ps to th is ad-
dress with th e J PBA in stru ction .
Th e PSET in stru ction is in serted im m ediately before th e first
h alf of th e J PBA in stru ction , so th at th e table look-u p is on
th e sam e page as th e paren t rou tin e, an d th e data table part
is on a differen t page.
DSCG:
ADD
A,A
;Set to jump to A and B
ADC
B,B
;
PSET
JPBA
DSCGTB
;Jump to table and form subroutine
;
Data table
Th e data table begin s at th e start address of th e page in
wh ich it is placed. Th e segm en t m em ory can be written to
in su ch a way th at n u m erals "0" to "9" an d letters "A" to "F"
an d " " (sin gle-figu re space) can be displayed. A ch aracter
can be gen erated by com bin in g LBPX in stru ction an d RETD
in stru ction .
Fu rth er, expan sion from " " (sin gle-figu re space) can be don e
accordin g to th e ru le below for settin g th e valu es of th e A
an d B registers.
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S1C62N33 TECHNICAL SOFTWARE
CHAPTER 5: PERIPHERAL CIRCUITS (LCD Driver)
ORG
×00H
;Start address of table
;
DSCGTB LBPX
RETD
LBPX
RETD
LBPX
RETD
LBPX
RETD
LBPX
RETD
LBPX
RETD
LBPX
RETD
LBPX
RETD
LBPX
RETD
LBPX
RETD
LBPX
RETD
LBPX
RETD
LBPX
RETD
LBPX
RETD
LBPX
RETD
LBPX
RETD
LBPX
MX,10000111B ;Generate "0" (write to segment memory)
01111000B ;, Return to parent routine
MX,01000001B ;Generate "1" (write to segment memory)
00000100B ;, Return to parent routine
MX,00010011B ;Generate "2" (write to segment memory)
00100010B ;, Return to parent routine
MX,00010011B ;Generate "3" (write to segment memory)
01100001B ;, Return to parent routine
MX,01010100B ;Generate "4" (write to segment memory)
00000101B ;, Return to parent routine
MX,00010110B ;Generate "5" (write to segment memory)
01100001B ;, Return to parent routine
MX,00010110B ;Generate "6" (write to segment memory)
01110001B ;, Return to parent routine
MX,00100110B ;Generate "7" (write to segment memory)
00010111B ;, Return to parent routine
MX,00010111B ;Generate "8" (write to segment memory)
01110001B ;, Return to parent routine
MX,00010111B ;Generate "9" (write to segment memory)
01000001B ;, Return to parent routine
MX,00110001B ;Generate "A" (write to segment memory)
01000010B ;, Return to parent routine
MX,01010011B ;Generate "B" (write to segment memory)
01100100B ;, Return to parent routine
MX,00000110B ;Generate "C" (write to segment memory)
00110000B ;, Return to parent routine
MX,01000011B ;Generate "D" (write to segment memory)
01100100B ;, Return to parent routine
MX,00010110B ;Generate "E" (write to segment memory)
01100001B ;, Return to parent routine
MX,00010110B ;Generate "F" (write to segment memory)
00010001B ;, Return to parent routine
MX,00000000B ;Generate " " (single-space figure)
(write to segment memory)
;, Return to parent routine
;
RETD
00000000B
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CHAPTER 5: PERIPHERAL CIRCUITS (LCD Driver)
(2 ) Wh en segm en t m em ory is assign ed t o C0 H–EFH
Specifications
Th is application exam ple, in wh ich th e assign m en t sh own in
(1) is m ade to th e segm en t data m em ory area C0H–EFH, is
th e "colu m n display rou tin e 'DSSG'" an d th e "apostroph e
an d period display rou tin e 'DSSGA'". Both assu m e, as in
(1), th at eigh t colu m n s of th e LCD pan el are to be u sed.
Th e SEG (0 + 4·n ) pin for th e LCD's first colu m n is assign ed
to segm en t m em ory C0H, an d th e rem ain in g 31 pin s are
assign ed in order.
Th e pin assign m en t for th e apostroph e an d period assign -
m en ts are n ot sh own in (1). Th ey are assign ed in th e m an -
n er sh own in Figu re 5.5.4.
Segment data memory assignment table
Data
Address
D3
A3
A7
P3
P7
D2
A2
A6
P2
P6
D1
A1
A5
P1
P5
D0
A0
A4
P0
P4
E0H
E1H
E2H
E3H
↑
A7
A6
A5
A4
A3
A2
A1
A0
Fig. 5.5.4
Example of LCD panel
P7
P6
P5
P4
P3
P2
P1
P0
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S1C62N33 TECHNICAL SOFTWARE
CHAPTER 5: PERIPHERAL CIRCUITS (LCD Driver)
Figure
display
routine
Th e segm en t data m em ory area C0H–EFH is write-on ly, so
th e display data stored in th e bu ffers "YDSB1"–"YDSB8" (for
arith m etic operation s) is written to th e segm en t m em ory.
Two words of th e bu ffer display data correspon d to on e
figu re of th e display. Th e low address data correspon ds to
th e valu e of th e A register of DSCG, an d th e h igh address
data correspon ds to th e valu e of th e B register.
YDSB1
YDSSG
EQU
EQU
0H
0C0H
;Segment data buffer first figure start address
;Segment memory first figure start address
;
;
DSSG:
LD
LD
X,YDSSG
Y,YDSB1
;Store the segment memory first figure start
;address to X register
;Store the segment data buffer first figure start
;address to Y register
;
DSSGLP: LDPY
A,MY
;Display: Set the display character
LDPY
B,MY
;
CALL
DSCG
;
Execute "DSCG"
CP
JP
XH,0EH
C,DSSGLP
;Continue up to the eighth figure
;
RET
;Return to parent routine
S1C62N33 TECHNICAL SOFTWARE
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CHAPTER 5: PERIPHERAL CIRCUITS (LCD Driver)
Apostrophe and As in th e Figu re display rou tin e, th e display data stored in
period display
routine
th e bu ffers "YDSBA"–"YDSBP" is written to th e segm en t data
m em ory.
YDSBA
YDSBP
YDSSGA EQU
EQU
EQU
ꢀ0H
;Segment data buffer apostrophe start address
;Segment data buffer period start address
;Segment data memory apostrophe start address
;Segment data memory period start address
ꢀ2H
0E0H
0E2H
YDSSGP EQU
;
;
DSSGA: LD
X,YDSSGA ;Store the segment data memory apostrophe start address in X register
LD
Y,YDSBA
;Store the segment data buffer apostrophe start address in Y register
;
DSSGAL: LDPX MX,MY
;Display: Transfer the data, and increment X register
INC
CP
Y
;
;
Increment the Y register
XL,4H
Repeat up to the eighth figure
JP
C,DSSGAL ;
;
RET
;Return to parent routine
(3 ) Zero-su ppression of bu ffer dat a
Specifications
With th e settin gs of (1) an d (2), zero-su ppression can be
effected if th e display data an d bu ffer data is m an ipu lated
by th is su brou tin e "DSSP".
Program
DSSP:
;
CP
JP
INC
LD
MY,0H
NZ,DSSPRT
Y
;If low address data is "0"
;
;then make high address data "1"
;
MY,1H
DSSPRT: RET
;Return to parent routine
II-54
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S1C62N33 TECHNICAL SOFTWARE
CHAPTER 5: PERIPHERAL CIRCUITS (LCD Driver)
LCD d rive r m e m ory
m a p
Table 5.5 I/O data memory map (LCD driver)
Register
Address
Comment
*1
D3
D2
D1
D0
Name
CSDC
SR
0
1
0
*7
CSDC
ETI2
ETI8
ETI32
LCD drive switch
Static
Dynamic
R/W
ETI2
ETI8
0
0
0
Enable
Enable
Enable
Mask
Mask
Mask
Interrupt mask register (clock timer 2 Hz)
Interrupt mask register (clock timer 8 Hz)
Interrupt mask register (clock timer 32 Hz)
78H
ETI32
*1 In itial valu e followin g in itial reset
*2 Not set in th e circu it
*3 Un defin ed
*5 Always "0" wh en bein g read
*6 Refer to m ain m an u al
*7 Page switch in g in I/ O m em ory is
n ot n ecessary
*4 Reset (0) im m ediately after bein g read
Th e sequ en ce for specifyin g LCD static drive is as follows:
Exa m p le of switc h-
ing LCD d rive
ꢀ Write "1" to th e register at address "78H.D3".
ꢀ Write th e sam e valu e to all registers correspon din g to th e
segm en t m em ory COM0–COM3.
Th e followin g is an exam ple of switch in g LCD drive wh en th e
segm en t m em ory is allocated to C0H–EFH.
S1C62N33 TECHNICAL SOFTWARE
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CHAPTER 5: PERIPHERAL CIRCUITS (LCD Driver)
(1 ) St at ic all lit for st ep adju st m en t
Specifications
Th is su brou tin e "SGHI" switch es to static drive an d ligh t all
segm en ts.
Program
XIO2SH EQU
0FH
0C0H
;The 2nd I/O memory, start high address
;Segment memory first start address
YDSSG
EQU
;
;
SGHI:
LD
OR
X,78H
MX,1000B
;Write "1" to CSDC (static drive)
;
;
LD
X,YDSSG
;All segments lit: Address to segment memory start
SGHILP: LDPX MX,1111B
;
Make segment high output
CP
JP
XH,XIO2SH
C,SGHILP
;Continue until no more area
;
;
RET
;Return to parent routine
Note
Perform step adju stm en t by settin g th e segm en t data after
all LCDs are lit.
(2 ) Ret u rn t o dyn am ic drive aft er n o segm en t s lit
Specifications
Th is su brou tin e pu ts all th e segm en ts ou t, an d th en
switch es to dyn am ic drive.
Program
XIO2SH EQU
0FH
;The 2nd I/O memory, start high address
YDSSG
EQU
0C0H
;Segment memory first start address
;
;
SGLO:
LD
X,YDSSG
;No segment lit: Address to segment memory start
SGLOLP: LDPX MX,0000B
;
Make segment low output
CP
JP
XH,XIO2SH
C,SGLOLP
;Continue until no more area
;
;
LD
X,78H
;Write "0" to CSDC (dynamic drive)
OR
MX,1000B
;
RET
;Return to parent routine
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S1C62N33 TECHNICAL SOFTWARE
CHAPTER 5: PERIPHERAL CIRCUITS (LCD Driver)
(1) Wh en 40H–6FH is selected for th e segm en t data m em ory,
th e m em ory data an d th e display will n ot m atch u n til th e
area is in itialized (th rou gh , for in stan ce, m em ory clear
processin g by th e CPU).
Prog ra m m ing note s
In itialize th e segm en t data m em ory by execu tin g in itial
processin g.
(2) Wh en C0H–EFH is selected for th e segm en t data m em ory,
th at area becom es write-on ly. Con sequ en tly, data can n ot
be rewritten by arith m etic operation s (su ch as AND, OR,
ADD, SUB).
(3) Data ou tpu t from segm en t pin s selected as DC ou tpu t
will be th e data correspon din g to th e COM0 pin s.
(4) Wh en perform in g step adju stm en t with th e static drive,
set th e segm en t data so th at all LCD segm en ts are lit.
S1C62N33 TECHNICAL SOFTWARE
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II-57
CHAPTER 5: PERIPHERAL CIRCUITS (Clock Timer)
5.6 Cloc k Tim e r
Th e S1C62N33 Series h as a clock tim er bu ilt-in . Th e clock
tim er can gen erate tim er in terru pts at 32 Hz, 8 Hz an d 2 Hz.
Ordin arily, th is clock tim er is u sed for all types of tim in g
fu n ction s su ch as clocks.
Cloc k tim e r m e m ory
m a p
Table 5.6.1 I/O data memory map (clock timer)
Register
Address
Comment
*1
D3
D2
D1
D0
Name
TM3
SR
0
1
0
*7
TM3
TM2
TM1
TM0
Timer data (clock timer 2 Hz)
Timer data (clock timer 4 Hz)
Timer data (clock timer 8 Hz)
Timer data (clock timer 16 Hz)
Clock timer reset *5
R
TM2
TM1
0
0
0
70H
TM0
TMRST SWRUN SWRST
IOC0
R/W
Reset
RUN
–
STOP
–
TMRST
SWRUN
SWRST
IOC0
Reset
0
W
R/W
W
Stopwatch counter RUN/STOP
Stopwatch counter reset *5
I/O control register 0 (P00–P03)
7EH
Reset
Output
Reset
0
Input
*1 In itial valu e followin g in itial reset
*2 Not set in th e circu it
*3 Un defin ed
*5 Always "0" wh en bein g read
*6 Refer to m ain m an u al
*7 Page switch in g in I/ O m em ory is
n ot n ecessary
*4 Reset (0) im m ediately after bein g read
TMRST: Th is bit resets th e clock tim er.
Clock timer reset
(7EH.D3)
Wh en "1" is written : Clock tim er reset
Wh en "0" is written : No operation
Read-ou t: Always "0"
Th e clock tim er restarts im m ediately on bein g reset.
II-58
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S1C62N33 TECHNICAL SOFTWARE
CHAPTER 5: PERIPHERAL CIRCUITS (Clock Timer)
Exa m p le of using
c loc k tim e r
(1 ) In it ializin g clock t im er
Specifications
Th is program resets th e clock tim er.
LD
OR
X,7EH
MX,1000B
;
;
Prog ra m
Reset the clock timer
Note s
1. Wh en th e clock tim er h as been reset, th e in terru pt factor
flag (TI) m ay som etim es be set to "1".
2. Th e watch dog tim er m ay be cou n ted u p at th e clock tim er
reset.
3. Resettin g th e clock tim er does n ot affect th e stopwatch
cou n ter.
(2 ) Readin g t h e clock t im er
Specifications Th is program reads th e clock tim er data in to A register.
A register
Fig. 5.6.1
D3
D2
D1
D0
Correspondence between
clock timer and A register
TM3
TM2
TM1
TM0
LD
LD
X,70H
A,MX
;
;
Prog ra m
Load the clock timer data into A register
S1C62N33 TECHNICAL SOFTWARE
EPSON
II-59
CHAPTER 5: PERIPHERAL CIRCUITS (Clock Timer)
(3 ) Det ect in g t h e edge of t h e clock t im er
Specifications
Th is su brou tin e, "TMEDG", detects th e edge of th e tim er
data, an d execu tes th e 4 Hz processin g rou tin e "TM4" if th e
2 Hz edge is detected.
Program
XTMDT2
YTMDTB
EQU
EQU
0100B
●×H
;Timer data 2 Hz
;Address of timer data buffer
;
;
TMEDG:
LD
X,70H
;Detect change (edge) in timer data
LD
Y,TMDTBF
MY,MX
MY,XTMDT2
Z,TMEDGRT
TM4
;
;
XOR
FAN
JP
;If 2 Hz edge
;
;then execute 4 Hz processing "TM4"
CALL
;
TMEDGRT: RET
;Return to parent routine
Th e processin g rou tin e for frequ en cies n ot set in th e clock
tim er in terru pt can be execu ted by repeatedly callin g th is
su brou tin e at h igh frequ en cy.
n sec
(n+1) sec
Time
TM2
"1"
"0"
125 ms
Fig. 5.6.2
Timing chart
Timeing for executing "TM4"
II-60
EPSON
S1C62N33 TECHNICAL SOFTWARE
CHAPTER 5: PERIPHERAL CIRCUITS (Clock Timer)
(4 ) Alarm bell u sin g clock t im er an d BZ ou t pu t
Specifications
Wh en called every 8 Hz, th is su brou tin e gen erates th e alarm
bell sou n d by switch in g th e BZ ou tpu t ON an d OFF, as
sh own in th e tim in g ch art.
n sec
(n+1) sec
Time
TISF
"1"
"0"
"1"
2 Hz
"0"
"1"
"0"
4 Hz
8 Hz interrupt
BZ output
Fig. 5.6.3
ON
Alarm bell timing chart
OFF
Program
XTISF
EQU 0001B
;0.5 sec flag (TISF)
XBESYNF EQU 0010B
;Bell sound synchro flag
;Address of timing flag set
YFTM
;
EQU ●●H
;
BE:
LD
Y,YFTM
;TISF = "0" or "1"?
FAN MY,XTISF
;
JP
NZ,BZOF
;TISF = "1": Execute "BZOF", return to parent routine
;
;
LD
LD
X,70H
A,MX
;TISF = "0": Is the timer data of 2 Hz and 4 Hz
;
;
;all "0"?
;
AND A,1100B
CP
JP
A,0000B
NZ,BE1
OR
JP
MY,XBESYNF
BZ
;Both 2 Hz and 4 Hz are "0": Reset BESYNF
;
Execute "BZ", return to parent routine
;
BE1:
FAN MY,XBESYNF
;2 Hz and 4 Hz not both "0":
JP
CP
JP
Z,BZOF
A,1000B
NZ,BZOF
;
;
;
When BESYNF = "0"
or 4 Hz = "1"
execute "BZOF", return to parent routine
;
AND MY,XBESYNF XOR 0FH ;
In other cases: Reset BESYNF
Execute "BZ", return to parent routine
JP
BZ
;
S1C62N33 TECHNICAL SOFTWARE
EPSON
II-61
CHAPTER 5: PERIPHERAL CIRCUITS (Clock Timer)
Tim e r inte rrup t
m e m ory m a p
Table 5.6.2 I/O data memory map (timer interrupt)
Register
Address
Comment
*1
D3
D2
D1
D0
Name
CSDC
SR
0
1
0
*7
CSDC
ETI2
ETI8
ETI32
LCD drive switch
Static
Dynamic
R/W
ETI2
ETI8
0
0
Enable
Enable
Enable
Mask
Mask
Mask
Interrupt mask register (clock timer 2 Hz)
Interrupt mask register (clock timer 8 Hz)
Interrupt mask register (clock timer 32 Hz)
Unused *5
78H
ETI32
0
–
TI2
TI8
TI32
–
*2
0
R
TI2
TI8
Yes
Yes
Yes
No
No
No
Interrupt factor flag (clock timer 2 Hz) *4
Interrupt factor flag (clock timer 8 Hz) *4
Interrupt factor flag (clock timer 32 Hz) *4
79H
0
TI32
0
*1 In itial valu e followin g in itial reset
*2 Not set in th e circu it
*3 Un defin ed
*5 Always "0" wh en bein g read
*6 Refer to m ain m an u al
*7 Page switch in g in I/ O m em ory is
n ot n ecessary
*4 Reset (0) im m ediately after bein g read
TI32, TI8, TI2: Th ese flags in dicate th e statu s of th e clock tim er in terru pt.
Interrupt factor flags
(79H.D0–D2)
Wh en "1" is read ou t: In terru pt h as occu rred
Wh en "0" is read ou t: In terru pt h as n ot occu rred
Writin g: In valid
Th ese flags can be reset th rou gh bein g read ou t by th e
software.
Note Even if these flag interrupts are masked, the flags are set to "1" at
the falling edge of the corresponding signal.
II-62
EPSON
S1C62N33 TECHNICAL SOFTWARE
CHAPTER 5: PERIPHERAL CIRCUITS (Clock Timer)
Cloc k tim e r tim ing
c ha rt
Address Register Frequency
Clock timer timing chart
D0
D1
D2
D3
16 Hz
8 Hz
4 Hz
2 Hz
70H
32 Hz interrupt request
8 Hz interrupt request
2 Hz interrupt request
Fig. 5.6.4
Timing chart of the
clock timer
In terru pt is gen erated at th e fallin g edge of th e frequ en cies
(32 Hz, 8 Hz, 2 Hz). At th is tim e, th e correspon din g in ter-
ru pt factor flag (TI32, TI8, TI2) is set to "1".
Exa m p le of using
tim e r inte rrup t
(1 ) In it ializin g clock t im er an d set t in g in t erru pt m ask regist er (2 Hz)
Specifications
Program
Th is program resets th e clock tim er after en ablin g th e tim er
2 Hz in terru pt on ly.
DI
LD
LD
LD
OR
LD
FAN
EI
;Disable interrupts
;Enable timer 2 Hz interrupt, and mask all others
;
;Reset clock timer
;
;Reset the timer interrupt factor flags
;
X,78H
MX,0100B
X,7EH
MX,1000B
X,79H
MX,0111B
;Enable interrupt
Notes
1. Write to th e in terru pt m ask registers (ETI) on ly in th e DI
statu s.
2. Th e gen erated tim er in terru pt factor flag is also reset
th rou gh th e clock tim er bein g reset.
S1C62N33 TECHNICAL SOFTWARE
EPSON
II-63
CHAPTER 5: PERIPHERAL CIRCUITS (Clock Timer)
(2 ) Operat in g in t erru pt m ask regist er by separat e bit s
Specifications
Program
Th is program en ables th e tim er 8 Hz in terru pt on ly, an d
th en m asks th e tim er 32 Hz in terru pt.
DI
LD
OR
;Disable interrupt
;Enable timer 8 Hz interrupt
;
X,78H
MX,0010B
MX,1110B
AND
EI
;Mask timer 32 Hz interrupt
;Enable interrupt
Note
Write to th e in terru pt m ask registers (ETI) on ly in th e DI
statu s.
(3 ) Processin g aft er t im er in t erru pt gen erat ed
Specifications
Th is program stores th e register wh en an in terru pt is gen er-
ated, an d wh en th e in terru pt processin g is com pleted it
recovers th e register data an d retu rn s to th e m ain rou tin e.
Th e order of priority for th e in terru pts is set as sh own in th e
table below, in terru pt n estin g is disabled, an d processin g
proceeds in descen din g order of priority. Th e in terru pt
processin g rou tin e is called with CALL in stru ction an d
processed.
Table 5.6.3
Order of Priority
Interrupt Factor
Clock timer 32 Hz
Clock timer 8 Hz
Clock timer 2 Hz
Order of priority of interrupts
in program example
1
2
3
Program
ORG
JP
104H
INTI
;Interrupt vector address of timer interrupt
;Go to "INTI" if timer interrupt is generated
;
;
;
YTIB
EQU
●●H
;Buffer address of timer interrupt factor flags
;
;
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S1C62N33 TECHNICAL SOFTWARE
CHAPTER 5: PERIPHERAL CIRCUITS (Clock Timer)
INTI: PUSH
XH
XL
YH
YL
A
;Store value of X register in stack
;
;Store value of Y register in stack
;
;Store value of A register in stack
;Store value of B register in stack
;Store value of F register in stack
PUSH
PUSH
PUSH
PUSH
PUSH
PUSH
B
F
;
LD
LD
LD
LD
X,79H
Y,YTIB
MY,MX
X,78H
MY,MX
;(Reset) the timer interrupt factor flags
;and store in buffer
;
;Mask the timer interrupt factor flags
;by the value of the timer interrupt mask register
AND
;
FAN
MY,0001B ;If the TM32Hz interrupt factor flag is set,
JP
CALL
Z,INTI8
TI32
;and enabled
;then "TI32" is executed
;
INTI8: LD
Y,YTIB
;If the TM8Hz interrupt factor flag is set,
FAN
MY,0010B ;and enabled
JP
CALL
Z,INTI2
TI8
;
;then "TI8" is executed
;
INTI2: LD
FAN
Y,YTIB
MY,0100B ;and enabled
;If the TM2Hz interrupt factor flag is set,
JP
Z,INRT
TI2
;
CALL
;
;then "TI2" is executed
INRT:
For details on "INRT", see th e in terru pt rou tin e in "4.5
Exam ple of In terru pt Vector Processin g".
1. Read th e in terru pt factor flags (TI) on ly in th e DI statu s.
Notes
2. Regardless of th e settin g of th e in terru pt m ask register
(ETI), th e in terru pt factor flag (TI) is set to "1" at th e
fallin g edge of th e correspon din g sign al. Hen ce, th e
presen ce of an in terru pt factor is ju dged by th e resu lt of
ANDin g th e factor flag stored in th e bu ffer an d th e in ter-
ru pt m ask register.
S1C62N33 TECHNICAL SOFTWARE
EPSON
II-65
CHAPTER 5: PERIPHERAL CIRCUITS (Clock Timer)
(4 ) Clock u sin g t im er 2 Hz in t erru pt
Specifications
Th is program is for a clock th at u ses th e tim er 2 Hz in ter-
ru pt. It ju dges wh en 1 secon d elapses after th e 2 Hz in ter-
ru pt an d cou n ts th e clock's secon ds.
Table 5.6.4
Clock data
Address
0H
Data
Second count data (single digit seconds column, BCD)
Second count data (ten's seconds column, BCD)
Minute count data (single digit minutes column, BCD)
Minute count data (ten's digit minutes column, BCD)
1H
2H
3H
Program
XTISF EQU
0001B
●●H
0H
;0.5 sec flag (TISF)
;Address of timing flag set
;Start address of second counter data (BCD)
YFTM
YCKS
;
EQU
EQU
;
TI2:
LD
X,YFTM
;TISF = "0" or "1"?
FAN
JP
MX,XBTSF
NZ,TI21
;
;
;
OR
MX,XTISF
;TISF = "0": Set TISF
RET
;
Return to "INTI"
TI21: AND
LD
MX,XTISF XOR 0FH ;TISF = "1": Reset TISF
X,YCKS
CT60
;
;
;
;
;
Increment the second counter data by 1
No carry: Return to "INTI"
CALZ
RET
JP
CK
Carry:
Execute clock processing for
at least a minute "CK",
;and return to "INTI"
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S1C62N33 TECHNICAL SOFTWARE
CHAPTER 5: PERIPHERAL CIRCUITS (Clock Timer)
Reference
Page 0 routine "CT60"
PAGE
0
;
;
Count 1 up the BCD counter
Where is the tens' position?
Not "6": Go to RTP0
CT60: CALZ
CTUP
;
;
;
;
;
CP
JP
LDPX
RETS
MX,6H
NZ,RTP0
MX,0H
"6":
Zero clear
Return to parent routine and skip
Page 0 routine "CTUP"
PAGE
0
;
;
CTUP: SDF
ADD
;
;
;
;
;
;
Preparation: Set D flag
MX,1H
X
MX,0H
Increment data by 1 with BCD
Set tens' place address
INC
ADC
RDF
Carry processing to tens' place
After process: Reset D flag
Return to parent routine
RTP0: RET
S1C62N33 TECHNICAL SOFTWARE
EPSON
II-67
CHAPTER 5: PERIPHERAL CIRCUITS (Clock Timer)
(1) Wh en th e clock tim er h as been reset, th e in terru pt factor
Prog ra m m ing note s
flag (TI) m ay som etim es be set to "1". Con sequ en tly,
perform flag read-ou t (reset th e flag) wh en n ecessary at
reset.
(2) Th e watch dog tim er m ay be cou n ted u p at clock tim er
reset.
(3) Resettin g th e clock tim er h as n o effect on th e stopwatch
cou n ter, an d vice versa.
(4) Writin g to th e in terru pt m ask register (ETI) can be don e
on ly in th e DI statu s (in terru pt flag = "0"). Writin g du rin g
EI statu s will cau se an error.
(5) Read ou t th e in terru pt flag (TI) on ly du rin g th e DI statu s
(in terru pt flag = "0"). Read-ou t du rin g EI statu s will
cau se an error.
(6) Regardless of th e settin g of th e in terru pt m ask register
(ETI), th e in terru pt factor flag (TI) is set to "1" at th e
fallin g edge of th e correspon din g sign al.
II-68
EPSON
S1C62N33 TECHNICAL SOFTWARE
CHAPTER 5: PERIPHERAL CIRCUITS (Input Ports)
5.7 Inp ut Ports (K00–K03, K10)
Th e S1C62N33 Series h as gen eral-pu rpose in pu t ports
con sistin g of a total of five bits. Fou r bits are reserved for
pin s K00–K03 an d on e bit is for K10. All five bits of th ese
in pu t ports h ave in terru pt fu n ction s.
Inp ut p ort m e m ory
m a p
Table 5.7.1 I/O data memory map (input ports)
Register
Address
Comment
*1
D3
D2
D1
D0
Name
K03
SR
1
0
*7
K03
K02
K01
K00
*2
High
Low
R
Input port
K02
K01
*2
*2
*2
0
High
High
Low
Low
(K00–K03)
73H
K00
High
Low
DFK03
DFK02
DFK01
DFK00
DFK03
Falling
Rising
R/W
DFK02
DFK01
DFK00
EIK03
EIK02
EIK01
EIK00
0
Falling
Falling
Falling
Enable
Enable
Enable
Enable
Rising
Rising
Rising
Mask
Mask
Mask
Mask
Differential register
(K00–K03)
74H
0
0
EIK03
EIK02
EIK10
IK0
EIK01
EIK00
0
0
0
0
Interrupt mask register
(K00–K03)
R/W
75H
Serial interface clock trigger
SIOF
SCTRG
SIOF
–
0
Trigger
Run
–
SCTRG
SIOF
DFK10
K10
R
Stop
W
R
Interrupt mask register (K10)
Differential register (K10)
EIK10
0
0
Mask
Enable
Falling
R/W
77H
DFK10
Rising
Input port (K10)
K10
IK1
*2
0
Low
No
High
Yes
Interrupt factor flag (K10) *4
Interrupt factor flag (K00–K03) *4
Interrupt factor flag (stopwatch 1 Hz) *4
Interrupt factor flag (stopwatch 10 Hz) *4
IK1
SWIT1
SWIT0
R
IK0
0
Yes
Yes
Yes
No
No
No
7AH
SWIT1
SWIT0
0
0
*1 In itial valu e followin g in itial reset
*2 Not set in th e circu it
*3 Un defin ed
*5 Always "0" wh en bein g read
*6 Refer to m ain m an u al
*7 Page switch in g in I/ O m em ory is
n ot n ecessary
*4 Reset (0) im m ediately after bein g read
S1C62N33 TECHNICAL SOFTWARE
EPSON
II-69
CHAPTER 5: PERIPHERAL CIRCUITS (Input Ports)
DFK00–DFK03, DFK10: In terru pt con dition s can be set with th ese registers.
Differential registers
Wh en read-ou t is "1": Fallin g edge
(74H, 77H.D1)
Wh en read-ou t is "0": Risin g edge
Read-ou t: Available
In th e K00–K03 pin grou p, th e in terru pt is en abled in side
K00–K03, bu t th e in terru pt factor flag IK0 is set to "1" wh en
th e valu es of th e in pu t port data an d th e differen tial register
ch an ges from m atch in g to n on -m atch in g.
Note
Even though the values of the input port data and the differential
register change from non-matching to matching, the interrupt factor
flag IK0 will not be set to "1".
Wh en th e in terru pt is en abled for K10, th e in terru pt factor
flag IK1 is set to "1" at th e fallin g edge wh en th e differen tial
register is "1" an d at th e risin g edge wh en "0". Fu rth erm ore,
sin ce th e SCTRG/ SIOF registers are at th is address, care
n eeds to be taken wh en u sin g operation al com m an ds (AND,
OR, ADD, SUB, etc.).
IK0, IK1:
Interrupt factor flags
(7AH.D2 and D3)
Th ese flags in dicate th e occu rren ce of in pu t in terru pt.
Wh en "1" is read ou t: In terru pt h as occu rred
Wh en "0" is read ou t: In terru pt h as n ot occu rred
Writin g: In valid
Th ese flags are reset wh en th e software reads th em .
Note
When "noise rejector circuit enable" is selected with the mask
option, a maximum delay of 1 ms occurs from the time the interrupt
conditions are established until the interrupt factor flag (IK) is set to
"1" (until the interrupt is actually generated).
Hence, pay attention to the timing when reading out (resetting) the
interrupt factor flag.
II-70
EPSON
S1C62N33 TECHNICAL SOFTWARE
CHAPTER 5: PERIPHERAL CIRCUITS (Input Ports)
Exa m p le of using
inp ut p orts
(1 ) Readin g t o in pu t port s
Specifications
Th is program reads th e in pu t port (K00–K03) data to RAM,
YINB.
Table 5.7.2
Data Bits
Address
Correspondence of input ports
D3
D2
D1
D0
(K00–K03) and store memory
ꢀꢀH
K03
K02
K01
K00
Th en it reads th e in pu t port (K10) data to th e A register.
A register
Fig. 5.7.1
Correspondence of input port
(K10) and A register
D3
D2
D1
D0
0
EIK10
DFK10
K10
Program
YINB
EQU
ꢀꢀH
;Buffer address of K00–K03 input data
;
;
LD
LD
LD
X,73H
Y,YINB
MY,MX
;Store K00–K03 data in RAM, YINB
;
;
;
LD
LD
X,77H
A,MX
;Load K10 data to A register (D0)
;
AND
A,0001B
;Reset all bits except D0 to "0"
Note
Wh en in pu t ports are ch an ged from h igh to low by pu ll-
down resistor, th e fall of th e waveform is delayed on accou n t
of th e tim e con stan t of th e pu ll-down resistan ce an d in pu t
gate capacitan ce.
S1C62N33 TECHNICAL SOFTWARE
EPSON
II-71
CHAPTER 5: PERIPHERAL CIRCUITS (Input Ports)
(2 ) In pu t port s det erm in at ion per bit
Specifications
Th is is an exam ple of wh eth er each term in al is h igh or low,
u sin g com pu tation al com m an d on th e in pu t port (K00–K03)
registers.
ON/ OFF switch in g of BZ ou tpu t, or BZ frequ en cy is con -
trolled accordin g to th e resu lt of th e determ in ation .
Program
YDTB
EQU
ꢀꢀH
;Data buffer address
;
;
KYTS:
LD
X,73H
;If only K00 is high input
CP
JP
CALL
MX,0001B
NZ,KYTS2
BZ4
;
;
;then sound BZ at 4 kHz
;
KYTS2:
LD
LD
Y,YDTB
A,MY
;If the value of RAM, YDTB
;
LD
XOR
JP
X,73H
A,MX
Z,KYTSOF
BZ2
;does not match the value of K00–K03
;
;
CALL
;then sound BZ at 2 kHz
;
KYTSOF: LD
FAN
X,73H
;If K00 is low input
;
;
MX,0001B
NZ,KYTSLP
BZOF
JP
CALL
;then stop the buzzer
;
KYTSLP: LD
FAN
X,77H
;Loop: K10 pin is low or high?
;
MX,0001B
Z,KYTSLP
KYTS
JP
JP
;
;
Low input: Loop
High input: Returns to KYTS
II-72
EPSON
S1C62N33 TECHNICAL SOFTWARE
CHAPTER 5: PERIPHERAL CIRCUITS (Input Ports)
(3 ) Set t in g differen t ial regist er an d in t erru pt m ask regist er
Specifications
Th is program sets th e m ask registers an d differen tial regis-
ters of K00–K03 an d K10 as sh own in th e table below.
Table 5.7.3
Port
K10
K03
K02
K01
K00
Setting of interrupt
Mask Register
1
0
1
1
1
generation conditions
Generation
of Interrupt
Enabled
0
Disabled
1
Enabled
Enabled
Enabled
Differential
1
0
1
Change from Change from Change from
High input Low input High input
status status status
Generation
Conditions
Rising
edge
Don't care
Interrupt
Generated
K1
interrupt
K0 interrupt
Program
DI
;Disable interrupts
;Set the differential registers of K00–K03
;
LD
X,74H
LDPX
LD
MX,1101B
MX,0111B
;to "1101", Set the interrupt mask registers of
;K00–K03 to "0111"
;
;
LD
LD
X,77H
MX,0100B
;Enable interrupt at the rising edge of K10
;
EI
;Enable interrupt
Note
Write to th e in terru pt m ask registers (EIK) on ly in th e DI
statu s (in terru pt flag = "0").
S1C62N33 TECHNICAL SOFTWARE
EPSON
II-73
CHAPTER 5: PERIPHERAL CIRCUITS (Input Ports)
(4 ) Processin g aft er in t erru pt gen erat ed
Specifications
Th is program stores th e register data wh en an in terru pt is
gen erated, recovers th e register data wh en th e in terru pt
processin g com pletes, an d retu rn s to th e m ain rou tin e. Th e
order of priority for th e in terru pts is set as sh own in th e
table below, in terru pt n estin g is disabled, an d processin g
proceeds in descen din g order of priority. Th e in terru pt
processin g rou tin e is called with CALL in stru ction an d
processed.
Table 5.7.4
Order of Priority
Interrupt Factor
Input ports K00–K03
Input port K10
Order of interrupt priority in
program example
1
2
Program
ORG
102H
INIK
;Interrupt vector address of K0 and K1 interrupts
;
JP
;If the K0 and K1 interrupts are generated, go to "INIK"
;
;
YIKB
EQU
ꢀꢀH
;Buffer address of input interrupt factor flags
;
;
INIK: PUSH
XH
XL
YH
YL
A
;Store the value of X register in stack
;
;Store the value of Y register in stack
;
;Store the value of A register in stack
;Store the value of B register in stack
;Store the value of the flag group in stack
PUSH
PUSH
PUSH
PUSH
PUSH
PUSH
B
F
;
LD
LD
LD
;
X,7AH
Y,YIKB
MY,MX
;(Reset) the input interrupt factor flags
;and store in buffer
;
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S1C62N33 TECHNICAL SOFTWARE
CHAPTER 5: PERIPHERAL CIRCUITS (Input Ports)
FAN
JP
CALL
MY,0100B
Z,INIK1
IK0
;If the K0 interrupt factor flag is set
;
;then execute "IK0"
;
INIK1: LD
FAN
Y,YIKB
MY,1000B
Z,INRT
IK1
;If the K1 interrupt factor flag is set
;
;then execute "IK1"
;
JP
CALL
;
INRT:
See details of "INRT" in th e section on "In terru pt rou tin e" in
"4.5 Exam ple of Processin g In terru pt Vector".
Note
Read th e in terru pt factor flags (IK) on ly in th e DI statu s.
(5 ) Evalu at in g in pu t pin s (K0 0 –K0 3 )
Specifications
Th is rou tin e decides wh ich of K00–K03 are h igh in pu t pin s
wh en an in terru pt is gen erated by h igh in pu t from th e in pu t
ports (K00–K03). It th en execu tes th e correspon din g su b-
rou tin e "K0n ".
If an in terru pt h as com e from m ore th an on e pin , th is is
treated as "m u ltiple key en try", an d su brou tin e "IK0MLT" is
execu ted.
Moreover, in case in terru pt is in adverten tly gen erated, th e
error display process "DSER" will be execu ted.
S1C62N33 TECHNICAL SOFTWARE
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CHAPTER 5: PERIPHERAL CIRCUITS (Input Ports)
Program
DI
LD
;Disable interrupts
;Set differential registers of K00–K03
X,74H
LDPX
LD
EI
MX,0000B ;to "0000"
MX,1111B ;Enable K00–K03 interrupt
;Enable interrupts
;
;
YINB
;
EQU
ꢀ H
;Read data buffer address
;
IK0:
LD
LD
LD
LD
X,73H
Y,YINB
MY,MX
A,0H
;Store K00–K03 data in RAM, YK0B
;
;
;Preparation:
;
CP
JP
JP
MY,0001B ;If only K00 is high input
Z,K00
;then execute K00 input processing "K00", and return to "INIK"
C,DSER
;If not high input pin
;then execute the error display processing "DSER",
;
and return to "INIK"
CP
JP
CP
JP
CP
JP
MY,0010B ;If only K01 is high input
Z,K01
;then execute K01 input processing "K01", and return to "INIK"
MY,0100B ;If only K02 is high input
Z,K02
;then execute K02 input processing "K02", and return to "INIK"
MY,1000B ;If only K03 is high input
Z,K03
;then execute K03 input processing "K03", and return to "INIK"
;
JP
IK0MLT
;Multiple key entry: Execute multiple key entry processing "IK0MLT", and
return to "INIK"
Th is rou tin e assu m es th at processin g rou tin es "K00"–"K03",
"IK0MLT" an d "DSER" h ave been prepared separately.
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CHAPTER 5: PERIPHERAL CIRCUITS (Input Ports)
(6 ) Key m at rix (K0 0 –K0 3 × R0 0 –R0 3 ) processin g
Specifications
Th is is th e in terru pt rou tin e "IK0" wh ich specifies th e h igh
in pu t key from th e key m atrix sh own in Figu re 5.7.2 an d
con verts it to th e key code.
Note, h owever, th at th e du plicate in pu t process "K0MLT" will
be execu ted wh en m u ltiple keys are sim u ltan eou sly pressed,
an d th e n o-en try process "K0NOENT" will be execu ted wh en
in terru pt is in adverten tly gen erated.
K03
K02
K01
K00
No.F
No.E
No.D
No.C
R03
R02
R01
R00
No.B
No.7
No.3
No.A
No.6
No.2
No.9
No.5
No.1
No.8
No.4
No.0
Address
Data
0
H
Input key code (No. 0–F)
Fig. 5.7.2
Key matrix
(K00–K03 × R00–R03)
Program
At first, th e key m atrix is scan n ed an d th en th e statu s of th e
16 keys is read in to th e bu ffer m em ory. Next, th ese 16 data
are con verted to h igh in pu t key n u m bers.
Table 5.7.5
Contents of RAM
Data Bits
Address
D3
D2
D1
D0
and input data buffer
●0H
●1H
●2H
●3H
No.3
No.7
No.B
No.F
No.2
No.6
No.A
No.E
No.1
No.5
No.9
No.D
No.0
No.4
No.8
No.C
DI
LD
;Disable interrupts
;Set the differential registers DFK00–DFK03
;to "0000"
X,74H
LDPX MX,0000B
LD
LD
LD
EI
MX,1111B
X,7BH
MX,1111B
;Enable K00–K03 interrupt
;Make R00–R03 high output
;
;Enable interrupts
;
;
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CHAPTER 5: PERIPHERAL CIRCUITS (Input Ports)
YK0B0:
EQU
ꢀ0H
;Input data buffer start address
;
;
IK0:
LD
LD
LD
LD
LD
X,75H
MX,0000B
X,7BH
MX,0001B
Y,YK0B0
;Mask K00–K03 interrupt
;
;Preparation: Make only R00 high output
;
;
Store YK0B0 in Y register
;
IK0SCLP: LD
A,1H
;Scanning loop: Delay: Preparation
IK0SCDLLP:ADD
A,0FH
;
Delay loop
JP
LD
NZ,IK0SCDLLP ;
X,73H
;
;
;
;
;
Store K00–K03 data in the buffer
Address next buffer
LDPY MY,MX
LD
ADD
JP
X,7BH
Shift high output to the left
MX,MX
NZ,IK0SCLP
Continue until all are low
;
CALL K0
;Execute key processing routine "K0"
LD
LD
LD
LD
X,75H
MX,1111B
X,7BH
;Enable K00–K03 interrupt again
;
;Make R00–R03 high output again
;
MX,1111B
RET
;Return to "INIK"
;
;
K0:
LD
A,0H
;Preparation: Clear A register
LD
CP
JP
ADD
INC
CP
Y,YK0B0
MY,0H
K0RDCT
A,1H
;
Store YK0B0 in Y register
K0RDLP:
K0RDCT:
;
;Loop: If contents of input data buffer
;
;
;
are not "0",
then add 1 to A register
and address next buffer
Y
YL,4H
NZ,K0RDLP
;Continue until four times
;
JP
CP
JP
A,0H
Z,K0N0ENT
;If not high input
;
;
execute non-input processing "K0NOENT"
and return to "IK0"
;
CP
JP
A,2H
NC,K0MLT
;If multiple key entry
;
;
execute multiple key entry processing "K0MLT"
and return to "IK0"
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S1C62N33 TECHNICAL SOFTWARE
CHAPTER 5: PERIPHERAL CIRCUITS (Input Ports)
;
LD
LD
LD
A,0H
B,0H
Y,YK0B0
;Preparation: Clear A register
;
;
Clear B register
Store YK0B0 in Y register
;
K0ECLP:
CP
JP
JP
CP
JP
CP
JP
CP
JP
JP
MY,0001B
Z,K0ECLP0
C,K0ECLP4
MY,0010B
Z,K0ECLP1
MY,0100B
Z,KPECLP2
MY,1000B
Z,K0ECLP3
K0MLT
;Coding loop: Judge high input pin
;
;
;
;
;
;
;
;
;
;
K00 high input: Go to K0ECLP0
Not high input: Go to K0ECLP4
K01 high input:
Go to K0ECLP1
K02 high input:
Go to K0ECLP2
K03 high input:
Go to K0ECLP3
Multiple key entry: Execute multiple key entry
processing "K0MLT", and return to "IK0"
;
K0ECLP3: ADD
K0ECLP2: ADD
K0ECLP1: ADD
K0ECLP0: ADD
A,1H
A,1H
A,1H
A,B
;
;
;
;
;
;
;
;
K03 high input: A ← 3
K02 high input: A ← 2
K01 high input: A ← 1
K00 high input: Add the value of B register
to A register
LD
Mꢀ,A
B,4H
Y
Store result in memory register Mꢀ
Increase the value of B register by four
Address next buffer
K0ECLP4: ADD
INC
CP
JP
YL,4H
NZ,K0ECLP
;Continue until four times
;
;
RET
;Return to "IK0"
Th is rou tin e assu m es th at processin g rou tin es "K0NOENT"
an d "K0MLT" h ave been prepared separately.
Notes
1. Wh en th e key scan is execu ted, th e in pu t statu s ch an ges
an d th e con dition is ready for an in terru pt factor flag to
be set. Hen ce, th e K00–K03 in terru pt is m asked in
advan ce.
2. Wh en in pu t ports are ch an ged from h igh to low by pu ll-
down resistan ce, th e fall of th e waveform is delayed.
Hen ce, wh en fetch in g key scan in pu t, set an appropriate
wait tim e.
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CHAPTER 5: PERIPHERAL CIRCUITS (Input Ports)
(1) Wh en in pu t ports are ch an ged from h igh to low by pu ll-
Prog ra m m ing note s
down resistor, th e fall of th e waveform is delayed on
accou n t of th e tim e con stan t of th e pu ll-down resistan ce
an d in pu t gate capacitan ce. Hen ce, wh en fetch in g in pu t
ports, set an appropriate wait tim e.
Particu lar care n eeds to be taken of th e key scan du rin g
key m atrix con figu ration . Aim for a wait tim e of abou t 1
m s.
(2) Writin g to th e in terru pt m ask registers (EIK) can be don e
on ly in th e DI statu s (in terru pt flag = "0"). Writin g du rin g
EI statu s can cau se an error.
(3) Wh en "n oise rejector circu it en able" is selected with th e
m ask option , a m axim u m delay of 1 m s occu rs from th e
tim e th e in terru pt con dition s are establish ed u n til th e
in terru pt factor flag (IK) is set to "1" (u n til th e in terru pt is
actu ally gen erated).
Hen ce, pay atten tion to th e tim in g wh en readin g ou t
(resettin g) th e in terru pt factor flag.
(4) In pu t in terru pt program in g related precau tion s
Port K input
Active status
Active status
Differential register
Falling edge interrupt
Rising edge interrupt
Mask register
ꢀ
Factor flag set Not set
ꢀ
Factor flag set
When the content of the mask register is rewritten, while the port K
input is in the active status. The input interrupt factor flags are set at
ꢀ and ꢀ, ꢀ being the interrupt due to the falling edge and ꢀ the
interrupt due to the rising edge.
Fig. 5.7.3
Input interrupt timing
Wh en u sin g an in pu t in terru pt, if you rewrite th e con ten t
of th e m ask register, wh en th e valu e of th e in pu t term in al
wh ich becom es th e in terru pt in pu t is in th e active statu s,
th e factor flag for in pu t in terru pt m ay be set.
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CHAPTER 5: PERIPHERAL CIRCUITS (Input Ports)
Th erefore, wh en u sin g th e in pu t in terru pt, th e active
statu s of th e in pu t term in al im plies
in pu t term in al = low statu s, wh en th e fallin g edge
in terru pt is effected an d
in pu t term in al = h igh statu s, wh en th e risin g edge
in terru pt is effected.
Wh en an in terru pt is triggered at th e fallin g edge of an
in pu t term in al, a factor flag is set with th e tim in g of ꢀ
sh own in Figu re 5.7.3. However, wh en clearin g th e
con ten t of th e m ask register with th e in pu t term in al kept
in th e low statu s an d th en settin g it, th e factor flag of th e
in pu t in terru pt is again set at th e tim in g th at h as been
set. Con sequ en tly, wh en th e in pu t term in al is in th e
active statu s (low statu s), do n ot rewrite th e m ask regis-
ter (clearin g, th en settin g th e m ask register), so th at a
factor flag will on ly set at th e fallin g edge in th is case.
Wh en clearin g, th en settin g th e m ask register, set th e
m ask register, wh en th e in pu t term in al is n ot in th e
active statu s (h igh statu s).
Wh en an in terru pt is triggered at th e risin g edge of th e
in pu t term in al, a factor flag will be set at th e tim in g of ꢀ
sh own in Figu re 5.7.3. In th is case, wh en th e m ask
registers cleared, th en set, you sh ou ld set th e m ask
register, wh en th e in pu t term in al is in th e low statu s.
In addition , wh en th e m ask register = "1" an d th e con ten t
of th e differen tial register is rewritten in th e in pu t term i-
n al active statu s, an in pu t in terru pt factor flag m ay be
set. Th u s, you sh ou ld rewrite th e con ten t of th e differen -
tial register in th e m ask register = "0" statu s.
(5) Read ou t th e in terru pt factor flag (IK) on ly in th e DI
statu s (in terru pt flag = "0"). Read-ou t du rin g EI statu s
can cau se an error.
(6) Even wh en th e valu es of th e in pu t data an d differen tial
register ch an ges from n on -m atch in g to m atch in g, th e
in terru pt factor flag is n ot set to "1".
(7) Sin ce th e SCTRG/ SIOF registers are at 77H, care n eeds
to be taken wh en u sin g operation al com m an ds (AND, OR,
ADD, SUB, etc.).
S1C62N33 TECHNICAL SOFTWARE
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CHAPTER 5: PERIPHERAL CIRCUITS (I/O Ports)
5.8 I/ O Ports
Th e S1C62N33 Series reserves eigh t bits for gen eral-pu rpose
I/ O ports. Th e I/ O ports are th e allocated in to two lots of
fou r bits, P00–P03 an d P10–P13, wh ich can be set to eith er
in pu t m ode or ou tpu t m ode.
I/ O p ort m e m ory
m a p
Table 5.8.1 I/O data memory map (I/O ports)
Register
Address
*7
Comment
*1
D3
D2
D1
D0
Name
P03
SR
1
0
P03
P02
P01
P00
*2
High
Low
R/W
*2
*2
*2
I/O port (P00–P03)
P02
P01
High
High
Low
Low
Output latch reset at time of initial reset
7DH
7EH
FDH
P00
High
Low
–
TMRST SWRUN SWRST
IOC0
R/W
Reset
TMRST
Reset
0
Clock timer reset *5
W
R/W
W
RUN
Reset
Output
High
STOP
–
SWRUN
SWRST
IOC0
P13
Stopwatch counter RUN/STOP
Stopwatch counter reset *5
I/O control register 0 (P00–P03)
Reset
0
Input
Low
Low
Low
Low
*2
P13
P12
P11
P10
*2
P12
High
I/O port (P10–P13)
R/W
Output latch reset at time of initial reset
*2
P11
High
*2
P10
High
*2
0
–
CLKCHG OSCC
R/W
IOC1
–
Unused *5
CLKCHG
OSCC
IOC1
OSC3
ON
OSC1
OFF
CPU clock switch
R
FEH
0
OSC3 oscillator ON/OFF
I/O control register 1 (P10–P13)
0
Output
Input
*1 In itial valu e followin g in itial reset
*2 Not set in th e circu it
*3 Un defin ed
*5 Always "0" wh en bein g read
*6 Refer to m ain m an u al
*7 Page switch in g in I/ O m em ory is
n ot n ecessary
*4 Reset (0) im m ediately after bein g read
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CHAPTER 5: PERIPHERAL CIRCUITS (I/O Ports)
P00–P03, P10–P13: I/ O port data can be read an d ou tpu t data can be set
I/O port data th rou gh th ese ports.
(7DH, FDH)
• Wh en writ in g dat a
Wh en "1" is written : High level
Wh en "0" is written : Low level
Port data can be written also in in pu t m ode.
• Wh en readin g dat a ou t
Wh en "1" is read ou t: High level
Wh en "0" is read ou t: Low level
Th e term in al voltage level of th e I/ O port is read ou t. Wh en
th e I/ O port is in th e in pu t m ode th e voltage level bein g
in pu t to th e port term in al can be read ou t; in ou tpu t m ode
th e ou tpu t voltage level can be read.
Fu rth er, th e bu ilt-in pu ll-down resistan ce goes ON du rin g
read-ou t, so th at th e I/ O port term in al is pu lled down .
Exa m p le of p rog ra m
for I/ O p orts
(1 ) Readin g t o I/ O port s (P0 0 –P0 3 , P1 0 –P1 3 ), wh en OSC1 ru n n in g
Specifications
Wh en th e CPU clock is OSC1, th is rou tin e sets I/ O ports
(P00–P03) to in pu t m ode, an d reads th e in pu t data to A
register.
A register
Fig. 5.8.1
D3
D2
D1
D0
Correspondence of I/O ports
(input) and A register
P03
P02
P01
P00
S1C62N33 TECHNICAL SOFTWARE
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CHAPTER 5: PERIPHERAL CIRCUITS (I/O Ports)
Next it sets P10–P13 to in pu t m ode, an d reads th e in pu t
data to RAM, YINB.
Fin ally it sets P00–P03 to ou tpu t m ode, an d reads th e statu s
of pin s P00–P03 in to RAM, YDTB.
Table 5.8.2
Correspondence of I/O ports
and RAM store data
Data Bits
Address
D3
P13
P03
D2
P12
P02
D1
P11
P01
D0
P10
P00
● H
●●H
Program
YINB
YDTB
;
EQU
EQU
● H
●●H
;Data buffer address to read
;Data buffer address
;
LD
AND
LD
X,7EH
MX,1110B
X,7DH
A,MX
;Set ports P00–P03 to input mode
;
;Load the input to P00–P03 into A register
;
LD
;
;
LD
AND
LD
LD
LD
X,0FEH
MX,1110B
X,0FDH
Y,YINB
MY,MX
;Set ports P10–P13 to input mode
;
;Store the input to P10–P13 into RAM, YINB
;
;
LD
OR
LD
LD
LD
X,7EH
MX,0001B
X,7DH
Y,YDTB
MY,MX
;Set ports P00–P03 to output mode
;
;Store the pin data of P00–P03 to RAM, YDTB
;
;
Note
Wh en th e I/ O port is set to ou tpu t m ode an d a low-im ped-
an ce load is con n ected to th e port pin s, th e valu e of data
written to th e register an d data read ou t m ay differ.
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S1C62N33 TECHNICAL SOFTWARE
CHAPTER 5: PERIPHERAL CIRCUITS (I/O Ports)
(2 ) Readin g t o I/ O port s (P0 0 –P0 3 ) wh en OSC3 ru n n in g
Specifications
Wh en th e CPU clock is OSC3, th is rou tin e sets I/ O ports
(P00–P03) to in pu t m ode, an d reads th e in pu t data to A
register.
Program
LD
X,7EH
;Set ports P00–P03 to input mode
AND
LD
MX,1110B
X,7DH
;
;Read: Preparation
LD
B,9H
;
PINLP: LD
A,MX
B,0FH
NZ,PINLP
;
;
Loop: Load to A register
ADD
JP
;Repeat 10 times
Note
Th is program exam ple assu m es th at th e pu ll-down resistor
u ses th e bu ilt-in pu ll-down resistor on ly, an d perform s th e
read operation ten tim es.
(3 ) Writ in g t o I/ O port s (P0 0 –P0 3 , P1 0 –P1 3 )
Specifications Th is rou tin e ou tpu ts th e valu e of A register to I/ O ports
(P00–P03), th en ou tpu ts th e valu e of RAM, YDTB to P10–
P13.
RAM, YDTB
A register
D3 D2 D1 D0
D3 D2 D1 D0
P13 register
P12 register
P11 register
P10 register
P13
P12
P11
P10
P03 register
P02 register
P01 register
P00 register
P03
P02
P01
P00
Fig. 5.8.2
Correspondence between I/O
ports (output) and A register
and RAM
S1C62N33 TECHNICAL SOFTWARE
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CHAPTER 5: PERIPHERAL CIRCUITS (I/O Ports)
Program
YDTB
;
EQU
●●H
;Data buffer address
LD
OR
LD
LD
X,7EH
MX,0001B
X,7DH
MX,A
;Set the ports P00–P03 to output mode
;
;Output the value of A register to P00–P03
;
;
LD
OR
LD
LD
LD
X,0FEH
MX,0001B
X,7DH
Y,YDTB
MX,MY
;Set the ports P10–P13 to output mode
;
;Output the value of RAM, YDTB to P10–P13
;
;
(1) Wh en th e I/ O port is bein g read ou t an d th e pu ll-down is
execu ted on ly with th e bu ilt-in pu ll-down resistor of th e
I/ O ports, th e read-ou t m u st be repeated abou t ten tim es
wh en th e CPU is operatin g with th e OSC3 oscillation
circu it.
Prog ra m m ing note s
(2) Wh en th e I/ O port is set to th e ou tpu t m ode an d th e data
register h as been read, th e pin data in stead of th e
register data can be read ou t. Becau se of th is, if a low-
im pedan ce load is con n ected an d read-ou t perform ed, th e
valu e of th e register an d th e read-ou t resu lt m ay differ.
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S1C62N33 TECHNICAL SOFTWARE
CHAPTER 5: PERIPHERAL CIRCUITS (Stopwatch Counter)
5.9 Stop wa tc h Counte r
Th e S1C62N33 Series in corporates a 1/ 100 sec an d 1/ 10
sec stopwatch cou n ter. Th e stopwatch cou n ter data can be
read ou t by th e software.
Fu rth er, th e stopwatch cou n ter can gen erate 10 Hz (ap-
proxim ated 10 Hz) an d 1 Hz in terru pts.
Th e stopwatch cou n ter can be u sed as a separate tim er from
th e clock tim er. In particu lar, digital watch stopwatch
fu n ction s can be realized easily with software.
Stop wa tc h c ounte r
m e m ory m a p
Table 5.9.1 I/O data memory map (stopwatch counter)
Register
Address
Comment
*1
D3
D2
D1
D0
Name
SWL3
SR
0
1
0
*7
SWL3
SWL2
SWL1
SWL0
MSB
SWL2
SWL1
0
0
0
0
0
0
0
Stopwatch counter
1/100 sec (BCD)
R
71H
SWL0
LSB
SWH3
SWH2
SWH1
SWH0
SWH3
SWH2
SWH1
SWH0
TMRST
SWRUN
SWRST
IOC0
MSB
Stopwatch counter
1/10 sec (BCD)
R
72H
LSB
TMRST SWRUN SWRST
IOC0
R/W
Reset
RUN
–
STOP
–
Reset
0
Clock timer reset *5
W
R/W
W
Stopwatch counter RUN/STOP
Stopwatch counter reset *5
I/O control register 0 (P00–P03)
7EH
Reset
Output
Reset
0
Input
*1 In itial valu e followin g in itial reset
*2 Not set in th e circu it
*3 Un defin ed
*5 Always "0" wh en bein g read
*6 Refer to m ain m an u al
*7 Page switch in g in I/ O m em ory is
n ot n ecessary
*4 Reset (0) im m ediately after bein g read
S1C62N33 TECHNICAL SOFTWARE
EPSON
II-87
CHAPTER 5: PERIPHERAL CIRCUITS (Stopwatch Counter)
SWRST: Th is bit resets th e stopwatch cou n ter.
Stopwatch counter reset
(7EH.D1)
Wh en "1" is written : Stopwatch cou n ter reset
Wh en "0" is written : No operation
Read-ou t: Always "0"
Exa m p le of p rog ra m
for stop wa tc h c oun-
te r
(1 ) Reset t in g, st art in g an d st oppin g t h e st opwat ch cou n t er
Specifications
Program
Con trollin g procedu re for th e in itial start, stop, start, an d
reset of th e stopwatch cou n ter is sequ en tially in dicated.
LD
OR
X,7EH
MX,0110B
;Initial start the stopwatch counter
;
;
;
;
LD
OR
X,7EH
MX,0010B
;Reset the stopwatch counter
;
LD
AND
X,7EH
MX,1011B
;Stop the stopwatch counter
;
LD
OR
X,7EH
MX,0100B
;Restart the stopwatch counter
;
1. Resettin g th e stopwatch cou n ter does n ot affect th e clock
tim er.
Notes
2. Wh en th e stopwatch cou n ter is reset in RUN statu s,
operation restarts im m ediately. Also, in STOP statu s th e
reset data is m ain tain ed.
3. In STOP statu s, th e cou n ter data is m ain tain ed u n til
reset or n ext RUN statu s occu rs. Also, wh en STOP statu s
ch an ges to RUN statu s, th e data th at was m ain tain ed can
be u sed for resu m in g th e cou n t.
II-88
EPSON
S1C62N33 TECHNICAL SOFTWARE
CHAPTER 5: PERIPHERAL CIRCUITS (Stopwatch Counter)
(2 ) Readin g t o t h e st opwat ch cou n t er
Specifications
Th is program reads th e stopwatch cou n ter's 1/ 100 sec data
to A register an d th e 1/ 10 sec data to B register.
Fig. 5.9.1
A register
B register
Correspondence between
stopwatch counter and
general-purpose register
D3
D2
D1
D0
D3
D2
D1
D0
SWL3 SWL2 SWL1 SWL0
SWH3 SWH2 SWH1 SWH0
Program
LD
X,71H
;Preparation: Store SWL address in X register
LD
Y,7EH
;Stop the stopwatch counter
AND
MY,1011B
;
;
LDPX
LD
;
A,MX
B,MX
;Load SWL data into A register
;Load SWH data into B register
OR
MY,0100B
;Restart the stopwatch counter
Note
To preven t erron eou s readin g du rin g carry from th e
stopwatch cou n ter's low order colu m n (SWL) to th e h igh
order colu m n (SWH), th e stopwatch cou n ter is stopped
du rin g read.
Th e du ration of th e stop statu s m u st be with in 976 µs (256
Hz 1/ 4 cycle).
S1C62N33 TECHNICAL SOFTWARE
EPSON
II-89
CHAPTER 5: PERIPHERAL CIRCUITS (Stopwatch Counter)
Stop wa tc h inte rrup t
m e m ory m a p
Table 5.9.2 I/O data memory map (stopwatch interrupt)
Register
Address
Comment
Normal Heavy load protection mode register
*1
D3
D2
SVDDT
SVDON
R
D1
D0
Name
HVLD
SR
0
1
0
*7
Heavy
load
HVLD
EISWIT1 EISWIT0
SVDDT
SVDON
0
0
Low voltage Normal SVD evaluation data (at read-out)
R/W
IK1
R/W
W
ON
OFF
SVD ON/OFF (at writing)
Interrupt mask register
(stopwatch 1 Hz)
76H
EISWIT1
EISWIT0
IK1
0
0
0
0
0
0
Enable
Mask
Interrupt mask register
(stopwatch 10 Hz)
Enable
Yes
Mask
No
Interrupt factor flag (K10) *4
IK0
SWIT1
SWIT0
Interrupt factor flag (K00–K03) *4
Interrupt factor flag (stopwatch 1 Hz) *4
Interrupt factor flag (stopwatch 10 Hz) *4
R
IK0
Yes
No
7AH
SWIT1
SWIT0
Yes
No
Yes
No
*1 In itial valu e followin g in itial reset
*2 Not set in th e circu it
*3 Un defin ed
*5 Always "0" wh en bein g read
*6 Refer to m ain m an u al
*7 Page switch in g in I/ O m em ory is
n ot n ecessary
*4 Reset (0) im m ediately after bein g read
Th ese flags in dicate th e statu s of th e stopwatch cou n ter
in terru pt.
SWIT0, SWIT1:
Interrupt factor flags
(7AH.D0 and D1)
Wh en "1" is read ou t: In terru pt h as occu rred
Wh en "0" is read ou t: In terru pt h as n ot occu rred
Writin g: In valid
Th ese flags are reset wh en read ou t by th e software.
Note Regardless of the interrupt mask register setting, these flags are
set to "1" by overflow of the corresponding counter.
II-90
EPSON
S1C62N33 TECHNICAL SOFTWARE
CHAPTER 5: PERIPHERAL CIRCUITS (Stopwatch Counter)
Stop wa tc h c ounte r
tim ing c ha rt
Stopwatch counter (SWL) timing chart
Address
71H
Register
D0
D1
(1/100 sec BCD)
D2
D3
10 Hz interrupt request
Address
Register
D0
Stopwatch counter (SWH) timing chart
D1
72H
(1/10 sec BCD)
D2
Fig. 5.9.2
Timing chart for
D3
1 Hz interrupt request
stopwatch counter
In terru pts are gen erated by th e overflow of th eir respective
cou n ters ("9" ch an gin g to "0"). At th is tim e th e correspon d-
in g in terru pt factor flags (SWIT0, SWIT1) are set to "1".
S1C62N33 TECHNICAL SOFTWARE
EPSON
II-91
CHAPTER 5: PERIPHERAL CIRCUITS (Stopwatch Counter)
Exa m p le of p rog ra m
for stop wa tc h inte r-
rup t
(1 ) Com bin in g in t erru pt fact or flag an d st opwat ch cou n t er
Specifications
Th is program u ses th e gen eration of th e stopwatch 1 Hz
in terru pt factor flag to execu te tim er display from th e 1/ 100
secon d to th e 10 m in u te colu m n s.
Table 5.9.3
Data Bits
Address
Correspondence between
stopwatch counter and store
data
D3
D2
D1
D0
▲0H
▲1H
SWL3
SWH3
SWL2
SWH2
SWL1
SWH1
SWL0
SWH0
Table 5.9.4
Address
▲2H
Data
Timer data by "SWTM"
Single digit seconds column (BCD)
Ten's digit seconds column (BCD)
Single digit minutes column (BCD)
Ten's digit minutes column (BCD)
▲3H
▲4H
▲5H
Program
Stores SWIT in th e m em ory register address M an d creates
data greater th an a secon d digit. Th rou gh th is, sim u ltan e-
ou s display of 1/ 100 secon d an d 1/ 10 secon d stopwatch
data, an d secon d/ m in u te data will be possible.
Table 5.9.5
Data Bits
Address
Data of memory register
D3
D2
D1
D0
0 H
IK1
IK0
SWIT1
SWIT0
YSITB EQU
0 H
;SWT interrupt factor flag buffer address
YSWLB EQU
▲0H
;Stopwatch counter low order data buffer address
;
;
DI
;Disable interrupts
LD
X,7EH
;Initial start stopwatch counter
OR
MX,0010B ;
;
SWLP: LD
LD
X,7AH
Y,7EH
;Preparation: Store interrupt factor flag address in the X register
;Stop the stopwatch counter
II-92
EPSON
S1C62N33 TECHNICAL SOFTWARE
CHAPTER 5: PERIPHERAL CIRCUITS (Stopwatch Counter)
AND
LD
LD
LD
LDPX
LD
MY,1011B ;
A,MX
M ,A
X,71H
A,MX
B,MX
;Store stopwatch interrupt factor flags
;
;
;
;
in the memory register M
Load SWL data to A register
Load SWH data to B register
OR
MY,0100B ;
Restart the stopwatch counter
LD
LDPX
LD
X,YSWLB
MX,A
MX,B
;
;
;
Store the value of the A register in RAM, YSWLB
Store the value of the B register in RAM, YSWLB+1
;
;
LD
FAN
JP
X,YSITB
MX,0010B ;
Z,SWDS
SWTM
;
If the ST1Hz interrupt factor flag is set
then execute stopwatch timer "SWTM"
;
;
CALL
SWDS: CALL
JP
DSSW
SWLP
;
;
Executes the stopwatch display routine "DSSW"
Back to SWLP
1. Regardless of th e settin g of th e m ask register (EISWIT),
th e in terru pt factor flag (SWIT) is set to "1" by overflow of
th e cou n ter. Th erefore, "in terru pt gen eration " is n ot
u sed.
Notes
Neverth eless, th e factor flag reset is execu ted, so th e DI
statu s m u st be in effect.
2. Th e stopwatch cou n ter is stopped wh en bein g read to, so
as to preven t an error occu rrin g wh en th e cou n ter is
perform in g carry from th e low order colu m n (SWL) to th e
h igh order colu m n (SWH).
Reference
Stopwatch timer "SWTM"
SWTM: LD
CALZ
X,YSWL+2 ;Increment the seconds by 1
CT60
;
RET
CALZ
RET
RET
;No carry up to minutes column: Return to parent routine
;Carry to higher column: Increment the minutes by 1
;No carry up to hours column: Returns to parent routine
;Carry to higher column: No carry up to hours column,
;return to parent routine
CT60
* For details abou t "CT60", see page 63, "Exam ple of u sin g
tim er in terru pt".
S1C62N33 TECHNICAL SOFTWARE
EPSON
II-93
CHAPTER 5: PERIPHERAL CIRCUITS (Stopwatch Counter)
(2 ) Set t in g st opwat ch in t erru pt s
Specifications
Program
In th e in terru pt disabled statu s, th is program en ables
stopwatch 1 Hz in terru pt on ly, an d th en en ables in terru pts.
DI
LD
LD
EI
;Disable interrupts
X,76H
MX,0010B
;Enable stopwatch 1 Hz interrupt
;and mask 10 Hz interrupt
;Enable interrupts
Notes
1. Write to th e in terru pt m ask registers (EISWIT) on ly in th e
DI statu s.
2. Th is program exam ple avoids u sin g arith m etic in stru c-
tion s to write to th e in terru pt m ask flag (EISWIT), an d
assu m es th at SVDON is fixed at "0".
(3 ) Processin g aft er in t erru pt is gen erat ed
Specifications Th is rou tin e stores th e register data wh en an in terru pt
occu rs, recovers th e register data wh en th e in terru pt proc-
essin g com pletes, an d retu rn s to th e m ain rou tin e. Th e
order of priority for settin g th e in terru pts is sh own in th e
table below. Nestin g of in terru pts can n ot be don e. Process-
in g proceeds in descen din g order of priority. Fu rth er, th e
in terru pt processin g rou tin e is called with CALL in stru ction
an d processed.
Table 5.9.6
Order of Priority
Interrupt Factor
Stopwatch 10 Hz
Stopwatch 1 Hz
Order of priority in program
example
1
2
II-94
EPSON
S1C62N33 TECHNICAL SOFTWARE
CHAPTER 5: PERIPHERAL CIRCUITS (Stopwatch Counter)
Program
ORG
JP
108H
INST
;
Vector address of stopwatch interrupts
;
;
If SWT interrupts occur, go to "INST"
;
;
YSITB
;
EQU
●●H
;
Buffer address of stopwatch interrupt factor flags
;
INST:
PUSH
PUSH
PUSH
PUSH
PUSH
PUSH
PUSH
XH
XL
YH
YL
A
;
;
;
;
;
;
;
Store value of X register in stack
Store value of Y register in stack
Store value of A register in stack
Store value of B register in stack
Store value of flag group in stack
B
F
;
LD
LD
LD
LD
AND
X,7AH
;
(Reset and) store
stopwatch interrupt factor flags
in the buffer
Mask the stopwatch interrupt factor flags
by value of stopwatch interrupt mask register
Y,YSITB
MY,MX
X,76H
MY,MX
;
;
;
;
;
;
FAN
JP
CALL
MY,0001B
Z,INSIT1
SIT0
;
;
;
If the ST10Hz interrupt factor flag is set
and enabled
then execute "SIT0"
INSIT1: FAN
JP
MY,0010B
Z,INRT
SIT1
;
;
;
If the ST1Hz interrupt factor flag is set
and enabled
then execute "SIT1"
CALL
;
INRT:
For details of "INRT", see "4.5 Exam ple of In terru pt Vector
Processin g".
Notes
1. Read th e in terru pt factor flags (SWIT) on ly in th e DI
statu s.
2. Regardless of th e settin g of th e m ask register (EISWIT),
th e in terru pt factor flag (SWIT) is set to "1" wh en th e
correspon din g cou n ter overflows. Th erefore, th e presen ce
of each in terru pt factor is ju dged accordin g to th e resu lt
of ANDin g th e factor flag stored in th e bu ffer with th e
m ask register.
S1C62N33 TECHNICAL SOFTWARE
EPSON
II-95
CHAPTER 5: PERIPHERAL CIRCUITS (Stopwatch Counter)
(1) Correct read-ou t is im possible wh en th ere is a carry from
Prog ra m m ing note s
th e low order bit (SWL) to th e h igh order bit (SWH).
Hen ce, wh en readin g ou t th e cou n ter data in th e RUN
statu s, th e cou n ter m u st first be stopped, an d th en th e
RUN statu s retu rn ed again .
Also, th e du ration of th e above STOP statu s m u st be
with in 976 µs (256 Hz 1/ 4 cycle).
(2) Resettin g th e clock tim er h as n o effect on th e stopwatch
cou n ter, an d vice versa.
(3) Writin g to th e in terru pt m ask registers (EISWIT) can be
don e on ly in th e DI statu s (in terru pt flag = "0"). Writin g
du rin g EI statu s will cau se an error.
Also, wh en u sin g arith m etic in stru ction s (AND, OR, ADD,
SUB, etc.), pay atten tion to th e con trol of SVD.
(4) Read-ou t of th e in terru pt factor flag (SWIT) m u st be don e
on ly in th e DI statu s (in terru pt flag = "0"). Read-ou t
du rin g EI statu s will cau se an error.
(5) Regardless of th e settin g of th e m ask register (EISWIT),
th e in terru pt factor flag (SWIT) is set to "1" wh en th e
correspon din g cou n ter overflows.
II-96
EPSON
S1C62N33 TECHNICAL SOFTWARE
CHAPTER 5: PERIPHERAL CIRCUITS (Event Counter)
5.10 Eve nt Counte r
Th e S1C62N33 Series h ou ses an even t cou n ter th at cou n ts
th e clock sign als in pu t from ou tside.
Th e even t cou n ter is con figu red of an eigh t-bit bin ary cou n -
ter (u p cou n ter). Th e cou n ter data can be read ou t by
software.
Eve nt c ounte r
m e m ory m a p
Table 5.10 I/O data memory map (event counter)
Register
Address
*7
Comment
*1
D3
D2
D1
D0
Name
EV03
SR
0
1
0
EV03
EV02
EV01
EV00
R
Event counter
EV02
EV01
0
0
low order (EV00–EV03)
F8H
F9H
EV00
EV07
0
0
EV07
EV06
EV05
EV04
R
EV06
EV05
EV04
–
0
0
Event counter
high order (EV04–EV07)
0
*2
0
–
EVRUN
R/W
–
EVRST
W
Unused *5
R
R
EVRUN
–
RUN
STOP
Event counter RUN/STOP
Unused *5
FCH
*2
EVRST
Reset
Reset
–
Event counter reset *5
*1 In itial valu e followin g in itial reset
*2 Not set in th e circu it
*3 Un defin ed
*5 Always "0" wh en bein g read
*6 Refer to m ain m an u al
*7 Page switch in g in I/ O m em ory is
n ot n ecessary
*4 Reset (0) im m ediately after bein g read
S1C62N33 TECHNICAL SOFTWARE
EPSON
II-97
CHAPTER 5: PERIPHERAL CIRCUITS (Event Counter)
EVRST: Th is it th e register for resettin g th e even t cou n ter.
Event counter reset
(FCH.D0)
Wh en "1" is written : Even t cou n ter reset
Wh en "0" is written : No operation
Read-ou t: Always "0"
Exa m p le of p rog ra m
for e ve nt c ounte r
(1 ) Reset t in g, st art in g, an d st oppin g t h e even t cou n t er
Con trollin g procedu re for th e in itial start, stop, start, an d
reset of th e even t cou n ter is sequ en tially in dicated.
Specifications
Program
LD
LD
X,0FCH
MX,0101B
;Initial start event counter
;
;
;
;
LD
LD
X,0FCH
MX,0000B
;Stop event counter
;
LD
LD
X,0FCH
MX,0100B
;Start event counter
;
LD
LD
X,0FCH
MX,0001B
;Reset event counter
;
II-98
EPSON
S1C62N33 TECHNICAL SOFTWARE
CHAPTER 5: PERIPHERAL CIRCUITS (Event Counter)
(2 ) Readin g even t cou n t er
Specifications
Th is program reads th e fou r h igh order bits of th e even t
cou n ter to B register, an d th e fou r low order bits to A regis-
ter.
Fig. 5.10
A register
B register
Correspondence between
event counter and general-
purpose register
D3
D2
D1
D0
D3
D2
D1
D0
EV03 EV02 EV01 EV00
EV07 EV06 EV05 EV04
Program
LD
X,0F8H
Y,0F9H
B,MY
A,MX
MY,B
Z,EV●●
A,MX
B,MY
;First reading: Preparation
LD
LD
LD
CP
JP
LD
LD
;
;
;
Load EV04–EV07 data to B register
Load EV00–EV03 data to A register
;If there is a carry to EV04–EV07
;
;
;
Redo read: EV00–EV03 data
EV04–EV07 data
;
EV●●: . . .
Note
To preven t erron eou s readin g wh en th ere is a carry from th e
even t cou n ter's low order data (EV00–EV03) to th e h igh
order data (EV04–EV07), th e cou n ter data is read ou t m u l-
tiple tim es an d com pared.
To preven t erron eou s readin g of th e even t cou n ter data, read
ou t th e cou n ter data m u ltiple tim es for com parison , an d u se
th e m atch in g data for th e resu lt.
Prog ra m m ing note
S1C62N33 TECHNICAL SOFTWARE
EPSON
II-99
CHAPTER 5: PERIPHERAL CIRCUITS (Analog Comparator)
5.11 Ana log Com p a ra tor
Th e S1C62N33 Series in corporates an MOS in pu t an alog
com parator. Th is an alog com parator, wh ich h as two differ-
en tial in pu t term in als (in verted in pu t term in al AMPM,
n on in verted in pu t term in al AMPP), can be u sed for gen eral
pu rposes.
To keep cu rren t con su m ption low, th e an alog com parator
circu it can be switch ed ON an d OFF by th e software.
Ana log c om p a ra tor
m e m ory m a p
Table 5.11 I/O data memory map (analog comparator)
Register
Address
Comment
*1
D3
D2
D1
D0
Name
–
SR
1
0
*7
*2
–
–
AMPDT AMPON
R/W
Unused *5
Unused *5
*2
1
–
R
F7H
+ > -
- > +
AMPDT
AMPON
Analog comparator data
0
ON
OFF
Analog comparator ON/OFF
*1 In itial valu e followin g in itial reset
*2 Not set in th e circu it
*3 Un defin ed
*5 Always "0" wh en bein g read
*6 Refer to m ain m an u al
*7 Page switch in g in I/ O m em ory is
n ot n ecessary
*4 Reset (0) im m ediately after bein g read
AMPDT: Reads ou t th e ou tpu t from th e an alog com parator.
Analog comparator data
Wh en "1" is read ou t: AMPP (+) > AMPM (-)
Wh en "0" is read ou t: AMPP (+) < AMPM (-)
(F7H.D1)
Note To keep the current consumption low, set the analog com-
parator to OFF when it is not needed.
Exa m p le of p rog ra m
for a na log
c om p a ra tor
II-100
EPSON
S1C62N33 TECHNICAL SOFTWARE
CHAPTER 5: PERIPHERAL CIRCUITS (Analog Comparator)
(1 ) Set t in g t h e an alog com parat or ON an d OFF, an d readin g dat a
(wh en OSC1 is ru n n in g)
Specifications
Program
With OSC1 as th e CPU clock, th is program sets th e AMP
circu it to ON, allows a delay, reads th e resu lt in to A register,
an d sets th e circu it to OFF.
AMP circuit ON
LD
X,0F7H
MX,0001B
A,0FH
;
;
;
;
;
;
;
LD
Delay: Preparation
Delay loop
LD
AMDLLP: ADD
A,0FH
JP
LD
LD
NZ,AMDLLP
A,MX
MX,1110B
Load the result to A register
AMP circuit OFF
Note
Th e delay is m ade to allow th e ou tpu t to stabilize.
(2 ) Set t in g t h e an alog com parat or ON an d OFF, an d readin g dat a
(wh en OSC3 is ru n n in g)
Specifications
With OSC3 as th e CPU clock, th is program sets th e AMP
circu it to ON, allows a delay, reads th e resu lt in to A register,
an d sets th e circu it to OFF.
LD
LD
LD
X,0F7H
MX,0001B
Y,54H
;AMP circuit ON
;
;Delay: Preparation
Program
AMDLLP: ADD
Y,0FH
NZ,AMDLLP
A,MX
;
;
Delay loop
JP
LD
AND
;Load the result to A register
;AMP circuit OFF
MX,1110B
Note
Th e delay is m ade to allow th e ou tpu t to stabilize.
(1) To keep th e cu rren t con su m ption low, set th e an alog
com parator to OFF wh en it is n ot n eeded.
Prog ra m m ing note s
(2) After AMPON is set to "1", allow a wait of at least 3 m s for
th e an alog com parator's operation to stabilize before
readin g ou t th e an alog com parator's ou tpu t data AMPDT.
S1C62N33 TECHNICAL SOFTWARE
EPSON
II-101
CHAPTER 5: PERIPHERAL CIRCUITS (Serial Interface)
5.12 Se ria l Inte rfa c e (SIN, SOUT, SCLK, SIOF)
Se ria l inte rfa c e
m e m ory m a p
Table 5.12.1 I/O data memory map (serial interface)
Register
Address
*7
Comment
*1
D3
D2
D1
D0
Name
SD3
SR
1
0
*3
SD3
SD2
SD1
SD0
×
*3
*3
*3
*3
*3
*3
*3
R/W
R/W
R/W
SD2
SD1
SD0
SD7
SD6
SD5
SD4
×
×
×
×
×
×
×
1
Serial interface data regsiter
Low order (SD0–SD3)
F0H
F1H
F2H
SD7
SD6
SD5
SD4
Serial interface data regsiter
High order (SD4–SD7)
*6
*6
*6
*6
SCS1
SCS0
SE2
EISIO
SCS1
SCS0
SE2
Clock mode selection register
(SCS0, SCS1)
1
Rising
Enable
Falling
Mask
Clock edge selection register
0
EISIO
0
Interrupt mask register (serial interface)
Unused *5
–
–
–
ISIO
–
–
*2
*2
*2
0
R
Unused *5
F3H
Unused *5
–
Interrupt factor flag (serial interface) *4
ISIO
Yes
No
Serial interface clock trigger
SIOF
SCTRG
SIOF
–
0
Trigger
RUN
–
SCTRG
SIOF
EIK10
DFK10
K10
R
STOP
W
R
R/W
EIK10
DFK10
K10
0
0
Enable
Falling
High
Mask
Rising
Low
Interrupt mask register (K10)
Input comparison register (K10)
Input port (K10)
77H
*2
*1 In itial valu e followin g in itial reset
*2 Not set in th e circu it
*3 Un defin ed
*5 Always "0" wh en bein g read
*6 Refer to m ain m an u al
*7 Page switch in g in I/ O m em ory is
n ot n ecessary
*4 Reset (0) im m ediately after bein g read
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S1C62N33 TECHNICAL SOFTWARE
CHAPTER 5: PERIPHERAL CIRCUITS (Serial Interface)
SD0–SD3, SD4–SD7: Th ese registers are u sed for writin g an d readin g serial data.
Serial interface data
• Wh en writ in g dat a
registers
Wh en "1" is written :
Wh en "0" is written :
High level
Low level
(F0H, F1H)
Th ese registers write serial data to be ou tpu t from th e
SOUT pin . Th e serially con verted data is ou tpu t from th e
SOUT pin as h igh (VDD) wh en th e bit is set to "1" an d as
low (VSS) wh en th e bit is set to "0".
• Wh en readin g dat a
Wh en "1" is read ou t: High level
Wh en "0" is read ou t: Low level
In pu t serial data is read ou t from th e SIN pin .
Th ese registers are loaded with data th at h as been paral-
lel con verted so th at th e h igh (VDD) level bit in pu t from
th e SIN pin is "1", an d th e low (VSS) bit is "0".
Perform data readin g on ly wh ile serial in terface is h alted
(i.e., th e syn ch ron ou s clock is n eith er bein g in pu t or
ou tpu t).
Data is u n defin ed in th is register at in itial reset.
SCS1, SCS0: Th e syn ch ron ou s clock (SCLK) of th e serial in terface can be
Clock mode selection selected with th ese registers.
register
(F2H.D3 and D2)
SCS1
SCS0
Mode
Synchronous Clock
CLK
0
0
1
1
0
1
0
1
Table 5.12.2
Master mode
Slave mode
CLK/2
Synchronous clock selection
CLK/4
External clock
CLK: system clock
Th e syn ch ron ou s clock (SCLK) can be selected from am on g
th e fou r types listed above, n am ely from th ree types of
in tern al clock an d on e extern al clock.
At in itial reset, th e extern al clock is selected.
S1C62N33 TECHNICAL SOFTWARE
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CHAPTER 5: PERIPHERAL CIRCUITS (Serial Interface)
SE2: Tim in g for readin g in th e serial data in pu t from th e SIN pin
Clock edge selection can be selected with th ese registers.
register
Wh en "1" is written :
Wh en "0" is written :
Read-ou t:
SCLK risin g edge
(F2H.D1)
SCLK fallin g edge
Valid
Th ese registers en able selection of wh eth er to perform
readin g to th e serial in pu t data register (SD0–SD7) at th e
SCLK sign al's risin g edge (wh en "1" is written ) or fallin g edge
(wh en "0" is written ).
Pay atten tion if th e syn ch ron ou s clock goes in to reverse
ph ase (SCLK→SCLK) th rou gh th e m ask option .
SCLK risin g = SCLK fallin g, SCLK fallin g = SCLK risin g
Wh en th e in tern al clock is selected as th e syn ch ron ou s
clock (SCLK), a h azard occu rs in th e syn ch ron ou s clock
(SCLK) wh en data is written to register SE2.
Th e tim in g for readin g in th e in pu t data can be selected, bu t
th e ou tpu t tim in g for th e ou tpu t data is fixed to th e SCLK
risin g edge.
At in itial reset, SCLK fallin g (SE2 = "0") is selected.
EISIO: Th e in terru pt m ask from th e serial in terface can be set with
Interrupt mask register th is register.
(F2H.D0)
Wh en "1" is written :
Wh en "0" is written :
Read-ou t:
En abled
Masked
Valid
At in itial reset, th e m ask (EISIO = "0") is selected.
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S1C62N33 TECHNICAL SOFTWARE
CHAPTER 5: PERIPHERAL CIRCUITS (Serial Interface)
ISIO: Th is flag in dicates th e statu s of th e in terru pt from th e serial
Interrupt factor flag in terface.
(F3H.D0)
Wh en "1" is read ou t: In terru pt h as occu rred
Wh en "0" is read ou t: In terru pt h as n ot occu rred
Writin g:
In valid
By readin g ou t th is in terru pt factor flag, th e software can
ju dge wh eth er an in terru pt from th e serial in terface h as
occu rred. Th e in terru pt factor flag is reset wh en it h as been
read ou t. Note, h owever, th at even if th e in terru pt is
m asked, th is flag will be set to "1" after th e 8 bits data
in pu t/ ou tpu t.
Th e flag can be read ou t on ly wh en in th e DI statu s
(in terru pt flag = "0").
At in itial reset, th is flag is set to "0".
SCTRG: Th is is th e trigger for startin g in pu t or ou tpu t of th e syn -
Clock trigger ch ron ou s clock (SCLK).
(77H.D3)
Wh en "1" is written :
Wh en "0" is written :
Read-ou t:
Trigger in pu t
No operation
Always "0"
Wh en th is trigger is su pplied to th e serial in terface activat-
in g circu it, th e syn ch ron ou s clock (SCLK) in pu t/ ou tpu t is
started.
As a trigger con dition , it is requ ired th at data writin g or
readin g on data registers SD0–SD7 be perform ed prior to
writin g "1" to SCTRG. (Th e in tern al circu it of th e serial
in terface is in itiated th rou gh data writin g/ readin g on data
registers SD0–SD7.)
Wh en ever th e serial in terface is in th e RUN statu s, apply
th is trigger in pu t on ce on ly. Refrain from perform in g trigger
in pu t m u ltiple tim es, as th is leads to m alfu n ction in g.
S1C62N33 TECHNICAL SOFTWARE
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CHAPTER 5: PERIPHERAL CIRCUITS (Serial Interface)
Fu rth er, if th e syn ch ron ou s clock (SCLK) is th e extern al
clock, start th e extern al clock in pu t after th e trigger in pu t.
SCTRG resides in th e sam e bit at th e sam e address as SIOF,
an d on e or th e oth er is selected by write or read operation .
Wh en writin g a "1" to SCTRG u se th e OR com m an d, an d
wh en writin g a "0" u se th e AND com m an d. No oth er com -
m an ds sh ou ld be u sed for th is pu rpose.
SIOF: In dicates th e ru n n in g statu s of th e serial in terface.
Special output port data
Wh en "1" is read ou t: RUN statu s
Wh en "0" is read ou t: STOP statu s
(77H.D3)
Writin g:
In valid
Th e RUN statu s is in dicated from th e en d of writin g "1" to
SCTRG th rou gh to th e en d of serial data in pu t/ ou tpu t.
Exa m p le of p rog ra m
for se ria l inte rfa c e
(1 ) Fet ch in g dat a u sed by t h e in t ern al clock
Specifications
Th is program ou tpu ts to th e ou tside a clock h avin g th e
sam e frequ en cy as th e CPU system clock, an d takes serial
data in to th e gen eral registers (A, B). Figu re 5.12.1 sh ows
an exam ple of data bein g taken in wh en th e m ask option
h as been u sed to select SCLK = positive logic, perm u tation =
MSB first.
SCLK
SIN
(SE2=0)
B register
A register
Fig. 5.12.1
D3 D2 D1 D0
D3 D2 D1 D0
Example of fetching serial
interface data
1
0
1
0
0
1
0
1
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S1C62N33 TECHNICAL SOFTWARE
CHAPTER 5: PERIPHERAL CIRCUITS (Serial Interface)
Program
ZK10
EQU
EQU
EQU
EQU
EQU
077H
077H
0F0H
0F1H
0F2H
1000B
1000B
1100B
ZR1
ZSDL
ZSDH
ZSC
XSCTRG EQU
XSIOF EQU
XSCS
;
EQU
LD
X,ZSC
;Select SCS address by X register
AND
MX,XSCS XOR 0FH ;Set internal clock mode
;( CLK/1 )
;
;
LD
LD
X,ZSDH
A,MX
;Select SD47 address by X register
;Initialize circuit
LD
OR
X,ZK10
MX,XSCTRG
;Select SCTRG address by X register
;Shot SCTRG
;
LD
FAN
JP
X,ZR1
MX,XSIOF
NZ,WAIT
;Select SIOF address by X register
;Check SIO status
;If SIO running then loop
WAIT
;
LD
LDPX
LD
X,ZSDL
A,MX
B,MX
;Select SD03 address by X register
;Read SD0–SD3 data to A register
;Read SD4–SD7 data to B register
S1C62N33 TECHNICAL SOFTWARE
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II-107
CHAPTER 5: PERIPHERAL CIRCUITS (Serial Interface)
(2 ) Ou t pu t of dat a u sed by t h e ext ern al clock
Specifications
Th is program syn ch ron izes SCLK with th e extern al clock it
is assign ed to, an d sen ds th e con ten ts of th e gen eral
registers (A, B) to th e ou tside. Figu re 5.12.2 sh ows an
ou tpu t exam ple wh en th e m ask option h as been u sed to
select SCLK = positive logic, perm u tation = MSB first.
B register
A register
D3 D2 D1 D0
D3 D2 D1 D0
1
0
1
0
0
1
0
1
SIOF
Fig. 5.12.2
SCLK
SOUT
Example of output of serial
interface data
Program
ZK10
ZSDL
ZSC
EQU
EQU
EQU
077H
0F0H
0F2H
XSCTRG EQU
1000B
1100B
XSCS
;
EQU
LD
OR
X,ZSC
MX,XSCS
;Select SCS address by X register
;Set external clock mode
;
;
LD
LDPX
LD
X,ZSDL
MX,A
MX,B
;Select SD03 address by X register
;Write A register to SD0–SD3
;Write B register to SD4–SD7
LD
OR
X,ZK10
MX,XSCTRG
;Select SCTRG address by X register
;Shot SCTRG
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S1C62N33 TECHNICAL SOFTWARE
CHAPTER 5: PERIPHERAL CIRCUITS (Serial Interface)
(1) Wh en u sin g th e serial in terface in th e m aster m ode, th e
syn ch ron ou s clock u ses th e CPU system clock. Accord-
in gly, do n ot ch an ge th e system clock (fosc1 ↔ fosc3)
wh ile th e serial in terface is operatin g.
Prog ra m m ing note s
(2) Perform data writin g/ readin g to data registers SD0–SD7
on ly wh ile th e serial in terface is h alted (i.e., th e syn ch ro-
n ou s clock is n eith er bein g in pu t or ou tpu t).
(3) As a trigger con dition , it is requ ired th at data writin g or
readin g on data registers SD0–SD7 be perform ed prior to
writin g "1" to SCTRG. (Th e in tern al circu it of th e serial
in terface is in itiated th rou gh data writin g/ readin g on
data registers SD0–SD7.) Su pply trigger on ly on ce every
tim e th e serial in terface is placed in th e RUN state. More-
over, wh en th e syn ch ron ou s clock SCLK is extern al clock,
start to in pu t th e extern al clock after th e trigger.
(4) If th e bit data of SE2 ch an ges wh ile SCLK is in th e m aster
m ode, a h azard will be ou tpu t to th e SCLK pin . If th is
poses a problem for th e system , be su re to set th e SCLK
to th e extern al clock m ode if th e bit data of SE2 is to be
ch an ged.
(5) Readin g th e in terru pt factor flag (ISIO) can be don e on ly
in th e DI statu s (in terru pt flag = "0"). Readin g du rin g EI
statu s (in terru pt flag = "1") will cau se m alfu n ction .
(6) Writin g th e in terru pt m ask register (EISIO) can be don e
on ly in th e DI statu s (in terru pt flag = "0"). Writin g du rin g
EI statu s (in terru pt flag = "1") will cau se m alfu n ction .
(7) SCTRG resides in th e sam e bit at th e sam e address as
SIOF, an d on e or th e oth er is selected by write or read
operation . Wh en writin g a "1" to SCTRG u se th e OR
com m an d, an d wh en writin g a "0" u se th e AND com -
m an d. No oth er com m an ds sh ou ld be u sed for th is
pu rpose.
S1C62N33 TECHNICAL SOFTWARE
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II-109
CHAPTER 6: INITIAL RESET
CHAPTER 6
INITIAL RESET
In itial reset is requ ired to in itialize th e circu its in th e
S1C62N33 Series.
6.1 Inte rna l Sta tus a t Initia l Re se t
At in itial reset, th e CPU can be in itialized in th e followin g
ways.
Table 6.1.1
CPU Core
Signal Number of Bits Setting Value
Initial setting values (1)
Name
Program cou n ter step
Program cou n ter page
New page poin ter
Stack poin ter
PCS
PCP
NPP
SP
IX
IY
RP
A
8
4
4
8
9
9
4
4
4
1
1
1
1
00H
1H
1H
Un defin ed
Un defin ed
Un defin ed
Un defin ed
Un defin ed
Un defin ed
0
In dex register IX
In dex register IY
Register poin ter
Gen eral-pu rpose register A
Gen eral-pu rpose register B
In terru pt flag
B
I
Decim al flag
D
Un defin ed
Un defin ed
Un defin ed
Zero flag
Z
Carry flag
C
Fu rth er, data m em ory is in itialized as below.
Table 6.1.2
Peripheral Circuits
Initial setting values (2)
Name
Number of Bits Setting Value
RAM
256 × 4
40 × 4
–
Un defin ed
Un defin ed
*1
Segm en t data
Oth er periph eral circu it
*1 See "3.4 I/ O Mem ory Map".
Note Undefined setting values must be initialized by the program.
II-110
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S1C62N33 TECHNICAL SOFTWARE
CHAPTER 6: INITIAL RESET
6.2 Exa m p le of Initia lize Prog ra m
After in itial reset, an d th e CPU an d data m em ory are reset
as sh own on th e previou s page, th is program starts from
address 100H (reset vector).
Th en th e in itialize program 's label (INIT) is defin ed in th e
reset vector, an d th e program execu tes th e in itialize opera-
tion .
ORG
JP
100H
INIT
;Reset vector address
;Start program
Reset vector
;
Specifications
Th is program defin es th e bottom address of Stack poin ter,
clears RAM (in clu din g segm en t data) an d resets Flag grou p,
in th at order.
Table 6.2
Internal Circuit
Setting Value
Result of initializing
internal circuits
General-purpose register
A
0H
0A0H
0
Stack pointer
Interrupt flag
Decimal flag
Zero flag
SP
IF
DF
0
ZF
0
Carry flag
CF
0
RAM data
(000H–06FH)
(080H–09FH)
(100H–16FH)
(0C0H–0EFH)
0H
0H
0H
0H
Segment data
* Th e valu es for th e B, X an d Y registers are
u n defin ed.
S1C62N33 TECHNICAL SOFTWARE
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II-111
CHAPTER 6: INITIAL RESET
Program
INIT:
LD
LD
LD
LD
LD
LD
A,0
;
XP,A
A,0AH
SPH,A
A,0H
SPL,A
;Page 0 selected
;Set Stack pointer bottom as 0A0H
;
;
;
;
LD
X,00H
MX,0H
XH,7H
;Clear RAM area 000H–06FH
CLRLP1:LDPX
;
;
Clear MX, and increment X register
CP
Continue until X register become 70H
JP
C,CLRLP1 ;
;
LD
X,80H
MX,0H
XH,0FH
;Clear RAM area 080H–0EFH
CLRLP2:LDPX
;
;
Clear MX, and increment X register
Continue until X register becomes F0H
CP
JP
C,CLRLP2 ;
;
LD
A,1
;
LD
XP,A
;Page 1 selected
LD
X,00H
MX,0H
XH,7H
;Clear RAM area 100H–16FH
CLRLP3:LDPX
;
;
Clear MX, and increment X register
Continue until X register becomes 70H
CP
JP
C,CLRLP3 ;
;
RST
F,0000B ;Reset Flag group
Note
Th is program is th e basic in itialize program for th e
S1C62N33 Series. Wh en th is program is execu ted, th e
in tern al circu its are in itialized as sh own in Table 6.2. Wh en
u sin g th e program exam ple, be su re to add an y settin g item s
n ecessary for you r application s.
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S1C62N33 TECHNICAL SOFTWARE
CHAPTER 7: SUMMARY OF NOTES
CHAPTER 7
SUMMARY OF NOTES
– Program Memory
(1) To u se a bran ch in stru ction su ch as "J P" to bran ch
ou tside th e page of th at in stru ction , th e page to bran ch
to m u st first be set with th e "PSET" in stru ction ; th en th e
bran ch in stru ction can be execu ted. Be su re to execu te
th e bran ch in stru ction as th e step im m ediately followin g
"PSET".
(2) Im m ediately after th e "PSET" in stru ction m en tion ed in
above item (1), it will au tom atically be DI state u n til
execu tion of th e bran ch in stru ction is com pleted.
(3) Wh en m ovin g from th e last step of on e page to th e top
step of th e n ext page, th ere is n o n eed to execu te bran ch
in stru ction s su ch as "PSET" an d "J P".
(4) With ju st th e on e in stru ction "CALZ", su brou tin es on
page 0 can be called from an y page with ou t u sin g "PSET".
Program m in g can be don e efficien tly if u n iversal su brou -
tin es are located on page 0.
(5) If th e "PSET" in stru ction is execu ted im m ediately before
"CALZ", "CALZ" will h ave priority an d data set with
"PSET" will be ign ored.
(6) Th e program m em ory can be u sed as a data table
th rou gh th e table look-u p in stru ction .
– Data Memory
(1) Part of th e data m em ory is u sed as stack area for su brou -
tin e calls an d register storage, so be carefu l n ot to overlap
th e data area an d stack area.
(2) Su brou tin e calls an d in terru pts take u p th ree words of
th e stack area.
(3) Wh en addresses 40H–6FH h ave been allocated as seg-
m en t m em ory by option selection , 48 words of RAM can
be u sed as segm en t area.
(4) Mem ory is n ot m ou n ted in u n u sed area with in th e m em -
ory m ap an d in m em ory area n ot in dicated in th is m an -
u al. For th is reason , n orm al operation can n ot be assu red
for program s th at h ave been prepared with access to
th ese areas.
S1C62N33 TECHNICAL SOFTWARE
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II-113
CHAPTER 7: SUMMARY OF NOTES
– Interrupt and HALT
(1) Write to th e in terru pt m ask registers on ly in th e DI statu s
(in terru pt flag = "0"). Writin g in th e EI statu s can cau se
an error.
(2) Even wh en th e in terru pt m ask registers (ETI, EISWIT) are
set to "0", th e in terru pt factor flags (TI, SWIT) of th e clock
tim er an d stopwatch cou n ter can be set wh en th e tim in g
con dition s are establish ed.
(3) Wh en an in terru pt is gen erated, th ree words of RAM are
u sed; also, it takes 12 cycles of th e CPU system clock
u n til th e valu e of th e in terru pt vector is set in th e pro-
gram cou n ter.
(4) Wh en an in terru pt occu rs, th e DI statu s (in terru pt flag =
"0") com es in to effect au tom atically.
(5) Read th e in terru pt factor flags on ly in th e DI statu s
(in terru pt flag = "0"). Readin g ou t in th e EI statu s can
cau se an error.
– Watchdog Timer
Wh en th e watch dog tim er is u sed for th e reset fu n ction , th e
software m u st reset th e watch dog tim er with in 3 secon ds.
In th is case, tim er data (WD0–WD2) can n ot be u sed for
tim er application s.
– OSC3
(1) It takes at least 5 m s from th e tim e th e OSC3 oscillation
circu it goes ON u n til th e oscillation stabilizes. Con se-
qu en tly, wh en switch in g th e CPU operation clock from
OSC1 to OSC3, do th is after a m in im u m of 5 m s h ave
elapsed sin ce th e OSC3 oscillation wen t ON.
Fu rth er, th e oscillation stabilization tim e varies depen d-
in g on th e extern al oscillator ch aracteristics an d con di-
tion s of u se, so allow am ple m argin wh en settin g th e wait
tim e.
(2) Wh en switch in g th e clock from OSC3 to OSC1, u se a
separate in stru ction for switch in g th e OSC3 oscillation
OFF.
(3) To lessen cu rren t con su m ption , keep OSC3 oscillation
OFF except wh en th e CPU m u st be ru n at h igh speed.
Also, with S1C62N33/ 62L33, keep OSCC fixed to "0".
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S1C62N33 TECHNICAL SOFTWARE
CHAPTER 7: SUMMARY OF NOTES
– SVD Circuit and Heavy (1) It takes 100 µs from th e tim e th e SVD circu it goes ON
Load Protection
Functions
u n til a stable resu lt is obtain ed. For th is reason , keep
th e followin g software n otes in m in d:
➀ Wh en th e CPU system clock is fosc1
1. Wh en detection is don e at HVLD
After writin g "1" on HVLD, read th e SVDDT after 1
in stru ction h as passed.
2. Wh en detection is don e at SVDON
After writin g "1" on SVDON, write "0" after at least
100 µs h as lapsed (possible with th e n ext in stru c-
tion ) an d th en read th e SVDDT.
➀ Wh en th e CPU system clock is fosc3 (in case of
S1C62A33 on ly)
1. Wh en detection is don e at HVLD
After writin g "1" on HVLD, read th e SVDDT after
0.6 sec h as passed. (HVLD h olds "1" for at least 0.6
sec)
2. Wh en detection is don e at SVDON
Before writin g "1" on SVDON, write "1" on HVLD
first; after at least 100 µs h as lapsed after writin g
"1" on SVDON, write "0" on SVDON an d th en read
th e SVDDT.
(2) To redu ce cu rren t con su m ption , set th e SVD operation to
OFF u n less oth erwise n ecessary.
(3) SVDON resides in th e sam e bit at th e sam e address as
SVDDT, an d on e or th e oth er is selected by write or read
operation . Wh en writin g a "1" to SVDON u se th e OR
com m an d, an d wh en writin g a "0" u se th e AND com -
m an d. No oth er com m an ds sh ou ld be u sed for th is pu r-
pose.
(4) Select on e of th e followin g software processin g to retu rn
to th e n orm al m ode after a h eavy load h as been driven in
th e h eavy load protection m ode (S1C62L33).
➀ After h eavy load drive is com pleted, retu rn to th e
n orm al m ode after at least on e secon d h as elapsed.
➀ After h eavy load drive is com pleted, switch SVD ON
an d OFF (at least 100 µs is n ecessary for th e ON
statu s) an d th en retu rn to th e n orm al m ode.
S1C62N33 TECHNICAL SOFTWARE
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CHAPTER 7: SUMMARY OF NOTES
(5) To redu ce cu rren t con su m ption , be carefu l n ot to set th e
h eavy load protection m ode with th e software u n less
oth erwise n ecessary.
– Output Ports
Wh en BZ h as been selected by th e ou tpu t application for pin
R13, th e m ask option decides wh eth er ou tpu t is con trolled
by register R13, or by register R10 sim u ltan eou sly with BZ.
In particu lar, wh en BZ ou tpu t is u n der R10 con trol, register
R13 can be u sed as a 1-bit gen eral register for read/ write.
Data in th is register h as n o affect on BZ ou tpu t (ou tpu t of
pin R13).
– LCD Driver
(1) Wh en 40H–6FH is selected for th e segm en t data m em ory,
th e m em ory data an d th e display will n ot m atch u n til th e
area is in itialized (th rou gh , for in stan ce, m em ory clear
processin g by th e CPU).
In itialize th e segm en t data m em ory by execu tin g in itial
processin g.
(2) Wh en C0H–EFH is selected for th e segm en t data m em ory,
th at area becom es write-on ly. Con sequ en tly, data can n ot
be rewritten by arith m etic operation s (su ch as AND, OR,
ADD, SUB).
(3) Data ou tpu t from segm en t pin s selected as DC ou tpu t
will be th e data correspon din g to th e COM0 pin s.
(4) Wh en perform in g step adju stm en t with th e static drive,
set th e segm en t data so th at all LCD segm en ts are lit.
– Clock Timer
(1) Wh en th e clock tim er h as been reset, th e in terru pt factor
flag (TI) m ay som etim es be set to "1". Con sequ en tly,
perform flag read-ou t (reset th e flag) wh en n ecessary at
reset.
(2) Th e watch dog tim er m ay be cou n ted u p at clock tim er
reset.
(3) Resettin g th e clock tim er h as n o effect on th e stopwatch
cou n ter, an d vice versa.
(4) Writin g to th e in terru pt m ask register (ETI) can be don e
on ly in th e DI statu s (in terru pt flag = "0"). Writin g du rin g
EI statu s will cau se an error.
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S1C62N33 TECHNICAL SOFTWARE
CHAPTER 7: SUMMARY OF NOTES
(5) Read ou t th e in terru pt flag (TI) on ly du rin g th e DI statu s
(in terru pt flag = "0"). Read-ou t du rin g EI statu s will
cau se an error.
(6) Regardless of th e settin g of th e in terru pt m ask register
(ETI), th e in terru pt factor flag (TI) is set to "1" at th e
fallin g edge of th e correspon din g sign al.
– Input Ports
(1) Wh en in pu t ports are ch an ged from h igh to low by pu ll-
down resistor, th e fall of th e waveform is delayed on
accou n t of th e tim e con stan t of th e pu ll-down resistan ce
an d in pu t gate capacitan ce. Hen ce, wh en fetch in g in pu t
ports, set an appropriate wait tim e.
Particu lar care n eeds to be taken of th e key scan du rin g
key m atrix con figu ration . Aim for a wait tim e of abou t 1
m s.
(2) Writin g to th e in terru pt m ask registers (EIK) can be don e
on ly in th e DI statu s (in terru pt flag = "0"). Writin g du rin g
EI statu s can cau se an error.
(3) Wh en "n oise rejector circu it en able" is selected with th e
m ask option , a m axim u m delay of 1 m s occu rs from th e
tim e th e in terru pt con dition s are establish ed u n til th e
in terru pt factor flag (IK) is set to "1" (u n til th e in terru pt is
actu ally gen erated).
Hen ce, pay atten tion to th e tim in g wh en readin g ou t
(resettin g) th e in terru pt factor flag.
(4) In pu t in terru pt program in g related precau tion s
Port K input
Active status
Active status
Differential register
Mask register
Falling edge interrupt
Rising edge interrupt
➀
Factor flag set Not set
➀
Factor flag set
When the content of the mask register is rewritten, while the port K
input is in the active status. The input interrupt factor flags are set at
➀ and ➀, ➀ being the interrupt due to the falling edge and ➀ the
interrupt due to the rising edge.
Fig. 7.1
Input interrupt timing
S1C62N33 TECHNICAL SOFTWARE
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CHAPTER 7: SUMMARY OF NOTES
Wh en u sin g an in pu t in terru pt, if you rewrite th e con ten t
of th e m ask register, wh en th e valu e of th e in pu t term in al
wh ich becom es th e in terru pt in pu t is in th e active statu s,
th e factor flag for in pu t in terru pt m ay be set. Th erefore,
wh en u sin g th e in pu t in terru pt, th e active statu s of th e
in pu t term in al im plies
in pu t term in al = low statu s, wh en th e fallin g edge
in terru pt is effected an d
in pu t term in al = h igh statu s, wh en th e risin g edge
in terru pt is effected.
Wh en an in terru pt is triggered at th e fallin g edge of an
in pu t term in al, a factor flag is set with th e tim in g of ➀
sh own in Figu re 7.1. However, wh en clearin g th e con ten t
of th e m ask register with th e in pu t term in al kept in th e
low statu s an d th en settin g it, th e factor flag of th e in pu t
in terru pt is again set at th e tim in g th at h as been set.
Con sequ en tly, wh en th e in pu t term in al is in th e active
statu s (low statu s), do n ot rewrite th e m ask register
(clearin g, th en settin g th e m ask register), so th at a factor
flag will on ly set at th e fallin g edge in th is case. Wh en
clearin g, th en settin g th e m ask register, set th e m ask
register, wh en th e in pu t term in al is n ot in th e active
statu s (h igh statu s).
Wh en an in terru pt is triggered at th e risin g edge of th e
in pu t term in al, a factor flag will be set at th e tim in g of ➀
sh own in Figu re 7.1. In th is case, wh en th e m ask regis-
ters cleared, th en set, you sh ou ld set th e m ask register,
wh en th e in pu t term in al is in th e low statu s.
In addition , wh en th e m ask register = "1" an d th e con ten t
of th e differen tial register is rewritten in th e in pu t term i-
n al active statu s, an in pu t in terru pt factor flag m ay be
set. Th u s, you sh ou ld rewrite th e con ten t of th e differen -
tial register in th e m ask register = "0" statu s.
(5) Read ou t th e in terru pt factor flag (IK) on ly in th e DI
statu s (in terru pt flag = "0"). Read-ou t du rin g EI statu s
can cau se an error.
(6) Even wh en th e valu es of th e in pu t data an d differen tial
register ch an ges from n on -m atch in g to m atch in g, th e
in terru pt factor flag is n ot set to "1".
II-118
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S1C62N33 TECHNICAL SOFTWARE
CHAPTER 7: SUMMARY OF NOTES
– I/O Ports
(1) Wh en th e I/ O port is bein g read ou t an d th e pu ll-down is
execu ted on ly with th e bu ilt-in pu ll-down resistor of th e
I/ O ports, th e read-ou t m u st be repeated abou t ten tim es
wh en th e CPU is operatin g with th e OSC3 oscillation
circu it.
(2) Wh en th e I/ O port is set to th e ou tpu t m ode an d th e data
register h as been read, th e pin data in stead of th e regis-
ter data can be read ou t. Becau se of th is, if a low-im ped-
an ce load is con n ected an d read-ou t perform ed, th e valu e
of th e register an d th e read-ou t resu lt m ay differ.
– Stopwatch Counter
(1) Correct read-ou t is im possible wh en th ere is a carry from
th e low order bit (SWL) to th e h igh order bit (SWH).
Hen ce, wh en readin g ou t th e cou n ter data in th e RUN
statu s, th e cou n ter m u st first be stopped, an d th en th e
RUN statu s retu rn ed again .
Also, th e du ration of th e above STOP statu s m u st be
with in 976 µs (256 Hz 1/ 4 cycle).
(2) Resettin g th e clock tim er h as n o effect on th e stopwatch
cou n ter, an d vice versa.
(3) Writin g to th e in terru pt m ask registers (EISWIT) can be
don e on ly in th e DI statu s (in terru pt flag = "0"). Writin g
du rin g EI statu s will cau se an error.
Also, wh en u sin g arith m etic in stru ction s (AND, OR, ADD,
SUB, etc.), pay atten tion to th e con trol of SVD.
(4) Read ou t of th e in terru pt factor flag (SWIT) m u st be don e
on ly in th e DI statu s (in terru pt flag = "0"). Read-ou t
du rin g EI statu s will cau se an error.
(5) Regardless of th e settin g of th e m ask register (EISWIT),
th e in terru pt factor flag (SWIT) is set to "1" wh en th e
correspon din g cou n ter overflows.
– Event Counter
To preven t erron eou s readin g of th e even t cou n ter data, read
ou t th e cou n ter data m u ltiple tim es for com parison , an d u se
th e m atch in g data for th e resu lt.
S1C62N33 TECHNICAL SOFTWARE
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CHAPTER 7: SUMMARY OF NOTES
– Analog Comparator
(1) To keep th e cu rren t con su m ption low, set th e an alog
com parator to OFF wh en it is n ot n eeded.
(2) After AMPON is set to "1", allow a wait of at least 5 m s for
th e an alog com parator's operation to stabilize before
readin g ou t th e an alog com parator's ou tpu t data AMPDT.
– Serial Interface
(1) Wh en u sin g th e serial in terface in th e m aster m ode, th e
syn ch ron ou s clock u ses th e CPU system clock. Accord-
in gly, do n ot ch an ge th e system clock (fosc1 ↔ fosc3)
wh ile th e serial in terface is operatin g.
(2) Perform data writin g/ readin g to data registers SD0–SD7
on ly wh ile th e serial in terface is h alted (i.e., th e syn ch ro-
n ou s clock is n eith er bein g in pu t or ou tpu t).
(3) As a trigger con dition , it is requ ired th at data writin g or
readin g on data registers SD0–SD7 be perform ed prior to
writin g "1" to SCTRG. (Th e in tern al circu it of th e serial
in terface is in itiated th rou gh data writin g/ readin g on
data registers SD0–SD7.) Su pply trigger on ly on ce every
tim e th e serial in terface is placed in th e RUN state.
Moreover, wh en th e syn ch ron ou s clock SCLK is extern al
clock, start to in pu t th e extern al clock after th e trigger.
(4) If th e bit data of SE2 ch an ges wh ile SCLK is in th e m as-
ter m ode, a h azard will be ou tpu t to th e SCLK pin . If th is
poses a problem for th e system , be su re to set th e SCLK
to th e extern al clock m ode if th e bit data of SE2 is to be
ch an ged.
(5) Readin g th e in terru pt factor flag (ISIO) can be don e on ly
in th e DI statu s (in terru pt flag = "0"). Readin g du rin g EI
statu s (in terru pt flag = "1") will cau se m alfu n ction .
(6) Writin g th e in terru pt m ask register (EISIO) can be don e
on ly in th e DI statu s (in terru pt flag = "0"). Writin g du rin g
EI statu s (in terru pt flag = "1") will cau se m alfu n ction .
(7) SCTRG resides in th e sam e bit at th e sam e address as
SIOF, an d on e or th e oth er is selected by write or read
operation . Wh en writin g a "1" to SCTRG u se th e OR
com m an d, an d wh en writin g a "0" u se th e AND com -
m an d. No oth er com m an ds sh ou ld be u sed for th is
pu rpose.
II-120
EPSON
S1C62N33 TECHNICAL SOFTWARE
CHAPTER 8: CPU
CHAPTER 8
CPU
Th e S1C62N33 Series em ploys th e fou r-bit core CPU
S1C6200 for th e CPU, so th at register con figu ration , in -
stru ction s an d so forth are virtu ally iden tical to th ose in
oth er fam ily processors u sin g th e S1C6200.
Refer to "S1C6200/ 6200A Core CPU Man u al" for details
abou t th e S1C6200.
8.1
S1C62N33 Re stric tions
Note th e followin g poin ts with regard to th e S1C62N33
Series:
(1) Th e SLEEP operation is n ot assu m ed, so th at SLP in -
stru ction can n ot be u sed.
(2) Becau se th e ROM capacity is 3,072 words, ban k bits are
u n n ecessary an d PCB an d NBP are n ot u sed.
(3) Sin ce RAM is set for u p to 1 page, on ly th e su bordin ate 1
bit of th e page section of th e in dex register wh ich speci-
fies address is effective. (Th e 3 su perordin ate bits are
ign ored.)
8.2
Instruc tion Se t
Th e S1C62N33 Series h as som e 108 types of in stru ction s
in clu din g arith m etical in stru ction s.
All in stru ction s con sist of on e word (= 12 bits).
Th e followin g pages con tain tables of th e in stru ction set of
th e 4-bit Core CPU, S1C6200.
S1C62N33 TECHNICAL SOFTWARE
EPSON
II-121
CHAPTER 8: CPU
Table 8.2(a) Instruction set (1)
Operation Code
Flag
Mne-
monic
Classification
Operand
Clock
Operation
B
1
0
0
0
0
0
1
0
A
1
0
0
0
1
1
1
1
9
1
0
1
1
1
1
1
0
8
7
6
5
4
3
2
1
0
I D Z C
Branch
PSET
p
0
0
1
0 p4 p3 p2 p1 p0
5
5
5
5
5
5
5
7
NBP ←p4, NPP←p3~p0
instructions JP
s
0 s7 s6 s5 s4 s3 s2 s1 s0
0 s7 s6 s5 s4 s3 s2 s1 s0
1 s7 s6 s5 s4 s3 s2 s1 s0
0 s7 s6 s5 s4 s3 s2 s1 s0
1 s7 s6 s5 s4 s3 s2 s1 s0
PCB ←NBP, PCP←NPP, PCS ←s7~s0
PCB ←NBP, PCP←NPP, PCS ←s7~s0 if C=1
PCB ←NBP, PCP←NPP, PCS ←s7~s0 if C=0
PCB ←NBP, PCP←NPP, PCS ←s7~s0 if Z=1
PCB ←NBP, PCP←NPP, PCS ←s7~s0 if Z=0
PCB ←NBP, PCP←NPP, PCSH ←B, PCSL ←A
M(SP-1) ←PCP, M(SP-2) ←PCSH, M(SP-3) ←PCSL+1
SP←SP-3, PCP←NPP, PCS ←s7~s0
C, s
NC, s
Z, s
NZ, s
JPBA
1 1 1 1 0 1 0 0 0
CALL
CALZ
RET
s
s
0 s7 s6 s5 s4 s3 s2 s1 s0
0
1
1
0
1
1
1
0
0
1
1
0
1 s7 s6 s5 s4 s3 s2 s1 s0
7
7
M(SP-1) ←PCP, M(SP-2) ←PCSH, M(SP-3)← PCSL+1
SP←SP-3, PCP ←0, PCS ←s7~s0
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
0
PCSL← M(SP), PCSH←M(SP+1), PCP ←M(SP+2)
SP ←SP+3
RETS
RETD
12 PCSL←M(SP), PCSH←M(SP+1), PCP← M(SP+2)
SP← SP+3, PC← PC+1
l
1 l 7 l 6 l 5 l 4 l 3 l 2 l 1 l 0
12 PCSL ←M(SP), PCSH←M(SP+1), PCP← M(SP+2)
SP← SP+3, M(X) ← l3~l0, M(X+1)← l 7~l 4, X ←X+2
System
control
NOP5
NOP7
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
0
0
0
1
0
0
0
1
1
0
0
0
1
1
0
0
0
5
7
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
7
7
7
7
No operation (5 clock cycles)
No operation (7 clock cycles)
Halt (stop clock)
X← X+1
instructions HALT
Index
INC
X
operation
Y
Y← Y+1
instructions LD
X, x
1 x7 x6 x5 x4 x3 x2 x1 x0
0 y7 y6 y5 y4 y3 y2 y1 y0
XH← x7~x4, XL ←x3~x0
YH← y7~y4, YL ←y3~y0
XP ←r
Y, y
XP, r
XH, r
XL, r
YP, r
YH, r
YL, r
r, XP
r, XH
r, XL
r, YP
r, YH
r, YL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
1
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0 r1 r0
1 r1 r0
0 r1 r0
0 r1 r0
1 r1 r0
0 r1 r0
0 r1 r0
1 r1 r0
0 r1 r0
0 r1 r0
1 r1 r0
0 r1 r0
XH←r
XL←r
YP ←r
YH←r
YL←r
r ←XP
r ←XH
r ←XL
r ←YP
r ←YH
r ←YL
ADC XH, i
XL, i
i3 i2 i1 i0
i3 i2 i1 i0
i3 i2 i1 i0
i3 i2 i1 i0
↑ ↑
↓ ↓
XH←XH+i3~i0+C
XL←XL+i3~i0+C
YH←YH+i3~i0+C
YL←YL+i3~i0+C
↑ ↑
↓ ↓
YH, i
↑ ↑
↓ ↓
YL, i
↑ ↑
↓ ↓
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S1C62N33 TECHNICAL SOFTWARE
CHAPTER 8: CPU
Table 8.2(b) Instruction set (2)
Operation Code
Flag
Mne-
monic
Classification
Operand
Clock
Operation
B
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
9
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
8
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
7
0
0
0
0
0
1
1
1
1
1
0
1
0
1
6
1
1
1
1
5
0
0
1
1
4
0
1
0
1
3
2
1
0
I D Z C
Index
CP
XH, i
XL, i
YH, i
YL, i
r, i
i3 i2 i1 i0
i3 i2 i1 i0
i3 i2 i1 i0
i3 i2 i1 i0
↑ ↑
↓ ↓
7
7
7
7
5
5
5
5
5
5
5
5
5
5
5
7
7
7
7
7
7
7
7
7
7
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
XH-i3~i0
operation
instructions
↑ ↑
↓ ↓
XL-i3~i0
↑ ↑
↓ ↓
YH-i3~i0
↑ ↑
↓ ↓
YL-i3~i0
Data
LD
0 r1 r0 i3 i2 i1 i0
r ←i3~i0
transfer
instructions
r, q
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
1
0 r1 r0 q1 q0
0 n3 n2 n1 n0
1 n3 n2 n1 n0
0 n3 n2 n1 n0
1 n3 n2 n1 n0
r ←q
A, Mn
B, Mn
Mn, A
Mn, B
A← M(n3~n0)
B← M(n3~n0)
M(n3~n0)←A
M(n3~n0)←B
LDPX MX, i
r, q
0
i3 i2 i1 i0
0 r1 r0 q1 q0
i3 i2 i1 i0
1 r1 r0 q1 q0
M(X)←i3~i0, X← X+1
r←q, X←X+1
LDPY MY, i
r, q
1
M(Y) ←i3~i0, Y ←Y+1
r ←q, Y←Y+1
LBPX MX,l
l 7 l 6 l 5 l 4 l 3 l 2 l 1 l 0
M(X) ← l3~ l0, M(X+1)← l 7~l4, X←X+2
F←F i3~i0
Flag
SET
RST
F, i
F, i
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
i3 i2 i1 i0 ↑ ↑ ↑ ↑
i3 i2 i1 i0 ↓ ↓ ↓ ↓
operation
F←F i3~i0
instructions SCF
0
1
0
1
0
1
1
0
1
1
0
0
0
0
0
1
1
1
0
0
0
0
0
0
1
0
1
1
0
0
1
0
0
0
1
1
0
0
1
0
1
1
1
1
0
0
1
0
1
0
1
1
1
↑
↓
C←1
RCF
SZF
RZF
SDF
RDF
EI
C←0
↑
↓
Z←1
Z←0
↑
↓
D←1 (Decimal Adjuster ON)
D←0 (Decimal Adjuster OFF)
I ←1 (Enables Interrupt)
I ←0 (Disables Interrupt)
SP← SP+1
↑
↓
DI
Stack
INC
SP
operation
DEC SP
SP← SP-1
instructions PUSH
r
0 r1 r0
SP← SP-1, M(SP)←r
SP← SP-1, M(SP)←XP
SP← SP-1, M(SP)←XH
SP← SP-1, M(SP)←XL
SP← SP-1, M(SP)←YP
SP← SP-1, M(SP)←YH
SP← SP-1, M(SP)←YL
SP← SP-1, M(SP)←F
r ←M(SP), SP←SP+1
XP← M(SP), SP← SP+1
XH← M(SP), SP← SP+1
XL← M(SP), SP← SP+1
YP← M(SP), SP← SP+1
XP
XH
XL
YP
YH
YL
F
1
1
1
1
0
0
0
0
0
1
1
0
0
1
0
1
0
1
0
1
0
POP
r
0 r1 r0
XP
XH
XL
YP
1
1
1
1
0
0
1
1
0
1
0
1
S1C62N33 TECHNICAL SOFTWARE
EPSON
II-123
CHAPTER 8: CPU
Table 8.2(c) Instruction set (3)
Operation Code
Flag
Mne-
monic
Classification
Operand
Clock
Operation
B
1
1
1
A
1
1
1
1
1
1
1
1
0
1
0
0
1
0
1
0
1
0
1
0
1
1
1
1
0
1
1
1
1
1
1
1
1
9
1
1
1
1
1
1
1
0
1
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
0
8
1
1
1
1
1
1
1
0
0
0
0
0
1
0
0
0
0
0
1
0
1
1
1
1
0
0
1
1
1
1
1
1
1
7
1
1
1
1
1
1
1
0
1
0
1
1
0
1
1
1
1
1
0
1
1
0
1
0
1
1
0
0
0
0
0
0
0
6
1
1
1
1
1
1
1
5
0
0
0
1
1
1
1
4
1
1
1
0
1
0
1
3
1
1
1
0
0
0
0
2
0
0
0
1
0
0
1
0
0
1
0
I D Z C
Stack
POP
YH
YL
F
5
5
5
5
5
5
5
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
5
7
7
7
7
7
7
7
YH← M(SP), SP← SP+1
operation
instructions
YL← M(SP), SP← SP+1
F←M(SP), SP←SP+1
SPH← r
↑ ↑ ↑ ↑
↓ ↓ ↓ ↓
LD
SPH, r 1
SPL, r
r, SPH 1
r, SPL
Arithmetic ADD r, i
0 r1 r0
0 r1 r0
1 r1 r0
1 r1 r0
1
SPL ← r
r← SPH
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
r← SPL
0 r1 r0 i3 i2 i1 i0
ꢀ ↑ ↑
↓ ↓
r← r+i3~i0
r← r+q
instructions
r, q
ADC r, i
r, q
0 0 0 r1 r0 q1 q0 ꢀ ↑ ↑
↓ ↓
1 r1 r0 i3 i2 i1 i0
ꢀ ↑ ↑
↓ ↓
r← r+i3~i0+C
r← r+q+C
0
0
0
1
1 r1 r0 q1 q0 ꢀ ↑ ↑
↓ ↓
SUB r, q
0 r1 r0 q1 q0 ꢀ ↑ ↑
r← r-q
↓ ↓
SBC
r, i
1 r1 r0 i3 i2 i1 i0
ꢀ ↑ ↑
↓ ↓
r← r-i3~i0-C
r← r-q-C
r, q
0 1 1 r1 r0 q1 q0 ꢀ ↑ ↑
↓ ↓
AND r, i
r, q
0 r1 r0 i3 i2 i1 i0
0 r1 r0 q1 q0
1 r1 r0 i3 i2 i1 i0
1 r1 r0 q1 q0
0 r1 r0 i3 i2 i1 i0
0 r1 r0 q1 q0
1 r1 r0 i3 i2 i1 i0
0 r1 r0 q1 q0
0 r1 r0 i3 i2 i1 i0
↑
↓
r← r i3~i0
1
0
↑
↓
r← r
r← r i3~i0
r← r
r← r i3~i0
r← r
q
OR
r, i
↑
↓
r, q
1
0
↑
↓
q
XOR r, i
r, q
↑
↓
1
1
↑
↓
q
CP
r, i
↑ ↑
↓ ↓
r-i3~i0
r-q
r, q
0
0
↑ ↑
↓ ↓
FAN r, i
r, q
↑
↓
r
r
i3~i0
q
0
1
0
1
1
0
0
0
0
0
1
0
1
1
1
1
1
1
1 r1 r0 q1 q0
1 r1 r0 r1 r0
↑
↓
RLC
RRC
INC
r
↑ ↑
↓ ↓
d3 ←d2, d2 ←d1, d1 ←d0, d0 ←C, C← d3
d3 ←C, d2 ←d3, d1 ←d2, d0 ←d1, C← d0
M(n3~n0) ←M(n3~n0)+1
r
0
1
1 r1 r0
↑ ↑
↓ ↓
Mn
0 n3 n2 n1 n0
1 n3 n2 n1 n0
↑ ↑
↓ ↓
DEC Mn
↑ ↑
↓ ↓
M(n3~n0) ←M(n3~n0)-1
ACPX MX, r
ACPY MY, r
SCPX MX, r
SCPY MY, r
0
0
1
1
1
1
1
1
0 r1 r0
1 r1 r0
0 r1 r0
1 r1 r0
ꢀ ↑ ↑
↓ ↓
M(X) ←M(X)+r+C, X ←X+1
M(Y) ←M(Y)+r+C, Y ←Y+1
M(X) ←M(X)-r-C, X← X+1
M(Y) ←M(Y)-r-C, Y← Y+1
r ←r
ꢀ ↑ ↑
↓ ↓
ꢀ ↑ ↑
↓ ↓
ꢀ ↑ ↑
↓ ↓
NOT
r
0 r1 r0 1
1
1
1
↑
↓
II-124
EPSON
S1C62N33 TECHNICAL SOFTWARE
CHAPTER 8: CPU
Abbreviation s u sed in th e explan ation s h ave th e followin g
m ean in gs.
A .............. A register
B .............. B register
Symbols associated with
registers and memory
X .............. XHL register (low order eigh t bits of in dex register
IX)
Y .............. YHL register (low order eigh t bits of in dex
register IY)
XH ........... XH register (h igh order fou r bits of XHL register)
XL ............ XL register (low order fou r bits of XHL register)
YH ............ YH register (h igh order fou r bits of YHL register)
YL ............ YL register (low order fou r bits of YHL register)
XP ............ XP register (h igh order fou r bits of in dex
register IX)
YP ............ YP register (h igh order fou r bits of in dex
register IY)
SP ............ Stack poin ter SP
SPH .......... High -order fou r bits of stack poin ter SP
SPL .......... Low-order fou r bits of stack poin ter SP
MX, M(X) .. Data m em ory wh ose address is specified with
in dex register IX
MY, M(Y)... Data m em ory wh ose address is specified with
in dex register IY
Mn , M(n ) .. Data m em ory address 000H–00FH (address
specified with im m ediate data n of 00H–0FH)
M(SP) ....... Data m em ory wh ose address is specified with
stack poin ter SP
r, q ........... Two-bit register code
r, q is two-bit im m ediate data; accordin g to th e
con ten ts of th ese bits, th ey in dicate registers A,
B, an d MX an d MY (data m em ory wh ose ad-
dresses are specified with in dex registers IX an d
IY)
r
q
Registers specified
r1
0
r0
0
q1
0
q0
0
A
B
0
1
0
1
1
0
1
0
MX
MY
1
1
1
1
S1C62N33 TECHNICAL SOFTWARE
EPSON
II-125
CHAPTER 8: CPU
Symbols associated with NBP ..... New ban k poin ter
program counter NPP ..... New page poin ter
PCB ..... Program cou n ter ban k
PCP ..... Program cou n ter page
PCS ..... Program cou n ter step
PCSH .. Fou r h igh order bits of PCS
PCSL ... Fou r low order bits of PCS
Symbols associated with
flags
F ......... Flag register (I, D, Z, C)
C ......... Carry flag
Z ......... Zero flag
D ......... Decim al flag
I .......... In terru pt flag
↓ ............. Flag reset
↑ ............. Flag set
ꢀ .......... Flag set or reset
Associated with p ......... Five-bit im m ediate data or label 00H–1FH
immediate data s .......... Eigh t-bit im m ediate data or label 00H–0FFH
l .......... Eigh t-bit im m ediate data 00H–0FFH
i .......... Fou r-bit im m ediate data 00H–0FH
Associated with
arithmetic and other
operations
+ ......... Add
- .......... Su btract
............. Logical AND
............. Logical OR
............ Exclu sive-OR
ꢀ......... Add-su btract in stru ction for decim al operation
wh en th e D flag is set
II-126
EPSON
S1C62N33 TECHNICAL SOFTWARE
APPENDIX
APPENDIX
• Table of cross assem bler pseu do-in st ru ct ion s
Item No. Pseudo-instruction
Meaning
Example of Use
1
2
3
4
5
EQU
(Equation)
To allocate data to label
ABC
BCD
ORG
ORG
ABC
ABC
ABC
BCD
EQU
EQU
100H
256
9
ABC+1
ORG
(Origin)
To define location counter
SET
(Set)
To allocate data to label
(data can be changed)
SET
0001H
0002H
'AB'
SET
DW
(Define word)
To define ROM data
DW
DW
0FFBH
1H
PAGE
(Page)
To define boundary of page
PAGE
PAGE
SECTION
11
6
7
8
9
SECTION
(Section)
To define boundary of section
To terminate assembly
To define macro
END
(End)
END
MACRO
(Macro)
CHECK
1
LOCAL
(Local)
To make local specification of
label during macro definition
CHECK MACRO DATA
LOCAL LOOP
LOOP
CP
JP
MX,DATA
NZ,LOOP
10
ENDM
To end macro definition
(End Macro)
ENDM
S1C62N33 TECHNICAL SOFTWARE
EPSON
II-127
APPENDIX
• Table of ICE com m an ds
Item No.
Function
Command Format
Outline of Operation
Assemble command mnemonic code and store at address "a"
Contents of addresses a1 to a2 are disassembled and displayed
Contents of program area a1 to a2 are displayed
Content of data area a1 to a2 are displayed
Data d is set in addresses a1 to a2 (program area)
Data d is set in addresses a1 to a2 (data area)
Program is executed from the "a" address
Execution time and step counter selection
On-the-fly display selection
1
2
3
Assemble
Disassemble #L,a1,a2
Dump
Fill
#A,a
#DP,a1,a2
#DD,a1,a2
#FP,a1,a2,d
#FD,a1,a2,d
#G,a
4
5
Set
Run Mode
#TIM
#OTF
6
7
Trace
Break
#T,a,n
Executes program while displaying results of step instruction
from "a" address
Displays only the final step of #T,a,n
Sets Break at program address "a"
Breakpoint is canceled
Break condition is set for data RAM
Breakpoint is canceled
Break condition is set for Evaluation Board CPU internal registers
Breakpoint is canceled
Combined break conditions set for program data RAM address
and registers
#U,a,n
#BA,a
#BAR,a
#BD
#BDR
#BR
#BRR
#BM
#BMR
Cancel combined break conditions for program data ROM
address and registers
#BRES
All break conditions canceled
#BC
Break condition displayed
#BE
Enter break enable mode
#BSYN
#BT
Enter break disable mode
Set break stop/trace modes
#BRKSEL,REM
#MP,a1,a2,a3
Set BA condition clear/remain modes
Contents of program area addresses a1 to a2 are moved to
addresses a3 and after
8
Move
#MD,a1,a2,a3
Contents of data area addresses a1 to a2 are moved to addresses
a3 and after
9
Data Set
#SP,a
#SD,a
Data from program area address "a" are written to memory
Data from data area address "a" are written to memory
Display Evaluation Board CPU internal registers
Set Evaluation Board CPU internal registers
Reset Evaluation Board CPU
10
Change CPU #DR
Internal
Registers
#SR
#I
#DXY
#SXY
Display X, Y, MX and MY
Set data for X and Y display and MX, MY
II-128
EPSON
S1C62N33 TECHNICAL SOFTWARE
APPENDIX
Item No.
Function
Command Format
Outline of Operation
Display history data for pointer 1 and pointer 2
Display upstream history data
11
History
#H,p1,p2
#HB
#HG
Display 21 line history data
#HP
Display history pointer
#HPS,a
#HC,S/C/E
Set history pointer
Sets up the history information acquisition before (S),
before/after (C) and after (E)
#HA,a1,a2
Sets up the history information acquisition from program area
a1 to a2
#HAR,a1,a2
Sets up the prohibition of the history information acquisition
from program area a1 to a2
#HAD
#HS,a
Indicates history acquisition program area
Retrieves and indicates the history information which executed
a program address "a"
#HSW,a
#HSR,a
#RF,file
#RFD,file
#VF,file
#VFD,file
#WF,file
#WFD,file
#CL,file
#CS,file
#CVD
Retrieves and indicates the history information which wrote or
read the data area address "a"
Move program file to memory
12
File
Move data file to memory
Compare program file and contents of memory
Compare data file and contents of memory
Save contents of memory to program file
Save contents of memory to data file
Load ICE set condition from file
Save ICE set condition to file
Indicates coverage information
Clears coverage information
13
14
Coverage
#CVR
ROM Access #RP
#VP
Move contents of ROM to program memory
Compare contents of ROM with contents of program memory
Set ROM type
#ROM
#Q
15
16
17
Terminate
ICE
Command
Display
Self
Terminate ICE and return to operating system control
#HELP
#CHK
Display ICE instruction
Report results of ICE self diagnostic test
Diagnosis
means press the RETURN key.
S1C62N33 TECHNICAL SOFTWARE
EPSON
II-129
International Sales Operations
AMERICA
ASIA
EPSON ELECTRONICS AMERICA, INC.
EPSON (CHINA) CO., LTD.
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Phone: 02-2717-7360
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Phone: 02-784-6027
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SALES OFFICE
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Phone: +49-(0)2171-5045-0
SEIKO EPSON CORPORATION
ELECTRONIC DEVICES MARKETING DIVISION
Fax: +49-(0)2171-5045-10
Electronic Device Marketing Department
IC Marketing & Engineering Group
421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN
UK BRANCH OFFICE
Unit 2.4, Doncastle House, Doncastle Road
Bracknell, Berkshire RG12 8PE, ENGLAND
Phone: +81-(0)42-587-5816
Fax: +81-(0)42-587-5624
Phone: +44-(0)1344-381700
Fax: +44-(0)1344-381701
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421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN
FRENCH BRANCH OFFICE
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Phone: +81-(0)42-587-5812
Fax: +81-(0)42-587-5564
Z.A. de Courtaboeuf 2, F-91976 Les Ulis Cedex, FRANCE
ED International Marketing Department Asia
Phone: +33-(0)1-64862350
Fax: +33-(0)1-64862355
421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN
Phone: +81-(0)42-587-5814
Fax: +81-(0)42-587-5110
BARCELONA BRANCH OFFICE
Barcelona Design Center
Edificio Prima Sant Cugat
Avda. Alcalde Barrils num. 64-68
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Phone: +34-93-544-2490
Fax: +34-93-544-2491
In pursuit of “Saving”Technology, Epson electronic devices.
Our lineup of semiconductors, liquid crystal displays and quartz devices
assists in creating the products of our customers’ dreams.
Epson IS energy savings.
S1C62N33
Technical Manual
ELECTRONIC DEVICES MARKETING DIVISION
EPSON Electronic Devices Website
http://www.epson.co.jp/device/
First issue January, 1992
M
Printed March, 2001 in Japan
B
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