S1D17C02D00B [SEIKO]
LIQUID CRYSTAL DISPLAY DRIVER, UUC301, DIE-301;
| 型号： | S1D17C02D00B |
| 厂家： | 
SEIKO EPSON CORPORATION |
| 描述： | LIQUID CRYSTAL DISPLAY DRIVER, UUC301, DIE-301 驱动 接口集成电路 |
| 文件： | 总44页 (文件大小：307K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MF1389-03
S1D17C02 Series
Rev.2.0
© Seiko Epson Corporation 2002, All rights reserved.
Rev.2.0
Contents
1. DESCRIPTION .................................................................................................................................................. 1
2. FEATURES........................................................................................................................................................ 1
3. PAD LAYOUT .................................................................................................................................................... 2
4. PAD CENTER COORDINATES ........................................................................................................................ 3
5. PIN DESCRIPTION ........................................................................................................................................... 5
6. BLOCK DIAGRAM ............................................................................................................................................. 9
7. EXPLANATION OF BLOCK DIAGRAM........................................................................................................... 10
7.1 Driver block............................................................................................................................................ 10
7.2 Power block ........................................................................................................................................... 10
8. FUNCTION DESCRIPTION ............................................................................................................................. 11
8.1 Outline of the operations of the power block ......................................................................................... 11
8.2 System configuration ............................................................................................................................. 11
8.3 Primary boosting circuit ......................................................................................................................... 13
8.4 Voltage regulating circuit ....................................................................................................................... 14
8.5 Secondary through quaternary boosting circuits ................................................................................... 17
8.6 Electric charge discharging circuit ......................................................................................................... 19
8.7 Regarding the power saving function .................................................................................................... 19
8.8 LCD driving circuit ................................................................................................................................. 21
8.9 Timing diagram for the driver section .................................................................................................... 22
9. ABSOLUTE MAXIMUM RATINGS .................................................................................................................. 23
10. ELECTRIC CHARACTERISTICS .................................................................................................................... 24
10.1 DC Characteristics................................................................................................................................. 24
10.2 DC Characteristics of the power supply section .................................................................................... 25
10.3 Operating current consumptions ........................................................................................................... 27
10.4 AC characteristics of the driver section ................................................................................................. 28
10.5 AC characteristics of the power supply section ..................................................................................... 30
11. THE POWER SUPPLY .................................................................................................................................... 32
11.1 Respective voltage levels ...................................................................................................................... 32
11.2 Precautions when turning on and off the power supply ......................................................................... 32
11.3 Timings of sleep and electric discharge signal inputs ........................................................................... 33
12. EXAMPLE OF CONNECTION......................................................................................................................... 34
12.1 Block diagram of an LCD module .......................................................................................................... 34
12.2 Detailed connection example 1 for the power block (Primary: ×1.5, Ternary: ×3) ................................. 36
12.3 Recommended capacitance values of the using capacitors and theoretical formulae
for the voltage to be biased on both ends of each capacitor ................................................................ 37
12.4 Detailed connection example 2 for the power block (Primary: ×2, Ternary: ×3) .................................... 38
12.5 Detailed connection example 3 for the power block
(Primary boosting: Interrupted. /Ternary boosting ratio: ×2) ................................................................ 39
12.6 Detailed connection example 4 for the power block
(Interrupting the operations of the primary, ternary and quaternary boosting circuits) ......................... 40
13. CAUTIONS ...................................................................................................................................................... 41
– i –
Rev.2.0
S1D17C02 Series
1. DESCRIPTION
2. FEATURES
S1D17C02 Series is a common (low) driver with built-
in MLS driving power by which low power consumption
and high picture quality features can be acquired, these
characteristics being deemed indispensable for various
portable equipment and devices. The key features of
the S1D17C02 include: 168 outputs, triple voltage level
outputs and built-in LCD driving power.
It should be used in a pair with a segment (column)
driver with built-in display RAM. Thanks to the built-
in power circuit, multiple power supplies necessary to
drive the MLS can be obtained by single power input of
1.7 to 3.6V, thus constituting a low power consumption
module.
• Number of LCD driving outputs: 168
• Driver low output ON resistance
• Built-in voltage conversion circuit employing the
charge pump type DC/DC converter:
Reference voltage
Temperature gradient selection circuit
Electronic volume control function with 128
steps
• Power saving function
Graphic icon indications—Sectional indications
during standing by
period at ultra-low
power consumption
As the LCD panel, the slip chip shape is being employed
which is said to be advantageous to realize narrower
frame and the LCD panel can be operated under low
logic power voltages suitable for a wide range of
applications.
• Non-biased display off function
• Built-in discharging circuit (This circuit works to
discharge unnecessary voltages being applied to the
LCD panel during sleep time.)
• Power supply
Being provided with bidirectional selectivities for the
pad layout and the output sequence of the driver which
facilitate substrate mounting, this device exhibits the
highest working efficiency for 1/160Duty panels.
Logic power: VCC–VSS = 1.7 to 3.7V
LCD driving power: V3–MV3 = 22V
• Wide working temperature range: –40 to +85°C
• CMOS processes
• Shipped form: In chips or TCP’s
S1D17C02D00B
S1D17C02T00A
• This device is not of a light-resistant design nor
radiation resistant design.
*
*
Rev.2.0
EPSON
1
S1D17C02 Series
3. PAD LAYOUT
283
284
111
110
93
X
(0, 0)
301
1
92
Chip size:
PAD pitch:
Chip thickness:
(reference value)
Substrate potential:
17.05 × 2.5 mm
96 µm (Min.)
625 µm
GND
Au bump specifications (reference value)
Au vertical bump
X
×
Y
Tolerance
Bump size A: 66.6 µm × 82.6 µm ± 4 µm (PAD Nos. 1 to 92)
Bump size B: 62.7 µm × 80.0 µm ± 4 µm (PAD Nos. 111 to 283)
Bump size C: 82.6 µm × 66.6 µm ± 4 µm (PAD Nos. 93 to 110, 284 to 301)
Bump height: 22.5 ± 5 µm
(reference value)
(Details are according to the delivery specifications.)
2
EPSON
Rev.2.0
S1D17C02 Series
4. PAD CENTER COORDINATES
PAD
No.
1
2
3
4
5
6
7
PIN
Name
DM
DM
V2
PAD
No.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
PIN
Name
V2
PAD
No.
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
PIN
Name
DM
DM
DM
DM
DM
DM
DM
DM
DM
DM
DM
DM
X
Y
X
Y
X
Y
–8213 –1077
–8112
–8012
–309 –1077
–208
–108
–7
94
194
295
396
491
769
8362 –100
V1
4
108
212
316
420
524
628
732
836
MV1
VCL
VC
TAP1
VSS
TAP2
RV
VEVL
VEV
FR
F1
F2
CI
CO
VCLK
VU/D
VSS
SKP
VDD
TC0
TC1
TC2
VSS
FACLK 4336
FBCLK 4600
FTEST 4863
FREST 5127
VSS
FA0
FA1
FA2
FA3
VSS
FB0
FB1
FB2
FB3
VSS
DM
CHC –7911
–7810
VC
V2C2P –7710
V2C2N –7609
V2C1P –7508
V2C1N –7408
V1CP
V1CN
MV1CP –7106
MV1CN –7005
VEC2P –6904
VEC2N –6804
VEC1P –6703
VEC1N –6603
VSS
CNT
VDD
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
–7307
–7206
870
968
8256 1099
8160
1231
1495
1758
2021
2418
2682
2960
3058
3336
3434
3697
3960
4238
COM1 8064
COM2 7968
COM3 7872
COM4 7776
COM5 7680
COM6 7584
COM7 7488
COM8 7392
COM9 7296
COM10 7200
COM11 7104
COM12 7008
COM13 6912
COM14 6816
COM15 6720
COM16 6624
COM17 6528
COM18 6432
COM19 6336
COM20 6240
COM21 6144
COM22 6048
COM23 5952
COM24 5856
COM25 5760
COM26 5664
COM27 5568
COM28 5472
COM29 5376
COM30 5280
COM31 5184
COM32 5088
COM33 4992
COM34 4896
COM35 4800
COM36 4704
COM37 4608
COM38 4512
–6502
–6404
–6126
TEST2 –6028
–5750
STBY –5652
–5374
PSAVE –5276
–4998
VSS
VDD
VSS
SLP1 –4900
SLP2 –4636
RES
DISCH –4110
–3832
TEST1 –3734
–4373
5404
5624
5907
6190
6473
6715
6934
7217
7501
7784
7982
8082
8183
8362 –932
–828
–724
–620
–516
–412
–308
–204
VSS
VDD
SHL
VSS
SEL
VDD
–3456
–3358
–3080
–2982
–2704
CSEL –2606
–2328
DOFF –2230
VSS
PCL
CL
PCA
CA
VSSL
MV3L
MV3
VDDH
V3L
–1966
–1703
–1440
–1176
–913
–812
–712
–611
–510
–410
DM
DM
DM
VREG1
VREG2
DM
DM
DM
V3
DM
Rev.2.0
EPSON
3
S1D17C02 Series
Unit: µm
PAD
No.
PIN
Name
PAD
No.
PIN
Name
PAD
No.
PIN
Name
X
Y
X
Y
X
Y
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
COM39 4416 1099
COM40 4320
COM41 4224
COM42 4128
COM43 4032
COM44 3936
COM45 3840
COM46 3744
COM47 3648
COM48 3552
COM49 3456
COM50 3360
COM51 3264
COM52 3168
COM53 3072
COM54 2976
COM55 2880
COM56 2784
COM57 2688
COM58 2592
COM59 2496
COM60 2400
COM61 2304
COM62 2208
COM63 2112
COM64 2016
COM65 1920
COM66 1824
COM67 1728
COM68 1632
COM69 1536
COM70 1440
COM71 1344
COM72 1248
COM73 1152
COM74 1056
COM75 960
COM76 864
COM77 768
COM78 672
COM79 576
COM80 480
COM81 384
COM82 288
COM83 192
201
202
203
204
205
206
207
208
209
210
211
212
COM88 –384 1099
COM89 –480
COM90 –576
COM91 –672
COM92 –768
COM93 –864
COM94 –960
COM95 –1056
COM96 –1152
COM97 –1248
COM98 –1344
COM99 –1440
251 COM138 –5184 1099
252 COM139 –5280
253 COM140 –5376
254 COM141 –5472
255 COM142 –5568
256 COM143 –5664
257 COM144 –5760
258 COM145 –5856
259 COM146 –5952
260 COM147 –6048
261 COM148 –6144
262 COM149 –6240
263 COM150 –6336
264 COM151 –6432
265 COM152 –6528
266 COM153 –6624
267 COM154 –6720
268 COM155 –6816
269 COM156 –6912
270 COM157 –7008
271 COM158 –7104
272 COM159 –7200
273 COM160 –7296
274 COM161 –7392
275 COM162 –7488
276 COM163 –7584
277 COM164 –7680
278 COM165 –7776
279 COM166 –7872
280 COM167 –7968
281 COM168 –8064
213 COM100 –1536
214 COM101 –1632
215 COM102 –1728
216 COM103 –1824
217 COM104 –1920
218 COM105 –2016
219 COM106 –2112
220 COM107 –2208
221 COM108 –2304
222 COM109 –2400
223 COM110 –2496
224 COM111 –2592
225 COM112 –2688
226 COM113 –2784
227 COM114 –2880
228 COM115 –2976
229 COM116 –3072
230 COM117 –3168
231 COM118 –3264
232 COM119 –3360
233 COM120 –3456
234 COM121 –3552
235 COM122 –3648
236 COM123 –3744
237 COM124 –3840
238 COM125 –3936
239 COM126 –4032
240 COM127 –4128
241 COM128 –4224
242 COM129 –4320
243 COM130 –4416
244 COM131 –4512
245 COM132 –4608
246 COM133 –4704
247 COM134 –4800
248 COM135 –4896
249 COM136 –4992
250 COM137 –5088
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
DM
DM
DM
DM
DM
DM
DM
DM
DM
DM
DM
DM
VL
–8160
–8256
–8362 836
732
628
524
420
316
212
108
4
–100
–204
–308
–412
–516
–620
–724
–828
–932
VH
COM84
DM
96
0
VLCP
VLCN
VHCP
VHCN
DM
DM
COM85 –96
COM86 –192
COM87 –288
4
EPSON
Rev.2.0
S1D17C02 Series
5. PIN DESCRIPTION
(1) Power terminal pins
Number of
pins
Pin name
I/O
Description
Substrate potential The substrate of the IC is of the grounding potential. When fixing the substrate
potential, set it to the grounding.
VCC
Power Connects to the system power.
supply
5
VSS
Power Connects to the system GND.
supply
Power LCD driving system intermediate power.
supply
12
1
VEVL
VDDH,V3L
Power Multi-level power to drive LCD. It is necessary to maintain the
one each
VCL,MV3L, supply following relations.
VSSL
VDDH ≥ V3L ≥ VCL ≥ MV3L ≥ VSSL
(2) Voltage modulation circuit
Number of
pins
Pin name
I/O
Description
VC
VCLK
O
I
VC output pin.
Electronic volume control clock input pin.
1
1
The electronic volume control values will change in synchronization
with the rising time of this pin. Also, the electronic volume control
value α will stop at the maximum value(α = 127) and the minimum
value (α = 0).
VU/D
I
Electronic volume control up-down setting input pin.
Controls the increases and decreases of the electronic volume
control value α.
1
VU/D
Functions
LOW
The electronic volume control value α decreases.
HIGH The electronic volume control value α increases.
When changing the settings for this pin, do so on the timing that the
VCLK input is on the low level.
SKP
I
Changes the number of steps of the electronic volume control.
1
SKP
Functions
LOW
Number of steps of the electronic volume control = 128
HIGH Number of steps of the electronic volume control = 64
TC0 to 2
SLP2
I
I
Temperature gradient setting pin.
Reference power control input pin.
Generation of the reference power will be interrupted when the
low level signal is input through this pin.
3
1
TEST 2
I
Input pin for the IC test. It is normally fixed at LOW.
1
RV
TAP 1
I
Input pin for regulating the voltage of the constant voltage circuit.
Internal resistance pin
1
1
I/ O
(Vc connection pin when internal resistance is used.)
TAP 2
I/ O
Internal resistance pin
(RV connection pin when internal resistance is used.)
1
Rev.2.0
EPSON
5
S1D17C02 Series
(3) Boosting timing generating circuit
Number of
pins
Pin name
I/O
Description
Boosting clock signal input pin.
Boosting operation control signal input pin.
The internal boosting clock will stop and the boosting operation will
be interrupted when the low level signal is input through this pin.
PCL
I
I
1
1
SLP1
(4) Primary boosting circuit
Number of
pins
Pin name
I/O
Description
VEV
VEC1P
I/O
(O)
Primary boosting circuit output pin.
Positive side connection pin for the 1st flying capacitor for
generation of the VEV output.
1
1
VEC1N
VEC2P
VEC2N
CNT
(O)
(O)
(O)
I
Negative side connection pin for the 1st flying capacitor for
generation of the VEV output.
Positive side connection pin for the 2nd flying capacitor for
generation of the VEV output.
Negative side connection pin for the 2nd flying capacitor for
generation of the VEV output.
Primary boosting (M1) mode selection pin.
When making M1 = Double boosting: Connect to HIGH.
When making M1 = 1.5 time boosting: Connect to LOW.
Primary boosting circuit control signal input pin
When using the primary boosting circuit: HIGH
When not using the primary boosting circuit: LOW
1
1
1
1
I
1
STBY1
(5) Secondary boosting circuit
Number of
pins
Pin name
I/O
Description
V2
V2C1P
O
(O)
V2 output pin.
1
1
Positive side connection pin for the 1st flying capacitor for
generation of the V2 output.
V2C1N
V2C2P
V2C2N
(O)
(O)
(O)
Negative side connection pin for the 1st flying capacitor for
generation of the V2 output.
Positive side connection pin for the 2nd flying capacitor for
generation of the V2 output.
Negative side connection pin for the 2nd flying capacitor for
generation of the V2 output.
1
1
1
V1
V1C1P
V1 output pin.
1
1
O
(O)
Positive side connection pin for the flying capacitor for generation
of the V1 output.
V1CN
(O)
Negative side connection pin for the flying capacitor for generation
of the V1 output.
1
MV1
MV1CP
O
O
MV1 output pin.
1
1
Positive side connection pin for the flying capacitor for generation
of the MV1 output.
MV1CN
O
Negative side connection pin for the flying capacitor for generation
of the MV1 output.
1
6
EPSON
Rev.2.0
S1D17C02 Series
(6) Ternary and quaternary boosting circuits
Number of
pins
Pin name
I/O
Description
VH
O
VH output pin.
1
VHCP
(O)
Positive side connection pin for the flying capacitor for generation
of the VH output.
1
VHCN
(O)
Negative side connection pin for the flying capacitor for generation
of the VH output.
1
VL
VLCP
O
(O)
VL output pin.
1
1
Positive side connection pin for the flying capacitor for generation
of the VL output.
VLCN
(O)
(I)
Negative side connection pin for the flying capacitor for generation
of the VL output.
Ternary boosting (M2) mode selection pin.
1
1
CHC
When making M2 = Triple boosting: Connect to the V2 pin.
When making M2 = Double boosting: Connect to the VC pin.
When making M2 = ×1 boosting: Connect to the V2 pin.
(7) VH, VL/V2, MV2 changeover circuit
Number of
pins
Pin name
I/O
Description
V3
O
O
I
V3 output pin.
MV3 output pin.
V3 and MV3 output voltage changing-over clock input pin.
Power saving control input pin.
1
1
1
1
MV3
PCA
PSAVE
I
Functions
V3 = V2
PSAVE
LOW
(Power save IN)
HIGH
MV3 = MV2
V3 = VH
(Power save OUT)
MV3 = VL
After finishing the setting of this pin, switch over the potential of the
V3 and MV3 taking 1-frame period.
Be sure to turn OFF the indication before changing the setting.
Also, make the settings on the timing that the PCA pin is on the low level.
Rev.2.0
EPSON
7
S1D17C02 Series
(8) LCD drive pin
Number of
pins
Pin name
I/O
Description
COM1 to
COM168
CL
CA
F1, F2
O
LCD driving common (low) driver output. The output changes
at the trailing edge of the CL.
Shift clock input pin for the indicating data.
Field start signal input pin.
Driving pattern selecting signal input pin.
LCD driving output alternating current signal input pin.
LCD indication blanking control signal input pin. When the low
level signal is input, all the common outputs will instantly become
the VC level. The contents of the shift register will be maintained.
Shifting direction selecting control signal input pin.
168
I
I
I
I
I
1
1
1
1
1
FR
DOFF
SHL, SEL
I
2
SHL
LOW
HIGH
LOW
HIGH
SEL
LOW
LOW
HIGH
HIGH
Output shifting direction
COM1→COM84→COM85→COM168
COM168→COM85→COM84→COM1
COM1→COM84→COM168→COM85
COM85→COM168→COM84→COM1
CSEL
CI
I
I
Chip selecting signal input pin under the cascade connection.
Master: Connect to LOW.
Slave: Connect to HIGH.
Scanning data input pin.
Master chip: Fixed to LOW
1
1
Slave chip: Connect to the CO of the master chip.
CO
TEST1
O
I
Scanning data output pin.
Input pin for IC tests. Normally fixed to LOW.
1
1
(9) Other pins
Number of
pins
Pin name
I/O
Description
DISCH
I
Discharging circuit controlling signal input pin.
1
When turning OFF the discharging operation: Connect to HIGH.
When turning ON the discharging operation: Connect to LOW.
Resetting signal input pin. Normally fixed to LOW.
Input pin for IC tests. Normally fixed to LOW.
Input pin for IC tests. Normally fixed to LOW.
Input pin for IC tests. Normally fixed to LOW.
Input pin for IC tests. Normally fixed to LOW.
Input pin for IC tests. Keep it open.
Input pin for IC tests. Keep it open.
Input pin for IC tests. Keep it open.
Input pin for IC tests. Keep it open.
Dummy pad. Not connected to any other pins.
I
I
I
I
I
–
–
–
–
–
RES
FTEST
FACLK
FBCLK
FREST
FA0 to 3
FB0 to 3
VREG1
VREG2
DM
1
1
1
1
one each
one each
1
1
34
8
EPSON
Rev.2.0
S1D17C02 Series
6. BLOCK DIAGRAM
VDDH
V
3L
V
V
CC
SS
VCL
MV3L
VSSL
VEVL
LCD Driving Circuit
DOFF
FR
F1
F2
TEST1
V3
VH,VL/V2,MV2
Changeover Circuit
Decoding Circuit
MV
3
VH
CL
VHCP
VHCN
CHC
VLCP
VLC
Bidirectional Shift Resistor
Ternary and
Quaternary
Boosting
CSEL
CA
CI
CO
SEL
SHL
Shifting
Direction
Control
Circuits
VL
V2
V2C1P
V2C1N
V2C2P
V2C2N
V1
Discharging
Circuit
DISCH
VEV
VEVC1P
VEVC1N
VEVC2P
VEVC2N
Secondary
Boosting Circuit
V1CP
V1CN
MV1
Primary Boosting
Circuit
MV1CP
MV1CN
VC
TAP1
RV
STBY
SLP1
CNT
Boosting Timing
Signal
TAP2
SKP
Generation
Circuit
PCL
Voltage
Regulation
Circuit
V
U/D
V
CLK
TEST2
SLP2
PCA
RES
PSAVE
TC0~2
Rev.2.0
EPSON
9
S1D17C02 Series
7. EXPLANATION OF BLOCK DIAGRAM
7.1 Driver block
(1) Bidirectional shift resistor
This is a bidirectional shift resistor for transferrence of the scanning data.
(2) Decoding circuit
It works to form the LCD driving patterns using the column driver signals.
(3) LCD driving circuit
It outputs LCD driving voltages.
7.2 Power block
(1) Voltage regulating circuit
The voltage regulating circuit regulates the voltages generated by the primary boosting circuits to output the LCD
driving voltage VC.
It incorporates a high precision constant voltage source, 128 step electronic volume control and a temperature
compensating circuit.
Desired temperature gradient can be selected from 8 types of temperature gradient choices.
The electronic volume control is being controlled by the clock signal (VCLK) and the up-down signal (VU/D).
(2) Boosting timing signal generation circuit
This circuit works to generate clock signals for the charge pump using the PCL signals. When the SLP is shifted
to the GND level, the boosting operation will be interrupted.
(3) Primary boosting circuit
This circuit is used when the system power supply is lower than the constant voltage output. It boosts the VCC
potential to ×1.5 level or ×2 level. When taking voltage from an external source, shift the STBY signal to the GND
level to stop the operation of the primary boosting circuit.
(4) Secondary boosting circuit
It generates the V2 potentials which are necessary for the segment (column) driver by double-boosting of the VC
potentials. It also generates the V1 and MV1 potentials which are necessary for the segment (column) driver by one-
second boosting of the V2 and Vc potentials.
(5) Ternary and quaternary boosting circuits
These circuits work to generate the V3 and MV3 potentials which are necessary for the common (low) driver by
generating VH or VL potentials from the V2 or VC potentials.
(6) VH, VL/V2, MV2 changeover circuit
It works to output the specified potentials to the V3 and MV3 using the PSAVE signals.
(7) Discharging circuit
This circuit works to discharge the electric charges remaining in the V3, V2, V1, MV1 and MV3 pins to the VSS level.
It is activated when the DISCH is shifted to the GND level. Although it can also be activated when the supply
voltage VCC is interrupted compulsorily, make it a rule to observe the power ON/OFF sequence.
10
EPSON
Rev.2.0
S1D17C02 Series
8. FUNCTION DESCRIPTION
8.1 Outline of the operations of the power block
All the bias voltages necessary to drive the LCD can be generated by a single power supply.
Voltage levels that can be generated are as follows:
• LCD driving supply voltages necessary for the column driver (V2, V1, VC, MV1 and GND=MV2)
• LCD driving supply voltages necessary for the low driver (V3, VC and MV3)
As the voltages for the low driver, desired boosting ratio can be selected from among ×1, ×2 or ×3 as the ternary boosting
ratio (M2), thus making them applicable to a wide range of duties.
The built-in electronic volume control function works to regulate the contrast of the LCD. The electronic volume
control is being controlled through the VCLK pin and the VU/D pin for variations in 128 steps. Also, thanks to the built-
in constant voltage circuit, stable LCD driving voltages can be constantly output without need for relying upon the
system power supply.
When the system side supply voltage (VCC–GND) is too low and insufficient as the LCD driving power (VC–GND),
necessary LCD driving power (VC–GND) can be supplied by use of the primary boosting circuit.
As the primary booster ratio, desired boosting ratio can be selected from between ×1.5 and ×2.
8.2 System configuration
(1) An exemplary system configuration
Indicated below is an exemplary system configuration for the power circuit.
S1D17C02D
****
LCD Panel
Row Driver
Power Circuit
V2,V1,VC,MV
1
Column
Driver
(S1D159 )
**
VCC
MV
2
GND
GND
Fig. 8.2.1 Block diagram of a system configuration
Rev.2.0
EPSON
11
S1D17C02 Series
(2) Correlations of the system potentials
Indicated below are the correlations of the system potentials.
VC = 0V reference
GND = 0V reference
S1D17C02
VH,V3
M2 = 3
3
4
3
2
Column Driver
V2
V1
VC
2
1
1
V2
V1
VC
0
VCC
MV1
MV2
VCC
GND
MV1
MV2
0
GND
–1
–2
–3
–1
VL,MV3
–2
System Side
(Settings — Primary boosting: M1 = ×1.5 and ternary boosting: M2 = ×3)
Fig. 8.2.2 Potential correlation diagram inside the system
12
EPSON
Rev.2.0
S1D17C02 Series
8.3 Primary boosting circuit
The primary boosting circuit works to make voltage conversion (×1.5 or ×2 boosting) of the inputted supply voltage
(VCC) coming from the system into the supply voltage (VEV) to the LCD driving circuit.
(1) When using the primary boosting circuit
In case supply voltages within the range of 3.7V ≤ VEV ≤ 5.5V are not available from an external source and when
it is necessary to make use of the primary boosting function, connect the STBY pin to the high (VCC) level.
At this time, make due settings for the primary boosting circuit so that the voltages within the range of 3.7V ≤ VEV
≤ 5.5V can be obtained.
To Secondary
Booster
STBY
VEV
VC
When the Circuit is
in Operation
VCC
VCC
GND
GND
GND
[Primary Boosting Circuit]
[Constant Voltage Circuit]
Fig. 8.3.1 When the primary boosting circuit is in operation
When switching over the primary boosting ratio (M1 = ×2 or M1 = ×1.5), connect the CNT pin according to the Table
8.3.1 given below.
Table 8.3.1 Boosting ratio switching over pin
Setting pin
×2 boosting (M1 = ×2) ×1.5 boosting (M1 = ×1.5)
HIGH (VCC) LOW (GND)
CNT
(2) When the primary boosting circuit is not necessary
In case supply voltages within the range of 3.7V ≤ VEV ≤ 5.5V are available from an external source and when it
is not necessary to use of the primary boosting function, connect the STBY pin to the GND level to interrupt the
primary boosting operation.
To Secondary
Booster
STBY
VEV
When the circuit
operation is being
interrupted
VC
VCC
VCC
GND
GND
GND
[Primary boosting circuit]
[Constant voltage circuit]
Fig. 8.3.2 When the primary boosting circuit operation is being interrupted
Rev.2.0
EPSON
13
S1D17C02 Series
8.4 Voltage regulating circuit
Since the S1D17C02 Series devices incorporate highly accurate constant voltage source and the electronic volume
control function at 128 steps, a high precision voltage regulating circuit can be constituted with the least number of
components.
(1) Constant voltage circuit
This constant voltage circuit is equipped with 64 or 128 step electronic volume functions. By combining internal
resistance R1, R2 or external resistance R1, R2 with the electronic volume functions, the contrast of LCD
indications can be regulated. The electronic volume setting can be controlled by the VCLK and VU/D signals. The
VC voltage can be calculated using the following equation.
Inside the S1D17C02
Outside the S1D17C02
VEV
VC
R2
VCREF
RV
Standard voltage + electronic volume
(Note1)
R1
VSS
Fig. 8.4.1 Constant voltage circuit
Note 1: Giving care to noise is required since the RV pin is high impedance.
R2
V
C
= 1+
= 1+
× VCREF
R1, R2 :External resistance
VREF : Standard internal voltage of IC
: Electronic volume control value (α = 0 to 127)
R1
R2
R1
1038 + 6α
VC
×
× VREF
α
1800
VREF, which is the standard internal voltage of IC, generates a voltage of VREF = 1.8 v (Ta = 25 ºC). It is also possible
to abbreviate parts by using the internal resistance when the VC output voltage range is within VC = 3.6V because the
.
=
resistance of R1 R2 is built in.
.
Inside the S1D17C02
Outside the S1D17C02
V
V
EV
C
TAP1
R2
RV
V
CREF
Standard voltage + electronic volume
TAP2
R1
V
SS
Fig. 8.4.2 An example of connection diagram when internal resistance is used
14
EPSON
Rev.2.0
S1D17C02 Series
(2) Temperature gradient selection circuit
This circuit works to select the temperature gradient characteristics of the LCD driving supply voltage. Through
the temperature gradient selection pins, desired temperature gradient characteristic can be selected from among 8
choices of temperature gradient characteristics. By selection of temperature gradient characteristics fitting to the
temperature characteristics of the using LCD, a system can be duly constituted without need for provision of
external elements for correction of the temperature characteristics.
Table 8.4.1 Temperature gradient setting pins
TC2
0
0
0
0
1
1
1
1
TC1
0
0
1
1
0
0
1
1
TC0 Temperature gradient [%/°C]
0
1
0
1
0
1
0
1
–0.063
–0.074
–0.084
–0.095
–0.106
–0.117
–0.128
–0.14
If you want to select random temperature gradient characteristics other than those in Table 8.4.1 for the output voltage,
use thermistor resistance, etc.
Inside the S1D17C02
Outside the S1D17C02
VEV
VC
Thermistor
resistance
VCREF
R2
R1
RV
Standard voltage + electronic volume
VSS
Note 1: Giving care to noise is required since RV pin is high impedance.
Fig. 8.4.3 An example of connection diagram when random temperature gradient characteristics
are selected for the output voltage
Rev.2.0
EPSON
15
S1D17C02 Series
(3) Electronic volume circuit
The contrast of LCD indications can be regulated. The electronic volume setting can be controlled by the VCLK and
VU/D signals.
When the VU/D signal is at the low level, the VCLK clock will be down-counted and the electronic volume control
values will be decremented. While, when the VU/D signal is at the high level, the VCLK clock will be up-counted
and the electronic volume control values will be incremented. The electronic volume control value changes in
synchronization with the fall time of the VCLK signal.
Table 8.4.2 Table of functions for VU/D pin
VU/D
Functions
LOW
HIGH
The VCLK clock is down-counted and the electronic volume control value are decreased.
The VCLK clock is up-counted and the electronic volume control value are increased.
The number of steps of the electronic volume control value can be changed using SKP.
Table 8.4.3 Table of functions for SKP pin
SKP
LOW
Functions
Electronic volume control value α = 0 to 127
Initial value at reset α = 64
HIGH
Electronic volume control value α = 0,2,4
Initial value at reset α = 32
124,126
The electronic volume control value α will stop at the maximum value (α = 127) or the minimum value (α = 0) regardless
of the clock input. After turning the power on, initialize by inputting on resetting or inputting at least 127 clocks (at
least 63 clocks at SKP = HIGH) into the VCLK pin. An example of initialization and the waveform diagram of the VC
output voltage is as follows:
V
CC–GND
1 Turn on the power supply.
2 Input at least 127 clocks of the clock signals
into the VCLK pin.
3 Input clock signals until desired electronic
volume control value is obtained.
4 Even when 128 clocks or more of clock signals
are input, the electronic volume control value
will stop at its maximum level.
V
U/D
1
2
127 128 129
127
V
V
CLK
0
1
2
V
V
C
C
maximum voltage
minimum voltage
C
voltage
GND=0V
Fig. 8.4.4 An example of initialization and waveform diagram of the VC output voltage (SKP = LOW)
16
EPSON
Rev.2.0
S1D17C02 Series
8.5 Secondary through quaternary boosting circuits
LCD driving supply voltages necessary after the electronic volume control stage are being generated by the voltage
conversion circuits of the CMOS charge pump method. The voltage conversion circuits are comprised of the secondary
boosting circuit, ternary boosting circuit and quaternary boosting circuit. Indicated below is the correlation diagram
among respective voltage conversion circuits.
Ternary Boosting
Circuit
V3
V2
V1
Secondary
Boosting
Circuit
VC
VC
MV1
MV2
GND
Quaternary Boosting
Circuit
MV3
Fig. 8.5.1 Correlation diagram among respective voltage conversion circuits
Also, theoretical formulae for respective potentials are as follows.
Table 8.5.1 Theoretical formulae for respective potentials
Signal
names
V3
Theoretical formulae
(When GND = 0V)
(M2 + 1) × (VC – GND)
2 × (VC – GND)
3/2 × (VC – GND)
VC – GND
Theoretical formulae
(When VC = 0V)
M2 × (VC – GND)
VC – GND
V2
V1
1/2 × (VC – GND)
0V
VC
MV1
MV2
MV3
1/2 × (VC – GND)
0V
–(M2 – 1) × (VC – GND)
–1/2 × (VC – GND)
–(VC – GND)
–M2 × (VC – GND)
M2 stands for the ternary boosting ratio
Rev.2.0
EPSON
17
S1D17C02 Series
The boosting ratio (M2) of the ternary boosting circuit can be set to ×1, ×2 or ×3 using external circuitry. Indicated below
are respective circuitries and relevant potential levels.
VH = 4 × (VC-GND)
V2
CHC
VC
VC
GND=MV
2
= 0V
Fig. 8.5.2 Circuitry for the boosting ratio M2 = 3 and relevant potential levels
VH = 3 × (VC-GND)
V2
CHC
VC
VC
GND=MV
2
= 0V
Fig. 8.5.3 Circuitry for the boosting ratio M2 = 2 and relevant potential levels
VH
V3
V2
VH = V3 = V2 = 2× (VC-GND)
CHC
VC
VC
MV3
VL
GND= MV3 = MV2 =0
PSAVE
Fig. 8.5.4 Circuitry for the boosting ratio M2 = 1 and relevant potential levels
Since boosting is being made in the sequence of secondary, ternary and quaternary boosting circuits on the basis of the
VC voltage, be careful not to let respective LCD driving voltages being generated exceed the absolute maximum rating.
18
EPSON
Rev.2.0
S1D17C02 Series
8.6 Electric charge discharging circuit
When the DISCH pin is shifted to the GND level, the electric charge discharging circuit being incorporated in this IC
will work to discharge the electric charges remaining in the power supplies VH, V3, V2, VC, VL and MV3 to the GND
level.
8.7 Regarding the power saving function
The power saving function works to control activation/interruption of the ternary boosting circuit and quaternary
boosting circuit and to switch over the outputs of the low side LCD driving voltage V3 and MV3 as shown in the table
indicated below, through the PSAVE pin.
Table 8.7.1
Functions
PSAVE = HIGH PSAVE = LOW
Ternary and quaternary
boosting circuits
activation
interruption
V3 output voltage
MV3 output voltage
VH
VL
V2
MV2 (GND)
RES
PSAVE
PCA
VH
OPEN
OPEN
VH
VL
OPEN
OPEN
V2
V3
MV
2
VL
MV3
The ternary and quaternary
boosting circuits are
being activated
The ternary and quaternary
boosting circuits are
being interrupted
Fig. 8.7.1 PSAVE Timing chart
Described below are the drives making use of the power save function of the S1D17C02.
(1) Graphic icon indications
Graphic icon indications at an even lower power than partial indications are available. In case of partial indications,
since the partial indications are being made with the indication duty remaining as is, the row driver is working under
a higher voltage. While, in case of the graphic icon indications, the indication duty is changed over to lower the
voltage for the row driver, thus realizing the low power consumption feature.
Theoretically, it is possible to acquire satisfactory contrasts without need for re-setting of the electronic volume
control value, as far as the ratio between the sectional indication duty n' and the overall indication duty n remains
n'
n
1
=
at
(M2 stands for the ternary boosting ratio), approximately. Nonetheless, do not fail to check and
(M2) 2
confirm if the displayed shapes are satisfactory on the actual equipment. This function is available only when the
device is combined with the column drier S1D15912. Necessary controls can be made by connecting the parallel
outputs (PO ) from the S1D15912 to the PSAVE pin. Consequently, when using the graphic icon indications, it
*
is necessary to input the following commands into the S1D15912.
Rev.2.0
EPSON
19
S1D17C02 Series
(1) Display OFF
(2) Port controls (LOW: Power saving HIGH: Ordinary)
(3) Duty change
(4) Dividing ratio change
(5) Display ON
To realize ultra-low power consumption feature while making graphic icon indications, change the dividing circuit
setting for the S1D15912 to bring down the frequency of the CL (PCL).
Do not apply large capacities to the V3 pin and MV3 pin since they may switch over.
Shown below is a table comparing the characteristics of partial indications and graphic icon indications. Select the
sectional indication means fitting to the desired specifications.
Table 8.7.2
Overall screen indications
Sectional indications
(Ordinary state)
Partial indications
HIGH to Intermediate
Graphic icon indications
LOW
Power consumption
Indication area
Location of indication
Indication duty
HIGH
Large
–
Large to Small
Small
COM1 to COMn'
n' *1
Optional
n
n
Switching over the
indication mode
Can be switched over instantly between
each other.
Necessary to turn off the
indication once.
(*1: Conditions wherein re-setting of the electronic volume control values is not necessary depend on the level of the
M2. Namely, n' = n × 0.3 to 0.067)
Shown below are the specific examples (reference values) of the driving duty ratios wherewith the values of the
electronic VR need not be changed when switching over between the overall indications and icon partial indications.
However, since these have been calculated on the basis of the driving conditions, do not fail to check and confirm if
the displayed shapes are satisfactory on the actual equipment.
Overall indication duty: n
Graphic icon indication duty: n'
Table 8.7.3 Indication duty examples (Reference values)
n
n'
M2 = 2
20
M2 = 3
8
80
100
120
140
160
200
240
24
32
36
40
50
60
12
12
16
16
24
28
20
EPSON
Rev.2.0
S1D17C02 Series
8.8 LCD driving circuit
Shown below are the relations between the drive pattern selection signals F1 and F2, alternating current signals FR,
indication blanking signals DOFF and common output voltages
DOFF
FR
HIGH
LOW
–
LOW
HIGH
F1, F2
1 line
2 line
3 line
4 line
1, 1
V3
0, 1
V3
1, 0
MV3
V3
0, 0
V3
1, 1
MV3
V3
0, 1
MV3
MV3
V3
1, 0
V3
0, 0
MV3
MV3
MV3
V3
–
VC
VC
VC
VC
MV3
V3
V3
V3
MV3
MV3
MV3
MV3
V3
V3
V3
MV3
MV3
V3
V3
MV3
MV3
Correlations among potentials: V3 > VC > MV3 (The VC is the center potential)
Rev.2.0
EPSON
21
S1D17C02 Series
8.9 Timing diagram for the driver section
1/168 Duty
SHL = LOW, SEL = LOW and CSEL = LOW (A reference example)
168 lines
CA
1
2
3
42 43 44 45
84 85 86 87
126 127 128 129
168
1
2
3
CL
CO
1 frame (168 lines)
1st field
2nd field
3rd field
4th field
1
2
3
42 43 44 45
84 85 86 87
126 127128129
168 1
2
3
CL
FR
F1
F2
V3
VC
COM1
MV
3
3
3
3
3
3
3
V
3
VC
COM2
COM3
COM4
COM5
COM6
COM7
COM8
MV
V3
VC
MV
V3
VC
MV
V3
VC
MV
V3
VC
MV
V3
VC
MV
V
3
VC
MV3
V3
V
C
COM
168
MV
3
22
EPSON
Rev.2.0
S1D17C02 Series
9. ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Rating
Min.
Unit
Applicable Pin
Remarks
Max.
6.0
6.0
16
Input power voltage 1
Input power voltage 2
Input power voltage 3
VCC
VEV
–0.3
–0.3
–8.0
V
V
V
VCC
VEV
—
—
VLCD
VDDH, V3L, VCL
MV3L, VSSL
VH
*2, *3
Output voltage 1
Output voltage 2
Output voltage 3
Output voltage 4
Input pin voltage
Input current 1
VV3
VV2
VVC
VMV3
VIN
0.0
0.0
0.0
–8.0
–0.3
—
16
16
V
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
V
V2
VC
VL
5.0
V
0.0
V
VCC+0.3
3.0
V
*1
ICC
mA
mA
mA
mA
mA
mA
mA
mA
°C
°C
°C
VCC
VEV
V3
Input current 2
IEV
—
3.0
Output current 1
Output current 2
Output current 3
Output current 4
Output current 5
Output current 6
Operating temperature
IV3
—
0.2
IV2
—
1.0
V2
IV1
—
2.0
V1
IVC
—
2.0
VC
MV1
V3
IMV1
IMV3
Topr
–2.0
–0.2
–40
–65
–55
—
—
85
—
Storage temperature 1 (Chip) Tstg1
Storage temperature 2 (TCP) Tstg2
150
100
—
—
*1: Applicable pin names are PCL, PCA, CNT, SLP1, SLP2, STBY, PSAVE, DISCH, RES, VCLK, VU/D,
SKP, TC0 to 2, CL, CA, DOFF, F1, F2, FR, CSEL, SHL, SEL, CI, CO, TEST1, TEST2
*2: Potential levels of the VDDH, V3L, MV3L and VSSL should always be maintained in the following state.
VDDH ≥ V3L ≥ VCL ≥ MV3L ≥ VSSL
*3 Do not let the logic powers float nor let the VCC vary widely while LCD driving power is being applied
since, otherwise, the LSI may go into permanent breakage. Particularly, pay great attention when
determining the sequences of turning on of the system power and turning off of the system power.
VDDH, V3L
VCL
VCC
GND
VSSL, MV3L
Logic Powers
LCD Driving
Powers
Rev.2.0
EPSON
23
S1D17C02 Series
10. ELECTRIC CHARACTERISTICS
GND=0V, VCC=+3.0V, and Ta=–40 to +85°C unless otherwise noted. (*1)
10.1 DC Characteristics
Item
Symbol
Conditions
Applicable
Pin
Standard
Min. Typ. Max.
Unit Note
Supply voltage (1)
Supply voltage (2)
Supply voltage (3)
Supply voltage (4)
VCC
VEV
V3
VCC
1.7
3.7
–
–
12
3
–6
–
3.7
5.5
V
V
V
V
V
V
V
V
V
VEV, VEVL
V3L, VDDH
VCL
MV3L, VSSL
*2
VC
Supply voltage (5)
MV3
VIH
VIL
VOH
VOL
ILI
HIGH level input voltage
LOW level input voltage
HIGH level output voltage
LOW level output voltage
Input leak current
VCC=1.7V
to 3.7V
0.8VCC
0
VCC
0.2VCC
VCC
VCC=1.7V IOH=–0.3mA CO VCC–0.4
to 3.7V
GND≤VIN≤VCC
IOH=–0.3mA
VSS
0.4
2.0 µA
3.0 µA
*2
CO
VCC
Output leak current
Resting current (1)
ILO
ICCQ
VIH = VCC or
VIL = GND
V3 – MV3 =
4.4 to 24.0V
VIH=VCC
5
µA
Resting current (2)
ILCDQ
VDDH, V3L
VH, VSSL
25 µA
MV3L,VL,V2
VIL=GND
Output resistance
Input pin capacity
RCOM
∆VON= Recommended COM 1 to
conditions for COM168
, V and MV
–
0.55
0.7 kΩ
0.5V
V3
C
3
CI
Freq=1MHz
*3
10
pF
Independent chips
Ta25°C
*1 Unless otherwise designated, conditions for the operation mode and the pins should be as follows:
Connection conditions: Standard connection according to “Section 12.4 Detailed connection example 3 for
the power block”.
Capacity conditions: According to “Section 12.3 Recommended capacities”
CL signal inputting conditions: CL cycle = 85 µsec., CL pulse duration = 200n sec. and Electronic volume
control value: α = 127 (Max.)
*2 Applicable pin names are PCL, PCA, SYNC, SLP1, SLP2, STBY1, PSAVE, DISCH, RES, VCLK, VU/D,
TC0 to 2, CL, CA, DOFF, F1, F2, FR, CSEL, SHL1, SHL2, CI, CO, TEST1, TEST2.
*3 Applicable pin names are PCL, PCA, SYNC, SLP1, SLP2, PSAVE, DISCH, RES, VCLK, VU/D, TC0 to 2,
CL, CA, DOFF, F1, F2, FR, CSEL, SHL1, SHL2, CI, TEST1, TEST2.
24
EPSON
Rev.2.0
S1D17C02 Series
10.2 DC Characteristics of the power supply section
Item
Symbol
Conditions
Applicable
Pin
Standard
Min. Typ. Max.
Unit Note
VC Output voltage
VEV=3.7V IO=1mA
V2=7.2V
VC
2.0
3.6
V
VEV Output resistance
RVEV VEV=3.6V M1=2
IO=1mA M1=1.5
VEV
VC
—
160 220
170 220
Ω
Ω
*4
*4
Load output saturating
resistance
RVC
VEV=3.6, IO=1mA
Electronic volume control
value α=127 (Max.)
V2=6.0V
—
50
100
V1 Output resistance
MV1 Output resistance
V2 Output resistance
RV1
V1
MV1
V2
—
—
—
—
—
—
—
—
—
—
190 300
100 150
260 350
Ω
Ω
Ω
*4
*4
*4
IO=0.5mA (Flowing out to VC)
RMV1 V2=6.0V
IO=0.5mA (Flowing in from VC)
RV2
RV31
RV32
RV33
VC=3.0V
IO
= 0.25mA (Flowing out to V
C
)
V3 Output resistance 1
(M2=1)
V3 Output resistance 2
(M2=2)
V3 Output resistance 3
(M2=3)
MV3 Output resistance 2
(M2=1)
MV3 Output resistance 3
(M2=2)
MV3 Output resistance 4
(M2=3)
VC=3.0V
V3
0.62 0.85 kΩ *4
I =0.05mA (Flowing out to VC)
O
VC=3.0V
V3
3.5
4.0
7.0 kΩ *4
7.0 kΩ *4
IO
=0.05mA (Flowing out to V
C
C
)
)
)
)
VC=3.0V
V3
IO=0.05mA (Flowing out to V
RMV31 VC=3.0V
MV3
MV3
MV3
VC
0.39 0.7 kΩ *4
IO=0.05mA (Flowing in from VC
RMV32 VC=3.0V
3.7
4.1
7.0 kΩ *4
7.0 kΩ *4
I =0.05mA (Flowing in from VC
O
RMV33 VC=3.0V
IO=0.05mA (Flowing in from VC)
Electronic volume control EVR Le VEV=3.6V
±1.7 ±5.0 % of *5
linearity error
VTAP1=1.8V
FSR
VTAP2=1.08V
Electronic volume control EVRd Le VEV=3.6V
VC
VC
±0.12 ±0.25 LSB *5
differential linearity error
VTAP1=1.8V
VTAP2=1.08V
Temperature gradient
CT0
CT1
CT2
CT3
CT4
CT5
CT6
CT7
(TC2, TC1, TC0)=(L, L, L)
–0.068 –0.063 –0.057 %/°C *6
–0.080 –0.074 –0.067 %/°C *6
–0.090 –0.084 –0.077 %/°C *6
–0.100 –0.095 –0.088 %/°C *6
–0.116 –0.106 –0.099 %/°C *6
–0.121 –0.117 –0.111 %/°C *6
–0.134 –0.128 –0.123 %/°C *6
–0.148 –0.140 –0.135 %/°C *6
(TC0, TC1, TC2)=(L, L, H)
(TC0, TC1, TC2)=(L, H, L)
(TC0, TC1, TC2)=(L, H, H)
(TC0, TC1, TC2)=(H, L, L)
(TC0, TC1, TC2)=(H, L, H)
(TC0, TC1, TC2)=(H, H, L)
(TC0, TC1, TC2)=(H, H, H)
Rev.2.0
EPSON
25
S1D17C02 Series
*4 PCL signal inputting conditions — PCL cycle: 85µsec. PCL pulse duration: 200nsec.
Do not apply loads to V1, MV1, V2, V3 and MV3 simultaneously when making measurement.
(Since the characteristics of respective power sources are being indicated independently, they are different from the
state when the modules are actually being driven.)
Assuming that VC = 3V, calculate the output resistance by the measurement value (E) as against the ideal value (E0).
R = (E0 - E)/I0 (I0: Load current)
*5 Definitions of errors are as follows:
VC(α=127)
Linearity error: What is the percentage of difference
of the measurement value against the VC at the full-
scale of the ideal value.
EVR Le = (VCmeasure –VCidel)/3.6V
Differential linearity error: What is the percentage
of the difference between the variation width of the
ideal value and the difference from the variation
width of the ideal value (dVCidel) of the variation
width of the measurement value (dVCmeasure).
dVCidle = 12mV
Ideal Values
(Vcidel)
b
Measurement Values
(Vcmeasure)
dVCmeasure = VCmeasure (α = n + 1) –VCmeasure
(α = n)
VC(α=0)
EVR dLe = (dVCmeasure – dVCidel) /dVCidel
127
0
Electronic Volume Control
Values (α)
*6 Definition of temperature gradient is as follows.
Vc 50°C − Vc 0°C
(
)
(
)
1
CT =
×
×100
50°C − 0°C
Vc 25°C
(
)
26
EPSON
Rev.2.0
S1D17C02 Series
10.3 Operating current consumptions
While the built-in power supply is being turned OFF
Item
Symbol
Conditions
Standard
Min. Typ. Max.
Unit Note
Current consumption 1
ICC
VCC=1.7V
VCC=2.7V
VCC=3.7V
—
—
—
—
—
1.5
2.5
3.5
5.0 µA *7
7.0 µA *7
9.0 µA *7
Current consumption 2
Current consumption 3
IDDH
ISSL
VCC=VEVL=3.7, VDDH=V3L=12V
6.5 10.0 µA *7
5.5 10.0 µA *7
VCL=3V, VSSL=MV3L=–6V
While the built-in power supply is being turned ON
Item
Symbol
Conditions
Standard
Unit Note
Min. Typ. Max.
Current consumption 1
Current consumption 2
Current consumption 3
Current consumption 1a
Current consumption 2a
Current consumption 3a
Current consumption 1b
Current consumption 2b
Current consumption 3b
IOP1
IOP2
Boost rate M2=1, M1=1
Boost rate M2=2, M1=1
Boost rate M2=3, M1=1
Boost rate M2=1, M1=1.5
Boost rate M2=2, M1=1.5
Boost rate M2=3, M1=1.5
Boost rate M2=1, M1=2
Boost rate M2=2, M1=2
Boost rate M2=3, M1=2
—
—
—
—
—
—
—
—
—
40
50
60
50
70
90
70
95
60
80
90
70
µA *8
µA *8
µA *8
µA *9
IOP3
IOP1a
IOP2a
IOP3a
IOP1b
IOP2b
IOP3b
100 µA *9
120 µA *9
100 µA *10
130 µA *10
120 150 µA *10
*7 VIH = VCC, VIL = GND, fFR = 70Hz and 1/168duty no-load
*8 The load conditions are, no-load and the primary boosting circuit is not being used.
Using the electronic volume control, adjust to VEV = 3.6V and VC = 3.0V.
*9 The load conditions are, no-load and with the primary boosting circuit being set to ×1.5 boosting.
Using the electronic volume control, adjust to VCC = 2.4V and VC = 3.0V.
*10 The load conditions are, no-load and with the primary boosting circuit being set to ×2 boosting.
Using the electronic volume control, adjust to VCC = 1.8V and VC = 3.0V.
Rev.2.0
EPSON
27
S1D17C02 Series
10.4 AC characteristics of the driver section
(1) Input timing characteristics for the driver section
FR
t
t
FRDH
FRDS
F1, F2
CL
t
t
WCLH
FFDH
t
t
f
r
t
FFDS
t
t
DH
DS
t
t
WCLL
SET
t
CCL
CA, CI
The FR latched at the “n”th CL will be reflected to the output of the “n+1”th CL.
AC characteristic measurement conditions:
* Input signal level:
VIH = 0.8VCC
VIL = 0.2VCC
* Input signal rise time: Tr ≤ 10ns
* Input signal fall time: Tf ≤ 10ns
VCC = 1.7 to 3.7V
Ta = –40 to +85°C
Item
CL synchronization
CL HIGH-level pulse width
CL LOW-level pulse width
FR setup time
Symbol
tCCL
Conditions
Min.
800
140
660
200
40
200
40
200
40
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWCLH
tWCLL
tFRDS
tFRDH
tFFDS
tFFDH
tDS
FR hold time
F1 and F2 setup time
F1 and F2 hold time
CA (CI) setup time
CA (CI) hold time
tDH
tSET
CA (CI) to CL allowable time
150
28
EPSON
Rev.2.0
S1D17C02 Series
(2) Output timing characteristics for the driver section
CL
t
pdDOC
CO
t
pdCCL
DOFF
t
pdCDOF
COM Output
AC characteristic measurement conditions:
* Input signal level:
VIH = 0.8VCC
VIL = 0.2VCC
* Input signal rise time: Tr ≤ 10ns
* Input signal fall time: Tf ≤ 10ns
VCC = 1.7 to 3.7V
V3L = 16V to 14V
MV3L = –8V to 0V
Ta = –40 to +85°C
Item
Symbol
tpdDOC
tpdCCL
Conditions
CL=15 pF
Min.
Max.
600
500
Unit
ns
ns
CL to CO output delay time
CL to COM output delay time
DOFF to COM output delay time
tpdCDOF
1400
ns
Rev.2.0
EPSON
29
S1D17C02 Series
10.5 AC characteristics of the power supply section
AC characteristic measurement conditions:
* Input signal level:
VIH = 0.8VCC
VIL = 0.2VCC
* Input signal rise time: Tr ≤ 10ns
* Input signal fall time: Tf ≤ 10ns
VCC = 1.7 to 3.7V
Ta = –40 to +85°C
(1) PCL input timing
tWPCLH
tr
tf
PCL
tWPCLL
tCPCL
Item
Symbol Parameter
Min.
50
140
660
Max.
—
—
Unit
us
ns
PCL synchronization
PCL HIGH pulse width
PCL LOW pulse width
tCPCL
tWPCLH
tWPCLL
—
ns
(2) Clock input timing
tCVCL
tWVCLH
VCLK
tWVCLL
tVUDH
tVUDS
VU/D
Item
Symbol Parameter
Min.
50
140
660
500
500
Max.
—
—
—
—
Unit
ns
ns
ns
ns
VCLK synchronization
VCLK HIGH pulse width
VCLK LOW pulse width
VU/D setup time
tCVCL
tWVCLH
tWVCLL
tVUDS
VU/D hold time
tVUDH
—
ns
When changing the setting for the VU/D pin, do so at the timing when the VCLK pin signal is on the LOW level.
30
EPSON
Rev.2.0
S1D17C02 Series
(3) PSAVE input timing
PCA
tPSDS
tPSDH
PSAVE
tPSFIXH, tPSFIX
Item
Symbol Parameter
Min.
500
Max.
—
Unit
ns
PSAVE setup time
tPSDS
tPSDH
PSAVE hold time
500
—
ns
PSAVE LOW hold time
PSAVE HIGH hold time
tPSFIXL
tPSFIXH
4 × tCACYC
4 × tCACYC
—
—
(4) RES signal input timing
RES
tRW
tR
Internal Status
During Reset
Reset Completed
Item
Symbol
tRW
Parameter
Min.
1.5
—
Max.
—
1.5
Unit
µs
µs
Reset LOW pulse width
Reset completion time
tR
Rev.2.0
EPSON
31
S1D17C02 Series
11. THE POWER SUPPLY
11.1 Respective voltage levels
When supplying the VEV power separate from the VCC, always supply a potential equal to that of the VCC or more.
(Always maintain the relation of VEV ≥ VCC.)
11.2 Precautions when turning on and off the power supply
Since this LSI is for LCD’s of higher voltages, if the logic powers float or if the VCC vary widely while driving voltage
is being applied to the LCD or before the voltage being applied to the LCD stabilizes, excess current may flow to break
the LSI.
Always observe the following sequences when turning on and off the power supply.
When turning on the power supply
Step
Operation
Status ready to proceed to the next step
1
VCC turns ON.
VCC becomes stable.
2
SLP1, SLP2, DISCH
LOW → HIGH
When the LCD power supplies (VH, V1 to V3, VL, MV1 and
MV3) have been stabilized.
(Boosting starts.)
Although it is dependent upon the LCD module, about
100ms will be necessary. (Always check and confirm the
above using the actual module.)
3
DOFF LOW → HIGH
During Power Off
Step
Operation
Status ready to proceed to the next step
1
2
DOFF HIGH → LOW
SLP1, SLP2, DISCH
When the LCD power supplies (VH, V1 to V3,VL, MV1 and
HIGH → LOW
(Boosting stops.)
(Discharging starts.)
MV3) are start discharging.
Although it is dependent upon the LCD module, about
100ms will be necessary.
(Always check and confirm the above using the actual
module.)
3
VCC Off.
32
EPSON
Rev.2.0
S1D17C02 Series
11.3 Timings of sleep and electric discharge signal inputs
Use the following timing chart when enabling SLP1, SLP2 and DISCH signals.
tSLPFIXH, tSLPFIXL
SLP1, SLP2
DISCH
Item
Reference value
100(*3)
Unit
ms
Pin(s) applied
SLP1,SLP2
DISCH
Remarks
Holding time of Sleep HIGH
Holding time of Sleep LOW
*1
*2
100(*3)
ms
*1: Corresponds to the power startup time.
*2: Corresponds to the power discharging time.
*3: Reference value for the standard connections (12,2 Example 1 of detailed power block connections) with all external
capacitors having a rating of 1µF.
Since the startup and discharging times depend on the external capacitors and LCD panels, it is required to verify
these times on your machine.
Rev.2.0
EPSON
33
S1D17C02 Series
12. EXAMPLE OF CONNECTION
12.1 Block diagram of an LCD module
(1) VDD = VDDI
CO
CI
SHL
SEL
CSEL
TEST1
TEST2
PSAVE
DOFF
FR
F2
F1
132(R,G,B) × 168 dot
CL
CA
PCL
PCA
1/168 duty
V
U/D
VCLK
SLP1
SLP2
DISCH
RES
V2
V1
VC
MV1
V
V
CC
SS
132(R,G,B)out
S1D15912
MPU
I/F
VDDI = VDD
GND
Fig. 12.1-1
34
EPSON
Rev.2.0
S1D17C02 Series
(2) VDD × 0.8 ≥ VDDI
V
V
DD
SS
CO
CI
SHL
SEL
CSEL
TEST1
TEST2
PSAVE
DOFF
FR
F2
F1
132(R,G,B) × 168 dot
CL
CA
PCL
PCA
1/168 duty
V
V
U/D
CLK
SLP1
SLP2
DISCH
RES
V
V
V
2
1
C
MV
1
V
V
CC
SS
132(R,G,B)out
S1D15912
MPU
I/F
V
DDI
DD
V
GND
Fig. 12.1-2
Rev.2.0
EPSON
35
S1D17C02 Series
12.2 Detailed connection example 1 for the power block (Primary: ×1.5, Ternary: ×3)
From column
SKP
driver
V
to VDDH,V3L
3
V
U/D
V
V
U/D
MV
3
to VSSL,MV3L
V
CLK
CLK
TEST2
V
H
+
SLP
SLP2
TC0
TC1
TC2
CB3
V
HCP
+
+
CP3
CP4
V
HCN
CHC
V
LCP
RES
PCA
RES
PCA
V
LCN
V
V
L
To column
driver
PSAVE
PSAVE
+
CB4
+
2
V
2
STBY
SLP1
CNT
V
V
CB2
2C1P
+
+
CP2M
CP2S
2C1N
V
PCL
PCL
2C2P
2C2N
V
DISCH
V
1
V
1
+
+
+
V
+
+
V
EV
1CP
1CN
CBV1
+
CPV1
CB1
V
VEC1P
MV
1
MV
1
CP1S
VEC1N
VEC2P
VEC2N
MV
1CP
1CN
CPVM1
+
CPMV1
MV
CP1M
V
C
V
C
RV
R2
R1
to V
CL
TAP1
TAP2
+
System power
supply
CBVC
V
CC
GND
Fig. 12.2
[Settings]
Primary boosting ratio: M1 = ×1.5
Ternary boosting ratio: M2 = ×3
Internal resistance is unused.
36
EPSON
Rev.2.0
S1D17C02 Series
12.3 Recommended capacitance values of the using capacitors and theoretical formulae
for the voltage to be biased on both ends of each capacitor
Theoretical formulae for the
voltage to be biased on
both ends of each capacitor
Circuit Name
Function
Capacitor Capacitance • Electronic maximum
Name
values
(µF)
control at position
• Voltage of storage
capacitor to the GND
VCC – GND
VCC – GND
VEV = 2 × (VCC – GND)
When the primary boosting
circuit setting is M1 = ×2
Flying
CP1M
CP1S
CB1
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
1.0
1.0
1.0
1.0
1.0
1.0
Accumulate
Flying
When the primary boosting
circuit setting is M1 = ×1.5
CP1M
CP1S
CB1
CBVC
CP2M
CP2S
CPV1
CPMV1
CB2
0.5 × (VCC – GND)
0.5 × (VCC – GND)
VEV = 1.5 × (VCC – GND)
VEV – GND
Accumulate
Smothing
Flying
Electronic volume control circuit
Secondary boosting circuit
VEV – GND
VEV – GND
VEV – GND
VEV – GND
Accumulate
V2 = 2 × (VEV – GND)
V1 = 1.5 × (VEV – GND)
MV1 = 0.5 × (VEV – GND)
VEV – GND
CBV1
CBMV1
CP3
When the ternary boosting
circuit setting is M2 = ×2
When the ternary boosting
circuit setting is M2 = ×3
Quaternary booster circuit
Flying
Accumulate
Flying
Accumulate
Flying
CB3
CP3
CB3
CP4
VH = 3 × (VEV – GND)
2 × (VEV – GND)
VH = 4 × (VEV – GND)
4 × (VEV – GND)
VL = 3 × (VEV – GND)
Accumulate
CB4
Capacitance values for respective capacitors listed above ar recommended values in case the LCD panel size is 2.2" (1/
120duty). Also, “Section 10. Electric characteristics” are characteristics when the capacitance values are as
aforementioned. Consequently, when the LCD panel size is smaller then 2.2" or when the LCD panel being used can
be driven at a lower current level, the capacitance of the capacitor can be smaller. Nonetheless, since the output
impedance will increase in such case, be sure to check the picture quality and find out the capacitance value where the
LCD driving voltage can be stabilized.
The electronic volume control circuit and the V1 and MV1 generating circuits (= voltage follower) are being comprised
of au-pair pumps. Use of corresponding storage capacitors of larger capacity levels (a few µ-farads) will work to lower
the frequency characteristics to create conditions suppressing oscillations. However, be sure to make checks in this
regard with each application. Especially, when using storage capacitors of smaller capacitance levels, oscillations may
occur and perform careful and sufficient checks before finalizing the circuit design.
Rev.2.0
EPSON
37
S1D17C02 Series
12.4 Detailed connection example 2 for the power block (Primary: ×2, Ternary: ×3)
From column
SKP
driver
to VDDH,V3L
V
3
V
U/D
V
V
U/D
MV
to VSSL,MV3L
3
V
CLK
CLK
TEST2
V
H
+
SLP
SLP2
TC0
TC1
TC2
CB3
V
HCP
+
+
CP3
CP4
V
HCN
CHC
V
LCP
RES
PCA
RES
PCA
V
LCN
V
V
L
To column
driver
PSAVE
PSAVE
+
CB4
+
2
V
2
STBY
SLP1
CNT
V
V
CB2
2C1P
+
+
CP2M
CP2S
2C1N
V
PCL
PCL
2C2P
2C2N
V
DISCH
V
1
V
1
+
+
+
V
+
+
VEV
1CP
1CN
CBV1
+
CPV1
CB1
V
VEC1P
MV
1
MV
1
CP1S
VEC1N
VEC2P
VEC2N
MV
1CP
1CN
CPVM1
CPMV1
+
MV
CP1M
V
C
V
C
RV
to V
CL
TAP1
TAP2
+
System power
supply
CBVC
V
CC
GND
Fig. 12.4
[Settings]
Primary boosting ratio: M1 = ×2
Ternary boosting ratio: M2 = ×3
Internal resistance is used.
38
EPSON
Rev.2.0
S1D17C02 Series
12.5 Detailed connection example 3 for the power block (Primary boosting: Interrupted.
/Ternary boosting ratio: ×2)
From column
SKP
driver
V
to VDDH,V3L
3
V
U/D
V
V
U/D
MV
3
to VSSL,MV3L
V
CLK
CLK
TEST2
V
H
+
SLP
SLP2
TC0
TC1
TC2
CB3
V
HCP
+
+
CP3
CP4
V
HCN
CHC
V
LCP
RES
PCA
RES
PCA
V
LCN
V
V
L
To column
driver
PSAVE
PSAVE
+
CB4
+
2
V
2
STBY
SLP1
CNT
V
V
CB2
2C1P
+
CP2M
2C1N
V
PCL
PCL
+
2C2P
2C2N
V
CP2S
DISCH
V
1
V
1
+
V
+
V
EV
1CP
1CN
CBV1
+
CPV1
V
VEC1P
MV
1
MV
1
VEC1N
VEC2P
VEC2N
MV
1CP
1CN
+
CPVM1
MV
CPMV1
V
C
V
C
RV
to V
CL
TAP1
TAP2
+
System power
supply
CBVC
V
CC
GND
Fig. 12.5
[Settings]
Primary boosting ratio: M1 = ×1 (Use the VCC.)
Ternary boosting ratio: M2 = ×2
Internal resistance is used.
Rev.2.0
EPSON
39
S1D17C02 Series
12.6 Detailed connection example 4 for the power block (Interrupting the operations of
the primary, ternary and quaternary boosting circuits)
From column
SKP
driver
V
to VDDH,V3L
3
V
U/D
V
V
U/D
MV
3
to VSSL,MV3L
V
CLK
CLK
TEST2
V
H
SLP
SLP2
TC0
TC1
TC2
V
HCP
V
HCN
CHC
V
LCP
RES
PCA
RES
PCA
V
LCN
V
V
L
To column
driver
PSAVE
PSAVE
2
V
2
STBY
SLP1
CNT
+
V
V
CB2
2C1P
+
+
CP2M
CP2S
2C1N
V
PCL
PCL
2C2P
2C2N
V
DISCH
V
1
V
1
+
V
+
+
VEV
1CP
1CN
CBV1
CPV1
V
VEC1P
MV
1
MV
1
+
VEC1N
VEC2P
VEC2N
MV
1CP
1CN
CPVM1
CPMV1
MV
V
C
V
C
RV
to V
CL
TAP1
TAP2
+
System power
supply
CBVC
V
CC
GND
Fig. 12.6
Primary boosting circuit: Interrupted. M1 = ×1 (Use the VCC.)
[Settings]
Ternary and quaternary boosting circuits: Interrupted. M2 = ×1 (V2 = V3 and MV2 = MV3)
Internal resistance is used.
40
EPSON
Rev.2.0
S1D17C02 Series
13. CAUTIONS
Pay attention to the following points when using these development specifications.
1. The contents of these development specifications are subject to change without prior notice for improvement
purposes.
2. These development specifications are not meant to guarantee authorization for implementation of industrial
properties and any other rights nor do they approve licensing of relevant patents.
Application examples being introduced in these development specifications are for our customers to appreciate the
characteristics of this product and we will not hold ourselves responsible for any troubles occurring from circuits
employing these examples.
Meanwhile, the magnitudes of respective figures in the characteristics table are being represented by the magnitude
on the number line.
3. No part of these development specifications can be reproduced in any form without our permission nor can they be
copied for other purposes.
4. When using semiconductor elements, pay attention to the following points:
“Handling precautions relevant to light”
Semiconductor elements change their characteristics when light is irradiated upon them. Consequently, when this IC
is exposed to flight, malfunctioning may occur. To prevent occurrence of malfunctioning of the IC by the light, observe
the following precautions when designing a printed wiring board and product incorporating this IC:
(1) Design a structure which can provide sufficient shading effects over this IC when the product is actually used and
install the IC properly for said purposes.
(2) For inspection processes, make an environmental design considering the shading effects for the ICs having been
installed.
(3) When examining the shading effects for this IC, consider the shading effects over the front surface, rear surface and
side surfaces of the IC chips.
Rev.2.0
EPSON
41
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