SED1648D0A_技术文档

OVERVIEW

The SED1648 is an 80 output segment (column) driver which is suitable for driving a very high

capacity dot-matrix LCD panels.

It is intended to be used in conjunction with the SED1651 as a pair.

The SED1648 is featured in a high quality of picture in LCD display. It employs a high-speed enable

chain system which is favorable to a low-power driving. Allowed to be operated with a low voltage

in the logic system power supply, it can meet a wide range of applications.

FEATURES

• Number of LCD drive output segments: 80

• Low current consumption

• Low voltage operation: –2.7 V (Max.)

• Wide range of LCD drive voltages* –8 V to –28 V

• High-speed and low-power data transfer enabled by means of a

• 4-bit bus and chain enable support

Shift clock frequency+ 6.5 MHZ (at –2.7 V)

10.0 MHZ (at –4.5 V)

• Selectable pin output shift direction

• Adjustable offset bias of LCD power to a VDD level

• Logic system power supply: –2.7 V to –5.5 V

• Chip packaging SED1648D0A (AL-pad die form)

• No radial rays countermeasure taken in designing

SED1648 LCD Driver

6-1

BLOCK DIAGRAM

······································

LCD driver 80 bit

O 0

O79

V0

V5

V2

V3

VSS

V

DD

Level shifter 80 bit

Latch 80 bit

FR

DSPOSS

LP

Data register 80 bit

Enable shift register

D3 to D0

SHL

EIO2

XSCL

EIO1

6-2

SEIKO EPSON CORP.

PIN DESCRIPTION

Number

of pins

Pin name

O0 ~ O79

I/O

O

Function

Segment (column) output for LCD driving

The output changes at the LP falling edge.

80

D0 ~ D3

XSCL

LP

I

Display data input

4

1

Display data shift clock input (Falling edge trigger)

Display data latch pulse input (Falling edge trigger)

Enable input/output

To be set to input or output according to the SHL input level.

The output is reset by the LP input. Upon the end of fetching of

80-bit data, the system starts up automatically to “H”.

EIO1, EIO2

I/O

2

Shift direction selection and EIO pin I/O control input When data

is input to (D3, D2 ... D0) pins sequentially in order of (a3, a2, a1,

a0), (b3, b2, b1, b0) ... (t3, t2, t1, t0), the relationship between

the data and segment output becomes as shown in the table

below:

O Output

79 78 77

EIO

SHL

I

1

2

1

0

EIO1 EIO2

L

a3 a2 a1 . . . t2 t1 t0 Output Input

t0 t1 t2 . . . a1 a2 a3 Input Output

H

(Note) The relationship between the data and segment output is

determined irrespective of the number of shift clock

inputs.

LCD drive output AC converted signal input

FR

I

1

3

Logic power supply

VDD: 0 V VSS: –2.7 V to –5.5 V

VDD, VSS

Power supply

LCD drive circuit power supply

VDD: 0 V V5: –8 V to –28 V

VDD ≥ V0 ≥ V2 ≥ 6/9 V5

3/9 V5 ≥ V3 ≥ V5

V0, V2,

V3, V5

Power supply

I

8

1

*1

Forced blank input

DSPOFF

Making the “L” output into V0 level forcibly.

*1 Be sure to connect the V0 to V5 pair to their LCD power, respectively.

Total: 107 (including

five NC’ s

SED1648 LCD Driver

6-3

PAD LAYOUT AND COORDINATES

90

80

70

60

50

40

(0,0)

1

5

10

15

20

25

Chip size: ........................... 11.93 mm × 1.45 mm

Chip thickness:................... 0.400 mm (Typ.)

1) Au pad specifications (SED16480D0A)

Chip edge

161µm

178µm

(Min)

156µm-α

151µm-α

a

b

c

109µm

165µm-α

b

(Min)

180µm

Chip edge

Pad

a

b

c

Opening (X, Y)

100 × 120µm

110 × 110µm

PAD No 38 to 97

PAD No 28 to 37, 98 to 107

PAD No 1 to 27

6-4

SEIKO EPSON CORP.

Unit (µm)

PAD

NAME

Actual dimensions

PAD

NAME

Actual dimensions

PAD

NAME

Actual dimensions

NO.

1

X

Y

NO.

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

X

Y

NO.

77

X

Y

569

460

351

241

132

23

EIO2

V0

–5653

–5297

–5117

–4936

–4547

–4091

–560

–414

–305

–196

–86

O11

O12

O13

O14

O15

O16

O17

O18

O19

O20

O21

O22

O23

O24

O25

O26

O27

O28

O29

O30

O31

O32

O33

O34

O35

O36

O37

O38

O39

O40

O41

O42

O43

O44

O45

O46

O47

O48

5090

4911

4732

4554

4375

4197

4018

3839

3661

3482

3304

3125

2946

2768

2589

2411

2232

2053

1875

1696

1518

1339

1160

982

569

O49

O50

O51

O52

O53

O54

O55

O56

O57

O58

O59

O60

O61

O62

O63

O64

O65

O66

O67

O68

O69

O70

O71

O72

O73

O74

O75

O76

O77

O78

O79

–1696

–1875

–2053

–2232

–2411

–2589

–2768

–2946

–3125

–3304

–3482

–3661

–3839

–4018

–4197

–4375

–4554

–4732

–4911

–5090

–5268

–5653

–5814

–5653

–5814

–5653

–5814

–5653

–5814

–5653

–5814

2

78

3

V2

79

4

V3

80

5

V5

81

6

V^SS

82

7

DUMMY –3839

SHL –3587

83

8

84

9

DUMMY –3065

DUMMY –2828

85

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

86

V^DD

–2590

87

DSPOFF –2086

88

FR

LP

–1583

–1079

1079

1583

2086

2590

3065

3587

3839

4091

4594

4984

5164

5345

5653

5814

5653

5814

5653

5814

5653

5814

5653

5814

5653

5268

89

90

XSCL

D0

91

92

D1

93

D2

94

DUMMY

D3

95

96

DUMMY

V^SS

V5

97

98

99

V3

100

101

102

103

104

105

106

107

V2

803

V0

625

EIO1

O0

446

267

–86

–195

–305

–414

O1

89

O2

–89

O3

–267

–446

–625

–803

–982

–1160

–1339

–1518

O4

23

O5

132

O6

241

O7

351

O8

460

O9

569

O10

569

SED1648 LCD Driver

6-5

FUNCTIONAL DESCRIPTION

Enable shift register

This is a bidirectional shift register with which the shift direction is selected by SHL input. The

output of this shift register is used to store the data bus signals to data register.

When the enable signal is in the disable status, the internal clock signal and data bus are fixed to “L”

and the system is made into the power save mode.

When using two or more segment drivers, connect the EIO pin of each driver in a cascade

arrangement and the EIO pin of the leading driver to “VDD”. (See the connection example in 11.)

Since the enable controller circuit automatically detects that the data for 80 bits have been fetched

thoroughly and then transfers the enable signal to the controller, it is not necessary to provide the

control signal using the control LSI.

Data register

This is a register used to convert the data bus signal into serial or parallel signal through the enable

shift register output. Consequently, the relationship between the serial display data and segment

output is determined irrespective of the number of shift clock inputs.

Latch

This latch is used to fetch the content of data register at the LP falling edge trigger and to send its

output to the level shifter.

Level shifter

This is a level interface circuit used to convert the signal voltage level from the logic system level

to LCD drive level.

LCD driver

This driver outputs the LCD drive voltage.

The relationship among the data bus signal, AC converted signal FR and segment output voltage is

as shown in the table below:

Data bus

signal

DSPOFF

FR

O output voltage

H

L

V0

V5

V2

V3

V0

H

L

H

L

–

6-6

SEIKO EPSON CORP.

TIMING CHART

When the duty is 1/200 (Reference Example)

200

1

2

3

4

199

200

1

2

199

200

1

LP

LATCH

DATA

FR

LP

XSCL

20

1

2

3

20

D0 to D3

1

2

3

1

2

3

1

2

3

1

EIO

EIO 2

EIO 3

1 to 3 stand for a cascade No. of driver.

LP

LATCH

DATA

L

H

FR

H

L

DSPOFF

V

0

2

3

5

SED1648 LCD Driver

6-7

ABSOLUTE MAXIMUM RATINGS

VDD=0V

Parameter

Supply voltage (1)

Supply voltage (2)

Supply voltage (3)

Input voltage

Symbol

VSS

Rating

–7.0 to +0.3

Unit

V

V5

–30.0 to +0.3

V5–0.3 to VDD+0.3

VSS–0.3 to VDD+0.3

20

V

V0, V2, V3

VI

V

Output voltage

VO

V

EIO output current

Operating temperature

Storing temperature 1

IO

mA

°C

Topr

Tstg 1

–40 to + 85

–65 to +150

Notes:

1. The storage temperature 1 stipulates the temperature by unit of a chip.

2. The voltage of V0, V2 and V3 must always satisfy the condition of VDD ≥ V0 ≥ V2 ≥ V3 ≥ V5.

System side

V

DD

SS

V

DD

0

V_CC

–5V

GND

2

–28V

V

3

V₅

3. Floating of the logic system power during while the LCD drive system power is applied, or

exceeding VSS = –2.6 V can cause permanent damage to the LSI. Functional operation under

these conditions is not implied.

Care should be taken to the power supply sequence especially in the system power ON or OFF.

6-8

SEIKO EPSON CORP.

ELECTRICAL CHARACTERISTICS

DC characteristics

Unless otherwise specified, VDD = V0 = 0V, VSS = –5.0V±10% and Ta = –40 to 85°C.

Symbol

V^SS

Condition

–

Min.

–5.5

Typ.

–5.0

Max.

–2.7

Unit

V

Applicable pin

V^SS

Parameter

Supply voltage (1)

Recommended

operating voltage

V

V^SS=–2.7 to –5.5V

–28.0

–

–12.0

V5

Function

–

–8.0

V^DD

V

V5

V0

V2

V3

Operation enable voltage

Supply voltage (2)

Supply voltage (3)

Supply voltage (4)

V5

V0

V2

V3

–

Recommended value

V^DD–2.5

3/9V⁵

V5

VDD

6/9V5

EIO1, EIO2, FR,

D0 ~ D3, XSCL,

SHL, LP, DSPOFF

“H” input voltage

“L” input voltage

0.2VSS

–

V

VIH

VIL

V^SS=–2.7 to –5.5V

0.8V^SS

I

OH=–0.6mA

–

V

“H” output voltage

“L” output voltage

VOH

VOL

V^DD–0.4

–

VSS=–2.7 to –5.5V

EIO1, EIO2

IOL=0.6mA

VSS+0.4

Input leakage

current

D0 to D3, LP, FR

XSCL, SHL, DSPOFF

V^SS≤ VIN ≤ VDD

VSS ≤ VIN ≤ VDD

–

2.0

5.0

25

µA

ILI

ILI/O

ISS

–

Input/output

leakage current

EIO1, EIO2

V^SS

V5=–28.0 to –14.0V

V^IH=VDD, VIL=VSS

Static current

∆VON=0.5V Ta=25°C

V⁵=–20.0V V3=13/15·V5

V2=2/15·V5 V0=VDD

Output resistance

–

1.5

1.9

0.2

KΩ

RSEG

O0 to O79

VSS=–5.0V, VIH=VDD

VIL=VSS, fXSCL=2.69MHz

fLP=16.8KHz, fFR=70Hz

Input data: Dice display at no

0.10

Average operating

current

consumption (1)

mA

ISS

V^SS

load

- - - - - - - - - - - - - - - - - - - - - - -

- - - - - - - - - - - - - - - - - - - - - - - -

V^SS=–3.0V

–

0.07

0.15

Other conditions are the

same as V^SS= –5 V

V^SS=–5.0V,

V⁰=0.0V, V2=–9.3V

V³=–18.6V, V5=–28.0V

Other conditions are the

same as in the item of ISS.

Average operating

current

consumption (2)

0.02

0.05

mA

–

V5

I5

Input pin

capacitance

D0 to D3, LP, FR

XSCL, SHL, DSPOFF

–

8

pF

CI

–

Freq.=1MHz

Ta=25°C

By unit of a chip

Input/output pin

capacitance

CI/O

15

EIO1, EIO2

SED1648 LCD Driver

6-9

AC CHARACTERISTICS

Input timing characteristics

VIH=0.2 × VSS

VIL=0.8 × VSS

FR

tWLH

tDF

tLH

LP

tLD

tC

XSCL

tDS

tDH

tWCH

tWCL

D3 to D0

SUE

t

EI01,2

(IN)

VSS=–5.0V±0.5V, Ta=–40 to 85°C

Parameter

Symbol

Condition

Min.

100

30

Max.

Unit

ns

XSCL period

tC

tWCH

tWCL

tDS

tDH

tLD

tLH

tWLH

tDF

–

XSCL “H” pulsewidth

XSCL “L” pulsewidth

Data setup time

–

30

–

20

–

Data hold time

–

10

–

XSCL-rise to LP-rise time

LP-fall to XSCL-fall time

LP “H” pulsewidth

–

0

–

40

*3

–

40

–

Allowable FR delay time

EIO setup time

–900

35

+900

–

tSUE

–

VSS=–4.5V to –2.7V, Ta=–40 to 85°C

Parameter

Symbol

tC

Condition

Min.

Max.

Unit

ns

VSS=–2.7V *1

153

133

50

–

XSCL period

VSS=–3.0V *2

XSCL “H” pulsewidth

XSCL “L” pulsewidth

Data setup time

tWCH

tWCL

tDS

tDH

tLD

–

ns

–

50

–

30

–

Data hold time

–

15

–

XSCL-rise to LP-rise time

–

0

–

VSS=–2.7V

VSS=–3.0V

VSS=–2.7V *3

VSS=–3.0V *3

–

75

–

LP-fall to XSCL-fall time

tLH

ns

65

–

75

–

LP “H” pulsewidth

Allowable FR delay time

EIO setup time

tWLH

tDF

ns

65

–

–900

60

+900

–

VSS=–2.7V

VSS=–3.0V

tSUE

50

–

*1 Equivalent to 6.5 MHz

*2 Equivalent to 7.5 MHz

*3 tWLH stipulates the time when LP is “H” and XSCL is “L”.

*4 tr and tf of input signal are stipulated by unit of 20 ns.

6-10

SEIKO EPSON CORP.

Output timing characteristics

V

IH=0.2 × VSS

IL=0.8 × VSS

FR

t

FRSD

LP

t

LSD

t

ER

XSCL

t

DCL

V

IH=0.2 × VSS

OL=0.8 × VSS

EIO1, 2

(OUT)

O n

(SEG)

Vn–0.5

Vn+0.5

VDD=–5.0±0.5V, V5=–12.0 to –28.0V

Parament

EIO reset time

Symbol

tER

Condition

Min.

–

Max.

90

Unit

ns

CL=15pF (EIO)

CL=100pF (On)

EIO output delay time

LP to SEG output delay time

FR to SEG output delay time

tDCL

–

55

ns

tLSD

–

200

400

ns

tFRSD

–

ns

VDD=–4.5V to 2.7V, V5=–12.0 to –28.0V

Parament

Symbols

tER

Condition

Min.

Max.

Unit

ns

EIO reset time

–

150

85

CL=15pF

VSS=–2.7V

VSS=–3.0V

EIO output delay time

tDCL

(EIO)

ns

75

LP to SEG output delay time

FR to SEG output delay time

tLSD

400

800

ns

CL=100pF (On)

tFRSD

*1 tr and tf of input signal are stipulated by unit of 20 ns.

SED1648 LCD Driver

6-11

LCD DRIVE POWER

Each voltage level forming method

To obtain each voltage level for LCD driving, it is optimum to divide the resistance of potential

between V5 and VDD to drive the LCD using the voltage follower with an operational amplifier.

In taking into consideration of such a case using the operational amplifier, the maximum potential

level V0 for LCD driving has been made a separate pin from VDD. When the potential of V0 lowers

than that of VDD and the potential difference between the two becomes larger, however, the capacity

of LCD drive output driver lowers. To avoid it, use the system with the potential difference of 0 V

to 2.5 V between V0 and VDD.

When no operational amplifier is used, connect V0 and VDD close to the IC chip.

When a series resistance exists in the power supply line of V5 and VDD, a voltage drop of V5 and

VDD occurs at the LSI power supply pin, the relationship with the LCD’ s intermediate potential

(VDD ≥ V0 ≥ V2 ≥ V3 ≥ V5) cannot be met, this causing the LSI to be broken down in some cases.

When a protection resistor is inserted, it is necessary to stabilize the voltage by capacitance.

Note in power ON/OFF

Since this LSI is high in the voltage of LCD driving system, when a high voltage is applied to the

LCD driving system with the logic system power supply kept floating or above VSS =–2.6 V, and

when the LCD driving signal is output before the applied voltage to the LCD driving system is

stabilized, an overcurrent flows and LSI breaks down in some cases.

It is recommended to make the potential of LCD drive output into V0 level using the display off

function (DSPOFF) until the LCD driving system voltage is stabilized.

Be sure to follow the power ON/OFF sequence as shown below:

At power ON ... Logic system ON

→ LCD driving system ON or simultaneous ON of the

both

At power OFF ... LCD driving system OFF → Logic system OFF or simultaneous OFF of the both

For a countermeasure to such overcurrent, it is effective to put a high-speed melting fuse or

protection resistor in series with the LCD power unit.

It is then required to select the optimum value in the protection resistance according to the

capacitance of LC cell.

1

t

V

t

2

V

DD

t

VSS

>

3

=

1

t

2

t

0s

5

V

Power ON

Power OFF

t

3

V

DD

SS

t

V

DSPOFF

6-12

SEIKO EPSON CORP.

TYPICAL CIRCUIT DIAGRAM

Configuration Drawing of Large Screen LCD

V

SS

+

V

DD

V

0

1

r

+

–

+

–

2

3

R

r

+

–

+

–

V

4

5

r

V

5

1 0 0

S E D 1 6 5 1

1 0 0

S E D 1 6 5 1

SED1648 LCD Driver

6-13


型号：	SED1648D0A
厂家：	SEIKO EPSON CORPORATION
描述：	Liquid Crystal Driver, 80-Segment, CMOS 驱动接口集成电路
文件：	总13页 (文件大小：48K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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