GS12190 [SEMTECH]
Bidirectional 12G UHD-SDI Reclocking Adaptive Cable Equalizer/Cable Driver;
| 型号： | GS12190 |
| 厂家： | 
SEMTECH CORPORATION |
| 描述： | Bidirectional 12G UHD-SDI Reclocking Adaptive Cable Equalizer/Cable Driver |
| 文件： | 总121页 (文件大小：2881K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
GS12190
Bidirectional 12G UHD-SDI Reclocking
Adaptive Cable Equalizer/Cable Driver
Automatic input offset compensation
Key Features
•
•
Trace Driver Features:
•
Single bidirectional 75Ω cable interface with on-chip
termination
Integrated 100Ω differential output termination
DC-coupling from 1.2V to 2.5V CML logic
•
•
On-die connection between equalizer and cable
SMPTE ST 2082-1, ST 2081-1, ST 424, ST 292-1 and ST
259 compliant input/output
Trace Driver data output pre-emphasis to
compensate for up to 20”FR4 at 11.88Gb/s
•
•
Multi-standard operation from 1Mb/s to 11.88Gb/s
Manual or automatic Mute or Disable on LOS
Supports reclocking for DVB-ASI at 270Mb/s and MADI
at 125Mb/s
Reclocker features:
Manual or automatic rate modes
Manual or automatic Reclocker Bypass
Wide-range Loop Bandwidth control
•
•
•
3D Input Signal Eye Monitor
PRBS Generator and Checker
Automatic cable equalization. Typical equalized cable
lengths of Belden 1694A cable:
Reclocking at the following data rates: 125Mb/s,
270Mb/s, 1.485Gb/s, 2.97Gb/s, 5.94Gb/s, and
11.88Gb/s. This includes the f/1.001 rates.
70m at 11.88Gb/s
90m at 5.94Gb/s
170m at 2.97Gb/s
240m at 1.485Gb/s
400m at 270Mb/s
•
Additional Features:
Single 1.8V power supply for analogue and digital
core
2.5V for Cable Driver output supply
1.2V, 1.8V, or 2.5V for Trace Driver output supply
GSPI serial control and monitoring interface
•
•
•
Cable Equalizer Mode Features:
Improved reach with stress patterns
Four configurable GPIO pins for control or status
monitoring
Manual or automatic power-down on loss of signal
Programmable carrier detect with squelch
threshold adjustment
Wide operating temperature range: -40ºC to +85ºC
Small 6mm x 4mm 40-pin QFN
Manual and automatic Cable Equalizer Bypass
Pin compatible with the GS12090 and GS3590
Pb-free, Halogen-free, RoHS / WEEE compliant
Cable Driver Mode Features:
Wide swing control
Pre-emphasis to compensate for significant
insertion loss between device output and BNC
Applications
Next-generation 12G UHD-SDI infrastructures designed to
support UHDTV1, UHDTV2, 4K D-Cinema and 3D HFR and
HDR production image formats. Typical applications:
Cameras, Switchers, Distribution Amplifiers and Routers.
Manual or automatic power-down on loss of signal
Manual or automatic Mute or Disable on LOS
Trace Equalizer Features:
Integrated 100Ω differential input termination
Manual or automatic power-down on loss of signal
Adjustable carrier detect threshold
DC-coupling from 1.2V to 2.5V CML logic
Trace Equalization to compensate for up to 20”FR4
at 11.88Gb/s
GS12190
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With high phase consistency between scans and
configurable space and time thresholds, algorithms can be
deployed in the field to analyse long-term signal quality
variation (Bathtub Plot) to reduce costly system installation
debug time for intermittent errors.
Description
The GS12190 is a low-power, configurable multi-rate
reclocking Cable Equalizer/Cable Driver supporting rates
up to 12G UHD-SDI. It can be configured to equalize or drive
signals over 75Ω coaxial cable. It includes DC restoration to
compensate for the DC content of SMPTE pathological test
patterns. Since the GS12190 is a reclocking device,
extremely low output jitter is achievable even at extended
cable/trace lengths.
Each output has highly-configurable pre-emphasis and
swing controls to compensate for long trace and connector
losses.
Additionally, automatic and user selectable output slew
rate control is provided for the Cable Driver output.
The integrated Eye Monitor provides non-disruptive
mission mode analysis of the post-equalized input signal.
The 256x128 resolution scan matrix allows accurate signal
analysis to speed-up prototyping and enable field analysis.
The GS12190 is pin compatible with the GS12090 and
GS3590 Bidirectional 3G-SDI Reclocking Adaptive Cable
Equalizer/Cable Driver.
Built-in macros enable customizable cross section analysis
and quick horizontal and vertical eye opening
measurements.
CS SCLK SDIN SDOUT
GPIO1 GPIO2 GPIO3 GPIO4
Control & Status
Selector
Cable
Equalizer
Trace
Equalizer
DDI
Eye Monitor
Slicer
SDIO
Cable
Driver
Trace
Driver
Reclocker
Selector
Selector
DDO
Pre-emphasis
Pre-emphasis
PRBS Checker
PRBS
Generator
GS12190 Functional Block Diagram
GS12190
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Revision History
Version
ECO
PCN
Date
Changes and/or Modifications
3
2
051867
051393
—
—
May 2020
April 2020
Datasheet status changed to Final.
Changes made to Table 2-2: DC Electrical Characteristics.
“Re-timer”changed to “Reclocker”. Changes made to GS12190
Functional Block Diagram, Key Features, Table 2-1: Absolute
Maximum Ratings, Table 2-3: AC Electrical Characteristics, Figure
7-3: Marking Diagram. Data Sheet status changed to Preliminary.
1
0
047121
045796
—
—
November 2019
March 2019
New Document.
Contents
1. Pin Out.................................................................................................................................................................5
1.1 GS12190 Pin Assignment ................................................................................................................5
1.2 GS12190 Pin Descriptions ...............................................................................................................6
2. Electrical Characteristics................................................................................................................................9
2.1 Absolute Maximum Ratings ...........................................................................................................9
2.2 DC Electrical Characteristics ........................................................................................................ 10
2.3 AC Electrical Characteristics ......................................................................................................... 13
3. Input/Output Circuits.................................................................................................................................. 16
4. Detailed Description.................................................................................................................................... 18
4.1 Device Description .......................................................................................................................... 18
4.1.1 Bidirectional Mode Control.............................................................................................. 18
4.1.2 Sleep Mode............................................................................................................................ 18
4.2 Cable Equalizer ................................................................................................................................. 19
4.2.1 Cable Equalizer Bypass...................................................................................................... 19
4.2.2 Upstream Launch Swing Compensation.................................................................... 20
4.2.3 Carrier Detect, Squelch Control, and Loss of Signal ............................................... 20
4.3 Trace Equalizer ................................................................................................................................. 23
4.3.1 Input Trace Equalizer ......................................................................................................... 23
4.3.2 Carrier Detect, and Loss of Signal.................................................................................. 24
4.4 Serial Digital Reclocker .................................................................................................................. 26
4.4.1 PLL Loop Bandwidth Control.......................................................................................... 27
4.4.2 Automatic and Manual Rate Detection....................................................................... 27
4.4.3 Lock Time ............................................................................................................................... 28
4.5 PRBS Checker .................................................................................................................................... 30
4.5.1 Timed PRBS Check Measurement Procedure............................................................ 30
4.5.2 Continuous PRBS Check Measurement Procedure................................................. 32
4.6 Eye Monitor ........................................................................................................................................ 34
4.6.1 Scan Matrix and Measurement Time............................................................................ 35
4.6.2 Matrix-Scan and Shape-Scan Operation..................................................................... 37
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4.7 PRBS Generator ................................................................................................................................ 44
4.8 Output Drivers .................................................................................................................................. 47
4.8.1 Bypassed Reclocker Signal Output Control ............................................................... 47
4.8.2 Output Driver Polarity Inversion.................................................................................... 47
4.8.3 Output Driver Data Rate Selection................................................................................ 48
4.8.4 Amplitude and Pre-Emphasis Control ......................................................................... 49
4.8.5 Trace Driver DC-Coupling Requirements ................................................................... 58
4.8.6 Output State Control Modes........................................................................................... 59
4.9 GPIO Controls .................................................................................................................................... 61
4.10 GSPI Host Interface ....................................................................................................................... 61
4.10.1 CS Pin..................................................................................................................................... 61
4.10.2 SDIN Pin................................................................................................................................ 62
4.10.3 SDOUT Pin ........................................................................................................................... 62
4.10.4 SCLK Pin................................................................................................................................ 63
4.10.5 Command Word 1 Description.................................................................................... 64
4.10.6 GSPI Transaction Timing ................................................................................................ 66
4.10.7 Single Read/Write Access............................................................................................... 67
4.10.8 Auto-increment Read/Write Access........................................................................... 68
4.10.9 Setting a Device Unit Address...................................................................................... 69
4.10.10 Default GSPI Operation ................................................................................................ 70
4.10.11 Clear Sticky Counts Through Four Way Handshake .......................................... 71
4.10.12 Device Power-Up Sequence....................................................................................... 72
4.10.13 Host Initiated Device Reset......................................................................................... 73
5. Register Map................................................................................................................................................... 75
5.1 Control Registers ............................................................................................................................. 75
5.2 Status Registers ................................................................................................................................ 78
5.3 Register Descriptions ..................................................................................................................... 79
5.3.1 Control Register Descriptions......................................................................................... 79
5.3.2 Status Register Descriptions..........................................................................................110
6. Application Information...........................................................................................................................117
6.1 Typical Application Circuit .........................................................................................................117
7. Package & Ordering Information ..........................................................................................................118
7.1 Package Dimensions .................................................................................................................... 118
7.2 Recommended PCB Footprint ..................................................................................................119
7.3 Packaging Data ..............................................................................................................................119
7.4 Marking Diagram ...........................................................................................................................120
7.5 Solder Reflow Profile .................................................................................................................... 120
7.6 Ordering Information ...................................................................................................................120
GS12190
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1. Pin Out
1.1 GS12190 Pin Assignment
40
39
38
37
36
35
34
33
32
31
30
29
VEE_DDI
NC
1
2
3
4
5
6
7
8
28
27
26
25
24
23
22
21
VEEO
SDIO
SDI_TERM
VCC_DDI
TERM
SDO
GS12190
40-pin QFN
6mm x 4mm
VCCO_0
VCCO_1
DDO
DDI
DDI
DDO
VEE_DDI
VEEO
9
10
11
12
13
14
15
16
17
18
19
20
Figure 1-1: GS12190 Pin Assignment
GS12190
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1.2 GS12190 Pin Descriptions
Table 1-1: GS12190 Pin Descriptions
Pin Number
Name
Type
Description
Most negative power supply connection for the Cable Equalizer and
Trace Equalizer.
1, 8
VEE_DDI
Power
Connect to ground.
2, 30
3
NC
—
—
Not internally connected.
Input Common Mode termination. Decouple to ground (see
Section 6.1 Typical Application Circuit for recommended values).
SDI_TERM
Most positive power supply connection for the Trace and Cable
Equalizer.
4
VCC_DDI
Power
Connect to 1.8V.
Input Common Mode termination. Decouple to ground (see
Section 6.1 Typical Application Circuit for recommended values).
5
TERM
DDI, DDI
RSVD
—
Input
—
Serial digital differential input. Differential CML input with internal
100Ω termination.
6, 7
9, 32
These pins may be left floating. Please contact your Semtech FAE for
additional information on circuit compatibility with the GS12190.
Chip Select input for the Gennum Serial Peripheral Interface (GSPI)
host control/status port.
1.8V CMOS input with 100kΩ pull-up.
Active-low input.
10
CS
Digital Input
Refer to Section 4.10.1 for more details.
Serial digital data input for the Gennum Serial Peripheral Interface
(GSPI) host control/status port.
11
12
13
SDIN
SDOUT
SCLK
Digital Input
Digital Output
Digital Input
1.8V CMOS input with 100kΩ pull-down.
Refer to Section 4.10.2 for more details.
Serial digital data output for the Gennum Serial Peripheral Interface
(GSPI) host control/status port.
1.8V CMOS output.
Refer to Section 4.10.3 for more details.
Burst-mode clock input for the Gennum Serial Peripheral Interface
(GSPI) host control/status port.
1.8V CMOS input with 100kΩ pull-down.
Refer to Section 4.10.4 for more details.
Most negative power supply for digital core logic.
Connect to ground.
14, 15
16
VSS
Power
Power
Most positive power supply connection for digital core logic.
Connect to 1.8V.
VDD
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Table 1-1: GS12190 Pin Descriptions (Continued)
Pin Number
Name
Type
Description
Multi-function Control/Status Input/Output 0.
Default function:
Digital
Input/Output
Direction = Output
Signal = High indicates LOS (Loss of Signal, inverse of Carrier Detect)
17
GPIO0
Pin is 1.8V CMOS I/O, please refer to GPIO0_CFG for more information
on how to configure GPIO0.
Multi-function Control/Status Input/Output 1.
Default function:
Digital
Input/Output
Direction = Output
Signal = High indicates PLL is locked
18
GPIO1
Pin is 1.8V CMOS I/O, please refer to GPIO1_CFG for more information
on how to configure GPIO1.
Most negative power supply connection for the analogue core.
Connect to ground.
19, 31, 37, 38
20
VEE_CORE
VCCO1P8_1
VEEO
Power
Power
Power
Most positive power supply connection for Trace Driver pre-driver.
Connect to 1.8V.
Most negative power supply connection for the output drivers.
Connect to ground.
21, 28
Differential CML output with two internal 50Ω pull-ups.
22, 23
24
DDO, DDO
VCCO_1
Output
Power
In cable equalizer mode, the data signal or PRBS Generator can be
selected for this output.
Most positive power supply connection for the DDO/ DDO output
driver.
Connect to 1.2V – 2.5V.
Most positive power supply connection for the SDIO/SDO output
driver.
25
26
VCCO_0
SDO
Power
Connect to 2.5V.
Single-ended CML output buffer with internal 75Ω pull-up. Decouple
to ground (see Section 6.1 Typical Application Circuit for
recommended values).
Output
Single-ended bidirectional CML buffer with internal 75Ω pull-up.
27
29
SDIO
Output
Power
In cable driver mode, the data signal or PRBS Generator can be
selected for this output.
Most positive power supply connection for Cable Driver pre-driver.
Connect to 1.8V.
VCCO1P8_0
Multi-function Control/Status Input/Output 2.
Default function:
Digital
Input/Output
Direction = Input
Signal = Set HIGH to put device in sleep
33
GPIO2
Pin is 1.8V CMOS I/O, please refer to GPIO2_CFG for more information
on how to configure GPIO2.
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Table 1-1: GS12190 Pin Descriptions (Continued)
Pin Number
Name
Type
Description
VCO filter capacitor connection. Decouple to ground. See Section 6.1
Typical Application Circuit for recommended values.
34
VCO_FILT
Passive
Most positive power supply connection for the analogue core.
Connect to 1.8V.
35
36
VCC_CORE
GPIO3
Power
Multi-function Control/Status Input/Output 3.
Default function:
Digital
Input/Output
Direction = Input
Signal = Set HIGH to put device in cable driver mode
Pin is 1.8V CMOS I/O, please refer to GPIO3_CFG for more information
on how to configure GPIO3.
Loop filter capacitor connection. Connect to pin 40 through a
capacitor (see Section 6.1 Typical Application Circuit for
recommended values).
39
40
LF+
LF-
Passive
Passive
Loop filter capacitor connection. Connect to pin 39 through a
capacitor (see Section 6.1 Typical Application Circuit for
recommended values).
Central paddle can be connected to ground or left unconnected. Its
purpose is to provide increased mechanical stability. It is not required
for thermal dissipation. It is not recommended to connect the device
ground pins to the central paddle.
Tab
—
—
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2. Electrical Characteristics
2.1 Absolute Maximum Ratings
Table 2-1: Absolute Maximum Ratings
Parameter
Value
Supply Voltage—Core (VCC_DDI
,
-0.5V to +2.2V
-0.5V to +2.8V
VCC_CORE, VDD
)
VCCO_0
VCCO_1
Supply Voltage—Output Driver
-0.5V to +2.8V
2kV HBM
Input ESD Voltage (any pin)
Storage Temperature Range (TS)
-50°C to +125°C
-0.3V to 2.6V
Input Voltage Range (SDIO)
-0.3V to (VCC_CORE + 0.3)V
Input Voltage Range (GPIO2, GPIO3)
Input Voltage Range (CS, SDIN, SCLK,
VSS, VDD, GPIO0, GPIO1)
-0.3V to (VDD +0.3)V
260°C
Solder Reflow Temperature
Note: Absolute Maximum Ratings are those values beyond which damage may occur.
Functional operation outside of the ranges shown in the AC/DC electrical characteristics
tables is not guaranteed.
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2.2 DC Electrical Characteristics
Table 2-2: DC Electrical Characteristics
TA = -40°C to +85°C, unless otherwise shown.
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Notes
Bi-Directional Characteristics (Applicable to Both Modes)
VCC_DDI
VCC_CORE, VDD
,
Supply Voltage
—
1.71
—
1.8
1.89
—
V
—
—
DDI Input and DDO
Output Termination
Differential
100
Ω
SDIO Bi-directional
Termination
Between SDIO and GND
Between SDO and GND
—
—
—
75
75
—
—
—
Ω
Ω
—
—
—
SDO Output Termination
Reclocker Unlocked During
Rate Search
182
mA
Supply Current—
Analogue Core
PRBS Generator Enabled
PRBS Checker Enabled
Eye Monitor Enabled
—
—
—
119
60
—
—
—
mA
mA
mA
2, 3
2
ICC_CORE
54
2
Supply Current—
Digital Logic
IDD
—
—
—
16
—
20
mA
V
—
—
0.65*
VDD
VIH
VDD
Input Voltage—Digital Pins
(CS, SDIN, SCLK, GPIO[0:1])
0.35*
VDD
VIL
VIH
VIL
—
—
—
0
—
—
—
V
V
V
—
—
—
0.65*
VCC_CORE
VCC_CORE
Input Voltage—Digital Pins
(GPIO[2:3])
0.35*
VCC_CORE
0
VDD -
0.45
VOH
VOL
VOH
VOL
IOH = -5mA
IOL = +5mA
IOH = -5mA
IOL = +5mA
—
—
—
—
—
0.45
—
V
V
V
V
—
—
—
—
Output Voltage—Digital Pins
(SDOUT, GPIO[0:1])
—
VCC_CORE
- 0.45
Output Voltage—Digital Pins
(GPIO[2:3])
—
0.45
Cable Equalizer Mode Characteristics
1.14
1.2
1.8
2.5
1.26
1.89
2.63
V
V
V
—
—
—
Supply Voltage—Trace
Driver
VCCO_1
1.71
2.38
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Table 2-2: DC Electrical Characteristics (Continued)
TA = -40°C to +85°C, unless otherwise shown.
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Notes
VCCO_1 = 1.2V,
Output Swing = 400mVppd
DDO/DDO enabled
,
,
,
,
,
—
430
—
mW
1
VCCO_1 = 1.8V,
Output Swing = 400mVppd
DDO/DDO enabled
—
—
—
—
440
455
445
470
—
—
—
—
mW
mW
mW
mW
1
1
1
1
VCCO_1 = 1.8V,
PD
Power
Output Swing = 800mVppd
DDO/DDO enabled
VCCO_1 = 2.5V,
Output Swing = 400mVppd
DDO/DDO enabled
VCCO_1 = 2.5V,
Output Swing = 800mVppd
DDO/DDO enabled
VCCO_1 = 1.2V,
Output Swing = 400mVppd
—
—
—
—
—
10
10
20
10
20
17
17
30
17
30
mA
mA
mA
mA
mA
1
1
1
1
1
VCCO_1 = 1.8V,
Output Swing = 400mVppd
VCCO_1 = 1.8V,
Output Swing = 800mVppd
ICCO_1
Supply Current—Trace Driver
VCCO_1 = 2.5V,
Output Swing = 400mVppd
VCCO_1 = 2.5V,
Output Swing = 800mVppd
Supply Current — Trace
Driver Pre Driver
ICCO_1P8_1
Output Swing = 800mVpp
—
—
25
32
18
mA
mA
—
—
VCCO_0 = 2.5V,
Output Swing = 800mVppd
Supply Current — VCCO_0
ICCO_0
13
55
Supply Current—
Cable Equalizer
ICC_SDI
ICC_CORE
VCMOUT
—
—
—
—
75
161
—
mA
mA
V
—
—
—
Supply Current—
Analogue Core
Reclocker Locked to Rate
125
DDO Output Common
Mode Voltage
VCCO_1 -
ΔVDDO/2
—
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Table 2-2: DC Electrical Characteristics (Continued)
TA = -40°C to +85°C, unless otherwise shown.
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Notes
Cable Driver Mode Characteristics
Supply Voltage — Cable
Driver
VCCO_0
—
2.38
—
2.5
2.63
—
V
—
1
VCCO_0 = 2.5V,
Output Swing = 800mVpp
,
375
mW
DDO/DDO disabled
PD
Power
VCCO_0 = 2.5V,
Output Swing = 800mVpp
with max pre-emphasis,
DDO/DDO disabled
—
390
—
mW
—
VCCO_0 = 2.5V,
Output Swing = 800mVpp
—
—
25
30
36
38
mA
mA
1
Supply Current—
Cable Driver
ICCO_0
VCCO_0 = 2.5V,
Output Swing = 800mVpp
,
—
with max pre-emphasis
Supply Current — Cable
Driver Pre Driver
ICCO1P8_0
ICC_CORE
ICC_DDI
Output Swing = 800mVpp
—
—
20
120
20
30
164
32
mA
mA
mA
V
—
—
—
4
Supply Current—
Analogue Core
Reclocker Locked to Rate
Supply Current — Trace
Equalizer
—
—
DDI Input Common
Mode Voltage
VCMIN
—
—
0.94
—
2.525
—
SDO Output Common Mode
Voltage
VCCO_0 -
VCMOUT
Single-Ended
—
VSDO/2
Sleep Mode
Cable Equalizer mode
Cable Driver mode
Sleep
Sleep
—
—
80
45
—
—
mW
mW
—
—
Notes:
1. Pre-emphasis is disabled.
2. Current listed is an increase to ICC_CORE when stated condition is true.
3. Selected clock source = VCO free running.
4. 0.94V is when the Trace Equalizer is DC-coupled to upstream driver running from 1.2V supply, and 2.525V is when Trace Equalizer is DC-coupled to
upstream driver running from 2.5V supply.
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2.3 AC Electrical Characteristics
Table 2-3: AC Electrical Characteristics
VCC_DDI, VCC_CORE, VDD = +1.8V ±5% and VCCO_0, VCCO_1 = +2.5V ±5%, TA = -40°C to +85°C, unless otherwise shown.
Parameter
Symbol
Conditions
Min
Typ
Max
Units Notes
Bi-Directional Characteristics (Applicable to Both Modes)
DRDDI, DRSDIO
Serial Input Data Rate
—
0.001
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
11.88
-17
-12
-8
Gb/s
dB
12
1
1
1
1
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5MHz to 1.485GHz
1.485GHz to 2.97GHz
2.97GHz to 5.94GHz
5.94GHz to 11.88GHz
Setting 0.0625x
Setting 0.125x
Setting 0.25x
—
dB
Return Loss
—
dB
—
-5
dB
5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
MHz
MHz
kHz
kHz
MHz
MHz
MHz
kHz
MHz
MHz
MHz
MHz
10
BWLOOP(125Mb/s)
BWLOOP(270Mb/s)
BWLOOP(1.485Gb/s)
BWLOOP(2.97Gb/s)
BWLOOP(5.94Gb/s)
BWLOOP(11.88Gb/s)
19
Setting 0.5x (Default)
Setting 1.0x
38
75
Setting 0.0625x
Setting 0.125x
Setting 0.25x
10
20
40
Setting 0.5x
80
Setting 1.0x (Default)
Setting 0.0625x
Setting 0.125x
Setting 0.25x
158
55
110
220
438
875
110
220
440
0.88
1.75
220
440
0.88
1.75
3.5
440
0.88
1.75
3.5
7.0
Setting 0.5x (Default)
Setting 1.0x
PLL Loop Bandwidth
Setting 0.0625x
Setting 0.125x
Setting 0.25x
Setting 0.5x (Default)
Setting 1.0x
Setting 0.0625x
Setting 0.125x
Setting 0.25x
Setting 0.5x (Default)
Setting 1.0x
Setting 0.0625x
Setting 0.125x
Setting 0.25x
Setting 0.5x (Default)
Setting 1.0x
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Table 2-3: AC Electrical Characteristics (Continued)
VCC_DDI, VCC_CORE, VDD = +1.8V ±5% and VCCO_0, VCCO_1 = +2.5V ±5%, TA = -40°C to +85°C, unless otherwise shown.
Parameter
Symbol
Conditions
Min
Typ
Max
Units Notes
Cable Equalizer Mode Characteristics
VSDIO
mVpp
mVppd
mVppd
BNC Input Voltage Swing
—
720
150
600
800
200
800
880
250
3
7
8
200mV
800mV
Differential Output
Voltage Swing
VDDO
1000
triseDDO
tfallDDO
,
DDO, DDO, Rise/Fall Time
All rates
—
—
40
ps
11
DDO Mismatch in
Rise/Fall Time
—
—
—
—
—
—
—
—
75
8
ps
ps
11
—
6
DDO Duty Cycle Distortion
DDO, DDO
10
—
PLL Lock Time —
Asynchronous
tALOCK
tSLOCK
ms
SD
—
—
—
—
—
10
2
µs
µs
UI
6
6
PLL Lock Time —
Synchronous
HD/3G/UHD
Belden 1694A: 400m
tOJ(125Mb/s)
tOJ(270Mb/s)
tOJ(1.485Gb/s)
tOJ(2.97Gb/s)
tOJ(5.94Gb/s)
tOJ(11.88Gb/s)
0.02
0.1
2, 14
Belden 1694A: 400m
Belden 1694A: 240m
—
—
—
—
—
0.04
0.04
0.05
0.1
0.1
0.1
UI
UI
UI
UI
UI
2, 14
2, 14
2, 14
2, 14
14
Serial Data Output Jitter (DDO)
Belden 1694A: 170m
0.1
Belden 1694A: 90m
0.15
0.15
Belden 1694A: 70m
0.07
Cable Driver Mode Characteristics
Differential Input
Voltage Swing
VDDI
mVppd
mVpp
—
200
—
800
13
V
SDIO, VSDO
BNC Output Voltage Swing
Single Ended
720
—
800
20
880
—
—
—
—
—
—
—
—
4
9
12G
Inches
Inches
Inches
Inches
Inches
Inches
UI
6G
—
30
9
3G
—
60
9
Loss Compensation (Input
Trace Equalization)
HD
—
60
9
SD
—
60
9
MADI
—
60
9
12G
0.7
0.8
0.85
0.95
—
—
Intrinsic Input Jitter Tolerance
IIJT
MADI/SD/HD/3G/6G
UI
All rates enabled, except
MADI.
—
—
16.7
ms
6
PLL Lock Time—
Asynchronous
tALOCK
All rates enabled.
SD
—
—
—
—
—
—
—
—
32
10
ms
µs
µs
ps
ps
ps
6
6
tSLOCK
PLL Lock Time—Synchronous
SDIO, SDO Rise/Fall Time
HD/3G/6G/12G
SD/MADI
—
5
6
400
—
1000
70
—
—
—
t
riseSDIO, tfallSDIO
HD/3G
6G/12G
—
40
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Table 2-3: AC Electrical Characteristics (Continued)
VCC_DDI, VCC_CORE, VDD = +1.8V ±5% and VCCO_0, VCCO_1 = +2.5V ±5%, TA = -40°C to +85°C, unless otherwise shown.
Parameter
Symbol
Conditions
SD/MADI
HD/3G
Min
—
Typ
—
Max
100
20
10
5
Units Notes
ps
ps
ps
%
%
%
%
UI
—
—
—
SDIO Mismatch
in Rise/Fall Time
—
—
6G/12G
SD/MADI
HD/3G
—
—
—
—
SDIO Eye Cross Shift
(SDIO, SDO)
—
—
8
—
—
6G/12G
—
—
—
9
SDIO Overshoot
—
—
10
0.08
—
tOJ(125Mb/s)
tOJ(270Mb/s)
tOJ(1.485Gb/s)
tOJ(2.97Gb/s)
tOJ(5.94Gb/s)
tOJ(11.88Gb/s)
tOJ(Bypass)
—
0.015
2, 10
—
—
—
—
—
—
0.035
0.025
0.04
0.04
0.1
0.08
0.08
0.08
0.1
UI
UI
UI
UI
UI
UI
2, 10
2, 10
2, 10
2, 10
2, 10
2, 10
BW = default,
Pattern = PRBS
Serial Data Output Jitter (SDIO)
0.16
0.2
0.1
Notes:
1. Values achieved with Semtech evaluation board and connector.
2. Measured using a clean input source.
3. Default value for CFG_EQ_INPUT_LAUNCH_SWING_COMP parameter in control register 0x18. The default parameter value is 80d (50h).
4. Default Cable Driver swing Setting.
5. Please see PLL_LOOP_ BANDWIDTH_ 0 for the full range of loop bandwidth settings.
6. Please see Section 4.4.3.1 for the further definition on Synchronous and Asynchronous Lock Time.
7. Output driver setting of 8.
8. Output driver setting of 36.
9. Trace insertion loss was measured with FR4 material using 7 mil strip-line traces using a PRBS23 signal.
10. Measured under minimal trace loss conditions.
11. Rise/fall time was measured between 80% and 20%.
12. When in Cable Equalizer Mode, the rise/fall time of signals at the source should not be more than 62ns.
13. Stated minimum and maximum voltages represent voltage levels at input pins.
14. Max jitter occurs at the maximum cable length.
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3. Input/Output Circuits
VCC_DDI
VCC_DDI VCC_DDI
DDI
RLC
RLC
50Ω
50Ω
TERM
DDI
Figure 3-1: DDI, DDI
VCCO_0
RLC
VCCO_0
VCCO_0
VCCO_1
VCCO_1
VCCO_1
RLC
75Ω
75Ω
50Ω
50Ω
SDIO
SDO
DDO
DDO
Figure 3-2: DDO/DDO
Figure 3-3: SDIO, SDO
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VDD
VDD
VDD
VDD
VDD
100kΩ
SDIN,
SCLK
CS
100kΩ
Figure 3-4: SDIN, SCLK
Figure 3-5: Chip Select (CS)
VCC_IO*
VCC_IO*
VCC_IO*
1kΩ
GPIO[0:3]
VDD
VDD
100kΩ
VCC_IO*
SDOUT
Note: VCC_IO makes reference to the following power supplies and pins:
VCC_IO = VDD for GPIO[0:1]
VCC_IO = VCC_CORE for GPIO[2:3]
Figure 3-6: SDOUT
Figure 3-7: GPIO[0:3]
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4. Detailed Description
4.1 Device Description
The GS12190 features a 75Ω internally-terminated bidirectional SDIO port, which can be
set as SMPTE-compliant Cable Driver or Cable Equalizer. In addition to the SDIO port,
there is a 100Ω differential Trace Driver to transmit the incoming SDI signal to the
system and a 100Ω differential Trace Equalizer to receive the outgoing signal from the
system. The bidirectional mode can be controlled through the host interface, or the
GPIO pin. The Cable Driver has amplitude and pre-emphasis control to compensate for
significant insertion loss between device output and BNC. The Trace Driver also has
amplitude and pre-emphasis control which can compensate for 15dB of insertion loss at
5.94GHz. The pre-emphasis control is two-dimensional in both the Cable Driver and
Trace Driver, where both pre-emphasis pulse amplitude and width adjustments can be
made to help optimize for interconnect mismatches such as vias and connectors. The
Trace Equalizer has boost control, which can compensate for 17dB of insertion loss at
5.94GHz.
4.1.1 Bidirectional Mode Control
The bidirectional mode of the GS12190 can be controlled through the GPIO or the host
interface.
By default the device is in pin control mode and GPIO3 is the control input pin. To put
the device in Cable Equalizer Mode drive this pin LOW. To put the device in Cable Driver
Mode, drive this pin HIGH.
In addition to GPIO control, the host can set the direction mode through the host
interface using the CTRL_DIRECTION_SEL_MODE and CTRL_DIRECTION_SEL
parameters in register 0x14h. To use the host interface to control the direction mode,
first choose host interface select mode by writing 1b to CTRL_DIRECTION_SEL_MODE
(default = 0b pin mode). Once the device is in host interface select mode, the host can
put the device in cable equalizer mode by writing 0b to the CTRL_DIRECTION_SEL
control parameter (default = 1b cable driver mode).
4.1.2 Sleep Mode
To enable low-power operation, the GS12190 has Manual and Automatic Sleep Mode
control.
The default mode is Automatic Sleep Mode on LOS (Loss Of Signal). The device can also
be manually put into Sleep Mode. When the device is in Sleep Mode, all the core blocks
are powered-down, except the host interface and carrier detect circuits. The SDIO Cable
Driver output buffer is always disabled (powered-down) in sleep mode, while the DDO
Trace Driver can be disabled or muted.
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The CTRL_AUTO_SLEEP and CTRL_MANUAL_SLEEP parameters in register 0x3h,
control the sleep mode of the device. The default value of the CTRL_AUTO_SLEEP
parameter is 1b (Auto Sleep). While in Auto Sleep Mode, the CTRL_MANUAL_SLEEP
parameter has no effect. To enable host control of the sleep mode, set the
CTRL_AUTO_SLEEP parameter to 0b for Manual Sleep Control. To prevent the device
from entering sleep, set the CTRL_MANUAL_SLEEP parameter to 0b (not sleep). To
manually configure the device to sleep, set the CTRL_MANUAL_SLEEP parameter to 1b
(sleep).
The device can also be manually made to sleep through the GPIO pins. The default GPIO
pin to control sleep is GPIO2 (pin 33). Drive this pin HIGH to make the device sleep.
Section 4.7 describes the PRBS Generator function. If the device's PRBS Generator is
intended to be used without a valid input signal, the device should be manually set to
not sleep as described above. Without a valid input signal, an LOS status will be
generated and the device will enter sleep mode and the PRBS block will be disabled. For
a description of LOS thresholds and settings, see Section 4.2.3 and Section 4.3.2.
4.2 Cable Equalizer
When the GS12190 is operating in Cable Equalizer Mode, it can automatically adjust its
gain to equalize and restore SMPTE-compliant signals received over different lengths of
coaxial cable having loss characteristics similar to Belden 1694A. With the default
settings, the device will automatically equalize MADI at 125Mb/s and most common
SMPTE-compliant signals between SD at 270Mb/s and UHD-SDI at 11.88Gb/s and
bypass signals below 125Mb/s.
The GS12190 features programmable Launch Swing Compensation, Squelch Threshold
Adjust, and Bypass, all of which can be set through the device's host interface.
The equalized or bypassed signal is then routed to the serial digital reclocker block.
Note: Section 4.2 to Section 4.2.3.2 are only applicable to the Cable Equalizer input
(SDIO).
4.2.1 Cable Equalizer Bypass
With the default settings, the device will automatically bypass signals below 125Mb/s.
During cable equalizer bypass mode, the device supports low data rate and slow edge
signals such as SMPTE310 and AES3id. The rise/fall times must not exceed 62ns. While in
cable equalizer bypass mode, signals will not be reclocked by the reclocker block.
To force the device to bypass the cable equalizer, DC restoration stage, and reclocker,
the following two methods can be used:
Host Interface Control:
Set the following parameters in register 17h
•
•
CTRL_CEQ_AUTO_BYPASS = 0
CTRL_CEQ_MANUAL_BYPASS = 1
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GPIO Control:
1. Configure a GPIO as an input by writing 0h to CFG_GPIO<n>_OUTPUT_ENA.
2. Configure the GPIO function as “cable equalizer bypass enable,”by writing 84h to
CFG_GPIO<n>_FUNCTION.
3. Drive the selected GPIO pin HIGH.
Note: The <n> in the control parameter names refers to the GPIO pin number.
4.2.2 Upstream Launch Swing Compensation
The GS12190 Cable Equalizer has an automatic gain control circuit, that is optimized on
the assumption that the Cable Driver in the upstream device is SMPTE-compliant and
has a launch swing of 800mVpp ±10%. When the source amplitude is known to be
non-SMPTE-compliant, a compensation adjustment can be made in the GS12190. The
GS12190 can adjust for launch swings in the range of 250mV to 1V in approximately
50mVppd increments. Upstream launch swing compensation can be adjusted through
the CFG_EQ_INPUT_LAUNCH_SWING_COMP parameter in control register 0x18. The
default parameter value is 80d (50h), which corresponds to a nominal launch swing of
800mVppd
.
4.2.3 Carrier Detect, Squelch Control, and Loss of Signal
The GS12190 Cable Equalizer has highly-configurable carrier detection and squelching
capability. The carrier detection can be made more robust against spurious signals and
noise at the inputs and the squelch control can be configured and enabled to reduce
false outputs to low level signals such as crosstalk.
The GS12190 reports two separate carrier detect parameters—STAT_PRI_CD and
STAT_SEC_CD. They are described in Section 4.2.3.1 and Section 4.2.3.2 respectively.
Note: The parameters referred to within Section 4.2.3 to Section 4.2.3.2 are linked to
their respective registers in Table 4-1.
4.2.3.1 Primary Carrier Detection (STAT_PRI_CD) Configuration
Primary carrier detection (STAT_PRI_CD) can be configured for higher stability by
filtering out longer transients or glitches. This can be achieved by increasing the
sampling window over which the signal is sampled and the number of samples required
to assert or de-assert it.
There are three configuration parameters that control assertion or de-assertion of
STAT_PRI_CD:
CFG_CD_FILTER_SAMPLE_WIN
CFG_FILTER_DEASSERT_CNT
CFG_CD_FILTER_ASSERT_CNT
See Figure 4-1 for a visual representation of the STAT_PRI_CD configuration
parameters.
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With the default values in place:
An assertion (setting HIGH) of STAT_PRI_CD will take place after a valid signal is
present for ~6.5ms
A de-assertion (setting LOW) of STAT_PRI_CD will take place after loss of a valid
signal for ~96µs
If the application requires any adjustment of the sampling window, assertion count, or
de-assertion count, please consult the following equations to calculate the associated
time to assert or de-assert STAT_PRI_CD.
STAT_PRI_CD de-assert time:
(1.6μs) * (CFG_CD_FILTER_SAMPLE_WIN + 1) * CFG_CD_FILTER_DEASSERT_CNT
STAT_PRI_CD assert time:
(1.6μs) * (CFG_CD_FILTER_SAMPLE_WIN + 1) * CFG_CD_FILTER_ASSERT_CNT
= ASSERT Threshold
CFG_CD_FILTER_ASSERT_CNT =n
n=1
n=2
n=3
…
Time in clock cycles
CFG_CD_FILTER_SAMPLE_WIN
= DEASSERT Threshold
…
CFG_CD_FILTER_DEASSERT_CNT =n
n=1
n=2
n=3
Time in clock cycles
CFG_CD_FILTER_SAMPLE_WIN
Figure 4-1: STAT_PRI_CD Configuration Parameters
4.2.3.2 Secondary Carrier Detection (STAT_SEC_CD) Configuration
The secondary carrier detection signal acts as an additional carrier detection which can
be further filtered through squelch controls. It also serves as the control signal for Mute
on LOS (Loss Of Signal) and Disable on LOS. Please refer to Section 4.8.6 to
Section 4.8.6.3 for further information on this.
If the application requires the use of squelch settings, start by setting the following:
CFG_SEC_CD_INCL_CLI_SQUELCH = 1
Once this parameter is set, the device will apply squelch based on the settings found
within the following parameters:
CFG_CLI_SQUELCH_THRESHOLD
CFG_CLI_SQUELCH_HYSTERESIS
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The device will use these parameters to determine squelch status and set that within
STAT_CLI_SQUELCH. Based off of this, secondary carrier detection can be described as:
STAT_SEC_CD = inverse of (STAT_CLI_SQUELCH & STAT_PRI_CD).
To help detail how the device determines the state of Squelch, we define the following
variables:
CLI = STAT_CABLE_LEN_INDICATION
THR = CFG_CLI_SQUELCH_THRESHOLD
HYS = CFG_CLI_SQUELCH_HYSTERESIS
SQL = STAT_CLI_SQUELCH
The following rules define the state of SQL.
Note: If the cable equalizer is in bypass (STAT_CEQ_BYPASS = 1), the device will set
SQL to 0.
If CLI > (THR + HYS), the device will set SQL to 1, otherwise:
If CLI < (THR - HYS), the device will set SQL to 0, otherwise:
If CLI ≥ (THR - HYS) and CLI ≤ (THR + HYS), SQL remains unchanged.
If SQL = 1, the device will not indicate lock and the trace driver state will be
defined by output state control parameters settings, see Section 4.8.6 for more
details.
Table 4-1: Cable Equalizer Status and Configuration Parameters
Register Addressh and Name
Parameter Name
Parameter Description
15, CARR_ DET_CFG
CFG_SEC_CD_INCL_CLI_SQUELCH Enables or disables squelch control.
Used to tune the squelch threshold based on the
tolerance requirements of the application.
CFG_CLI_SQUELCH_THRESHOLD
CFG_CLI_SQUELCH_HYSTERESIS
16, SQUELCH_ PARAMETERS
Used to tune the squelch hysteresis based on the
tolerance requirements of the application.
20, CD_FILTER_ DELAYS_0
21, CD_FILTER_ DELAYS_1
22, CD_FILTER_ DELAYS_2
CFG_CD_FILTER_SAMPLE_WIN
CFG_CD_FILTER_DEASSERT_CNT
CFG_CD_FILTER_ASSERT_CNT
Primary carrier detect sampling window size.
Primary carrier detect de-assertion count.
Primary carrier detect assertion count.
A counter showing the number of times the primary
Carrier Detect signal changed.
STAT_CNT_PRI_CD_CHANGES
84, STICKY_ COUNTS_0
86, CURRENT_ STATUS_0
A counter showing the number of times the secondary
Carrier Detect signal changed.
STAT_CNT_SEC_CD_CHANGES
STAT_CLI_SQUELCH
Cable equalizer Squelch status.
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Table 4-1: Cable Equalizer Status and Configuration Parameters (Continued)
Register Addressh and Name
87, CURRENT_ STATUS_1
88, EQ_GAIN_IND
Parameter Name
Parameter Description
Primary filtered carrier detect of the analogue carrier
detect signal.
STAT_PRI_CD
Secondary filtered carrier detect of the analogue carrier
detect signal.
STAT_SEC_CD
SDIO cable length indication when in cable equalizer
mode.
STAT_CABLE_LEN_INDICATION
4.3 Trace Equalizer
The GS12190 features a differential input buffer with 100Ω differential input
termination, which includes a Trace Equalizer that can be configured to compensate for
up to 20" of 7mil strip-line in FR4 at 11.88Gb/s and up to 60" at 2.97Gb/s.
The differential input signal can be either DC-coupled or AC-coupled, and is capable of
operation with any binary coded signal between 1Mb/s and 11.88Gb/s.
The input circuit is compatible with industry standard CML differential transmitters
when DC-coupled using industry standard 100Ω differential termination circuitry.
The Trace Equalizer includes an automatic input offset compensation circuit. This
reduces offset-induced data jitter in the link due to asymmetric performance of
DC-coupled upstream differential drivers. The input offset compensation circuit also
improves the input sensitivity of the Trace Equalizer.
Note: When working with the Trace Equalizer, note the following:
•
•
The parameters referred to within Section 4.3 to Section 4.3.2 are linked to their
respective registers in Table 4-2. For a complete list of registers and functions, see
Section 5.
Section 4.3 to Section 4.3.2 are only applicable to the Trace Equalizer input (DDI).
4.3.1 Input Trace Equalizer
The Trace Equalizer can compensate for up to 17dB of insertion loss at 5.94GHz in 8
increments, which can be adjusted through the CFG_TREQ0_BOOST parameter in
control register 0x1Eh. The default value of CFG_TREQ0_BOOST is (0h), which
corresponds to the minimum equalization boost level.
Please refer to Figure 4-2 for recommended boost setting.
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8
7
6
5
4
3
2
1
0
boost setting 8
boost setting 7
boost setting 6
boost setting 5
boost setting 4
boost setting 3
boost setting 2
boost setting 1
boost setting 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Insertion Loss at 5.94GHz (dB)
Figure 4-2: GS12190 Trace EQ Boost Setting Recommendation
By default at power-up or after system reset, the Trace Equalizer is configured to
compensate for up to 3" of 7mil strip-line in FR4 material at high frequencies.
Note: If using input trace lengths longer than 5", use an upstream launch swing of
~ 800mVppd
.
4.3.2 Carrier Detect, and Loss of Signal
The Trace Equalizer has a highly-configurable Carrier Detection mechanism that allows
the system designer to optimize the sensitivity and hysteresis of the Carrier Detection
mechanism to meet specific system requirements.
Default settings should satisfy most applications; however, designers can modify the
following three parameters to customize the Trace Equalizer's carrier detection for their
application:
•
•
•
CFG_TREQ0_CD_BOOST
CFG_TREQ0_CD_ASSERT_THRESH
CFG_TRE0Q_CD_DEASSERT_THRESH
The Trace Equalizer Carrier Detect is reported by status parameter STAT_PRI_CD in
register 0x87h.
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The first CD control parameter is CFG_TREQ0_CD_BOOST in register 0x1Eh. This
parameter determines the method and therefore the level of equalization to be used on
the input signal routed to the Carrier Detection sub-block. The default value is 0b, which
maximizes the level of equalization. Alternatively, the designer can choose to have this
signal equalized at the same level as the main signal routed to the reclocker by setting
CFG_TREQ0_CD_BOOST to 1b. The setting of this parameter has no impact on the main
signal routed to the reclocker.
The last two CD control parameters can be found in register 0x1Fh. Parameters
CFG_TREQ0_CD_ASSERT_THRESH and CFG_TRE0Q_CD_DEASSERT_THRESH set
the Carrier Detect assert and de-assert thresholds to the input signal, which also defines
the hysteresis of CD signal.
The default values of CFG_TREQ0_CD_ASSERT_THRESH and
CFG_TREQ0_CD_DEASSERT_THRESH are 4d and 3d respectively. With the default
settings, the minimum launch swing needed to assert the carrier detect is 200mV and it
will be de-asserted when the signal level falls below 150mV.
The STAT_PRI_CD (Carrier Detect) parameter will be set to 0b and the LOS will be set to
1b whenever a new signal at the input does not exceed the assert threshold, or an
existing signal falls below the de-assert threshold. The result is that the device will not
indicate lock, and the outputs will mute (assuming Mute on LOS is left to its default value
in the CONTROL_OUTPUT_MUTE register—0x49h). See Section 4.8.6 for more details.
Given a differential input trace with 17dB of insertion loss at 5.94GHz and
CFG_TREQ_CD_BOOST = 0b, Figure 4-3 illustrates the relationship between launch
swing voltage, and minimum threshold setting to assert or de-asset Carrier Detect at all
rates up to threshold setting at 11.88Gb/s.
Min Launch Swing vs. CD Threshold Setting
800
700
600
500
400
300
200
100
0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
Carrier Detect Threshold Setting
Figure 4-3: Input Voltage vs. Carrier Detect Threshold Setting
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Table 4-2: Trace Equalizer Status and Configuration Parameters
Register Addressh and Name
84, STICKY_ COUNTS_0
Parameter Name
Description
A counter showing the number of times the
primary Carrier Detect signal changed.
STAT_CNT_PRI_CD_CHANGES
Primary filtered carrier detect of the
analogue carrier detect signal.
87, CURRENT_ STATUS_1
STAT_PRI_CD
CFG_TREQ0_CD_ASSERT_THRESH
CFG_TREQ0_CD_DEASSERT_THRESH
CFG_TREQ0_BOOST
Sets the Carrier Detect assert threshold.
Sets the Carrier Detect de-assert threshold.
Sets the Trace Equalizer boost level.
1F, TREQ0_CD_ HYSTERESIS
1E, TREQ0_ INPUT_BOOST
CFG_TREQ0_CD_BOOST
Selects the boost method of the CD signal.
4.4 Serial Digital Reclocker
The GS12190 includes an integrated Reclocker, whose purpose is to lock to a valid
incoming signal from the Cable Equalizer stage (when operating in cable equalizer
mode) or the Trace Equalizer stage (when operating in cable driver mode) and produce
a lower jitter signal at the Cable Driver or Trace Driver outputs. The Reclocker has the
ability to lock to any of the following data rates: MADI (125Mb/s), SD-SDI (270Mb/s),
HD-SDI (1.485Gb/s), 3G-SDI (2.97Gb/s), 6G-SDI (5.94Gb/s) and 12G-SDI (11.88Gb/s). This
includes the f/1.001 rates.
The default settings of the Reclocker block are optimal for most applications. However,
the following controls allow the user to customize the behaviour of the Reclocker: loop
bandwidth control, Automatic and Manual Rate Detection.
Note: The parameters referred to within Section 4.4.1 to Section 4.4.2 are linked to their
respective registers in Table 4-4: Reclocker Control and Status Parameters. For a
complete list of registers and functions, please see Section 5.
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4.4.1 PLL Loop Bandwidth Control
The ratio of output peak-to-peak jitter to input peak-to-peak jitter of the Reclocker can
be represented by a low-pass jitter transfer function, with a bandwidth equal to the PLL
loop bandwidth. Although the default loop bandwidth settings for the GS12190
reclocker are ideal for most SDI signals, the GS12190 allows the user to adjust the loop
bandwidth for each MADI and SMPTE-compliant rate.
Registers 0x0Ah through 0x0Ch contain the following parameters which allow the user
to configure rate-dependent loop bandwidth: CFG_PLL_LBW_12G,
CFG_PLL_LBW_6G,CFG_PLL_LBW_3G, CFG_PLL_LBW_HD, CFG_PLL_LBW_SD, and
CFG_PLL_LBW_MADI. The loop bandwidth settings are defined in terms of ratios of the
nominal loop bandwidth. For each rate, where '1.0x' is the nominal loop bandwidth, the
following ratios are available: 0.0625x, 0.125x, 0.25x, 0.5x, and 1.0x. Table 2-3 provides
the specific loop bandwidths for each data rate and loop bandwidth setting. Lowering
the loop bandwidth will lower the jitter amplitude above the loop bandwidth
frequency. Although lower output jitter is desirable, the lower loop bandwidth may
reduce the device’s IJT to very high jitter that may be present outside the loop
bandwidth.
4.4.2 Automatic and Manual Rate Detection
In Cable Equalizer mode, with the default rate detect settings, the Reclocker will
automatically attempt to lock to any of following data rates: MADI (125Mb/s), SD-SDI
(270Mb/s), HD-SDI (1.485Gb/s), 3G-SDI (2.97Gb/s), 6G-SDI (5.94Gb/s) and 12G-SDI
(11.88Gb/s). This includes the f/1.001 rates.
In Cable Driver mode, with the default rate detect settings, the Reclocker will
automatically attempt to lock to any of the following data rates: SD-SDI (270Mb/s),
HD-SDI (1.485Gb/s), 3G-SDI (2.97Gb/s), 6G-SDI (5.94Gb/s) and 12G-SDI (11.88Gb/s). This
includes the f/1.001 rates.
However, the reclocker can be configured to only lock to a single rate, by setting the
CFG_AUTO_RATE_DETECT_ENA and CFG_MANUAL_RATE parameters in register
0x06. In addition to CFG_MANUAL_RATE, when operating in cable driver mode and
with automatic rate detection enabled (CFG_AUTO_RATE_DETECT_ENA = 1), specific
rates can be excluded from the rate detect list through the CFG_RATE_ENA_<r> rate
disable mask parameter in 0x06h, where r is the rate to be disabled. For details on
specific settings, please see Table 5-3: Control Register Descriptions, RATE_ DETECT_
MODE.
Note: The CFG_RATE_ENA_<r> parameter is only applicable to the Trace Equalizer
input DDI in cable driver mode.
The STAT_LOCK parameter in register 0x86h will indicate that the Reclocker is locked
when its value is 1b and unlocked when its value is 0b. The lock status can also be
monitored externally on any GPIO pin, however it is the default mode for GPIO1, pin 18.
The STAT_DETECTED_RATE parameter in register 0x87h will indicate the data rate at
which the Reclocker is locked to. A value of 0d in the STAT_DETECTED_RATE parameter
indicates that the device is not locked, while values between 1d and 6d will indicate that
the device is locked to one of the six available rates between MADI at 125Mb/s and
UHD-SDI at 11.88Gb/s.
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If the Reclocker cannot lock to any of the valid rates in automatic mode or the selected
rate in manual mode, the signal can automatically be bypassed to the output. If the
reclocker does lock to the incoming signal, the reclocked and bypassed (if manual
bypass control enabled) signals are available at the appropriate output. See Section 4.8
for more details.
Table 4-3: Detected Data Rates
STAT_DETECTED_
Detected Data Rate
RATE [2:0]
0
1
2
3
4
5
6
7
Unlocked
MADI (125Mb/s)
SD (270Mb/s)
HD (1.485Gb/s)
3G (2.97Gb/s)
6G (5.94Gb/s)
12G (11.88Gb/s)
Reserved
4.4.3 Lock Time
4.4.3.1 Synchronous and Asynchronous Lock Time
Synchronous lock time is defined as the time it takes the device to re-lock to an existing
signal that has been momentarily interrupted or to a new signal of the same data rate
as the previous signal which has been quickly switched in.
Asynchronous lock time is defined as the time it takes the device to lock when a signal
is first applied to the serial digital inputs, or when the signal rate changes. The
asynchronous and synchronous lock times are defined in Table 2-3.
Note: To ensure synchronous lock times are met, the maximum interruption time of the
signal is 10µs for an SD-SDI signal. HD, 3G, 6G, or 12G signals must have a maximum
interruption time of 6µs. The new signal, after interruption, must have the same
frequency as the original signal but may have an arbitrary phase.
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Table 4-4: Reclocker Control and Status Parameters
Register
Addresshand
Parameter Name
Description
Name
Enables or disables the automatic rate detection mode of the
reclocker.
CFG_AUTO_RATE_DETECT_ENA
CFG_MANUAL_RATE
Select a single rate for the reclocker rate detection when
CFG_AUTO_RATE_DETECT_ENA is 0b.
06,
CFG_RATE_ENA_12G
CFG_RATE_ENA_3G
CFG_RATE_ENA_6G
CFG_RATE_ENA_HD
CFG_RATE_ENA_SD
CFG_RATE_ENA_MADI
CFG_PLL_LBW_12G
12G auto rate detection enable
3G auto rate detection enable
RATE_DETECT_
MODE
6G auto rate detection enable
HD auto rate detection enable
SD auto rate detection enable
MADI auto rate detection enable
Configures the Loop Bandwidth for 12G signals.
0A,
PLL_LOOP_
BANDWIDTH_ 0
CFG_PLL_LBW_6G
CFG_PLL_LBW_3G
CFG_PLL_LBW_HD
CFG_PLL_LBW_SD
CFG_PLL_LBW_MADI
Configures the Loop Bandwidth for 6G signals.
Configures the Loop Bandwidth for 3G signals.
Configures the Loop Bandwidth for HD signals.
Configures the Loop Bandwidth for SD signals.
Configures the Loop Bandwidth for MADI signals.
0B,
PLL_LOOP_
BANDWIDTH_ 1
0C,
PLL_LOOP_
BANDWIDTH_ 2
CFG_GPIO1_FUNCTION
Sets the function of GPIO1.
11,
GPIO1_CFG
CFG_GPIO1_OUTPUT_ ENA
Sets the GPIO pin as either an output or an input.
Counter showing the number of times the PLL lock status
changed.
STAT_CNT_PLL_LOCK_CHANGES
STAT_CNT_RATE_CHANGES
85,
STICKY_
COUNTS_1
Counter showing the number of times the PLL lock rate
changed.
86,
CURRENT_
STATUS_0
STAT_LOCK
The status of the PLL. Locked, or unlocked.
The rate at which the PLL is locked to.
87,
CURRENT_
STATUS_1
STAT_DETECTED_RATE
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4.5 PRBS Checker
The GS12190 includes an integrated PRBS Checker, which can error check a PRBS7 signal
out of the Trace or Cable equalizer input blocks.
There are two modes of operation for the PRBS checker:
•
Timed Mode: Used for precise measurements of up to ~3.34s
In Timed Mode, the host sets the measurement time and executes the
checker operation. The device ends the PRBS error check measurement
when the timer expires, and the host reads back the measurement status
and error count
•
Continuous Mode: Can be used for longer measurements but with less precision in
the time interval
In Continuous Mode, the host controls the starts and stops of the PRBS error
checking operation then reads back the measurement status and error count
Note: When working with the PRBS Checker, please note the following:
•
The parameters referred to in Section 4.5 to Section 4.5.2 are briefly described and
linked to their respective registers in Table 4-5
•
The PRBS Generator and Checker can be active at the same time. However, the
Generator can not be looped back on itself for error checking
4.5.1 Timed PRBS Check Measurement Procedure
For applications where measurement times are ~3.34s or less, the timed PRBS check
mode is the most suitable. Alternatively, to achieve precise timing for lower BER signals,
the timed PRBS check measurement can be repeated by the host and the total
measurement time and error count is determined by summing the individual
measurements.
In timed mode, the host sets the total measurement time by setting the
CFG_PRBS_CHECK_PREDIVIDER and the CFG_PRBS_CHECK_MEAS_TIME
parameters to the required values to achieve the total measurement time required by
the application.
To perform a timed PRBS measurement, please complete the following steps:
1. Set the appropriate settings within CFG_PRBS_CHECK_PREDIVIDER and
CFG_PRBS_CHECK_MEAS_TIME to achieve the total measurement time
required by the application. The TMT (Total Measurement Time) is determined
by the following equation:
TMT = CFG_PRBS_CHECK_PREDIVIDER * (CFG_PRBS_CHECK_MEAS_TIME
*256+1) * (1/40MHz)
Note: Using the default CFG_PRBS_CHECK_PREDIVIDER setting of 0
(pre-divider = 4) and CFG_PRBS_CHECK_MEAS_TIME setting of 3
(MEAS_TIME = 3), the TMT is ~77µs per measurement.
2. Follow the steps outlined in the flowchart found within Figure 4-4: Timed PRBS
Check Flow.
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Note:
The host must not change CTRL_PRBS_CHECK_START
during a PRBS timed check except as described in
this diagram. There is no capability for the host to
abort a timed PRBS check once requested.
In particular, after setting CTRL_PRBS_CHECK_START
to 1 for a timed check, the host is not permitted to
write CTRL_PRBS_CHECK_START back to 0 until the
device sets STAT_PRBS_CHECK_STATUS to 2 or 3
indicating completion or abort. Behaviour is
undefined if it does so; it would lead to race
conditions in the host <-> device handshake.
Start Timed PRBS Check Measurement
Host sets
CTRL_PRBS_CHECK_TIMED_CONT_B = 1
CTRL_PRBS_CHECK_START = 1
Device clears error count
And attempts to start PRBS
checker based on lock
condition of device
Device Sets
STAT_PRBS_CHK_ERR_CNT = 0
Loss of lock occurred during measurement
or at the beginning of measurement
initiation. Error count is invalid
Resets PRBS
checker.
STAT_PRBS_CHECK_STATUS
= 3
Host sets
CTRL_PRBS_CHECK_START = 0
YES
YES
Prepares device
for next
operation
NO
NO
Device Sets
STAT_PRBS_CHECK_STATUS =
0
STAT_PRBS_CHECK_STATUS
= 1
YES
PRBS Checker is ready for new
operation
NO
Status indicates that
timer Expired, PRBS
Timed Measurement
Complete
NO
STAT_PRBS_CHECK_STATUS
= 2
Resets PRBS
checker.
YES
Host sets
CTRL_PRBS_CHECK_START = 0
NO
STAT_PRBS_CHECK_STATUS
= 0
YES
PRBS Error Check Completed
Successfully
User reads Error count from
STAT_PRBS_CHK_ERR_CNT
Figure 4-4: Timed PRBS Check Flow
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4.5.2 Continuous PRBS Check Measurement Procedure
The maximum measurement time for a timed PRBS error measurement is ~3.35
seconds. For links with very low error rates, this time is insufficient to capture an
adequate number of errors. For these situations, the continuous PRBS check
measurement is more appropriate.
In continuous PRBS measurement mode, the measurement can run as long as required
(assuming the device remains locked) to ensure the BER test level is met.
To perform a continuous PRBS measurement, please follow the steps outlined in the
flowchart found within Figure 4-5: Continuous PRBS Flow Chart
Table 4-5: PRBS Checker Parameter Description
Register Addressh and Name
Parameter Name
Parameter Description
Selects pre-divider for PRBS check measurement
timer.
CFG_PRBS_CHECK_PREDIVIDER
50, PRBS_ CHK_CFG
Selects PRBS check measurement interval for timed
measurements.
CFG_PRBS_CHECK_MEAS_TIME
Selects between timed and continuous type PRBS
measurement.
CTRL_PRBS_CHECK_TIMED_CONT_B
51, PRBS_CHK_ CTRL
CTRL_PRBS_CHECK_START
STAT_PRBS_CHK_ERR_CNT
Used to start and stop PRBS measurements.
PRBS error count storage location.
89, PRBS_ CHK_ERR_CNT
8A, PRBS_ CHK_STATUS
STAT_PRBS_CHECK_STATUS
STAT_PRBS_CHECK_LAST_ABORT
Status indication of PRBS checker.
Indication bit for PRBS successful completion or abort.
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Start Continuous PRBS Check
Measurement
Device clears error count
And attempts to start PRBS
checker based on lock
condition of device
Host sets
CTRL_PRBS_CHECK_TIMED_CONT_B = 0
CTRL_PRBS_CHECK_START = 1
Device Sets
STAT_PRBS_CHK_ERR_CNT = 0
Loss of lock occurred during
measurement or at the
beginning of measurement
initiation. Error count is invalid
Resets PRBS
checker.
STAT_PRBS_CHECK_STATUS
= 3
Host sets
CTRL_PRBS_CHECK_START = 0
YES
Prepares device
for next
operation
NO
Device Sets
STAT_PRBS_CHECK_STATUS
= 0
STAT_PRBS_CHECK_STATUS
= 1
NO
YES
NO
Host may terminate PRBS
measurement at anytime
by completing this action.
PRBS Checker is ready for new
operation
Host sets
CTRL_PRBS_CHECK_START
=0
YES
YES
NO
STAT_PRBS_CHECK_STATUS
= 0
YES
STAT_PRBS_CHECK_LAST_ABORT
= 1
This step is to ensure that an error did
not occur between ending the PRBS
measurement and the last polling of
STAT_PRBS_CHECK_STATUS.
NO
PRBS Error Check Completed
Successfully
User reads Error count from
STAT_PRBS_CHK_ERR_CNT
Figure 4-5: Continuous PRBS Flow Chart
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4.6 Eye Monitor
The GS12190 includes an integrated Eye Monitor, which can scan the equalized signal
from the Trace or Cable equalizer input blocks. The Eye Monitor is capable of performing
a full 128h x 256v matrix-scan or simply a 4 coordinate shape-scan of the equalized
signal (See Figure 4-6).
Figure 4-6: Full Matrix-Scan (left) and 4-Point Shape-Scan (right)
The Eye Monitor is highly-configurable, and the host can configure the offset,
resolution, sample time, and error threshold parameters to control the depth and
execution time of the scan. The Eye Monitor scans the signal from whichever of the
Trace or Cable equalizer blocks is active for the current direction (see Section 4.1.1 for
directional mode configuration). Similar to the PRBS Checker, the Eye Monitor is
controlled through a 4-way handshake mechanism. The following sections outline the
scan parameters and procedure to configure the eye scan area, error threshold, and run
a shape or full scan.
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4.6.1 Scan Matrix and Measurement Time
0
Max Horizontal Scan Resolution
Default
128
Vertical
Offset
Start
Vertical Offset Step = 1
Phase Step = 1
Vertical
Offset Start
Vertical
Offset Stop
Phase Start
Phase Stop
Vertical Offset Step = 2
Phase Step = 1
Default
Vertical
Offset
Stop
255
0
127
Default
Default
Phase
Start
Phase
Stop
Vertical Offset Step = 4
Phase Step = 4
Figure 4-7: Eye Scan Matrix Parameters
Figure 4-7 shows a visual representation of the scan matrix and indicates the spatial
parameters that determine the scan area and resolution. Running a scan using the
default offset and step parameters, results in 32768 (128x256) samples. The number of
samples and thus, the total scan time can be reduced to meet the needs of the
application. The scan area can be reduced by reducing the span determined by the
vertical and phase start and stop offsets or the resolution can be reduced by increasing
the step size between adjacent samples. On the right in Figure 4-7, there are three step
settings used as examples, however there are a total of nine combinations possible. See
Table 4-6 for the register addresses and parameter names of the spatial eye scan
parameters.
For example, by increasing the vertical and phase step size to 4, the resolution is
reduced to (1/4)2, thus reducing the number of samples down to 2048 (32768x1/16).
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The vertical and horizontal scan information is useful when adjusting pre-emphasis and
equalization of a link. However, once this is accomplished, it may be sufficient to use the
Eye Scanner to only monitor jitter by setting the offsets to simply slice the eye at the
centre offset position, thus obtaining a simple 128 sample horizontal scan. A horizontal
eye can be configured to run in just over a millisecond.
In addition to the spatial parameters, the sample time, and thus the bit error rate
resolution for the eye scan can be adjusted; longer scans can detect finer bit error rates.
However, this proportionally increases the total scan time. The sample time in
microseconds is determined by a 32-bit time-out value split across two 16 bit registers.
See Table 4-7 for the register addresses and parameter names of the time-out eye scan
parameters.
For example, using the default spatial and temporal measurement scan parameters, the
scan time is approximately 6.6 seconds (32768 x 2 x 100µs). However, by changing the
vertical and horizontal step size to 4, the scan time can be reduced to 400ms (2048 x 2 x
100µs).
The error count information can be used as is to determine the minimum inner contour
based on the measurement time. However, the basic data can be post-processed to
determine things like error rate, and error threshold. The following equations provide
guidance for user post-processing:
Equation 4-1
sample1error1count
-------------------------------------------------------------
error1rate =
sample1time
Contour maps can be created by defining error rate thresholds, and grouping sampled
points that fall between thresholds.
For example:
Equation 4-2
Equation 4-3
sample1time
error1rate1threshold11
sample1time
error1rate1threshold12
-----------------------------------------------------------------------
-----------------------------------------------------------------------
sample1error1threshold
Some sampling scopes provide eye maps with BER contours; similar limited BER contour
approximations can be obtained from the eye scan by using BER threshold groups.
For example:
sample1time1x1data1rate
sample1time1x1data1rate
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
sample1error1threshold
error1rate1threshold11
error1rate1threshold12
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Table 4-6: Spatial Scan Configuration Parameters
Register Addressh and Name
Parameter Name
Description
CTRL_EYE_PHASE_START
CTRL_EYE_PHASE_STOP
Horizontal phase start index
Horizontal phase stop index
Horizontal phase step size
Vertical offset start index
Vertical offset stop index
Vertical offset step size
5A, EYE_MON_ SCAN_CTRL_0
CTRL_EYE_PHASE_STEP
5B, EYE_MON_ SCAN_CTRL_1
5C, EYE_MON_ SCAN_CTRL_2
CTRL_EYE_VERT_OFFSET_START
CTRL_EYE_VERT_OFFSET_STOP
CTRL_EYE_VERT_OFFSET_STEP
4.6.2 Matrix-Scan and Shape-Scan Operation
The previous section described the parameters used to adjust the spatial and temporal
eye scan settings. Each sample of the eye scan can record up to 65536 errors. A full eye
scan would require 64KB (256 x 128 x 2 Bytes) of memory to store the data of a full scan.
The Eye Monitor was implemented to use device resources more efficiently by
segmenting a full scan into several partial scan segments. Each partial scans segment
can contain up to 512B of scan data.
In the case of a full matrix-scan, there are 128 partial scan segments and each partial
scan segment contains two complete scan lines (2 x 128 x 2B = 512B). In the case of a
partial matrix-scan, each scan segment contains multiple partial scan lines including
partial lines (see Figure 4-8).
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1st Partial Scan
Error Count = Max
0 < rror Count < Max
E
Error Count = 0
1st Partial Scan
1st
1 st
Vertical Offset Start
2nd
2nd
2nd
2nd
...
...
...
...
Last
Last
Vertical Offset Stop
128th Partial Scan
Phase Start
Phase Stop
Figure 4-8: Full Matrix-Scan (left) and Partial Matrix-Scan (right)
Figure 4-7 illustrates an example of an eye scan, where the sampled eye data is not
centred within the scan matrix. The eye scan data has an arbitrary centre phase relative
to the centre of the matrix which is determined when the Eye Monitor is powered-up.
While the Eye Monitor remains powered, subsequent scans will maintain the same
relative phase allowing for consecutive scans to be compared for changes.
Although the scan data is not centred, a simple algorithm can be applied to the data to
shift the eye data and extract the relevant information.
In addition to the matrix-scan, the Eye Monitor includes a built-in function called a
shape-scan. The shape-scan returns four coordinates corresponding to the horizontal
and vertical extremes of the inner eye (See Figure 4-9).
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Error Count = Max
> Error Count Threshold
Error Count = 0
Positive Edge
(PE)
Left Edge
(LE)
Right Edge
(RE)
Negative Edge
(NE)
Figure 4-9: 4-Point Scan Coordinates Relative to the Eye
The four points obtained from the shape-scan can be used to quickly and easily
calculate the eye height and width of the signal eye. The shape-scan alone will most
likely meet the signal analysis requirements of most applications. Alternatively, the
coordinates obtained from the shape-scan can be used to optimize the bounds of a
partial matrix-scan. The four points returned from the shape-scan are determined by the
error rate threshold set by the error threshold parameter and the time-out parameters
previously discussed.
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Table 4-7: Time-out Eye Scan Parameters
Register Addressh and Name
Parameter Name
Description
56, EYE_MON_ INT_CFG_2
54, EYE_MON_ INT_CFG_0
55, EYE_MON_ INT_CFG_1
CFG_EYE_BER_THRESHOLD
CFG_EYE_MON_TIMEOUT_MS
CFG_EYE_MON_TIMEOUT_LS
Number of sample errors to determine fail
MSB of measurement time in microseconds
LSB of measurement time in microseconds
This section provides a step-by-step procedure to run a matrix and shape-scan. The
shape-scan procedure is described first.
Shape-Scan Procedure:
1. Ensure the offset and step parameters described in Table 4-6 are set to their default
values.
2. Configure the 4-point error rate threshold by setting each of the parameters listed
in Table 4-7.
3. Configure the eye monitor to run a shape-scan by setting
CTRL_EYE_SHAPE_SCAN_B to 1.
4. Start the scan and poll the scanner status register until the scan is complete. Please
refer to the flow diagram in Figure 4-10.
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Run Shape Scan
Please Note the Following:
- While the Eye Monitor is
powered-up, the Cable Equalizer
input only has partial adaptation
enabled
Host powers up eye monitor and starts
Shape Scan by setting:
Note: the host can write
CTRL_EYE_MON_POWER_CTRL = 1
CTRL_EYE_MON_START = 1
CTRL_EYE_MON_POWER_CTRL = 1 and
CTRL_EYE_MON_START = 1 in the
same GSPI write (i.e. at the
- Status = STAT_EYE_MON_STATUS
same time). It is not necessary to set
the power up first.
Host reads scan status from
STAT_EYE_MON_STATUS
3
1 or 0
Status
2
Host determines Eye Width and Eye Height by reading from
the following 4 registers:
le = STAT_EYE_SHAPE_LEFT_EDGE_PHASE
re = STAT_EYE_SHAPE_RIGHT_EDGE_PHASE
pe =STAT_EYE_SHAPE_POS_EDGE_OFFSET
ne =STAT_EYE_SHAPE_NEG_EDGE_OFFSET
if pe > ne:
Scan Failed
Reset Eye Scanner
EyeHeight = (256 + ne - pe)
else:
EyeHeight = (ne - pe)
if le > re:
EyeWidtht = (128 + re - le)
else:
EyeWidtht = (re - le)
Host Resets Eye Scanner for new scan by
setting CTRL_EYE_MON_START = 0
Or power down by setting
CTRL_EYE_MON_POWER_CTRL = 0
NO
Status = 0?
Shape Scan
Complete
Figure 4-10: Shape-Scan Flow Diagram
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Matrix-Scan Procedure:
1. Set the bounds of the matrix-scan with the offset and step parameters described in
Table 4-6. The default value results in a full matrix-scan. Alternatively, the
shape-scan can be executed and the coordinates returned can be used to minimize
the scan time and data size of the scan.
2. Configure the 4-point error rate threshold by setting each of the parameters listed
in Table 4-7.
3. Configure the eye monitor to run a matrix-scan by setting
CTRL_EYE_SHAPE_SCAN_B to 0.
4. Start the scan and poll the scanner status register until the scan is complete. Refer
to the flow diagram in Figure 4-11.
Read Eye Scan Buffer Procedure:
1. Host reads image size from STAT_EYE_IMAGE_SIZE.
Note: The matrix-scan is composed of multiple partial scan segments. The size (in
Bytes) of the last partial scan segment is stored in STAT_EYE_IMAGE_SIZE.
2. Host reads scan buffer data from register 0x6C00h to (0x6C00 + (size read from
STAT_EYE_IMAGE_SIZE)/2).
Address 0x6C00h is the first header word corresponding to the last vertical offset
position in the matrix that was read
Address 0x6C01h is the second header word corresponding to the image size.
This value is a copy of the image size that was read from
STAT_EYE_IMAGE_SIZE
Address 0x6C02h to (0x6C00 + (size read from STAT_EYE_IMAGE_SIZE)/2) is the
eye scan data:
The image data is 2 bytes per sample point
Making reference to the Matrix shown in Figure 4-7, the eye scan data
starting at 0x6C02h is stored in order from left to right, top to bottom, from
the last stored vertical/horizontal position in the matrix
The number of samples contained in the scan buffer is equal to (size read from
STAT_EYE_IMAGE_SIZE - 4)/2
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Please Note the Following:
Run Scan
- While the Eye Monitor is powered-up,
the Cable Equalizer input only has partial
adaptation enabled
YES
Status = 0?
Host powers up eye monitor and starts
Matrix Scan by setting:
- Status = STAT_EYE_MON_STATUS
Note: the host can write
CTRL_EYE_MON_POWER_CTRL = 1
CTRL_EYE_MON_START = 1
- Partial = STAT_EYE_SCAN_PARTIAL_OR_FULL
CTRL_EYE_MON_POWER_CTRL = 1 and
CTRL_EYE_MON_START = 1 in the
same GSPI write (i.e. at the same time).
It is not necessary to set the
power up first.
NO
Host reads scan status from
STAT_EYE_MON_STATUS
3
1 or 0
status
2
Host preforms
Read Buffer
Scan
Host Resets Eye Scanner for
new scan by setting
CTRL_EYE_MON_START = 0
Scan Failed
Reset Eye Scanner
Eye Scan
Data
Procedure
NO
Partial = 1?
YES
Host Resets Eye Scanner for new scan by
setting CTRL_EYE_MON_START = 0
Or power down by setting
CTRL_EYE_MON_POWER_CTRL = 0
NO
Status = 0?
Full Eye Scan
Complete
Figure 4-11: Matrix-Scan Flow Diagram
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4.7 PRBS Generator
The GS12190 includes an integrated PRBS Generator which can produce a differential
PRBS7 or a divided clock signal on SDIO/SDO or DDO/DDO for system testing.
Note: The parameters referred to within this section are briefly described and linked to
their respective registers in Table 4-8.
•
The PRBS Generator and Checker can be active at the same time. However, the
Generator can not be looped back on itself for error checking
Please consider the following before initializing the PRBS Generator for use:
•
Ensure that the directional mode setting is set to utilize the appropriate output.
Refer to Section 4.1.1 for more information:
Cable Driver Mode PRBS output = SDIO/SDO
Cable Equalizer Mode PRBS output = DDO/DDO
•
If the application requires adjustment to the default output swing on either PRBS
output. Please see Section 4.8.4 for details on how to adjust these settings
To configure the PRBS Generator for use, please see the following steps:
1. Select the PRBS Generator as the source on the appropriate output:
To switch DDO/DDO from data mode to PRBS generator mode, set
CTRL_OUTPUT1_SIGNAL_SEL = 1
To switch SDIO/SDO from data mode to PRBS generator mode, set
CTRL_OUTPUT0_SIGNAL_SEL = 1
2. The default device settings are configured to power-down the device on loss of
input signal. If the PRBS Generator is to be used without a valid input signal, then
the following automatic setting parameters must be disabled. This must be done to
ensure device is powered-up and the outputs are active for the PRBS Generator.
The following settings are required for PRBS output on either output:
CTRL_AUTO_SLEEP = 0
CTRL_MANUAL_SLEEP = 0
The following settings are required when DDO/DDO is selected as PRBS
output:
CTRL_OUTPUT1_AUTO_MUTE = 0
CTRL_OUTPUT1_MANUAL_MUTE = 0
CTRL_OUTPUT1_AUTO_DISABLE = 0
CTRL_OUTPUT1_MANUAL_DISABLE = 0
The following settings are required when SDIO/SDO is selected as PRBS
output:
CTRL_OUTPUT0_AUTO_MUTE = 0
CTRL_OUTPUT0_MANUAL_MUTE = 0
CTRL_OUTPUT0_AUTO_DISABLE = 0
CTRL_OUTPUT0_MANUAL_DISABLE = 0
CTRL_OUTPUT0_AUTO_SLEW = 0
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Manually set the appropriate slew rate in CTRL_OUTPUT0_MANUAL_SLEW for
the rate to be selected in CTRL_PRBS_GEN_DATA_RATE
0 for SD and MADI
1 for HD and 3G
2 for 6G and 12G
3. Set the values within the following parameters which meet the needs of the
application:
CTRL_PRBS_GEN_SIGNAL_SELECT
CTRL_PRBS_GEN_CLK_SRC
CTRL_PRBS_GEN_DATA_RATE
Note: If CTRL_PRBS_GEN_CLK_SRC was set to reclocker recovered clock a
valid signal that the reclocker has locked to must be present for proper
operation, and the PRBS Generator will match this data rate regardless of
what rate CTRL_PRBS_GEN_DATA_RATE is set to
CTRL_PRBS_GEN_CLK_DIVIDER
CTRL_PRBS_GEN_INVERT
4. Start the Generator by setting CTRL_PRBS_GEN_ENABLE = 1.
To stop the Generator at any time, set CTRL_PRBS_GEN_ENABLE = 0. If the use of the
PRBS Generator is complete, revert any settings made in steps 1, 2 and/or 4 to return to
normal operation.
Table 4-8 provides a brief description of the parameters used to configure and enable
the PRBS Generator. For a detailed description of each parameter, please reference the
linked registers.
Table 4-8: PRBS Generator Parameter Descriptions
Register Addressh and Name
Parameter Name
Parameter Description
CTRL_AUTO_SLEEP
Set the device to auto or manual sleep
Manually set the sleep setting of the
device when auto sleep mode is turned
off
3, CONTROL_ SLEEP
CTRL_MANUAL_SLEEP
Selects between data or PRBS Generator
as the driver source for DDO/DDO
CTRL_OUTPUT1_SIGNAL_SEL
CTRL_OUTPUT0_SIGNAL_SEL
48, OUTPUT_ SIG_SELECT
Selects between data or PRBS Generator
as the driver source for SDIO/SDO
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Table 4-8: PRBS Generator Parameter Descriptions (Continued)
Register Addressh and Name
Parameter Name
Parameter Description
Select automatic or manual mute control
for DD0/DDO
CTRL_OUTPUT1_AUTO_MUTE
Manually set the mute control for
DD0/DDO when auto mute mode is
turned off
CTRL_OUTPUT1_MANUAL_MUTE
CTRL_OUTPUT0_AUTO_MUTE
CTRL_OUTPUT0_MANUAL_MUTE
CTRL_OUTPUT1_AUTO_DISABLE
49, CONTROL_ OUTPUT_ MUTE
Select automatic or manual mute control
for SDIO/SDO
Manually set the mute control of the
SDIO/SDO when auto mute mode is
turned off
Selects automatic or manual disable
control for DD0/DDO
Manually set the disable control of
CTRL_OUTPUT1_MANUAL_DISABLE DD0/DDO when auto disable mode is
turned off
4A, CONTROL_ OUTPUT_ DISABLE
Selects automatic or manual disable
CTRL_OUTPUT0_AUTO_DISABLE
control for SDIO/SDO
Manually set the disable control of the
CTRL_OUTPUT0_MANUAL_DISABLE SDIO/SDO when auto disable mode is
turned off
Selects auto or manual slew rate selection
CTRL_OUTPUT0_AUTO_SLEW
for SDIO/SDO
4B, CONTROL_ OUTPUT_ SLEW
Manually set the slew rate for SDIO/SDO
CTRL_OUTPUT0_MANUAL_SLEW
when auto slew mode is turned off
Selects between setting the output of the
CTRL_PRBS_GEN_SIGNAL_SELECT
CTRL_PRBS_GEN_CLK_SRC
CTRL_PRBS_GEN_CLK_DIVIDER
CTRL_PRBS_GEN_INVERT
PRBS Generator to being a clock or a PRBS
test signal
Selects the clock source used by the PRBS
Generator
If a clock is selected as the PRBS output
signal, this parameter sets the divide ratio
of the clock
52, PRBS_GEN_ CTRL
Allows the polarity of the PRBS signal to
be inverted
If a PRBS test signal is selected as the
output signal, this parameter sets the
data rate of the PRBS7 signal
CTRL_PRBS_GEN_DATA_RATE
CTRL_PRBS_GEN_ENABLE
Used to enable or disable the PRBS
Generator
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4.8 Output Drivers
The GS12190 features two independent output drivers (see Figure 3-2 and Figure 3-3),
with data and PRBS Generators available on both outputs. The two drivers provide
highly-configurable amplitude and pre-emphasis control. The Cable Driver output on
SDIO can compensate for significant loss between the device output and BNC. The Trace
Driver, DDO, can compensate for up 15dB of insertion loss at 5.94GHz. This can represent
up to 20" of compensation at 12G for typical micro-strip and strip-line routing. In normal
operation, reclocked and bypassed data is available at both outputs. The signal on the
outputs can be inverted to help with signal polarity when layout requires trace
inversion. The PRBS Generator is available at both outputs. The LOS (Loss Of Signal)
status from the equalizer stage can be used to automatically mute or disable the
outputs on their assertion. The Loss Of Lock status from the reclocker block can be used
to mute the outputs. The Cable Driver is always disabled during sleep, while the Trace
Driver can be configured to mute or disable during sleep. The sleep control modes takes
precedence over the manual or automatic LOS and Loss of Lock output control modes.
Note: The <n> in the control parameter names refers to the output number. Output 0 is
the cable driver output SDIO and output 1 is the trace driver output DDO.
4.8.1 Bypassed Reclocker Signal Output Control
With the default power-up settings, the GS12190 outputs will automatically switch to
the bypassed signal (non-reclocked) whenever the PLL is unlocked. Alternatively,
manual reclocker bypass may be configured by setting the
CTRL_OUTPUT<n>_RETIMER_AUTO_BYPASS and
CTRL_OUTPUT<n>_RETIMER_MANUAL_BYPASS parameters in register 0x4Ch to 0b
and 1b respectively via the host interface, in which case the PLL will remain bypassed for
all rates.
The reclocker bypass function, manual or automatic, does not affect the input
equalization function of the device.
If the GS12190 is in Cable Driver Mode, and loop-back is not enabled, then setting SDIO
to manual bypass will power-down the reclocker block and features of the reclocker
such as rate detect and lock detect will no longer be accessible in this mode. The same
is true if the GS12190 is in Cable Equalizer Mode and DDO is set to manual bypass.
4.8.2 Output Driver Polarity Inversion
While in Data Mode, the signal polarity may be inverted at the outputs through the
CTRL_OUTPUT<n>_DATA_INVERT parameters in register 0x48h. This may be useful to
compensate for an inverted upstream signal or to facilitate board signal routing. To
invert the polarity of either of the two output drivers, write 1b to control parameter
CTRL_OUTPUT<n>_DATA_INVERT.
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4.8.3 Output Driver Data Rate Selection
The following information describes the default output driver configuration for each
operational mode, and how to modify them if required by the application.
4.8.3.1 Cable Driver Mode
In cable driver mode, with default settings active, the GS12190 uses the output driver
and slew rate group settings for the data rate to which the reclocker is locked.
When the reclocker is unlocked it will use the 6G/12G rate group:
CFG_OUTPUT0_CD_UHD_DRIVER_SWING
CFG_OUTPUT0_CD_UHD_PREEMPH_WIDTH
CFG_OUTPUT0_CD_UHD_PREEMPH_AMPL
CFG_OUTPUT0_CD_UHD_PREEMPH_PWRDWN
If required, manual selection of the output driver and slew rate group is possible using
the following steps:
1. Set CTRL_OUTPUT0_AUTO_SLEW = 0
2. Set CTRL_OUTPUT0_MANUAL_SLEW to the desired rate group. The slew rate
options are as follows:
0 = SD/MADI
1 = HD/3G
2 = 6G/12G
4.8.3.2 Trace Driver Mode
In trace driver mode, with default settings active, the GS12190 uses the SD trace driver
output group settings for all data rates, regardless of reclocker lock condition or data
rate being applied.
The following parameters are used to control the output for all data rates in the default
condition:
CFG_OUTPUT1_TD_SD_DRIVER_SWING
CFG_OUTPUT1_TD_SD_PREEMPH_WIDTH
CFG_OUTPUT1_TD_SD_PREEMPH_AMPL
CFG_OUTPUT1_TD_SD_PREEMPH_PWRDWN
If required, per-rate selection of the trace driver output group setting is possible by
setting CTRL_OUTPUT1_TRDR_PER_RATE = 1. Once set, the trace driver output group
will be determined by the rate to which the reclocker is locked.
For example, if the reclocker is locked to 12G, the following parameters will be used to
control the output drivers:
CFG_OUTPUT1_TD_12G_DRIVER_SWING
CFG_OUTPUT1_TD_12G_PREEMPH_WIDTH
CFG_OUTPUT1_TD_12G_PREEMPH_AMPL
CFG_OUTPUT1_TD_12G_PREEMPH_PWRDWN
Note: If per-rate settings are being used, when the reclocker is not locked the trace
driver will use the 12G trace driver output group settings.
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4.8.4 Amplitude and Pre-Emphasis Control
The two output drivers offer very granular amplitude and pre-emphasis control. For
optimal loss compensation, both the pre-emphasis pulse amplitude and the
pre-emphasis pulse width can be independently configured on both output drivers.
This extra flexibility provides a mechanism to better shape the pre-emphasis gain to
match the frequency loss response of interconnect composed of trace, connector and
via losses. The swing and pre-emphasis can be independently configured for specific
data rates.
Note: Output 0 references the Cable Driver, and Output 1 references the Trace Driver.
The output swing on the Cable Driver can be configured for the following three rate
groups:
•
•
•
CFG_OUTPUT0_CD_SD_DRIVER_SWING (MADI and SD)
CFG_OUTPUT0_CD_HD_DRIVER_SWING (HD and 3G)
CFG_OUTPUT0_CD_UHD_DRIVER_SWING (6G and 12G)
The output pre-emphasis on the Cable Driver can be configured for the following two
rate groups:
•
•
•
•
CFG_OUTPUT0_CD_HD_PREEMPH_WIDTH (HD and 3G)
CFG_OUTPUT0_CD_HD_PREEMPH_AMPL (HD and 3G)
CFG_OUTPUT0_CD_UHD_PREEMPH_WIDTH (6G and 12G)
CFG_OUTPUT0_CD_UHD_PREEMPH_AMPL (6G and 12G)
The output driver swing and pre-emphasis will use the rate specific swing configuration
when the reclocker is locked to that rate. The default swing setting is ~800mVpp
single-ended into an external 75Ω load, and is adjustable in each of the output swing
parameters listed above. The Cable Driver supply is pin 25 (VCCO_0) and should be
connected to a 2.5V supply. The default pre-emphasis settings provide minimal
insertion loss compensation.
The Trace Driver amplitude can be configured to use the same swing for all rates, or
similarly to the Cable Driver, can have a specific swing for each rate.
The following registers allow a per rate swing to be configured for five rates:
•
•
•
•
•
CFG_OUTPUT1_TD_SD_DRIVER_SWING (SD)
CFG_OUTPUT1_TD_HD_DRIVER_SWING (HD)
CFG_OUTPUT1_TD_3G_DRIVER_SWING (3G)
CFG_OUTPUT1_TD_6G_DRIVER_SWING (6G)
CFG_OUTPUT1_TD_12G_DRIVER_SWING (12G)
The output pre-emphasis on the Trace Driver can be configured for the following five
rates:
•
•
•
•
•
•
•
•
CFG_OUTPUT1_TD_SD_PREEMPH_WIDTH (SD)
CFG_OUTPUT1_TD_SD_PREEMPH_AMPL (SD)
CFG_OUTPUT1_TD_HD_PREEMPH_WIDTH (HD)
CFG_OUTPUT1_TD_HD_PREEMPH_AMPL (HD)
CFG_OUTPUT1_TD_3G_PREEMPH_WIDTH (3G)
CFG_OUTPUT1_TD_3G_PREEMPH_AMPL (3G)
CFG_OUTPUT1_TD_6G_PREEMPH_WIDTH (6G)
CFG_OUTPUT1_TD_6G_PREEMPH_AMPL (6G)
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•
•
CFG_OUTPUT1_TD_12G_PREEMPH_WIDTH (12G)
CFG_OUTPUT1_TD_12G_PREEMPH_AMPL (12G)
The Trace Driver swing can be adjusted in ≈25mVpp increments. The default swing value
is 400Vppd into an external 100Ω differential load. Although an adequate swing and
pre-emphasis can be achieved with a 1.8V output supply, for long traces where
maximum output swing and pre-emphasis range is desired, it is recommended that the
device VCC_DDO output supply pin be connected to a 2.5V supply. The default
pre-emphasis settings provide minimal insertion loss compensation.
4.8.4.1 Pre-emphasis Optimization
The goal of pre-emphasis is to open the eye at the downstream receiver as much as
possible. This means minimizing ISI jitter while meeting sufficient inner eye amplitude
to meet a receiver's input sensitivity. The Cable Driver has the additional requirement to
meet the SMPTE output specification.
The GS12190 has a high level of precision for pre-emphasis control, which allows for fine
optimization of any loss channel. The default Cable Driver settings should meet SMPTE
output specification for most applications with short (1 to 2 inch) trace between the
GS12190 and the output BNC. However, the pre-emphasis values may be adjusted to
produce a better-looking eye. It is difficult to provide guidance regarding dB, as a 12G
eye diagram looks different depending on the video test equipment used. The designer
must optimize for their targets.
The only requirement of the Trace Driver pre-emphasis settings is to minimize ISI
introduced by a lossy link and maximize the eye opening at the receiver. The
pre-emphasis compensation of the GS12190 output channel is a two-step process. The
first step is to use the settings from Figure 4-12 to Figure 4-19 that best match the
insertion loss of the link in the application, while the second step is a fine optimization
procedure.
In most cases, where the downstream device has a reclocker, the first step alone may
meet the design target. However, if the downstream device is a non-reclocked buffer or
crosspoint, it may be required to further optimize the settings to minimize the jitter
thereby maximizing the system jitter budget. To do this, please see the Fine
Optimization Procedure.
In the remainder of this section the following abbreviations are used for clarity:
DS = Driver Swing
PPA = Pre-emphasis Pulse Amplitude
PPW = Pre-emphasis Pulse Width
7
6
5
5
10 15
3
5 10 15 10 15 20 10 15 20 15 20 25 15 20 25 20 25 30
PPA
4
7
8
11
12
15
PPW
Figure 4-12: Pre-emphasis Settings for VCCO_1 = 1.2V and DS = 7 (swing = 200mVpp
)
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4
3
10
20
15
30
PPA
PPW
Figure 4-13: Pre-emphasis Settings for VCCO_1 = 1.2V and DS = 16 (swing = 400mVpp
)
12
10
8
6
5
10 15
3
5 10 15 10 15 20 10 15 20 15 20 25 15 20 25 20 25 30 35 40 45 50
PPA
4
7
8
11
12
15
PPW
Figure 4-14: Pre-emphasis Settings for VCCO_1 = 1.8V and DS = 7 (swing = 200mVpp
)
8
7
6
5
4
3
2
5
15 25
3
5
15 25 10 20 30 10 20 30 15 25 35 15 25 35 20 30 40 45 50 PPA
11 12 15
4
7
8
PPW
Figure 4-15: Pre-emphasis Settings for VCCO_1 = 1.8V and DS = 16 (swing = 400mVpp
)
3.5
3
2.5
2
1.5
10
20
30
15
40
50
PPA
PPW
Figure 4-16: Pre-emphasis Settings for VCCO_1 = 1.8V and DS = 35 (swing = 800mVpp
)
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13
12
11
10
9
8
7
6
5
10 15
3
5 10 15 10 15 20 10 15 20 15 20 25 15 20 25 20 25 30 35 40 45 50
PPA
4
7
8
11
12
15
PPW
Figure 4-17: Pre-emphasis Settings for VCCO_1 = 2.5V and DS = 7 (swing = 200mVpp
)
8
7
6
5
4
3
5
15 25
3
5 15 25 10 20 30 10 20 30 15 25 35 15 25 35 20 30 40 45 50
PPA
4
7
8
11
12
15
PPW
Figure 4-18: Pre-emphasis Settings for VCCO_1 = 2.5V and DS = 16 (swing = 400mVpp
)
3.5
3
2.5
2
1.5
40
30
15
50
10
20
PPA
PPW
Figure 4-19: Pre-emphasis Settings for VCCO_1 = 2.5V and DS = 35 (swing = 800mVpp
)
4.8.4.1.1 Fine Optimization Procedure
The procedure requires access to the signal at the downstream device input, or
non-reclocked device output. If there are multiple stages between the initial
downstream device input and final measurement point, it is still possible to perform
optimization; however link settings within the other stages must be fairly optimized.
The pre-emphasis amplitude (PPA) and pre-emphasis width (PPW) settings can be
optimized by sweeping the PPA and PPW settings in increments of 'a' and 'w' and
selecting the setting which results in the lowest jitter. For Trace Driver optimization, 'a'
and 'w' increments of 5 should be sufficient.
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The procedure has three steps.
1. Pre-emphasis Amplitude (PPA) Optimization: Set the PPA and PPW to the values
obtained from the graph selected out of Figure 4-12 to Figure 4-19, and then
measure the downstream jitter. While keeping PPW constant, increment the PPA by
'a'. If the jitter is lower after the first increment, continue to increment by 'a' until the
jitter begins increasing or a setting of 50 is reached. If there was a setting which
resulted in a lower jitter measurement than the initial setting, that is the Optimized
Pre-emphasis Amplitude setting: PPAOptimal, and the PPA optimization procedure is
complete.
However, if the jitter increased after the first increment, decrement the setting by 'a'
below the initial value. If the jitter is lower after the first decrement, continue to
decrement by 'a' until the jitter begins increasing or a setting of 0 is reached. If there
was a setting which resulted in a lower jitter measurement than the initial setting,
that is the Optimized Pre-emphasis Amplitude: PPAOptimal
.
If incrementing the PPA or decrementing the PPA did not result in a setting with
lower jitter, then the initial setting obtained from the graph selected out of
Figure 4-12 to Figure 4-19 is the PPA optimized Pre-emphasis Amplitude setting:
PPAOptimal.
2. The second step is to set the PPA to the optimized setting PPAOptimal determined in
step 1 and PPW to the values obtained from the graph selected out of Figure 4-12
to Figure 4-19, then measure the downstream jitter. While keeping PPA constant,
increment the PPW by 'w'. If the jitter is lower after the first increment, continue to
increment by 'w' until the jitter begins increasing or a setting of 15 is reached. If
there was a setting which resulted in a lower jitter measurement than the initial
setting, that is the Optimized Pre-emphasis Width setting: PPWOptimal, and the
optimization procedure is complete.
However, if the jitter increased after the first increment, decrement the setting by
'w' below the initial value. If the jitter is lower after the first decrement, continue to
decrement by 1 until the jitter begins increasing or a value of 0 is reached. If there
was a setting which resulted in a lower jitter measurement than the initial setting,
that is the Optimized Pre-emphasis Width setting: PPWOptimal, and the optimization
procedure is complete.
If incrementing the PPW or decrementing the PPW did not result in a setting with
lower jitter, then the initial setting value obtained from the graph selected out of
Figure 4-12 to Figure 4-19 is the optimized Pre-emphasis Width setting: PPWOptimal
.
3. Pre-emphasis pulse amplitude has a direct impact on swing amplitude. The third
and final step is to readjust the driver swing until the swing amplitude design
target is met. The fine optimization procedure maybe repeated to ensure that the
PPAOptimal and PPWOptimal settings previously determined still hold with the new
DS setting.
Steps 1 and 2 are illustrated in Figure 4-20: PPA Optimization Flow Chart and Figure
4-21: PPW Optimization Flow Chart below.
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Parameter and Variable Definition
PPAinit: Initial PPA value from equation result.
PPWinit: Initial PPW value from equation result.
DSinit: Measurement sweep Initial Driver Swing Setting = 9.
PPAoptimal: Post measurement sweep Optimal Pre-emphasis Pulse Amplitude setting.
PPWoptimal: Post measurement sweep Optimal Pre-emphasis Pulse Width setting.
a: Measurement sweep PPA increment value.
Start Optimization
n: Measurement sweep test number value.
Set
PPA: Current Measurement Pre-emphasis Pulse Amplitude setting.
PPW: Current Measurement Pre-emphasis Pulse Width setting.
DS: Current Measurement Driver Swing Amplitude setting.
PPA = PPAinit
PPW = PPWinit
DS = DSinit
Recorded
Jitter
Measurement
1, 2, 3, …, n
Measure initial Jitter
record results for
measurement# n=0
Record Data
Read Data
PPA Optimization
Complete
PPAoptimal = PPA(n-1)
no
no
If (PPA – a) > 0
yes
If (PPA + a) < 50
yes
PPA = PPA + a
n = n + 1
PPA = PPA - a
n = n + 1
Measure Jitter
record results for
measurement# n
Measure Jitter
record results for
measurement# n
If n > 1
Or
PPA – (2*a) < 0
PPA Optimization
Complete
PPAoptimal = PPA(n-1)
yes
no
no
PPA Optimization
Complete
PPAoptimal = PPA(n-1)
no
If Jitter(n) <
jitter(n-1)
Is Jitter(n) <
jitter(n-1)
PPA = PPAinit
PPW = PPWinit
yes
yes
Figure 4-20: PPA Optimization Flow Chart
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Parameter and Variable Definition
PPWinit: Initial PPW value from equation result.
DSinit: Measurement sweep Initial Driver Swing Setting = 9.
PPAoptimal: Post measurement sweep Optimal Pre-emphasis Pulse Amplitude setting.
PPWoptimal: Post measurement sweep Optimal Pre-emphasis Pulse Width setting.
w: Measurement sweep PPW increment value.
Start Optimization
n: Measurement sweep test number value.
Set
PPA: Current Measurement Pre-emphasis Pulse Amplitude setting.
PPW: Current Measurement Pre-emphasis Pulse Width setting.
DS: Current Measurement Driver Swing Amplitude setting.
PPA = PPAoptimal
PPW = PPWinit
DS = DSinit
Recorded
Jitter
Measurement
1, 2, 3, …, n
Measure initial Jitter
record results for
measurement# n = 0
Record Data
Read Data
PPW Optimization
Complete
PPWoptimal = PPW(n-1)
no
no
If (PPW + w) <
16
If (PPW – w) > 0
yes
yes
PPW = PPW + w
n = n + 1
PPW = PPW - w
n = n + 1
Measure Jitter
record results for
measurement# n
Measure Jitter
record results for
measurement# n
If n > 1
Or
PPW – (2*w) < 0
PPW Optimization
Complete
PPWoptimal = PPW(n-1)
yes
no
no
PPW Optimization
Complete
PPWoptimal = PPW(n-1)
no
If Jitter(n) <
jitter(n-1)
Is Jitter(n) <
jitter(n-1)
PPW = PPWinit
yes
yes
Figure 4-21: PPW Optimization Flow Chart
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Table 4-9: Output Swing and Pre-emphasis Control Parameters
Register
Addresshand
Parameter Name
Description
Name
2B/29
OUTPUT_
PARAM_CD_
SD_3/OUTPUT_
PARAM_
Output amplitude configuration parameter.
<n> = 0: For SD and MADI rates on SDIO.
<n> = 1: For SD or all rates* on DDO.
CFG_OUTPUT<n>_CD/TD_
SD_DRIVER_SWING
Note: If CTRL_OUTPUT1_TRDR_PER_RATE = 0, this setting will
be used for all data rates output form DDO.
TD_SD_1
Output pre-emphasis pulse width configuration parameter.
<n> = 0: Reserved - do not modify.
<n> = 1: For SD or all rates* on DDO.
CFG_OUTPUT<n>_CD/TD_SD_
PREEMPH_WIDTH
Note: If CTRL_OUTPUT1_TRDR_PER_RATE = 0, this setting will
be used for all data rates output form DDO.
2A/28
OUTPUT_
PARAM_CD_
SD_2/OUTPUT_
PARAM_TD_
SD_0
Output pre-emphasis power-down configuration parameter.
<n>=0:Reserved - do not modify.
<n>=1:For SD or all rates* on DDO.
CFG_OUTPUT<n>_CD/TD_SD_
PREEMPH_PWRDWN
Note: If CTRL_OUTPUT1_TRDR_PER_RATE = 0, this setting will
be used for all data rates output form DDO.
Output amplitude configuration parameter.
<n> = 0: Reserved - do not modify.
<n> = 1: For SD or all rates* on DDO.
CFG_OUTPUT<n>_CD/TD_SD_
PREEMPH_AMPL
Note: If CTRL_OUTPUT1_TRDR_PER_RATE = 0, this setting will
be used for all data rates output form DDO.
2D/2F
OUTPUT_
PARAM_
TD_HD_1/
OUTPUT_
PARAM_
CD_HD_3
Output amplitude configuration parameter.
CFG_OUTPUT<n>_CD/TD_
HD_DRIVER_SWING
<n> = 0: For HD and 3G rates on SDIO.
<n> = 1: For HD rates on DDO.
Output pre-emphasis pulse width configuration parameter.
CFG_OUTPUT<n>_CD/TD_
HD_PREEMPH_WIDTH
<n> = 0: For HD and 3G rates on SDIO.
<n> = 1: For HD rates on DDO.
2C/2E
OUTPUT_
PARAM_
TD_HD_0/
OUTPUT_
PARAM_
CD_HD_2
Output pre-emphasis power-down configuration parameter.
CFG_OUTPUT<n>_CD/TD_
HD_PREEMPH_PWRDWN
<n> = 0: For HD and 3G rates on SDIO.
<n> = 1: For HD rates on DDO.
Output pre-emphasis power-down configuration parameter.
CFG_OUTPUT<n>_CD/TD_
HD_PREEMPH_AMPL
<n> = 0: For HD and 3G rates on SDIO.
<n> = 1: For HD rates on DDO.
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Table 4-9: Output Swing and Pre-emphasis Control Parameters (Continued)
Register
Addresshand
Parameter Name
Description
Name
31/33
OUTPUT_
PARAM_
TD_3G_1/
OUTPUT_
PARAM_
CD_UHD_3
Output amplitude configuration parameter.
CFG_OUTPUT<n>_TD/CD_
3G/UHD_DRIVER_SWING
<n> = 0: For 6G and 12G rates on SDIO.
<n> = 1: For 3G rates on DDO.
Output pre-emphasis pulse width configuration parameter.
CFG_OUTPUT<n>_TD/CD_
3G/UHD_PREEMPH_WIDTH
<n> = 0: For 6G and 12G rates on SDIO.
<n> = 1: For 3G rates on DDO.
30/32
OUTPUT_
PARAM_
TD_3G_0/
OUTPUT_
PARAM_
CD_UHD_2
Output pre-emphasis power-down configuration parameter.
CFG_OUTPUT<n>_TD/CD_
3G/UHD_PREEMPH_
PWRDWN
<n> = 0: For 6G and 12G rates on SDIO.
<n> = 1: For 3G rates on DDO.
Output pre-emphasis pulse amplitude configuration parameter.
CFG_OUTPUT<n>_TD/CD_
3G/UHD_PREEMPH_AMPL
<n> = 0: For 6G and 12G rates on SDIO.
<n> = 1: For 3G rates on DDO.
35
OUTPUT_
PARAM_
TD_6G_1
CFG_OUTPUT1_TD_6G_
DRIVER_SWING
DDO Trace Driver amplitude configuration parameter for 6G.
CFG_OUTPUT1_TD_6G_
PREEMPH_WIDTH
DDO Trace Driver output pre-emphasis pulse width
configuration parameter for 6G.
0x34
OUTPUT_
PARAM_
TD_6G_0
CFG_OUTPUT1_TD_6G_
PREEMPH_PWRDWN
DDO output pre-emphasis power-down configuration
parameter for 6G.
CFG_OUTPUT1_TD_6G_
PREEMPH_AMPL
DDO Trace Driver output pre-emphasis pulse amplitude
configuration parameter for 6G.
39
OUTPUT_
PARAM_
TD_12G_1
CFG_OUTPUT1_TD_12G_
DRIVER_SWING
DDO Trace Driver amplitude configuration parameter for 12G.
CFG_OUTPUT1_TD_12G_
PREEMPH_WIDTH
DDO Trace Driver output pre-emphasis pulse width
configuration parameter for 12G.
38
OUTPUT_
PARAM_
TD_12G_0
CFG_OUTPUT1_TD_12G_
PREEMPH_PWRDWN
DDO output pre-emphasis power-down configuration
parameter for 12G.
CFG_OUTPUT1_TD_12G_
PREEMPH_AMPL
DDO Trace Driver output pre-emphasis pulse amplitude
configuration parameter for 12G.
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4.8.5 Trace Driver DC-Coupling Requirements
Table 4-10 lists the required Vcco (driver supply voltage) and DS (driver swing) required
to achieve three common nominal VDDOppd (peak-to-peak differential output voltages)
and their associated nominal Vcmout (output common mode voltage).
In the DC-coupled case, where Vcco is connected to the same supply as the input buffer
supply voltage of the downstream device, Vcmount in Table 4-10 is the common mode
voltage at the output of the GS12190 driver. For short low-loss transmission lines, this
will also be the common mode voltage created at the input termination of the
downstream input buffer. However, for long and lossy transmission lines, the amplitude
will be attenuated at the downstream receiver and therefore the common mode
voltage created at the input termination will be higher and must be measured or
simulated for accuracy. For proper link operation, the common mode voltage created at
the input termination of the downstream input buffer must be within the Vcmin range
specified by that device.
In the AC-coupled case, Vcmout is the common mode voltage at the driver side of the
AC-coupling capacitor placed near the driver. In the AC-coupled case, Vcmout does not
need to be within the Vcmin range specified by the downstream device. However, the
capacitor should have a voltage rating that exceeds |Vcmout-Vcmin|. In addition to the
voltage rating, the recommended value of the AC-coupling capacitor should be at least
4.7μF to meet the low cut-off frequency requirement of low transition density signals
such as the check-field pattern defined in SMPTE RP-198. The capacitor should have a
temperature rating that maintains the capacitance over the required operating range.
Table 4-10: ΔVDDO (mVppd) and VCMOUT(V) vs. DS Setting and VCCO
DC-Coupled
ΔVDDO (mVppd) vs. DS Setting
AC-Coupled
VCMOUT (V) vs. DS Setting
VCMOUT (V) vs. DS Setting
Vcco (V)
8
17
37
8
17
37
8
17
37
1.2
1.8
2.5
200
200
200
400
400
400
—
1.15
1.75
2.45
1.1
1.7
2.4
—
1.6
2.3
1.1
1.7
2.4
1
—
1.4
2.1
800
800
1.6
2.3
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4.8.6 Output State Control Modes
The GS12190 provides several output state control modes to meet specific application
requirements. The Trace Driver has the following three output modes: operational,
muted, or disabled. The Cable Driver also has these three modes and additionally has a
balanced mode. During non-sleep, if the control modes are configured such that
multiple output modes are enabled, the priorities of the control modes from highest to
lowest are the following: balanced (Cable Driver only), disabled, and then muted.
Section 4.8.6.1 through Section 4.8.6.3 describe how to configure the output control
modes that are enabled during non-sleep.
If the device enters sleep, either manually or automatically, the sleep output control
modes take precedence over the non-sleep control modes. During sleep, the Cable
Driver will always be disabled, while the Trace Driver can be configured to mute or
disable during sleep. The default Trace Driver configuration is for it to be disabled
during sleep; however the Trace Driver can be configured to mute during sleep by
setting the CFG_SLEEP_OUTPUT1_MUTE parameter in register 0x5h to 1b.
4.8.6.1 Output Mute Control Mode
Each of the outputs on the GS12190 have independent mute control modes, which can
be configured through the host interface.
The following are the four output mute control modes:
1. The outputs automatically mute on LOS (default).
2. The outputs automatically mute on LOS and during rate search.
3. The outputs never mute.
4. The outputs are always muted.
The first mute control mode is the default power-up configuration for both output
drivers (the CTRL_OUTPUT<n>_AUTO_MUTE control parameter in register 0x49h is
set to 1b). In this mode, the outputs will automatically mute on the assertion of LOS. This
includes LOS as a result of setting up Squelch Adjust (see Section 4.2.3 for more details).
In addition to mute on LOS, with auto mute control mode configured, setting the
CTRL_OUTPUT<n>_AUTO_MUTE_DURING_RATE_SEARCH control parameter in
register 0x49h to 1b, will configure the outputs to also mute when the device loses lock
and begins to rate search.
The outputs can be manually configured to never mute by setting both the
CTRL_OUTPUT<n>_AUTO_MUTE and CTRL_OUTPUT<n>_MANUAL_MUTE control
parameters in register 0x49h to 0b. Alternatively, the outputs can be manually
configured to always be muted by setting the CTRL_OUTPUT<n>_AUTO_MUTE and
CTRL_OUTPUT<n>_MANUAL_MUTE control parameters to 0b and 1b respectively.
4.8.6.2 Output Disable Control Mode
Each of the outputs on the GS12190 also have independent disable control modes,
which can be configured through the host interface.
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The following are the three output disable control modes:
1. The outputs are never disabled (default).
2. The outputs are automatically disabled on LOS.
3. The outputs are always disabled.
The first disable control mode is the default power-up configuration for both output
drivers (the CTRL_OUTPUT<n>_AUTO_DISABLE and
CTRL_OUTPUT<n>_MANUAL_DISABLE control parameters in register 0x4Ah are both
set to 0b). In this mode, the outputs will never disable. By setting the
CTRL_OUTPUT<n>_AUTO_DISABLE control parameter in register 0x4Ah to 1b, the
outputs will automatically disable on the assertion of LOS. This includes LOS as a result
of setting up Squelch Adjust (see Section 4.2.3 for more details).
The output can be manually disabled by leaving the
CTRL_OUTPUT<n>_AUTO_DISABLE control parameter set to 0b and setting the
CTRL_OUTPUT<n>_MANUAL_DISABLE control parameter to 1b.
The disable control mode takes precedence over the output mute control mode.
4.8.6.3 Output Balanced Control Mode
The GS12190 has a feature designed to facilitate reliable Output Return Loss (ORL)
measurements on SDIO/SDO while the device is still powered. The device can be put into
balanced control mode which prevents the outputs from toggling while ORL is being
measured. Balanced control mode can be enabled through the host interface, by setting
control parameter CTRL_OUTPUT0_BALANCED in register 4Dh to 1b. This control is
solely for the Cable Driver output. This control mode takes precedence over both the
output mute and output disable control modes.
4.8.6.4 Loopback Control
The GS12190 has the ability to loop a reclocked version of the signal applied to the Trace
Equalizer input (DDI) to the Trace Driver output (DDO) while in Cable Driver Mode. To
enable this feature set CTRL_LOOPBACK_ENA to 1.
With default settings applied, and the device set to Cable Driver Mode, the Trace Driver
is inactive and it is controlled by the CFG_TRDR_MUTE_WHEN_CABLE_DRIVER
parameter to determine whether it is muted or disabled. Once CTRL_LOOPBACK_ENA
is set to 1, it overrides any setting in CFG_TRDR_MUTE_WHEN_CABLE_DRIVER.
Note: When using the Loopback feature, please note the following:
•
•
•
The Loopback signal of DDI appearing on DDO will be only be reclocked if the
device is locked to the signal applied to the Trace Equalizer input (DDI). If the
reclocker is bypassed or not locked, the loopback signal will not be reclocked.
The output state control modes described in Section 4.8.6.1 to Section 4.8.6.3
(disable, mute, and balanced) take priority over the CTRL_LOOPBACK_ENA
parameter.
This mode is only applicable to Cable Driver Mode, using DDI as the input.
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4.9 GPIO Controls
There are four configurable GPIO pins which can independently be configured as inputs
or outputs. Each GPIO has a default function which can be re-configured through the
host interface.
If there is a conflict between the internal register configuration of a given device
function and the logic-level applied to a GPIO pin that is configured to control that same
device function, the GPIO logic-level takes precedence over the internal register
configuration. The logic HIGH and LOW levels of the GPIO[3:0] pin to which LOS is
connected are specified by the EIA/JESD8-5A standard for 1.8V operation.
For a list of available functions and configuration details of GPIO[3:0], please refer to the
GPIO Configuration Registers in Section 5.
4.10 GSPI Host Interface
The GS12190 is configured via the Gennum Serial Peripheral Interface (GSPI).
The GSPI host interface is comprised of a serial data input signal (SDIN pin), serial data
output signal (SDOUT pin), an active-LOW chip select (CS pin) and a burst clock (SCLK
pin).
The GS12190 is a slave device, so the SCLK, SDIN and CS signals must be sourced by the
application host processor.
All read and write access to the device is initiated and terminated by the application
host processor.
4.10.1 CS Pin
The Chip Select pin (CS) is an active-low signal provided by the host processor to the
GS12190.
The HIGH-to-LOW transition of this pin marks the start of serial communication to the
GS12190.
The LOW-to-HIGH transition of this pin marks the end of serial communication to the
GS12190.
Each device may use its own separate Chip Select signal from the host processor or up
to 32 devices may be connected to a single Chip Select when making use of the Unit
Address feature.
Only those devices whose Unit Address matches the UNIT ADDRESS in GSPI Command
Word 1 will respond to communication from the host processor (unless the B’CAST ALL
bit in GSPI Command Word 1 is set to 1).
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4.10.2 SDIN Pin
The SDIN pin is the GSPI serial data input pin of the GS12190.
The 32-bit Command and 16-bit Data Words from the host processor or from the SDOUT
pin of other devices are shifted into the device on the rising edge of SCLK when the CS
pin is LOW.
4.10.3 SDOUT Pin
The SDOUT pin is the GSPI serial data output of the GS12190.
All data transfers out of the GS12190 to the host processor or to the SDIN pin of other
connected devices occur from this pin.
By default at power-up or after system reset, the SDOUT pin provides a non-clocked path
directly from the SDIN pin, regardless of the CS pin state, except during the GSPI Data
Word portion for read operations from the device. This allows multiple devices to be
connected in Loop-Through configuration.
For read operations, the SDOUT pin is used to output data read from an internal
Configuration and Status Register (CSR) when CS is LOW. Data is shifted out of the device
on the falling edge of SCLK, so that it can be read by the host processor or other
downstream connected device on the subsequent SCLK rising edge.
4.10.3.1 GSPI Link Disable Operation
It is possible to disable the direct SDIN to SDOUT (Loop-Through) connection by writing
a value of 1 to the GSPI_LINK_DISABLE bit in CONTROL_REG. When disabled, any data
appearing at the SDIN pin will not appear at the SDOUT pin and the SDOUT pin is HIGH.
Note: Disabling the Loop-Through operation is temporarily required when initializing
the Unit Address for up to 32 connected devices.
The time required to enable/disable the Loop-Through operation from assertion of the
register bit is less than the GSPI configuration command delay as defined by the
parameter tcmd_GSPI_config (4 SCLK cycles).
Table 4-11: GSPI_LINK_DISABLE Bit Operation
Bit State
Description
0
1
SDIN pin is looped through to the SDOUT pin
Data appearing at SDIN does not appear at SDOUT, and SDOUT pin is HIGH.
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SDIN pin
Configuration and
Status Register
SDOUT pin
GSPI_LINK
_DISABLE
High-Z
BUS_THROUGH_
ENABLE
CS pin
Figure 4-22: GSPI_LINK_DISABLE Operation
4.10.3.2 GSPI Bus-Through Operation
Using GSPI Bus-Through operation, the GS12190 can share a common PCB trace with
other GSPI devices for SDOUT output.
When configured for Bus-Through operation, by setting
GSPI_BUS_THROUGH_ENABLE bit to 1, the SDOUT pin will be high-impedance when
the CS pin is HIGH.
When the CS pin is LOW, the SDOUT pin will be driven and will follow regular read and
write operation as described in Section 4.10.3.
Multiple chains of GS12190 devices can share a single SDOUT bus connection to host by
configuring the devices for Bus-Through operation. In such configuration, each chain
requires a separate Chip Select (CS).
SDIN pin
Configuration and
Status Register
SDOUT pin
GSPI_LINK
_DISABLE
High-Z
BUS_THROUGH_
ENABLE
CS pin
Figure 4-23: GSPI_BUS_THROUGH_ENABLE Operation
4.10.4 SCLK Pin
The SCLK pin is the GSPI serial data shift clock input to the device, and must be provided
by the host processor.
Serial data is clocked into the GS12190 SDIN pin on the rising edge of SCLK. Serial data
is clocked out of the device from the SDOUT pin on the falling edge of SCLK (read
operation). SCLK is ignored when CS is HIGH.
The maximum interface clock rate is 27MHz.
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4.10.5 Command Word 1 Description
All GSPI accesses are a minimum of 48 bits in length (two 16-bit Command Words
followed by a 16-bit Data Word) and the start of each access is indicated by the
HIGH-to-LOW transition of the Chip Select (CS) pin of the GS12190.
The format of the Command Words and Data Word are shown in Figure 4-24.
Data received immediately following this HIGH-to-LOW transition will be interpreted as
a new Command Word.
4.10.5.1 R/W bit—B15 Command Word 1
This bit indicates a read or write operation.
When R/W is set to 1, a read operation is indicated, and data is read from the register
specified by the ADDRESS field of the Command Word.
When R/W is set to 0, a write operation is indicated, and data is written to the register
specified by the ADDRESS field of the Command Word.
4.10.5.2 B'CAST ALL—B14 Command Word 1
This bit is used in write operations to configure all devices connected in Loop-Through
and Bus-Through configuration with a single command.
When B’CAST ALL is set to 1, the following Data Word (AUTOINC = 0) or Data Words
(AUTOINC = 1) are written to the register specified by the ADDRESS field of the
Command Words (and subsequent addresses when AUTOINC = 1), regardless of the
setting of the UNIT ADDRESS(es).
When B’CAST ALL is set to 0, a normal write operation is indicated. Only those devices
that have a Unit Address matching the UNIT ADDRESS field of Command Word 1 write
the Data Word to the register specified by the ADDRESS field of the Command Words.
4.10.5.3 EMEM—B13 Command Word 1
The EMEM bit must be set to 1 in Command Word 1. When EMEM is set to 1, a 23-bit
address split between Command Word 1 and Command Word 2 is used to access the
registers in this device.
4.10.5.4 AUTOINC—B12 Command Word 1
When AUTOINC is set to 1, Auto-Increment read or write access is enabled.
In Auto-Increment Mode, the device automatically increments the register address for
each contiguous read or write access, starting from the address defined in the ADDRESS
field of the Command Word.
The internal address is incremented for each 16-bit read or write access until a
LOW-to-HIGH transition on the CS pin is detected.
When AUTOINC is set to 0, single read or write access is required.
Auto-Increment write must not be used to update values in CONTROL_REG.
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4.10.5.5 UNIT ADDRESS—B11:B7 Command Word 1
The 5 bits of the UNIT ADDRESS field of the Command Word are used to select one of 32
devices connected on a single chip select in Loop-Through or Bus-Through
configurations.
Read and write accesses are only accepted if the UNIT ADDRESS field matches the
programmed DEV_UNIT_ADDRESS in CONTROL_REG.
By default at power-up or after a device reset, the DEV_UNIT_ADDRESS is set to 00h.
4.10.5.6 ADDRESS—B6:B0 Command Word 1 and B15:B0 Command Word 2
The Command and Data Word formats are shown in Figure 4-24 and Figure 4-25. As an
example of the command word structure, reading register 0x90h from a device with unit
address 3, that has AUTOINC = 0, and B’CAST ALL = 0 would be structured as follows:
•
•
Command word 1: 1010 0001 1000 0000 (0xA180h)
Command word 2: 0000 0000 1001 0000 (0x90h)
Command Words
MSB
LSB
UNIT ADDRESS
ADDRESS[22:16]
A19
B’CAST
ALL
EMEM
A13
AUTOINC
A12
UA4
A11
UA3
A10
UA2
A9
UA1
UA0
A22
A6
A21
A5
A20
A4
A18
A2
A17
A1
A16
R / W
ADDRESS[15:0]
A8 A7
A15
A14
A3
D3
A0
D0
Data Word
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D2
D1
Figure 4-24: Command and Data Word Format
Command Word 1
MSB
R / W
LSB
UNIT ADDRESS
UA2
ADDRESS[22:16]
A19
B’CAST
ALL
EMEM
AUTOINC
UA4
UA3
UA1
UA0
A22
A21
A20
A18
A17
A16
23-bit CSR address field.
5-bit UNIT ADDRESS field providing up to
32 devices to be connected on a single CS.
Auto increment read/write access when set.
Single read write access when reset.
Extended memory mode. When set, the extended memory mode is
enabled. When reset, normal GSPI addressing is enabled.
When set, the UNIT ADDRESS field is ignored and
all data accesses are actioned by the device.
When reset, the Unit Address is used to
manage data accesses in the device.
Read access when this bit is set.
Write access when this bit is reset.
Command Word 2
ADDRESS[15:0]
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Figure 4-25: Command Word 1 and Command Word 2 Details
Note: Please see Section 4.10.5.6 ADDRESS—B6:B0 Command Word 1 and B15:B0
Command Word 2 for an example of the command word structure.
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4.10.6 GSPI Transaction Timing
tcmd_GSPI_config
tcmd
t9
SCLK
CS
X
X
SDIN
SDOUT
t0
t1
t2
t4
t7
SCLK
CSb
t3
t8
R/W
BCST
EMEM
Auto_Inc
UA4
UA3
UA2
UA1
UA0
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SDIN
SDOUT
R/W
BCST
EMEM
Auto_Inc
UA4
UA3
UA2
UA1
UA0
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D15
D14
D13
D
12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SDIN signal is looped out on SDOUT
Write Mode
t5
t9
SCLK
CSb
t6
R/W
RSV
EMEM
Auto_Inc
UA4
UA3
UA2
UA1
UA0
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
SDIN
SDOUT
R/W
RSV
EMEM
Auto_Inc
UA4
UA3
UA2
UA1
UA0
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Read Data is output on SDOUT
SDIN signal is looped out on SDOUT
Read Mode
Figure 4-26: GSPI External Interface Timing
Table 4-12: GSPI Timing Parameters
Equivalent
SCLK
Parameter
Symbol
Min
Typ
Max
Units
Cycles
SCLK Frequency
—
t0
—
—
—
—
—
1
—
1.7
37
—
—
—
50
—
—
—
—
27
—
—
60
—
—
—
—
MHz
ns
CS LOW Before SCLK Rising Edge
SCLK Period
t1
t2
ns
SCLK Duty Cycle
40
%
t3
Input Data Setup Time
SCLK Idle Time – Write
SCLK Idle Time – Read
Inter–Command Delay Time
2.3
ns
38.51
138
t4
ns
t5
—
3
ns
tcmd
115
ns
Inter–Command Delay Time (after
GSPI configuration write)
2
4
139
1.3
0
—
—
—
—
6.4
—
ns
ns
ns
tcmd_GSPI_conf
t6
t7
SDOUT After SCLK Falling Edge
—
—
CS HIGH After Final SCLK Falling
Edge
t8
t9
Input Data Hold Time
CS HIGH Time
—
—
1.2
58
—
—
—
—
ns
ns
SDIN to SDOUT Combinatorial
Delay
—
—
—
—
3.4
ns
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Table 4-12: GSPI Timing Parameters (Continued)
Equivalent
SCLK
Cycles
Parameter
Symbol
Min
Typ
Max
Units
# of
Max chips daisy-chained at max
SCLK frequency (26 MHz)
compatible
Semtech
devices
—
—
—
—
8
When host clocks in SDOUT
data on falling edge of SCLK
Max frequency for 32
daisy-chained devices
7.5
MHz
Note:
1. Parameter is exactly multiple of SCLK periods and scales proportionally.
2. tcmd_GSPI_conf inter-command delay must be used whenever modifying CONTROL_REG register at address 0x00.
4.10.7 Single Read/Write Access
Single read/write access timing for the GSPI interface is shown in Figure 4-27 to
Figure 4-31.
When performing a single read or write access, one Data Word is read from/written to
the device per access. Each access is a minimum of 48-bits long, consisting of two
Command Words and a single Data Word. The read or write cycle begins with a
HIGH-to-LOW transition of the CS pin. The read or write access is terminated by a
LOW-to-HIGH transition of the CS pin.
The maximum interface clock rate is 27MHz and the inter-command delay time
indicated in the figures as tcmd, is a minimum of 3 SCLK clock cycles. After modifying
values in CONTROL_REG, the inter-command delay time, tcmd_GSPI_config, is a minimum
of 4 SCLK clock cycles.
For read access, the time from the last bit of Command Word 2 to the start of the data
output, as defined by t5, corresponds to no less than 4 SCLK clock cycles at 27MHz.
t
cmd
SCLK
CS
COMMAND WORD 1
COMMAND WORD 1
COMMAND WORD 2
COMMAND WORD 2
DATA WORD
DATA WORD
X
X
COMMAND WORD 1
COMMAND WORD 1
SDIN
SDOUT
Figure 4-27: GSPI Write Timing—Single Write Access with Loop-Through Operation (default)
t
cmd
SCLK
CS
SDIN
COMMAND WORD 2
COMMAND WORD 1
DATA WORD
X
COMMAND WORD 1
SDOUT
Figure 4-28: GSPI Write Timing—Single Write Access with GSPI Link-Disable Operation
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t
cmd
SCLK
CS
COMMAND WORD 2
COMMAND WORD 2
COMMAND WORD 1
COMMAND WORD 1
DATA WORD
DATA WORD
X
High-z
COMMAND WORD 1
COMMAND WORD 1
SDIN
High-Z
SDOUT
Figure 4-29: GSPI Write Timing—Single Write Access with Bus-Through Operation
SCLK
t
5
CS
COMMAND WORD 1
COMMAND WORD 1
COMMAND WORD 2
COMMAND WORD 2
SDIN
DATA WORD
SDOUT
Figure 4-30: GSPI Read Timing—Single Read Access with Loop-Through Operation (default)
SCLK
t
5
CS
SDIN
COMMAND WORD
COMMAND WORD
1
1
COMMAND WORD
COMMAND WORD
2
2
High-z
X
DATA WORD
SDOUT
Figure 4-31: GSPI Read Timing—Single Read Access with Bus-Through Operation
4.10.8 Auto-increment Read/Write Access
Auto-increment read/write access timing for the GSPI interface is shown in Figure 4-32
to Figure 4-36.
Auto-increment mode is enabled by the setting the AUTOINC bit of Command Word 1.
In this mode, multiple Data Words can be read from/written to the device using only one
starting address. Each access is initiated by a HIGH-to-LOW transition of the CS pin, and
consists of two Command Words and one or more Data Words. The internal address is
automatically incremented after the first read or write Data Word, and continues to
increment until the read or write access is terminated by a LOW-to-HIGH transition of
the CS pin.
Note: Writing to CONTROL_REG using Auto-increment access is not allowed.
The maximum interface clock rate is 27MHz and the inter-command delay time
indicated in the diagram as tcmd, is a minimum of 3 SCLK clock cycles.
For read access, the time from the last bit of the second Command Word to the start of
the data output of the first Data Word as defined by t5 will be no less than 4 SCLK cycles
at 27MHz. All subsequent read data accesses will not be subject to this delay during an
Auto-Increment read.
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SCLK
CS
SDIN
COMMAND WORD 1
COMMAND WORD 1
COMMAND WORD 2
COMMAND WORD 2
DATA 1
DATA 1
DATA 2
DATA 2
SDOUT
Figure 4-32: GSPI Write Timing—Auto-Increment with Loop-Through Operation (default)
SCLK
CS
COMMAND WORD 1
COMMAND WORD 2
DATA 1
DATA 2
SDIN
SDOUT
Figure 4-33: GSPI Write Timing—Auto-Increment with GSPI Link Disable
Operation
SCLK
CS
SDIN
COMMAND WORD 2
COMMAND WORD 2
COMMAND WORD 1
COMMAND WORD 1
DATA 1
DATA 1
DATA 2
DATA 2
High-Z
SDOUT
Figure 4-34: GSPI Write Timing—Auto-Increment with Bus-Through Operation
SCLK
t
5
CS
SDIN
COMMAND WORD 1
COMMAND WORD 1
COMMAND WORD 2
COMMAND WORD 2
SDOUT
DATA 1
DATA 2
Figure 4-35: GSPI Read Timing—Auto-Increment Read with Loop-Through Operation (default)
SCLK
t
5
CS
SDIN
COMMAND WORD 1
COMMAND WORD 1
COMMAND WORD 2
COMMAND WORD 2
High-z
SDOUT
X
DATA 1
DATA 2
Figure 4-36: GSPI Read Timing—Auto-Increment Read with Bus-through Operation
4.10.9 Setting a Device Unit Address
Multiple (up to 32) GS12190 devices can be connected to a common Chip Select (CS) in
Loop-Through or Bus-Through operation.
To ensure that each device selected by a common CS can be separately addressed, a
unique Unit Address must be programmed by the host processor at start-up as part of
system initialization or following a device reset.
Note: By default at power-up or after a device reset, the DEV_UNIT_ADDRESS of each
device is set to 0h and the SDINSDOUT non-clocked loop-through for each device is
enabled.
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These are the steps required to set the DEV_UNIT_ADDRESS of devices in a chain to
values other than 0:
1. Write to Unit Address 0 selecting CONTROL_REG (ADDRESS = 0h), with the
GSPI_LINK_DISABLE bit set to 1 and the DEV_UNIT_ADDRESS field set to 0. This
disables the direct SDINSDOUT non-clocked path for all devices on chip select.
2. Write to Unit Address 0 selecting CONTROL_REG (ADDRESS = 0h), with the
GSPI_LINK_DISABLE bit set to 0 and the DEV_UNIT_ADDRESS field set to a
unique Unit Address. This configures DEV_UNIT_ADDRESS for the first device in
the chain. Each subsequent such write to Unit Address 0 will configure the next
device in the chain. If there are 32 devices in a chain, the last (32nd) device in the
chain must use DEV_UNIT_ADDRESS value 0.
3. Repeat step 2 using new, unique values for the DEV_UNIT_ADDRESS field in
CONTROL_REG until all devices in the chain have been configured with their own
unique Unit Address value.
Note: tcmd_GSPI_conf delay must be observed after every write that modifies
CONTROL_REG.
All connected devices receive this command (by default the Unit Address of all devices
is 0), and the Loop-Through operation will be re-established for all connected devices.
Once configured, each device will only respond to Command Words with a
UNIT ADDRESS field matching the DEV_UNIT_ADDRESS in CONTROL_REG.
Note: Although the Loop-Through and Bus-Through configurations are compatible
with previous generation GSPI enabled devices (backward compatibility), only devices
supporting Unit Addressing can share a chip select. All devices on any single chip select
must be connected in a contiguous chain with only the last device's SDOUT connected
to the application host processor. Multiple chains configured in Bus-Through mode can
have their final SDOUT outputs connected to a single application host processor input.
4.10.10 Default GSPI Operation
By default at power-up or after a device reset, the GS12190 is set for Loop-Through
Operation and the internal DEV_UNIT_ADDRESS field of the device is set to 0.
Figure 4-37 shows a functional block diagram of the Configuration and Status Register
(CSR) map in the GS12190.
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At power-up or after a device reset, DEVICE_UNIT_ADDRESS = 00h
[15]
R/W
[14]
[13]
[12]
[11:7]
[6:0]
bits
BCAST
ALL
Auto
Inc
Unit Address
32 devices
Register Address
Upper 7 bits
EMEM
COMMAND 1
[15:0]
bits
COMMAND 2
Lower 16 bits of Register Address
[15:0]
bits
Compare
DATA
Data to be written / Read Data
[4:0]
[15]
[14]
[12:5]
bits
[13]
Read/Write
GSPI_BUS_
THROUGH
_ENABLE
GSPI_LINK
_DISABLE
Reg 0
RESERVED
DEV_UNIT_ADDRESS
RESERVED
Configuration and Status Registers
Figure 4-37: Internal Register Map Functional Block Diagram
The steps required for the application host processor to write to the Configuration and
Status Registers via the GSPI, are as follows:
1. Set Command Word 1 for write access (R/W = 0); set Auto Increment; set the Unit
Address field in the Command Word 1 to match the configured
DEV_UNIT_ADDRESS which will be zero after power-up. Set the Register Address
bits in Command Word 1 to match the upper 7 bits of the register address to be
accessed. Set the bits in Command Word 2 to match the lower 16 bits of the register
address to be accessed. Write Command Word 1 and Command Word 2.
2. Write the Data Word to be written to the first register.
3. Write the Data Word to be written to the next register in Auto Increment mode, etc.
Read access is the same as the above with the exception of step 1, where the Command
Word 1 is set for read access (R/W = 1).
Note: The UNIT ADDRESS field of Command Word 1 must always match
DEV_UNIT_ADDRESS for an access to be accepted by the device. Changing
DEV_UNIT_ADDRESS to a value other than 0 is only required if multiple devices are
connected to a single chip select (in Loop-Through or Bus-Through configuration).
4.10.11 Clear Sticky Counts Through Four Way Handshake
There are four sticky counters that keep count of changes in status of primary and
secondary carrier detect, rate changes, and lock changes. The counters can be read from
the following four parameters in register 0x84h and 0x85h:
STAT_CNT_PRI_CD_CHANGES, STAT_CNT_SEC_CD_CHANGES,
STAT_CNT_RATE_CHANGES, and STAT_CNT_PLL_LOCK_CHANGES. The counters
saturate at 255 (0xFFh) and must be cleared before additional status changes can be
counted. The following four way handshake procedures clears the counters.
1. Poll STAT_CLEAR_COUNTS_STATUS parameter until equal to 0 (idle), then set
CTRL_CLEAR_COUNTS = 1 (clear sticky counts).
2. Poll STAT_CLEAR_COUNTS_STATUS parameter until equal to 2 (cleared), then
reset CTRL_CLEAR_COUNTS to 0.
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The device will now reset STAT_CLEAR_COUNTS_STATUS to 0 (idle) and the clearing
process can be repeated at any time.
4.10.12 Device Power-Up Sequence
If all power supplies cannot be guaranteed to power-up simultaneously, ensure that
VCC_DDI powers up first. Please note that there is no minimum time requirement
between power supply initializations after VCC_DDI is energized.
Note: Please check with your local FAE (Field Applications Engineer), as some devices
may need updated configuration settings. If a configuration file has been provided by
the FAE, see the timing information in the Serial Routing and Distribution Product
Configuration Loading Procedure Application Note (PDS-061176).
4.10.12.1 Power-Up Timing Sequence
The following timing sequence must be observed after power-up when no external
configuration loading is required. See Figure 4-38 for the timing requirements of Steps
1 and 2 below.
Step 1 – No GSPI Access Allowed
a) Device supply reaches 90% of target. POR (Power On Reset) is activated.
b) Internal blocks reset, default device configuration boot-up begins.
c) Default device configuration boot-up process.
Step 2 – GSPI Access Allowed
a) Host sets EYE_MON_INT_CFG_3 (register address 0x57) to 0x8006.
b) If there are multiple devices on the GSPI chain, the host should configure the unit
address of each device. See Section 4.10.9 for further information on unit
addressing.
c) Host sets custom application specific settings.
d) Normal operation begins.
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5.11 ms – no GSPI Access Allowed
GSPI Access Allowed
All blocks reset.
After Completion of Reset, device
automatically initiates default
configuration boot-up.
Eye Monitor
Reset:
Host
writes 0x8006
to register 0x57
at unit address
0.
Normal Operation Begins.
Host must reconfigure the unit addresses of
devices that were reset to 0.
After which, host may read/write any
register of a specific device on the chain, or
use broadcast write to concurrently write a
command to all devices on the GSPI chain.
All devices that
received reset
command will
have their unit
address reset to
0.
Command will
be broadcast to
all devices that
were reset.
Device Blocks
Resetting.
Device
Configuration
Booting.
Application Defined GSPI Read/Write
Access.
GSPI Access..
110 μs
5 ms
Host writes
0xAD00 to
Internal Reset
Sequence
Complete.
Default
Configuration
Boot-Up
Eye
Monitor
Reset.
Register 0x007F
to reset device.
Host may reset
all devices by
using broadcast
mode.
Complete.
Figure 4-38: Power-Up Sequence.
4.10.13 Host Initiated Device Reset
The GS12190 includes a reset function accessible via the device's host interface, which
reverts all internal logic and register values to their default values.
The device can be reset with a single write of AD00h to the RESET_CONTROL bits of the
CONTROL_RESET register, which will assert and de-assert the device reset within the
duration of the GSPI write access Data Word.
The device can be placed and held in reset by writing AA00h to the RESET_CONTROL
bits of the CONTROL_RESET register. Subsequent writes of DD00h to the
RESET_CONTROL bits will de-assert device reset.
The current state of user-initiated device reset can be read from the RESET_CONTROL
bits of CONTROL_RESET register.
While in reset, host interface access to any other register will not be functional and all
logic and configuration registers will be in reset state. While in reset, output behaviour
is undefined. The digital logic and registers within the device will exit the reset state 5ms
after device reset is de-asserted.
The following timing sequence must be observed to initiate a device reset.
Note: Please check with your local FAE, as some devices may need updated
configuration settings. If a configuration file has been provided by the FAE, see the
timing information in the Serial Routing and Distribution Product Configuration
Loading Procedure Application Note (PDS-061176).
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4.10.13.1 Host Initiated Device Reset Timing Sequence
The following timing sequence must be observed after a Host Initiated Device Reset
when no external configuration loading is required. See Figure 4-39 for the timing
requirements of the Steps 1 to 3 below.
Step 1 – GSPI Access Allowed
a) Host writes 0xAD00h to register 0x007Fh to reset selected devices, or all devices
using broadcast.
Step 2– No GSPI Access Allowed
a) Internal blocks reset, default device configuration boot-up begins.
b) Default device configuration boot-up completes.
Step 3 – GSPI Access Allowed
a) Host sets EYE_MON_INT_CFG_3 (register address 0x57h) to 0x8006h.
b) If there are multiple devices on the GSPI chain, host must reconfigure unit address
of each device that was reset. See Section 4.10.9 for further information on unit
addressing.
c) Host sets custom application specific settings.
d) Normal operation begins.
5.11 ms – No GSPI Access Allowed
GSPI Access Allowed
All blocks reset.
After Completion of Reset, device
automatically initiates default
configuration boot-up.
Eye Monitor
Reset:
Host
writes 0x8006
to register 0x57
at unit address
0.
Normal Operation Begins.
Host must reconfigure the unit addresses of
devices that were reset to 0.
After which, the host may read/write any
register of specific device on the chain, or
use broadcast write to concurrently write a
command to all devices on the GSPI chain.
All devices that
received reset
command will
have their unit
address reset to
0.
Command will
be broadcast to
all devices that
were reset.
Device Blocks
Resetting.
Device
Configuration
Booting.
Application Defined GSPI Read/Write
Access.
GSPI Access.
110 μs
5 ms
Host writes
0xAD00 to
Internal Reset
Sequence
Complete.
Default
Configuration
Boot-Up
Eye
Monitor
Reset.
Register 0x007F
to reset device.
Host may reset
all devices by
using broadcast
mode.
Complete.
Figure 4-39: Host Initiated Device Reset Timing Sequence.
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5. Register Map
The host interface on the GS12190 provides users complete control of key features such
as GPIO configuration, PLL loop bandwidth settings, reclock parameters, carrier
detection, cable equalization, bypass modes, output swing controls, mute functions,
pre-emphasis control and many others.
It also includes a wide selection of Status Registers which allow the user to read back
several key metrics of information from the GS12190 to add more flexibility to their
designs.
Section 5.1 to Section 5.3 cover each Control and Status Register in detail.
5.1 Control Registers
Table 5-1: Control Registers
GSPI
Addressh
Register Name
R/W
0
1
CONTROL_ REG
DEVICE_ID
RW
RO
2
RSVD
RW
RW
RW
RW
RW
RW
RW
7F
3
CONTROL_ RESET
CONTROL_ SLEEP
MISC_CNTRL
4
5
MISC_CFG
6
RATE_ DETECT_ MODE
RATE_ DETECT_CFG
7
Reclocker Configuration
8
9
RSVD
RW
RW
RW
RW
RW
RW
FACTORY_ CDR_ PARAMETERS
PLL_LOOP_ BANDWIDTH_ 0
PLL_LOOP_ BANDWIDTH_ 1
PLL_LOOP_ BANDWIDTH_ 2
RSVD
0A
0B
0C
0D to 0F
GPIO Configuration
10
11
12
GPIO0_CFG
RW
RW
RW
GPIO1_CFG
GPIO2_CFG
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Table 5-1: Control Registers (Continued)
GSPI
Register Name
Addressh
R/W
13
GPIO3_CFG
RW
Equalizer Configuration
14
15
INPUT_ SELECT_CTRL
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
CARR_ DET_CFG
16
SQUELCH_ PARAMETERS
CABLE_EQ_ BYPASS_ MODE
INPUT_ LAUNCH_ SWING_CFG
RSVD
17
18
19 to 1D
1E
TREQ0_ INPUT_BOOST
TREQ0_CD_ HYSTERESIS
CD_FILTER_ DELAYS_0
CD_FILTER_ DELAYS_1
CD_FILTER_ DELAYS_2
RSVD
1F
20
21
22
23 to 25
Output Configuration
26 to 27
28
RSVD
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
OUTPUT_ PARAM_TD_ SD_0
OUTPUT_ PARAM_ TD_SD_1
OUTPUT_ PARAM_CD_ SD_2
OUTPUT_ PARAM_CD_ SD_3
OUTPUT_ PARAM_ TD_HD_0
OUTPUT_ PARAM_ TD_HD_1
OUTPUT_ PARAM_ CD_HD_2
OUTPUT_ PARAM_ CD_HD_3
OUTPUT_ PARAM_ TD_3G_0
OUTPUT_ PARAM_ TD_3G_1
OUTPUT_ PARAM_ CD_UHD_2
OUTPUT_ PARAM_ CD_UHD_3
OUTPUT_ PARAM_ TD_6G_0
OUTPUT_ PARAM_ TD_6G_1
RSVD
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36 to 37
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Table 5-1: Control Registers (Continued)
GSPI
Register Name
Addressh
R/W
38
OUTPUT_ PARAM_ TD_12G_0
OUTPUT_ PARAM_ TD_12G_1
RSVD
RW
RW
RW
RW
RW
39
3A to 40
41
OUTPUT_ PARAM_ MUTE_1
RSVD
42 to 47
Output Control
48
OUTPUT_ SIG_SELECT
RW
RW
RW
RW
RW
RW
RW
49
CONTROL_ OUTPUT_ MUTE
CONTROL_ OUTPUT_ DISABLE
CONTROL_ OUTPUT_ SLEW
CONTROL_ RETIMER_ BYPASS
CONTROL_ BALANCED_ MODE
RSVD
4A
4B
4C
4D
4E to 4F
Test Functions
50
51
PRBS_ CHK_CFG
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
PRBS_CHK_ CTRL
PRBS_GEN_ CTRL
RSVD
52
53
54
EYE_MON_ INT_CFG_0
EYE_MON_ INT_CFG_1
EYE_MON_ INT_CFG_2
EYE_MON_ INT_CFG_3
RSVD
55
56
57
58 to 59
5A
EYE_MON_ SCAN_CTRL_0
EYE_MON_ SCAN_CTRL_1
EYE_MON_ SCAN_CTRL_2
EYE_MON_ SCAN_CTRL_3
RSVD
5B
5C
5D
5E to 5F
Internal Only Configuration (Do not write to these registers)
60 to 7E RSVD
—
GS12190
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5.2 Status Registers
Table 5-2: Status Registers
GSPI
Register Name
Addressh
R/W
80
81
RSVD
RW
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RW
VERSION_0
82
VERSION_1
83
VERSION_2
84
STICKY_ COUNTS_0
STICKY_ COUNTS_1
CURRENT_ STATUS_0
CURRENT_ STATUS_1
EQ_GAIN_IND
85
86
87
88
89
PRBS_ CHK_ERR_CNT
PRBS_ CHK_STATUS
EYE_MON_ SCAN_ SIZE_OUTPUT
EYE_MON_ SHAPE_ OUTPUT_0
EYE_MON_ SHAPE_ OUTPUT_1
EYE_MON_ SHAPE_ OUTPUT_2
EYE_MON_ SHAPE_ OUTPUT_3
EYE_MON_ STATUS
RSVD
8A
8B
8C
8D
8E
8F
90
91 to BF
GS12190
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5.3 Register Descriptions
5.3.1 Control Register Descriptions
Table 5-3: Control Register Descriptions
Reset
Valueh
Register
Name
Bit
Slice
Addressh
Parameter Name
R/W
Description
RSVD
15
RW
0
0
Reserved—do not modify.
0 = Enable loop-through. SDIN pin is
looped through to the SDOUT pin
GSPI_LINK_DISABLE
14
RW
1 = Disable loop-through. Data
appearing at SDIN does not appear at
SDOUT, and SDOUT pin is HIGH
CONTROL_
REG
0
0 = Disable bus-through mode
1 = Enable bus-through mode
GSPI_BUS_THROUGH_
ENABLE
13
RW
RW
0
0
RSVD
12:5
Reserved—do not modify.
Device address programmed by
application. See Section 4.10.9 for
further information.
DEV_UNIT_ADDRESS
4:0
RW
0
This register contains the device’s
identification, including revision.
Contact the local technical sales
representative for details.
1
2
DEVICE_ID
RSVD
DEVICE_VERSION
RSVD
15:0
15:0
RO
—
0
R/W
Reserved—do not modify.
Device Reset, Reverts all internal logic
and register values to defaults.
Write Values:
AA00h = Asserts device reset
DD00h = De-assert device reset
AD00h = Assert/de-assert device reset in
a single write
CONTROL_
RESET
7F
RESET_CONTROL
15:0
R/W
DD00
Read Values:
AA00h = User-initiated reset is asserted
DD00h = User-initiated reset is
de-asserted
See Section 4.10.13 for further
information.
GS12190
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Table 5-3: Control Register Descriptions (Continued)
Reset
Valueh
Register
Name
Bit
Slice
Addressh
Parameter Name
R/W
Description
RSVD
15:2
R/W
0
Reserved—do not modify.
Sleep manual mode control:
0 = Never Sleep
1 = Always Sleep
CTRL_MANUAL_SLEEP
1
R/W
R/W
0
Controls sleep mode when auto sleep
(CTRL_AUTO_SLEEP) is disabled.
CONTROL_
SLEEP
Sleep auto mode control:
3
0 = Disable auto sleep mode
1 = Enable auto sleep mode
If CTRL_AUTO_SLEEP = 0 (manual sleep
mode), then CTRL_MANUAL_SLEEP
controls sleep.
CTRL_AUTO_SLEEP
0
1
If CTRL_AUTO_SLEEP = 1 (auto sleep
mode), sleep is automatically entered
on loss of signal.
RSVD
15:1
R/W
R/W
0
0
Reserved—do not modify.
Clear sticky counts control register.
0 = no action
1 = clear sticky counts.
4
MISC_CNTRL
Part of a four way handshake with
STAT_CLEAR_COUNTS_STATUS. See
Section 4.10.11 for more details on
implementing the four way handshake
for this operation.
CTRL_CLEAR_COUNTS
0
RSVD
15:5
4
R/W
R/W
0
0
Reserved—do not modify.
Controls whether Trace Driver (DDO) is
muted or disabled when GS12190
bi-directional part is in Cable Driver
Mode and CTRL_LOOPBACK_ENA = 0:
CFG_TRDR_MUTE_
WHEN_CABLE_DRIVER
0 = Disable (power-down)
1 = Mute
5
MISC_CFG
Controls whether Trace Driver (DDO) is
muted or disabled (powered-down)
during sleep:
CFG_SLEEP_OUTPUT1_
MUTE
3
R/W
R/W
0
1
0 = Disable (power-down) output
during sleep
1 = mute output during sleep
RSVD
2:0
Reserved—do not modify.
GS12190
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Table 5-3: Control Register Descriptions (Continued)
Reset
Valueh
Register
Name
Bit
Slice
Addressh
Parameter Name
R/W
Description
RSVD
15:14
R/W
0
Reserved—do not modify.
12G auto rate detection enable:
0 = Disable rate
1 = Enable rate
CFG_RATE_ENA_12G
CFG_RATE_ENA_6G
CFG_RATE_ENA_3G
CFG_RATE_ENA_HD
CFG_RATE_ENA_SD
13
R/W
R/W
R/W
R/W
R/W
1
Note: This parameter is only applicable
to the Trace Equalizer input (DDI).
6G auto rate detection enable:
0 = Disable rate
1 = Enable rate
12
11
10
9
1
1
1
1
Note: This parameter is only applicable
to the Trace Equalizer input (DDI).
3G auto rate detection enable:
0 = Disable rate
1 = Enable rate
Note: This parameter is only applicable
to the Trace Equalizer input (DDI).
HD auto rate detection enable:
0 = Disable rate
1 = Enable rate
Note: This parameter is only applicable
to the Trace Equalizer input (DDI).
RATE_
DETECT_
MODE
6
SD auto rate detection enable:
0 = Disable rate
1 = Enable rate
Note: This parameter is only applicable
to the Trace Equalizer input (DDI).
MADI auto rate detection enable:
0 = Disable rate
1 = Enable rate
CFG_RATE_ENA_MADI
RSVD
8
R/W
R/W
0
0
Note: This parameter is only applicable
to the Trace Equalizer input (DDI).
7:5
Reserved—do not modify.
Manual rate selection. The reclocker will
only lock to the selected rate if
CFG_AUTO_RATE_DETECT_ENA = 0:
0 = < MADI (only applicable in Cable
Equalizer Mode)
1 = MADI
2 = SD
CFG_MANUAL_RATE
4:1
R/W
0
3 = HD
4 = 3G
5 = 6G
6 = 12G
7 = Reserved—do not modify
GS12190
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Table 5-3: Control Register Descriptions (Continued)
Reset
Valueh
Register
Name
Bit
Slice
Addressh
Parameter Name
R/W
Description
Set or disable auto rate detection mode.
0 = Disable auto rate detection
1 = Enable auto rate detection
When automatic rate detection is
disabled, the rate is set by
CFG_MANUAL_RATE.
RATE_
DETECT_
MODE
CFG_AUTO_RATE_
DETECT_ENA
6
0
R/W
1
(Continued)
(Continued)
Note: If using manual rate selection
while in cable driver mode, the host
should set CFG_MANUAL_RATE to 1
through 7 first, then set
CFG_AUTO_RATE_ENA = 0.
RSVD
15:5
4
R/W
R/W
0
0
Reserved—do not modify.
Select data rate threshold between SD
and MADI:
CFG_RD_SD_MADI_
THRESHOLD
0 = 181Mb/s
1 = 198Mb/s
Note: This parameter is only applicable
to the cable equalizer input (SDIO).
CFG_RD_SD_MADI_THRESHOLD and
CFG_RD_MADI_LTMADI_DATADIV (bit
slice [3:0]) determines the rate detection
threshold between MADI and <MADI
rates. The following threshold settings
are available:
RATE_
DETECT_CFG
7
0x0 = 53Mb/s
0x2 = 32Mb/s
0x3 = 79Mb/s (default)
0x6 = 63Mb/s
CFG_RD_MADI_
LTMADI_DATADIV
3:2
R/W
0
0x9 = 48Mb/s
0xA = 95Mb/s
0xC = 111Mb/s
0x1, 0x4, 0x5, 0x7, 0x8, 0xB, 0xD, and 0xE
= Reserved—do not use
Note: This parameter is only applicable
to the cable equalizer input (SDIO).
See CFG_RD_MADI_ LTMADI_DATADIV.
CFG_RD_MADI_
LTMADI_CLKDIV
1:0
R/W
3
Note: This parameter is only applicable
to the cable equalizer input (SDIO).
GS12190
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Table 5-3: Control Register Descriptions (Continued)
Reset
Valueh
Register
Name
Bit
Slice
Addressh
Parameter Name
R/W
Description
Reclocker Configuration
8
9
RSVD
RSVD
RSVD
15:0
15:2
R/W
R/W
3
Reserved—do not modify.
Reserved—do not modify.
1C
To maximize loop bandwidth of PLL and
consequently IJT of the reclocker, set
this parameter to 0.
FACTORY_
CDR_
PARAMETERS
CFG_MIN_LBW
1
R/W
1
RSVD
RSVD
0
R/W
R/W
0
0
Reserved—do not modify.
Reserved—do not modify.
15:13
Configure PLL loop bandwidth in terms
of ratio to nominal loop bandwidth 'x'
(see Table 2-3).
11.88Gb/s (12G) loop bandwidth
setting:
0x00 = Reserved—do not use
0x01 = 0.0625x
0x02 = 0.125x
0x03 = 0.1875x
0x04 = 0.25x
0x05 = 0.3125x
0x06 = 0.375x
0x07 = 0.4375x
0x08 = 0.5x
CFG_PLL_LBW_12G
12:8
R/W
8
0x09 = 0.5625x
0x0A = 0.625x
0x0B = 0.6875x
0x0C = 0.75x
PLL_LOOP_
BANDWIDTH_
0
0A
0x0D = 0.8125x
0x0E = 0.875x
0x0F = 0.9375x
0x10 to 0x1B = Reserved—do not use
0x1C = 1.0x (nominal)
0x1D = 1.0625x
0x1E = 1.125x
0x1F = 1.1875x
RSVD
7:5
4:0
R/W
R/W
0
8
Reserved—do not modify.
Configure 5.94Gb/s (6G) PLL loop
bandwidth in terms of ratio to nominal
loop bandwidth 'x' (see Table 2-3).
CFG_PLL_LBW_6G
See CFG_PLL_LBW_12G parameter for
available settings.
GS12190
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Table 5-3: Control Register Descriptions (Continued)
Reset
Valueh
Register
Name
Bit
Slice
Addressh
Parameter Name
R/W
Description
RSVD
15:13
12:8
7:5
R/W
0
8
Reserved—do not modify.
Configure 2.97Gb/s (3G) PLL loop
bandwidth in terms of ratio to nominal
loop bandwidth 'x' (see Table 2-3).
CFG_PLL_LBW_3G
RSVD
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
See CFG_PLL_LBW_12G parameter for
available settings.
PLL_LOOP_
BANDWIDTH_
1
0B
0
Reserved—do not modify.
Configure 1.485Gb/s (HD) PLL loop
bandwidth in terms of ratio to nominal
loop bandwidth 'x' (see Table 2-3).
CFG_PLL_LBW_HD
RSVD
4:0
8
See CFG_PLL_LBW_12G parameter for
available settings.
15:13
12:8
7:5
0
Reserved—do not modify.
Configure 270Mb/s (SD) PLL loop
bandwidth in terms of ratio to nominal
loop bandwidth 'x' (see Table 2-3).
CFG_PLL_LBW_SD
RSVD
1C
0
See CFG_PLL_LBW_12G parameter for
available settings.
PLL_LOOP_
BANDWIDTH_
2
0C
Reserved—do not modify.
Configure 125Mb/s (MADI) PLL loop
bandwidth in terms of ratio to nominal
loop bandwidth 'x' (see Table 2-3).
CFG_PLL_LBW_MADI
RSVD
4:0
8
See CFG_PLL_LBW_12G parameter for
available settings.
0D to 0F
RSVD
15:0
0
Reserved—do not modify.
GPIO Configuration
RSVD
15:9
R/W
0
1
Reserved—do not modify.
GPIO0 buffer mode control.
10
GPIO0_CFG
CFG_GPIO0_
OUTPUT_ENA
0 = GPIO pin is configured as an input
(tri-stated / high impedance)
8
R/W
1 = GPIO pin is configured as an output
GS12190
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Table 5-3: Control Register Descriptions (Continued)
Reset
Valueh
Register
Name
Bit
Slice
Addressh
Parameter Name
R/W
Description
Function select for GPIO0 pin.
GPIO0 output functions:
0x00 = Output driven LOW
0x01 = Output driven HIGH
0x02 = PLL lock status
(HIGH—PLL locked)
0x03 to 0x7F = Reserved—do not use
0x80 = LOS—equivalent to inverse of
STAT_PRI_CD for Trace Equalizer input
(DDI) and STAT_SEC_CD for cable
equalizer input (SDIO)
0x81 = Carrier detect status of the
selected input (STAT_PRI_CD for Trace
Equalizer input (DDI) and STAT_SEC_CD
for cable equalizer input (SDIO))
0x82 = Sleep mode status
(HIGH—Device in sleep mode)
0x83 = HIGH for SD, LOW for all other
rates
0x84 = Rate detected [0]
0x85 = Rate detected [1]
0x86 = Rate detected [2]
Note: To have full rate range using the
GPIO rate detect function, one GPIO pin
must be used for each Rate Detect bit
[2:0]. Please see Table 4-3: Detected
Data Rates for the indication values.
10
GPIO0_CFG
(Continued)
CFG_GPIO0_FUNCTION
7:0
R/W
80
(Continued)
0x87 to 0xFF = Reserved—do not use
GPIO0 input functions:
0x00 to 0x80 = Reserved—do not use
0x81 = SDIO disable control
(HIGH—disable)
0x82 = DDO disable control
(HIGH—disable)
0x83 = Reserved—do not modify
0x84 = Cable equalizer bypass enable
(HIGH—Bypass enabled), Cable
equalizer input (SDIO) only.
0x85 = reclocker bypass enable
(HIGH—Bypass enabled)
0x86 = Sleep control (HIGH—Sleep)
0x87 = Cable Driver / Equalizer mode
selection (HIGH = Cable Driver Mode,
DDI as input / LOW = Cable Equalizer
Mode, SDIO as input).
0x88 to 0xFF = Reserved—do not use
GS12190
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Table 5-3: Control Register Descriptions (Continued)
Reset
Valueh
Register
Name
Bit
Slice
Addressh
Parameter Name
R/W
Description
RSVD
15:9
R/W
0
Reserved—do not modify.
GPIO1 buffer mode control.
See GPIO0_CFG:
CFG_GPIO0_OUTPUT_ENA parameter
for description and available settings.
CFG_GPIO1_OUTPUT_
ENA
8
R/W
1
11
GPIO1_CFG
Default mode: Output
Function select for GPIO1 pin.
See GPIO0_CFG:
CFG_GPIO1_FUNCTION
RSVD
7:0
15:9
8
R/W
R/W
R/W
2
0
0
CFG_GPIO0_FUNCTION parameter for
description and available settings.
Default Function: 0x02 = PLL lock status
Reserved—do not modify.
GPIO2 buffer mode control.
See GPIO0_CFG:
CFG_GPIO0_OUTPUT_ENA parameter
for description and available settings.
CFG_GPIO2_OUTPUT_
ENA
12
GPIO2_CFG
Default mode: Input
Function select for GPIO2 pin.
See GPIO0_CFG:
CFG_GPIO2_FUNCTION
RSVD
7:0
15:9
8
R/W
R/W
R/W
86
0
CFG_GPIO0_FUNCTION parameter for
description and available settings.
Default Function: 0x86 = Sleep control
Reserved—do not modify.
GPIO3 buffer mode control.
See GPIO0_CFG:
CFG_GPIO0_OUTPUT_ENA parameter
for description and available settings.
CFG_GPIO3_OUTPUT_
ENA
0
Default mode: Input
13
GPIO3_CFG
Function select for GPIO3 pin.
See GPIO0_CFG:
CFG_GPIO0_FUNCTION parameter for
description and available settings.
CFG_GPIO3_FUNCTION
7:0
R/W
87
Default Function: 0x87 = Cable
Equalizer/Driver mode selection
GS12190
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Table 5-3: Control Register Descriptions (Continued)
Reset
Valueh
Register
Name
Bit
Slice
Addressh
Parameter Name
R/W
Description
Equalizer Configuration
RSVD
15:11
R/W
R/W
0
0
Reserved—do not modify.
Enables trace input (DDI) to trace output
(DDO) loopback mode when in cable
driver mode.
0 = Loopback is disabled. The Trace
Driver is controlled by CFG_TRDR_
MUTE_WHEN_CABLE_DRIVER.
CTRL_LOOPBACK_ENA
10
1 = Loopback is enabled. (subject to
output state control modes, see
Section 4.8.6)
Note: This parameter is only applicable
to the Trace Equalizer input (DDI).
INPUT_
SELECT_CTRL
RSVD
9:3
2:1
R/W
R/W
60
0
Reserved—do not modify.
14
Select bi-directional control method.
0 = pin mode (default mode)
1 = Host Interface Mode
CTRL_DIRECTION_
SEL_MODE
2 = Reserved—do not select
3 = Reserved—do not select
The host should configure one of the
GPIO pins for input select before
selecting mode 0.
Selects bidirectional mode when
CTRL_DIRECTION_SEL_MODE = 1 (Host
Interface mode).
CTRL_DIRECTION_SEL
RSVD
0
R/W
R/W
1
0
0 = Cable Equalizer Mode
1 = Cable Driver Mode
15:1
Reserved—do not modify.
Enable or disable squelch control
conditions for deriving secondary
carrier detection (LOS) status for Cable
Equalizer mode.
CARR_
DET_CFG
15
CFG_SEC_CD_INCL_
CLI_SQUELCH
0
R/W
0
0 = Ignore CLI squelch
1 = Take into account CLI squelch
Note: This parameter is only applicable
to the cable equalizer input (SDIO).
GS12190
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Table 5-3: Control Register Descriptions (Continued)
Reset
Valueh
Register
Name
Bit
Slice
Addressh
Parameter Name
R/W
Description
RSVD
15
R/W
0
Reserved—do not modify.
Set the input signal squelch threshold.
Range = 0 to 64d (64d is max cable reach
CFG_CLI_SQUELCH_
THRESHOLD
determined for specific rate, cable type,
and launch swing compensation).
Note: This parameter is only applicable
to the cable equalizer input (SDIO).
14:8
R/W
40
SQUELCH_
PARAMETERS
16
RSVD
7
R/W
R/W
R/W
0
2
0
Reserved—do not modify.
Set the input signal squelch hysteresis.
Range = 1d to 30d
CFG_CLI_SQUELCH_
HYSTERESIS
6:0
Note: This parameter is only applicable
to the cable equalizer input (SDIO).
RSVD
15:2
Reserved—do not modify.
Controls Cable Equalizer bypass when
auto cable equalizer bypass is disabled
(CTRL_CEQ_AUTO_BYPASS= 0).
CTRL_CEQ_MANUAL_
BYPASS
1
R/W
0
0 = Cable Equalizer never bypassed
1 = Cable Equalizer always bypassed
Note: This parameter is only applicable
to the cable equalizer input (SDIO).
CABLE_EQ_
BYPASS_
MODE
17
Auto Cable Equalizer bypass mode
control:
0 = Disable auto mode
1 = Enable auto mode
CTRL_CEQ_AUTO_
BYPASS
0
R/W
1
When CFG_CEQ_AUTO_BYPASS = 0,
CEQ bypass is controlled by
CFG_CEQ_BYPASS_MANUAL.
Note: This parameter is only applicable
to the cable equalizer input (SDIO).
RSVD
15:7
6:0
R/W
R/W
0
Reserved—do not modify.
Input launch swing compensation
setting in units of 10 mVppd
INPUT_
LAUNCH_
SWING_CFG
Default setting of 80d (0x50)
CFG_CEQ_INPUT_
LAUNCH_SWING_
COMP
18
corresponds to 800mV. Default for
upstream SMPTE-compliant cable
drivers operating at 800mv ±10%.
50
Note: This parameter is only applicable
to the cable equalizer input (SDIO).
19
1A
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
15:0
15:0
15:0
15:0
R/W
R/W
R/W
R/W
1
0
1
0
Reserved—do not modify.
Reserved—do not modify.
Reserved—do not modify.
Reserved—do not modify.
1B
1C to 1D
GS12190
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Table 5-3: Control Register Descriptions (Continued)
Reset
Valueh
Register
Name
Bit
Slice
Addressh
Parameter Name
R/W
Description
RSVD
15:5
R/W
0
Reserved—do not modify.
Trace Equalizer input boost setting:
0 = Bypass equalization stage
1 to 8 = 1 to 17dB of insertion loss at
5.94GHz (see Figure 4-2)
CFG_TREQ0_BOOST
4:1
R/W
0
Bypass is the minimum boost setting;
boost 8 is maximum boost setting.
TREQ0_
INPUT_BOOST
Note: This parameter is only applicable
to the Trace Equalizer input (DDI).
1E
Selects boost level applied to Trace
Equalizer input signal for carrier
detection function only.
CFG_TREQ0_CD_
BOOST
0
R/W
R/W
0
0
0 = Sets to boost 8 (See Figure 4-2)
1 = Use CFG_TREQ0_BOOST setting
Note: This parameter is only applicable
to the Trace Equalizer input (DDI).
RSVD
15:8
Reserved—do not modify.
Sets assert threshold for Trace Equalizer
input carrier detect.
0 to15d, where 0 is minimum threshold
and 15d is maximum threshold (see
Figure 4-3).
CFG_TREQ0_CD_
ASSERT_THRESH
7:4
R/W
4
Note: This parameter is only applicable
to the Trace Equalizer input (DDI).
TREQ0_CD_
HYSTERESIS
1F
Sets de-assert threshold for Trace
Equalizer input carrier detect
0 to15d, where 0 is minimum threshold
and 15d is maximum threshold (see
Figure 4-3).
CFG_TREQ0_CD_DEAS
SERT_THRESH
3:0
R/W
R/W
3
0
Note: This parameter is only applicable
to the Trace Equalizer input (DDI).
RSVD
15:8
Reserved—do not modify.
Cable Equalizer input carrier detect filter
sample window period in clock cycles.
Sample window size is this value plus 1
clock cycle.
CD_FILTER_
DELAYS_0
20
CFG_CD_FILTER_
SAMPLE_WIN
7:0
R/W
3
Valid Range = 0x03 to 0xFF
See Section 4.2.3 for details.
Note: This parameter is only applicable
to the cable equalizer input (SDIO).
GS12190
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Table 5-3: Control Register Descriptions (Continued)
Reset
Valueh
Register
Name
Bit
Slice
Addressh
Parameter Name
R/W
Description
RSVD
15:10
9:0
R/W
0
Reserved—do not modify.
Number of samples for detecting cable
equalizer carrier detection de-assertion:
CD_FILTER_
DELAYS_1
21
Valid Range = 0x00 to 0x3FF
See Section 4.2.3 for details.
CFG_CD_FILTER_
DEASSERT_CNT
R/W
R/W
R/W
R/W
F
Note: This parameter is only applicable
to the cable equalizer input (SDIO).
RSVD
15:10
9:0
0
Reserved—do not modify.
Number of samples for detecting cable
equalizer carrier detection assertion:
CD_FILTER_
DELAYS_2
22
Valid Range = 0x00 to 0x3FF
See Section 4.2.3 for details.
CFG_CD_FILTER_
ASSERT_CNT
3FF
Note: This parameter is only applicable
to the cable equalizer input (SDIO).
23 to 25
26 to 27
RSVD
RSVD
RSVD
RSVD
15:0
0
0
Reserved—do not modify.
Output Configuration
15:0
R/W
Reserved—do not modify.
GS12190
Final Data Sheet
PDS-061916
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Rev.3
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Table 5-3: Control Register Descriptions (Continued)
Reset
Valueh
Register
Name
Bit
Slice
Addressh
Parameter Name
R/W
Description
RSVD
15:13
12:8
7
R/W
0
2
0
Reserved—do not modify.
Configure the Trace Driver output (DDO)
SD pre-emphasis pulse width.
Range: 0 to 15d.
Adjust the pre-emphasis pulse width to
better match the channel loss response
shape.
CFG_OUTPUT1_TD_
SD_PREEMPH_WIDTH
R/W
R/W
Note: By default, the Trace Driver SD
settings are applied for all rates (see
CTRL_OUTPUT1_TRDR_PER_RATE for
per rate setting).
RSVD
Reserved—do not modify.
Trace Driver output (DDO) SD
Pre-Emphasis power-down
DDO power-down control for
pre-emphasis driver.
OUTPUT_
PARAM_TD_
SD_0
28
0 = Pre-emphasis driver powered-up
(pre-emphasis enabled)
1 = Pre-emphasis driver powered-down
(pre-emphasis disabled)
CFG_OUTPUT1_TD_
SD_PREEMPH_
PWRDWN
6
R/W
0
Note: By default, the Trace Driver SD
settings are applied for all rates (see
CTRL_OUTPUT1_TRDR_PER_RATE for
per rate setting).
Configure the Trace Driver output (DDO)
SD pre-emphasis pulse amplitude.
Range = 0d to 50d
Adjust the pre-emphasis pulse
amplitude to better match the channel
loss at Nyquist.
CFG_OUTPUT1_TD_
SD_PREEMPH_AMPL
5:0
R/W
1
Note: By default, the Trace Driver SD
settings are applied for all rates (see
CTRL_OUTPUT1_TRDR_PER_RATE for
per rate setting).
RSVD
15:14
13:8
7:0
R/W
R/W
R/W
0
Reserved—do not modify.
Configure the trace driver output (DDO)
SD amplitude. Range: 0 to 40d.
Adjust the differential Trace Driver
amplitude. The default value produces
an amplitude of 400mVppd
CFG_OUTPUT1_TD_
SD_DRIVER_SWING
OUTPUT_
PARAM_
TD_SD_1
29
11
70
Note: By default, the Trace Driver SD
settings are applied for all rates (see
CTRL_OUTPUT1_TRDR_PER_RATE for
per rate setting).
RSVD
Reserved—do not modify.
GS12190
Final Data Sheet
PDS-061916
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Rev.3
May 2020
Table 5-3: Control Register Descriptions (Continued)
Reset
Valueh
Register
Name
Bit
Slice
Addressh
Parameter Name
R/W
Description
RSVD
15:13
12:8
R/W
0
Reserved—do not modify.
Configures the MADI/SD rate
pre-emphasis pulse width on Cable
Driver output (SDIO):
CFG_OUTPUT0_CD_
SD_PREEMPH_
WIDTH
Range = 0d to 15d
R/W
3
Adjust the pre-emphasis pulse width to
better match the channel loss response
shape.
RSVD
7
6
R/W
R/W
0
1
Reserved—do not modify.
Power-down the MADI/SD rate
pre-emphasis on Cable Driver output
(SDIO):
OUTPUT_
PARAM_CD_
SD_2
2A
CFG_OUTPUT0_CD_
SD_PREEMPH_
PWRDWN
0 = Pre-emphasis driver powered-up
(pre-emphasis enabled)
1 = Pre-emphasis driver powered-down
(pre-emphasis disabled).
Configures the MADI/SD rate
pre-emphasis amplitude on Cable
Driver output (SDIO):
CFG_OUTPUT0_CD_
SD_PREEMPH_AMPL
Range = 0d to 15d
5:0
R/W
R/W
0
0
Adjust the pre-emphasis pulse
amplitude to better match the channel
loss at Nyquist.
RSVD
15:14
Reserved—do not modify.
Configure the Cable Driver output
(SDIO) SD/MADI amplitude in ~25mVpp
steps:
Functional Range = 9d to 31d
Precision Range = 21d to 27d
Default value = 24d (~800mVpp
)
CFG_OUTPUT0_CD_
SD_DRIVER_
SWING
OUTPUT_
PARAM_CD_
SD_3
2B
13:8
R/W
18
Note: In auto slew mode
(CTRL_OUTPUT0_AUTO_SLEW=1), the
slew rate is determined by the rate at
which the reclocker is locked. If the
reclocker is unlocked, the slew will
default to 6G/12G Slew. See Table 2-3
for Rise/Fall Times, and Section 4.8.3 for
more details on output driver selection.
RSVD
7:0
R/W
A0
Reserved—do not modify.
GS12190
Final Data Sheet
PDS-061916
92 of 121
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Rev.3
May 2020
Table 5-3: Control Register Descriptions (Continued)
Reset
Valueh
Register
Name
Bit
Slice
Addressh
Parameter Name
R/W
Description
RSVD
15:13
12:8
7
R/W
0
2
0
Reserved—do not modify.
Configure the Trace Driver output (DDO)
HD pre-emphasis pulse width.
Range = 0d to 15d
CFG_OUTPUT1_TD_
HD_PREEMPH_WIDTH
R/W
R/W
Adjust the pre-emphasis pulse width to
better match the channel loss response
shape.
RSVD
Reserved—do not modify.
Trace Driver output (DDO) HD
pre-emphasis power-down
OUTPUT_
PARAM_
TD_HD_0
2C
Power-down control for pre-emphasis
driver.
CFG_OUTPUT1_TD_
HD_PREEMPH_
PWRDWN
6
R/W
0
0 = Pre-emphasis driver powered-up
(pre-emphasis enabled)
1 = Pre-emphasis driver powered-down
(pre-emphasis disabled)
Configure the Trace Driver output (DDO)
HD pre-emphasis pulse amplitude.
Range = 0d to 50d
CFG_OUTPUT1_TD_
HD_PREEMPH_AMPL
5:0
15:14
13:8
7:0
R/W
R/W
R/W
R/W
1
0
Adjust the pre-emphasis pulse
amplitude to better match the channel
loss at Nyquist.
RSVD
Reserved—do not modify.
Configure the Trace Driver output (DDO)
HD amplitude.
OUTPUT_
PARAM_
TD_HD_1
Range = 0d to 40d
CFG_OUTPUT1_TD_
HD_DRIVER_SWING
2D
11
70
Adjust the differential trace driver
amplitude. The default value produces
an amplitude of 400mVppd
.
RSVD
Reserved—do not modify.
GS12190
Final Data Sheet
PDS-061916
93 of 121
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Rev.3
May 2020
Table 5-3: Control Register Descriptions (Continued)
Reset
Valueh
Register
Name
Bit
Slice
Addressh
Parameter Name
R/W
Description
RSVD
15:13
12:8
7
R/W
0
9
0
Reserved—do not modify.
Configure the Cable Driver output
(SDIO) HD/3G pre-emphasis pulse
width.
CFG_OUTPUT0_CD_
HD_PREEMPH_WIDTH
Range = 0d to 15d
R/W
R/W
Adjust the pre-emphasis pulse width to
better match the channel loss response
shape.
RSVD
Reserved—do not modify.
Cable Driver output (SDIO) HD/3G
pre-emphasis power-down.
OUTPUT_
PARAM_
CD_HD_2
2E
SDIO power-down control for
pre-emphasis driver.
CFG_OUTPUT0_CD_
HD_PREEMPH_
PWRDWN
6
R/W
0
0 = Pre-emphasis driver powered-up
(pre-emphasis enabled)
1 = Pre-emphasis driver powered-down
(pre-emphasis disabled)
Configure the Cable Driver output
(SDIO) HD/3G pre-emphasis pulse
amplitude.
CFG_OUTPUT0_CD_
HD_PREEMPH_AMPL
Range = 0d to 15d
5:0
R/W
R/W
7
0
Adjust the pre-emphasis pulse
amplitude to better match the channel
loss at Nyquist.
RSVD
15:14
Reserved—do not modify.
Configure the Cable Driver output
(SDIO) HD/3G amplitude in ~20mVpp
steps.
Functional Range = 9d to 31d
Precision Range = 20d to 26d
Default value = 23d (~800mVpp
)
OUTPUT_
PARAM_
CD_HD_3
CFG_OUTPUT0_CD_
HD_DRIVER_SWING
2F
13:8
R/W
17
Note: In auto slew mode
(CTRL_OUTPUT0_AUTO_SLEW=1), the
slew rate is determined by the rate at
which the reclocker is locked. If the
reclocker is unlocked, the slew will
default to 6G/12G Slew. See Table 2-3
for Rise/Fall Times, and Section 4.8.3 for
more details on output driver selection.
RSVD
7:0
R/W
80
Reserved—do not modify.
GS12190
Final Data Sheet
PDS-061916
94 of 121
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Rev.3
May 2020
Table 5-3: Control Register Descriptions (Continued)
Reset
Valueh
Register
Name
Bit
Slice
Addressh
Parameter Name
R/W
Description
RSVD
15:13
12:8
7
R/W
0
2
0
Reserved—do not modify.
Configure the Trace Driver output (DDO)
3G pre-emphasis pulse width.
Range = 0d to 15d
CFG_OUTPUT1_TD_
3G_PREEMPH_WIDTH
R/W
R/W
Adjust the pre-emphasis pulse width to
better match the channel loss response
shape.
RSVD
Reserved—do not modify.
Trace Driver output (DDO) 3G
pre-emphasis power-down
OUTPUT_
PARAM_
TD_3G_0
30
DDO power-down control for
pre-emphasis driver.
CFG_OUTPUT1_TD_
3G_PREEMPH_
PWRDWN
6
R/W
0
0 = Pre-emphasis driver powered-up
(pre-emphasis enabled)
1 = Pre-emphasis driver powered-down
(pre-emphasis disabled)
Configure the trace driver output (DDO)
3G pre-emphasis pulse amplitude.
Range = 0d to 50d
CFG_OUTPUT1_TD_
3G_PREEMPH_AMPL
5:0
15:14
13:8
7:0
R/W
R/W
R/W
R/W
1
0
Adjust the pre-emphasis pulse
amplitude to better match the channel
loss at Nyquist.
RSVD
Reserved—do not modify.
Configure the Trace Driver output (DDO)
3G amplitude.
OUTPUT_
PARAM_
TD_3G_1
Range = 0d to 40d
CFG_OUTPUT1_TD_
3G_DRIVER_SWING
31
11
70
Adjust the differential Trace Driver
amplitude. The default value produces
an amplitude of 400mVppd
.
RSVD
Reserved—do not modify.
GS12190
Final Data Sheet
PDS-061916
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Rev.3
May 2020
Table 5-3: Control Register Descriptions (Continued)
Reset
Valueh
Register
Name
Bit
Slice
Addressh
Parameter Name
R/W
Description
RSVD
15:13
12:8
7
R/W
0
7
0
Reserved—do not modify.
Configure the Cable Driver output
(SDIO) 6G/12G pre-emphasis pulse
width.
Range = 0d to 15d
Adjust the pre-emphasis pulse width to
better match the channel loss response
shape.
CFG_OUTPUT0_CD_
UHD_PREEMPH_
WIDTH
R/W
Note: In auto slew mode (CTRL_
OUTPUT0_AUTO_SLEW = 1), the slew
rate is determined by the rate at which
the reclocker is locked. If the reclocker is
unlocked, the slew will default to
6G/12G Slew. See Table 2-3 for Rise/Fall
times, and Section 4.8.3 for more details
on output driver selection.
32
OUTPUT_
PARAM_
CD_UHD_2
RSVD
R/W
Reserved—do not modify.
Cable Driver output (SDIO) 6G/12G
pre-emphasis power-down
SDIO power-down control for
pre-emphasis driver.
0 = Pre-emphasis driver powered-up
(pre-emphasis enabled)
1 = Pre-emphasis driver powered-down
(pre-emphasis disabled)
CFG_OUTPUT0_CD_
UHD_PREEMPH_
PWRDWN
6
R/W
0
Note: In auto slew mode (CTRL_
OUTPUT0_AUTO_SLEW = 1), the slew
rate is determined by the rate at which
the reclocker is locked. If the reclocker is
unlocked, the slew will default to
6G/12G Slew. See Table 2-3 for Rise/Fall
times, and Section 4.8.3 for more details
on output driver selection.
Configure the Cable Driver output
(SDIO) 6G/12G pre-emphasis pulse
amplitude.
Range = 0d to 50d
Adjust the pre-emphasis pulse
amplitude to better match the channel
loss at Nyquist.
OUTPUT_
PARAM_
CD_UHD_2
(Continued)
CFG_OUTPUT0_CD_
UHD_PREEMPH_AMPL
32
5:0
R/W
B
(Continued)
Note: In auto slew mode (CTRL_
OUTPUT0_AUTO_SLEW = 1), the slew
rate is determined by the rate at which
the reclocker is locked. If the reclocker is
unlocked, the slew will default to
6G/12G Slew. See Table 2-3 for Rise/Fall
times, and Section 4.8.3 for more details
on output driver selection.
GS12190
Final Data Sheet
PDS-061916
96 of 121
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Rev.3
May 2020
Table 5-3: Control Register Descriptions (Continued)
Reset
Valueh
Register
Name
Bit
Slice
Addressh
Parameter Name
R/W
Description
RSVD
15:14
13:8
7:0
R/W
0
Reserved—do not modify.
Configure the Cable Driver output
(SDIO) 6G/12G amplitude in ~15mVpp
steps.
Functional Range = 9d to 31d
Precision Range = 21d to 27d
Default value = 24d (~800mVpp
)
Note:
• At 12G, it is the combined default
pre-emphasis and amplitude settings
that result in 800mV on most test
equipment. Shorter trace may require
reduced pre-emphasis and increased
swing setting up to 27d to achieve
CFG_OUTPUT0_CD_
UHD_DRIVER_
SWING
OUTPUT_
PARAM_
CD_UHD_3
33
R/W
18
800mV.
• In auto slew mode (CTRL_OUTPUT0_
AUTO_SLEW = 1), the slew rate is
determined by the rate at which the
reclocker is locked. If the reclocker is
unlocked, the slew will default to
6G/12G Slew. See Table 2-3 for Rise/Fall
times, and Section 4.8.3 for more details
on output driver selection.
RSVD
R/W
60
Reserved—do not modify.
GS12190
Final Data Sheet
PDS-061916
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Rev.3
May 2020
Table 5-3: Control Register Descriptions (Continued)
Reset
Valueh
Register
Name
Bit
Slice
Addressh
Parameter Name
R/W
Description
RSVD
15:13
12:8
7
R/W
0
2
0
Reserved—do not modify.
Configure the Trace Driver output (DDO)
6G pre-emphasis pulse width.
Range = 0d to 15d
CFG_OUTPUT1_TD_
6G_PREEMPH_WIDTH
R/W
R/W
Adjust the pre-emphasis pulse width to
better match the channel loss response
shape.
RSVD
Reserved—do not modify.
Trace Driver output (DDO) 6G
pre-emphasis power-down.
OUTPUT_
PARAM_
TD_6G_0
34
DDO power-down control for
pre-emphasis driver.
CFG_OUTPUT1_TD_
6G_PREEMPH_
PWRDWN
6
R/W
0
0 = Pre-emphasis driver powered-up
(pre-emphasis enabled)
1 = Pre-emphasis driver powered-down
(pre-emphasis disabled)
Configure the Trace Driver output (DDO)
6G pre-emphasis pulse amplitude.
Range = 0d to 50d
CFG_OUTPUT1_TD_
6G_PREEMPH_AMPL
5:0
15:14
13:8
R/W
R/W
R/W
1
0
Adjust the pre-emphasis pulse width to
better match the channel loss at
Nyquist.
RSVD
Reserved—do not modify.
Configure the Trace Driver output (DDO)
6G amplitude.
OUTPUT_
PARAM_
TD_6G_1
Range = 0d to 40d
CFG_OUTPUT1_TD_
6G_DRIVER_SWING
35
11
Adjust the differential Trace Driver
amplitude. The default value produces
an amplitude of 400mVppd
.
RSVD
RSVD
RSVD
7:0
R/W
R/W
R/W
70
Reserved—do not modify.
Reserved—do not modify.
Reserved—do not modify.
36
37
RSVD
RSVD
15:0
15:0
201
1170
GS12190
Final Data Sheet
PDS-061916
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Rev.3
May 2020
Table 5-3: Control Register Descriptions (Continued)
Reset
Valueh
Register
Name
Bit
Slice
Addressh
Parameter Name
R/W
Description
RSVD
15:13
12:8
7
R/W
0
2
0
Reserved—do not modify.
Configure the Trace Driver output (DDO)
12G pre-emphasis pulse width.
Range = 0d to 15d
Adjust the pre-emphasis pulse width to
better match the channel loss response
shape.
CFG_OUTPUT1_TD_
12G_PREEMPH_WIDTH
R/W
R/W
Note: When per rate settings are
chosen, the Trace Driver 12G settings
are applied for all rates when the
reclocker is unlocked (see
CTRL_OUTPUT1_TRDR_
PER_RATE for per rate setting).
RSVD
Reserved—do not modify.
Trace driver output (DDO) 12G
pre-emphasis power-down.
DDO power-down control for
pre-emphasis driver.
OUTPUT_
PARAM_
TD_12G_0
0 = Pre-emphasis driver powered-up
(pre-emphasis enabled)
1 = Pre-emphasis driver powered-down
(pre-emphasis disabled)
38
CFG_OUTPUT1_TD_
12G_PREEMPH_
PWRDWN
6
R/W
0
Note: When per rate settings are
chosen, the Trace Driver 12G settings
are applied for all rates when the
reclocker is unlocked (see
CTRL_OUTPUT1_TRDR_
PER_RATE for per rate setting).
Configure the Trace Driver output (DDO)
12G pre-emphasis pulse amplitude.
Range: 0 to 50d
Adjust the pre-emphasis pulse
amplitude to better match the channel
loss at Nyquist.
CFG_OUTPUT1_TD_
12G_PREEMPH_AMPL
5:0
R/W
1
Note: When per rate settings are
chosen, the Trace Driver 12G settings
are applied for all rates when the
reclocker is unlocked (see
CTRL_OUTPUT1_TRDR_
PER_RATE for per rate setting).
GS12190
Final Data Sheet
PDS-061916
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May 2020
Table 5-3: Control Register Descriptions (Continued)
Reset
Valueh
Register
Name
Bit
Slice
Addressh
Parameter Name
R/W
Description
RSVD
15:14
R/W
0
Reserved—do not modify.
Configure the Trace Driver output (DDO)
12G amplitude.
Range = 0d to 40d
Adjust the differential Trace Driver
amplitude. The default value produces
OUTPUT_
PARAM_
TD_12G_1
CFG_OUTPUT1_TD_
12G_DRIVER_SWING
an amplitude of 400mVppd
.
39
13:8
R/W
11
Note: When per rate settings are
chosen, the Trace Driver 12G settings
are applied for all rates when the
reclocker is unlocked (see
CTRL_OUTPUT1_TRDR_
PER_RATE for per rate setting).
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
7:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:14
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
70
201
1170
342
1C90
342
1C90
340
0
Reserved—do not modify.
Reserved—do not modify.
Reserved—do not modify.
Reserved—do not modify.
Reserved—do not modify.
Reserved—do not modify.
Reserved—do not modify.
Reserved—do not modify.
Reserved—do not modify.
3A
3B
3C
3D
3E
3F
40
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
Controls the output mute differential
latch voltage. Default is 8=~200mVdiff
.
Increasing the setting may be required
for noisy environment, but mute power
increases proportionally to mute
differential latch voltage.
OUTPUT_
PARAM_
MUTE_1
CFG_OUTPUT1_MUTE_
DRIVER_SWING
41
13:8
R/W
8
Range = 0d to 63d
Note: This parameter is only applicable
to the trace driver output (DDO).
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
7:0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
50
340
Reserved—do not modify.
Reserved—do not modify.
Reserved—do not modify.
Reserved—do not modify.
Reserved—do not modify.
Reserved—do not modify.
Reserved—do not modify.
42
43
44
45
46
47
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
15:0
15:0
15:0
15:0
15:0
15:0
850
342
1C90
342
1C90
GS12190
Final Data Sheet
PDS-061916
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Rev.3
May 2020
Table 5-3: Control Register Descriptions (Continued)
Reset
Valueh
Register
Name
Bit
Slice
Addressh
Parameter Name
R/W
Description
Output Control
RSVD
15:4
R/W
10
0
Reserved—do not modify.
Controls optional signal polarity
inversion on SDIO when data is selected
(CTRL_OUTPUT0_SIGNAL_SEL = 0).
CTRL_OUTPUT0_
DATA_INVERT
3
R/W
Controls optional signal polarity
inversion on DDO when data is selected
(CTRL_OUTPUT1_SIGNAL_SEL = 0).
CTRL_OUTPUT1_
DATA_INVERT
2
1
R/W
R/W
0
0
SDIO data vs PRBS select:
0 = Data
OUTPUT_
SIG_SELECT
48
CTRL_OUTPUT0_
SIGNAL_SEL
1 = PRBS Generator output (PRBS7 or
divided version of PRBS Generator
clock)
DDO data vs PRBS select:
0 = Data
1 = PRBS Generator output (PRBS7 or
divided version of PRBS Generator
clock)
CTRL_OUTPUT1_
SIGNAL_SEL
0
R/W
R/W
0
0
RSVD
15:6
Reserved—do not modify.
Selects if device is auto muted during
rate search, based on loss of lock at the
input in cable equalizer mode.
1 = Mutes DDO when the reclocker is
not locked to the applied signal.
CTRL_OUTPUT1_
AUTO_MUTE_DURING_
RATE_SEARCH
5
R/W
0
0 = Device does not auto mute.
Note: If passing non-standard rates
through the device or using the PRBS
generator, set this parameter to 0.
Selects if device is auto muted during
rate search, based on loss of lock at the
input in cable driver mode.
CONTROL_
OUTPUT_
MUTE
49
1 = Mutes SDIO when the reclocker is
not locked to the applied signal.
CTRL_OUTPUT0_
AUTO_MUTE_DURING_
RATE_SEARCH
4
R/W
0
0 = Device does not auto mute.
Note: If passing non-standard rates
through the device or using the PRBS
generator, set this parameter to 0.
Force manual mute mode for DDO.
0 = Unmute
1 = Mute
CTRL_OUTPUT1_
MANUAL_MUTE
3
R/W
0
Controls mute for DDO when auto mute
(CTRL_OUTPUT1_AUTO_MUTE) is
disabled.
GS12190
Final Data Sheet
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Table 5-3: Control Register Descriptions (Continued)
Reset
Valueh
Register
Name
Bit
Slice
Addressh
Parameter Name
R/W
Description
Select automatic or manual mute
control for DD0.
0 = Disable auto mute mode
1 = Enable auto mute mode
CTRL_OUTPUT1_
AUTO_MUTE
2
1
R/W
1
0
If CTRL_OUTPUT1_AUTO_MUTE = 0,
then CTRL_OUTPUT1_MANUAL_MUTE
controls mute for DDO.
CONTROL_
OUTPUT_
MUTE
49
(Continued)
Force manual mute mode for SDIO.
CTRL_OUTPUT0_
MANUAL_MUTE
(Continued)
R/W
Same settings description as
CTRL_OUTPUT1_ MANUAL_MUTE.
Select automatic or manual mute
control for SDIO
CTRL_OUTPUT0_
AUTO_MUTE
0
R/W
R/W
1
0
Same settings description as
CTRL_OUTPUT1_ AUTO_MUTE.
RSVD
15:4
Reserved—do not modify.
Force manual disable mode for DDO.
0 = Enable output driver
CTRL_OUTPUT1_
MANUAL_DISABLE
1 = Disable (power-down) output driver.
3
2
R/W
0
Controls disable for DDO when auto
mute (CTRL_OUTPUT1_AUTO_DISABLE)
is disabled.
Select automatic or manual disable
control for DD0.
0 = Disable auto disable mode
1 = Enable auto disable mode
CONTROL_
OUTPUT_
DISABLE
CTRL_OUTPUT1_
AUTO_DISABLE
4A
R/W
0
If CTRL_OUTPUT1_AUTO_DISABLE = 0,
then
CTRL_OUTPUT1_MANUAL_DISABLE
controls disable for DDO.
Force manual disable mode for SDIO.
CTRL_OUTPUT0_
MANUAL_DISABLE
1
0
R/W
R/W
0
0
Same settings description as
CTRL_OUTPUT1_ MANUAL_DISABLE.
Select automatic or manual disable
control for SDIO.
CTRL_OUTPUT0_
AUTO_DISABLE
Same settings description as
CTRL_OUTPUT1_ AUTO_DISABLE.
GS12190
Final Data Sheet
PDS-061916
102 of 121
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Table 5-3: Control Register Descriptions (Continued)
Reset
Valueh
Register
Name
Bit
Slice
Addressh
Parameter Name
R/W
Description
RSVD
15:13
R/W
0
Reserved—do not modify.
Controls whether common or per rate
trace driver output (DDO) settings are
used:
0 = Common trace driver settings:
CFG_OUTPUT1_TD_SD_* settings are
used for all rates
CTRL_OUTPUT1_
TRDR_PER_RATE
12
R/W
0
1 = Per rate trace driver settings:
CFG_OUTPUT1_TD_<rate>_* are used
when the reclocker is locked to <rate>
(See Table 2-3).
Note: CFG_OUTPUT1_TD_12G_* are
used when the reclocker is not locked.
RSVD
11:3
2:1
R/W
R/W
A0
2
Reserved—do not modify.
CONTROL_
OUTPUT_
SLEW
4B
Selects slew rate for SDIO when auto
slew rate is disabled.
CTRL_OUTPUT0_
MANUAL_SLEW
0 = SD/MADI slew
1 = HD/3G slew
2 = 6G/12G slew
Selects between auto or manual slew
rate selection for SDIO.
0 = Disable auto slew rate selection
1 = Enable auto slew rate selection
Note: In auto slew mode (CTRL_
CTRL_OUTPUT0_
AUTO_SLEW
OUTPUT0_AUTO_SLEW = 1), the slew
rate is determined by the rate at which
the reclocker is locked. If the reclocker is
unlocked, the slew will default to
6G/12G Slew. See Table 2-3 for Rise/Fall
times, and Section 4.8.3 for more details
on output driver selection.
0
R/W
1
GS12190
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Table 5-3: Control Register Descriptions (Continued)
Reset
Valueh
Register
Name
Bit
Slice
Addressh
Parameter Name
R/W
Description
RSVD
15:4
3
R/W
0
0
Reserved—do not modify.
Controls reclocker bypass for DDO when
auto mode is disabled.
CTRL_OUTPUT1_
RETIMER_MANUAL_
BYPASS
R/W
R/W
R/W
0 = Disable reclocker bypass
1 = Enable reclocker bypass
Selects between auto and manual
control of reclocker bypass for DDO.
CTRL_OUTPUT1_
RETIMER_AUTO_
BYPASS
2
1
1
0
0 = Disable auto mode
1 = Enable auto mode
CONTROL_
RETIMER_
BYPASS
4C
Controls reclocker bypass for SDIO
when auto mode is disabled.
CTRL_OUTPUT0_
RETIMER_MANUAL_
BYPASS
0 = Disable reclocker bypass
1 = Enable reclocker bypass
Selects between auto and manual
control of reclocker bypass for SDIO.
CTRL_OUTPUT0_
RETIMER_AUTO_
BYPASS
0
R/W
R/W
1
0
0 = Disable auto mode
1 = Enable auto mode
RSVD
15:1
Reserved—do not modify.
Enable or disable balanced mode on
SDIO for powered output return loss
measurement.
CONTROL_
BALANCED_
MODE
4D
CTRL_OUTPUT0_
BALANCED
0
R/W
R/W
0
0
0 = Disable
1 = Enable
4E to 4F
RSVD
RSVD
15:0
Reserved—do not modify.
GS12190
Final Data Sheet
PDS-061916
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Table 5-3: Control Register Descriptions (Continued)
Reset
Valueh
Register
Name
Bit
Slice
Addressh
Parameter Name
R/W
Description
Test Functions
RSVD
15
R/W
0
0
Reserved—do not modify.
Adjusts the phase of the clock to the
PRBS Checker. Values are:
0 = 0°
1 = 90°
2 = 180°
3 = 270°
CFG_PRBS_CHECK_
PHASEADJUST
14:13
R/W
Note: A setting of 0° is ideal for most
applications. Adjustment is not
expected.
Optionally inverts the reclocked data at
the input to the PRBS Checker:
CFG_PRBS_CHECK_
INVERT
12
R/W
0
0 = no inversion
1 = data inverted
PRBS_
CHK_CFG
50
Selects pre-divider for PRBS check
measurement timer:
0 = 4
1 = 8
2 = 16
3 = 32
4 = 64
5 = 128
6 = 256
7 = 512
8 = 1024
9 = 2048
CFG_PRBS_CHECK_
PREDIVIDER
11:8
R/W
R/W
0
3
Selects PRBS check measurement
interval for timed measurements.
CFG_PRBS_CHECK_
MEAS_TIME
7:0
See Section 4.5.1 for more details.
RSVD
15:9
8
R/W
R/W
R/W
0
0
0
Reserved—do not modify.
0 = Selects continuous PRBS check
mode
1 = Selects timed PRBS check mode
CTRL_PRBS_CHECK_
TIMED_CONT_B
RSVD
7:1
Reserved—do not modify.
PRBS_CHK_
CTRL
Set to 1 by host to start a timed
operation.
51
Set to 0 by host after completion or
abort of the operation (by the device
due to LOL) to tell the device that PRBS
result has been read by the host.
CTRL_PRBS_CHECK_
START
0
R/W
0
See Section 4.5 PRBS Checker for more
details on PRBS checker function.
GS12190
Final Data Sheet
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Table 5-3: Control Register Descriptions (Continued)
Reset
Valueh
Register
Name
Bit
Slice
Addressh
Parameter Name
R/W
Description
RSVD
15:10
R/W
0
Reserved—do not modify.
Selects whether the PRBS generator is
enabled or not:
0 = PRBS Generator disabled
1 = PRBS Generator enabled
Note: enabling the PRBS Generator
does not automatically override other
device modes such as auto-sleep,
auto-output-mute,auto-output-disable,
etc. These continue to function
CTRL_PRBS_GEN_
ENABLE
9
R/W
0
normally. The user/host may need to
adjust those settings to ensure the part
will output the PRBS signal.
Select output signal from PRBS
Generator as either PRBS7 or divided
clock (divided version of the PRBS
Generator’s clock source):
CTRL_PRBS_GEN_
SIGNAL_SELECT
8
R/W
R/W
1
0
0 = clock divider (using ratio set by
CTRL_PRBS_GEN_CLK_DIVIDER)
PRBS_GEN_
CTRL
52
1 = PRBS7
Selects clock source for PRBS Generator:
0 = VCO (free running)
1 = Reserved.
2 = Reserved.
CTRL_PRBS_GEN_
CLK_SRC
7:6
3 = Data reference PLL (reclocker
recovered clock)
Selects clock divider ratio for when host
selects divided clock to output on PRBS
Generator
CTRL_PRBS_GEN_
CLK_DIVIDER
(CTRL_PRBS_GEN_SIGNAL_SELECT = 0):
5:4
R/W
R/W
0
0
0 = Divide by 2
1 = Divide by 4
2 = Divide by 8
3 = Divide by 16
Controls optional inversion of the
generated PRBS pattern:
CTRL_PRBS_GEN_
INVERT
3
0 = true sense
1 = inverted
GS12190
Final Data Sheet
PDS-061916
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Table 5-3: Control Register Descriptions (Continued)
Reset
Valueh
Register
Name
Bit
Slice
Addressh
Parameter Name
R/W
Description
Select PRBS7 data rate when PRBS clock
source not recovered clock
(CTRL_PRBS_GEN_CLK_SRC ≠ 3)
0 = Reserved—do not use
1 = MADI
2 = SD
3 = HD
4 = 3G
5 = 6G
6 = 12G
7 = Reserved - do not use.
PRBS_GEN_
CTRL
(Continued)
CTRL_PRBS_GEN_
DATA_RATE
52
2:0
R/W
6
(Continued)
If CTRL_PRBS_GEN_CLK_SRC = 3, then
CTRL_PRBS_GEN_DATA_RATE setting
has no effect and the reclocker rate is
used (based on automatic rate
detection or manual rate selection).
Additionally, if the device is locked to an
input signal, only the same rate can be
selected for the PRBS Generator.
53
54
RSVD
RSVD
15:0
15:0
R/W
R/W
0
0
Reserved—do not modify.
CFG_EYE_MON_TIMEOUT[31:16] Most
significant 16 bits of the measurement
time. This is the time spent measuring
bit errors at each point in the eye scan,
i.e. the time to measure one point in the
eye. Units are in microseconds. The Eye
Scanner scans each point twice and
there is some overhead, so the actual
measurement time is twice the number
entered.
CFG_EYE_MON_
TIMEOUT_MS
EYE_MON_
INT_CFG_0
Valid range:
1 to 6555d
65536 d to 104895d
131072d to 3350000d
CFG_EYE_MONT_TIMEOUT[15:0] Least
significant 16 bits of the measurement
time.
CFG_EYE_MON_
TIMEOUT_LS
EYE_MON_
INT_CFG_1
55
56
15:0
15:0
R/W
R/W
64
64
See CFG_EYE_MON_ TIMEOUT_MS.
Threshold of bit error counts to define
good vs bad points in eye for
shape-scan.
CFG_EYE_BER_
THRESHOLD
EYE_MON_
INT_CFG_2
See Section 4.6 for further details.
GS12190
Final Data Sheet
PDS-061916
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Table 5-3: Control Register Descriptions (Continued)
Reset
Valueh
Register
Name
Bit
Slice
Addressh
Parameter Name
R/W
Description
The vertical offset slice that will be used
for eye shape queries. Offset values: 0 to
255d. 0 represents the most negative
slice since 128d is the 0V slice level and
255d is the most positive slice level.
Default is 128d.
CFG_EYE_DEFAULT_
VERT_OFFSET
15:8
R/W
80
EYE_MON_
INT_CFG_3
57
RSVD
7:3
2
R/W
R/W
0
0
Reserved—do not modify.
Eye monitor initialization bit. Set HIGH
during Device Power-up Sequence. See
Section 4.10.12 for details.
CFG_EYE_INIT_RESET
RSVD
RSVD
RSVD
1:0
15:0
15
R/W
R/W
R/W
2
0
0
Reserved—do not modify.
Reserved—do not modify.
Reserved—do not modify.
58 to 59
RSVD
Starting phase offset. Valid range is 0d to
127d. Reset value must be used for
shape-scan.
CTRL_EYE_PHASE_
START
14:8
7
R/W
R/W
0
0
EYE_MON_
SCAN_CTRL_0
RSVD
Reserved—do not modify.
5A
Phase offset limit. Valid range is 0d to
127d. CTRL_EYE_PHASE_STOP must be
greater or equal to
CTRL_EYE_PHASE_START. Reset value
must be used for shape-scan.
CTRL_EYE_PHASE_
STOP
6:0
15
R/W
R/W
7F
0
RSVD
Reserved—do not modify.
Unsigned value for phase step size. Valid
values are 1,2, and 4. Reset value must
be used for shape-scan. Behaviour is
undefined for other values.
CTRL_EYE_PHASE_
STEP
14:8
R/W
1
In order to use a step size of 2 or 4,
CTRL_EYE_PHASE_START and
CTRL_EYE_PHASE_STOP must be set to
their default values.
EYE_MON_
SCAN_CTRL_1
5B
RSVD
7
R/W
R/W
0
0
Reserved—do not modify.
Starting voltage offset. Valid range is 0d
to 255d.
CTRL_EYE_VERT_
OFFSET_START
6:0
GS12190
Final Data Sheet
PDS-061916
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Table 5-3: Control Register Descriptions (Continued)
Reset
Valueh
Register
Name
Bit
Slice
Addressh
Parameter Name
R/W
Description
Voltage offset limit. Valid range is 0 to
255d. CTRL_EYE_VERT_OFFSET_STOP
must be greater or equal to
CTRL_EYE_VERT_OFFSET_START. Reset
value must be used for shape-scan.
CTRL_EYE_VERT_
OFFSET_STOP
15:8
7
R/W
R/W
FF
0
RSVD
Reserved—do not modify.
EYE_MON_
SCAN_CTRL_2
5C
Unsigned value for voltage offset step
size. Valid values are 1,2, and 4.
Behaviour is undefined for other values.
In order to use a step size of 2 or 4,
CTRL_EYE_VERT_OFFSET_START and
CTRL_EYE_VERT_OFFSET_STOP mustbe
set to their default values.
CTRL_EYE_VERT_
OFFSET_STEP
6:0
R/W
1
RSVD
15:9
8
R/W
R/W
R/W
0
0
0
Reserved—do not modify.
Selects whether the Eye Monitor should
perform an eye scan or eye shape
capture:
CTRL_EYE_SHAPE_
SCAN_B
0 = Selects eye scan (new or continued)
1 = Selects eye shape capture
RSVD
7:2
Reserved—do not modify.
Power control for the Eye Monitor:
0 = Power-down the Eye Monitor
1 = Power-up the Eye Monitor
Host is permitted to change this any
time between eye scans (but not
between partial eye scans).
CTRL_EYE_MON_
POWER_CTRL
1
R/W
0
EYE_MON_
SCAN_CTRL_3
5D
This must be set to 1 to run an eye scan.
Behaviour is undefined if host sets
CTRL_EYE_MON_START = 1 without
setting this bit to 1.
Part of a four way handshake with
STAT_EYE_MON_STATUS:
0 = Set by host to tell the device to clear
the status bit
1 = Set by host only in order to
begin/continue an eye scan or start an
eye shape capture
CTRL_EYE_MON_START
0
R/W
—
0
See Section 4.6 for more details on
implementing the four way hand shake
for this operation.
5E to 5F
60 to 7E
RSVD
RSVD
RSVD
RSVD
15:0
—
—
Reserved.
Factory Settings
15:0
—
Reserved.
GS12190
Final Data Sheet
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5.3.2 Status Register Descriptions
Table 5-4: Status Register Descriptions
Reset
Valueh
Register
Name
Bit
Slice
Addressh
Parameter Name
R/W
Description
80
RSVD
RSVD
15:0
15:0
RO
—
—
Reserved—do not modify.
This register contains the first part of
the device configuration version. Please
contact your local technical sales
representative for more details.
81
82
83
VERSION_0
VERSION_1
VERSION_2
STAT_CONFIG_VER0
STAT_CONFIG_VER1
STAT_HW_VERSION
RO
RO
RO
This register contains the second part
of the device configuration version.
Please contact your local technical sales
representative for more details.
15:0
15:0
—
—
This register contains the devices
identification, including revision. Please
contact your local technical sales
representative for more details.
Count of primary carrier detection
status changes (ignoring CLI squelch in
Cable Equalizer Mode). The count
saturates at 255d (0xFF).
STAT_CNT_PRI_CD_
CHANGES
15:8
RO
—
See Section 4.10.11 for procedure to
clear the counts.
Count of secondary carrier detection
status changes (based on STAT_CLI_
SQUELCH if CFG_SEC_CD_ INCL_
CLI_SQUELCH = 1; otherwise this
parameter is based on STAT_PRI_CD).
STICKY_
COUNTS_0
84
STAT_CNT_SEC_CD_
CHANGES
7:0
RO
—
The count saturates at 255d (0xFF). See
Section 4.10.11 for procedure to clear
the counts.
Note: This parameter is only applicable
to the cable equalizer input (SDIO).
Count of rate changes. The count
saturates at 255d (0xFF).
STAT_CNT_RATE_
CHANGES
15:8
7:0
RO
RO
—
—
See Section 4.10.11 for procedure to
clear the counts.
STICKY_
COUNTS_1
85
Count of PLL lock status changes. The
count saturates at 255d (0xFF).
STAT_CNT_PLL_
LOCK_CHANGES
See Section 4.10.11 for procedure to
clear the counts.
GS12190
Final Data Sheet
PDS-061916
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Table 5-4: Status Register Descriptions (Continued)
Reset
Valueh
Register
Name
Bit
Slice
Addressh
Parameter Name
R/W
Description
RSVD
15
RO
—
Reserved—do not modify.
0 = Idle
1 = Reserved
2 = Indicates device has cleared the
sticky counts
3 = Reserved
STAT_CLEAR_COUNTS_
STATUS
14:13
RO
—
Part of a four way handshake with
CTRL_CLEAR_COUNTS.
See Section 4.10.11 for more details on
implementing the four way handshake
for this operation.
0 = PLL is unlocked
1 = PLL is locked
STAT_LOCK
12
RO
—
0 = Device is not in sleep
1 = Device is currently in sleep
STAT_SLEEP
RSVD
11
10
RO
RO
—
—
Reserved—do not modify.
Indicates currently selected direction of
device:
STAT_ACTIVE_
DIRECTION
9
8
RO
RO
—
—
0 = Cable Equalizer / receiver mode
1 = Cable Driver / transmitter mode
CURRENT_
STATUS_0
86
Cable Equalizer squelch status.
0 = CLI squelch is de-asserted
1 = CLI squelch is asserted
STAT_CLI_SQUELCH
Note: This parameter is only applicable
to the cable equalizer input (SDIO).
DDO output status:
0 = Mission Trace Driver <= SD rate
1 = Mission Trace Driver HD rate
2 = Mission Trace Driver 3G rate
3 = Mission Trace Driver 6G rate
4 = Mission Trace Driver 12G
5 = Reserved
6 = Muted
7 = Disabled
STAT_OUTPUT1_MODE
7:4
RO
—
Note: The device will only indicate 1-4 if
the per rate settings are enabled,
otherwise, it will always indicate 0 if it is
locked to a valid signal and the output
is not muted or disabled. See section
Section 4.8.3 Output Driver Data Rate
Selection for more details.
GS12190
Final Data Sheet
PDS-061916
111 of 121
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Table 5-4: Status Register Descriptions (Continued)
Reset
Valueh
Register
Name
Bit
Slice
Addressh
Parameter Name
R/W
Description
SDIO output status:
0 = Mission Cable Driver SD/MADI slew
rate
1 = Mission Cable Driver HD/3G slew
rate
86
CURRENT_
STATUS_0
(Continued)
2 = Mission Cable Driver 6G/12G slew
rate
(Continued)
STAT_OUTPUT0_MODE
3:0
RO
—
3 = Reserved
4 = Reserved
5 = Balanced
6 = Muted
7 = Disabled
DDO Disable Status
0 = DDO is not disabled
1 = DDO is disabled
STAT_OUTPUT1_
DISABLE
15
14
13
12
RO
RO
RO
RO
—
—
—
—
SDIO Disable Status
0 = SDIO is not disabled
1 = SDIO is disabled
STAT_OUTPUT0_
DISABLE
DDO Mute Status
0 = DDO is not muted
1 = DDO is muted
STAT_OUTPUT1_
MUTE
SDIO Mute Status
0 = SDIO is not muted
1 = SDIO is muted
STAT_OUTPUT0_MUTE
DDO Reclocker Status
STAT_OUTPUT1_
RETIMER_BYPASS
0 = reclocker path to DDO is not
bypassed
1 = reclocker path to DDO is bypassed
CURRENT_
STATUS_1
11
10
RO
RO
—
—
87
SDIO Reclocker Status
0 = reclocker path to SDIO is not
bypassed
STAT_OUTPUT0_
RETIMER_BYPASS
1 = reclocker path to SDIO is bypassed
Secondary carrier detection status
(based on STAT_CLI_SQUELCH if
CFG_SEC_CD_INCL_CLI_SQUELCH=1;
otherwise this parameter is based on
STAT_PRI_CD).
STAT_SEC_CD
9
RO
—
0 = Secondary carrier is not detected
1 = Secondary carrier is detected
Note: This status is only applicable to
the cable equalizer input (SDIO).
GS12190
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Table 5-4: Status Register Descriptions (Continued)
Reset
Valueh
Register
Name
Bit
Slice
Addressh
Parameter Name
R/W
Description
Primary carrier detection status
(ignoring CLI squelch for Cable
Equalizer input (SDIO)).
STAT_PRI_CD
8
7
RO
—
—
0 = Primary carrier is not detected
1 = Primary carrier is detected
Cable Equalizer bypass status:
0 = CEQ is not bypassed
1 = CEQ is bypassed
STAT_CEQ_BYPASS
RSVD
RO
Note: This parameter is only applicable
to the cable equalizer input (SDIO).
6:5
4:3
RO
RO
—
—
Reserved—do not modify.
CURRENT_
STATUS_1
(Continued)
87
SDIO slew rate when in Cable Driver
Mode.
(Continued)
STAT_OUTPUT0_
SLEW_RATE
0 = SD/MADI slew
1 = HD/3G slew
2 = 6G/12G slew
Rate at which the reclocker is locked.
0 = Unlocked
1 = MADI (125Mb/s)
2 = SD (270Mb/s)
3 = HD (1.485Gb/s)
4 = 3G (2.97Gb/s)
5 = 6G (5.94Gb/s)
6 = 12G (11.88Gb/s)
7 = Reserved
STAT_DETECTED_RATE
2:0
RO
RO
—
—
RSVD
15:8
Reserved—do not modify.
SDIO cable length indication when in
Cable Equalizer Mode.
Range = 0 to 64d (64d is max cable
reach determined for specific rate,
cable type, and launch swing
compensation).
88
EQ_GAIN_IND
STAT_CABLE_LEN_
INDICATION
7:0
RO
—
0xFF = Unknown cable length
Note: This parameter is only applicable
to the cable equalizer input (SDIO).
PRBS Checker error count. Cleared to 0
at the start of a measurement. Updated
by the device on completion of a
measurement. Value is undefined in
case of abort due to loss of the
reclocker lock
STAT_PRBS_CHK_
ERR_CNT
PRBS_
CHK_ERR_CNT
89
15:0
RO
—
(STAT_PRBS_CHECK_LAST_ABORT = 1).
GS12190
Final Data Sheet
PDS-061916
113 of 121
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Table 5-4: Status Register Descriptions (Continued)
Reset
Valueh
Register
Name
Bit
Slice
Addressh
Parameter Name
R/W
Description
RSVD
15:10
RO
—
Reserved—do not modify.
0 = Normal
1 = No data transitions were seen
during the previous PRBS check
This bit is set to 1 to indicate that the
input data was all 0’s during a PRBS
check. When that happens, the error
count will be zero when in fact there
was no valid PRBS pattern.
STAT_PRBS_CHECK_
NODATA
9
RO
—
This bit is updated by the device on
completion of a measurement. It
retains its value until the next PRBS
check operation is requested. Value is
undefined in case of abort
(STAT_PRBS_CHECK_LAST_ABORT = 1).
Value does not increment during a
measurement until it completes.
This bit retains its value until the next
PRBS operation is requested.
STAT_PRBS_CHECK_
LAST_ABORT
8
RO
RO
—
—
0 = Normal
1 = PRBS check was aborted due to loss
of lock or sleep
PRBS_
CHK_STATUS
8A
RSVD
7:2
Reserved—do not modify.
Status for PRBS Checker:
0 = PRBS check idle; ready for new
operation
1 = PRBS check timed or continuous
operation in progress
2 = PRBS check timed operation
completed (success)
3 = PRBS check timed or continuous
operation aborted (error)
STAT_PRBS_CHECK_
STATUS
1:0
RO
—
Part of a four way handshake with
CTRL_PRBS_CHECK_START
(Section 4.5).
Abort will be reported if loss of lock or
sleep occurred during a PRBS check
operation or those conditions existed
when the operation was requested by
the host.
EYE_MON_
SCAN_
SIZE_OUTPUT
The size in bytes of the last partial scan
segment.
8B
STAT_EYE_IMAGE_SIZE
15:0
RO
—
GS12190
Final Data Sheet
PDS-061916
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Table 5-4: Status Register Descriptions (Continued)
Reset
Valueh
Register
Name
Bit
Slice
Addressh
Parameter Name
R/W
Description
Left Edge Voltage Offset—Offset values
0 to 255d, 0 represents most negative
voltage, 127d is 0V 255d is most positive
voltage.
STAT_EYE_SHAPE_
LEFT_EDGE_OFFSET
15:8
7:0
RO
RO
RO
RO
RO
RO
RO
RO
—
—
—
—
—
—
—
—
EYE_MON_
SHAPE_
OUTPUT_0
8C
Left Edge Phase of eye shape-scan.
Phase values 0 to 127d.
STAT_EYE_SHAPE_
LEFT_EDGE_PHASE
Positive (top) Edge Voltage Offset—
Offset values 0 to 255d, 0 represents
most negative voltage, 127d is 0V 255d
is most positive voltage.
STAT_EYE_SHAPE_
POS_EDGE_OFFSET
15:8
7:0
EYE_MON_
SHAPE_
8D
8E
8F
OUTPUT_1
Positive (top) Edge Phase of eye
shape-scan. Phase values 0 to 127d.
STAT_EYE_SHAPE_
POS_EDGE_PHASE
Right Edge Voltage Offset—Offset
values 0 to 255d, 0 represents most
negative voltage, 127d is 0V 255d is
most positive voltage.
STAT_EYE_SHAPE_
RIGHT_EDGE_OFFSET
15:8
7:0
EYE_MON_
SHAPE_
OUTPUT_2
Right Edge Phase of eye shape-scan.
Phase values 0 to 127d.
STAT_EYE_SHAPE_
RIGHT_EDGE_PHASE
Negative (bottom) Edge Voltage
Offset—Offset values 0 to 255d, 0
represents most negative voltage, 127d
is 0V 255d is most positive voltage.
STAT_EYE_SHAPE_
NEG_EDGE_OFFSET
15:8
7:0
EYE_MON_
SHAPE_
OUTPUT_3
Negative (bottom) Edge Phase of eye
shape-scan. Phase values 0 to 127d.
STAT_EYE_SHAPE_
NEG_EDGE_PHASE
GS12190
Final Data Sheet
PDS-061916
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Table 5-4: Status Register Descriptions (Continued)
Reset
Valueh
Register
Name
Bit
Slice
Addressh
Parameter Name
R/W
Description
RSVD
15:9
RO
—
—
—
Reserved—do not modify.
0 = Full scan
1 = Partial scan
On completion of an Eye Monitor eye
scan (CRTL_EYE_SHAPE_SCAN_B = 0),
indicates whether the Eye Monitor
completed the full scan or a partial
scan.
STAT_EYE_SCAN_
PARTIAL_OR_FULL
8
RO
RO
Undefined for eye shape-scan
(CTRL_EYE_SHAPE_SCAN_B = 1).
RSVD
7:2
Reserved—do not modify.
0 = Eye Monitor idle; ready for new
operation
EYE_MON_
STATUS
90
1 = Eye Monitor operation in progress
2 = Eye Monitor operation completed
(success)
3 = Eye Monitor operation aborted
(error)
Part of a four way handshake with
CTRL_EYE_MON_START, see Section 4.6
for procedure.
STAT_EYE_MON_
STATUS
1:0
RO
—
Abort will be reported by device if loss
of lock or sleep occurred during an Eye
Monitor operation or those conditions
existed when the operation was
requested by the host.
91 to BF
RSVD
RSVD
15:0
RO
—
Reserved—do not modify.
GS12190
Final Data Sheet
PDS-061916
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6. Application Information
6.1 Typical Application Circuit
VCC1V8
VCC1V8
470nF
C14
C11
100nF
10μF
C13
35
C12 10μF
34
40
39 38
37
36
33 32
31
30 29
1
VEE_DDI
28
VEEO
4.7μF
C10
27
26
2
3
SDIO
IO
NC
4.7μF
C2
4.7μF
C9
2Ω
75Ω
SDI_TERM
SDO
VCCSDIO2V5
100nF
VCC1V8
C8
25
24
VCCO_0
VCCO_1
4
5
VCC_DDI
TERM
GS12190
C3 1μF
VCCDDO1V8
100nF
Note: The device central paddle is not an electrical
connection. Refrain from connecting device pins to
the central paddle.
C7
23
22
DDO
OUT
OUT
C4 100nF
6
7
8
IN
IN
DDI
DDO
21
DDI
VEEO
VEE_DDI
9
10
11
12
13 14
15
16
17
18
19
20
VCC1V8
100nF
VCCD1V8
100nF
C5
C6
Figure 6-1: Typical Application Circuit
Note 1: 4.7µF AC-coupling capacitors are required on DDO/DDO when the downstream
IC has an input common mode range that is incompatible with the output common
mode range of the GS12190.
Note 2: It is recommended that separate filtered supplies are used for the following
three groups: (VCC_DDI, VCC_CORE), (VCCO1P8_0, VCCO1P8_1, VDD, VCCO_1*), (VCCO_0).
*Assuming VCCO_1 supply is chosen as 1.8V.
Multiple devices can share the same filtered supply plane.
GS12190
Final Data Sheet
PDS-061916
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7. Package & Ordering Information
7.1 Package Dimensions
DIMENSIONS
MILLIMETERS
MIN NOM MAX
0.80 0.90 1.00
A1 0.00 0.02
A
D
B
E
DIM
A
0.05
(0.02)
0.20 0.25
5.95 6.00 6.05
A2
b
D
PIN 1
INDICATOR
(LASER MARK)
0.15
D1 3.45 3.60 3.70
3.95 4.00 4.05
E1 1.43 1.58 1.68
E
e
0.40 BSC
L
0.30 0.40 0.50
N
40
aaa
bbb
0.08
0.10
A
SEATING
PLANE
aaa
C
C
A1
A2
D1
LxN
E/1
E1
2
1
N
bxN
0.30 x 45°
NOTES:
e/2
bbb
C A B
e
D/2
1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.
3. DIMENSION OF LEAD WIDTH APPLIES TO TERMINAL AND IS MEASURED BETWEEN
0.15 to 0.30mm FROM THE TERMINAL TIP.
Figure 7-1: Package Dimensions
GS12190
Final Data Sheet
PDS-061916
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7.2 Recommended PCB Footprint
0.20
0.60
Pin #1
3.60
0.40
5.20
Figure 7-2: Recommended PCB Footprint
7.3 Packaging Data
Table 7-1: Packaging Data
Parameter
Value
Package Type
6mm x 4mm 40-pin QFN
Moisture Sensitivity Level
3
Junction to Air Thermal Resistance, j-a (at zero airflow)
Junction to Board Thermal Resistance, j-b
Junction to Case Thermal Resistance, j-c
40.0°C/W
32.0°C/W
36.0°C/W
<1.0°C/W
Yes
Junction-to-Top Characterization Parameter, Psi,
Pb-free and RoHS compliant
GS12190
Final Data Sheet
PDS-061916
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7.4 Marking Diagram
Pin 1
GS12190
XXXXE3
YYWW
XXXX = Last 4 Digits of Assembly lot
E3 = Pb-free & Green Indicator
YYWW = Date Code
Figure 7-3: Marking Diagram
7.5 Solder Reflow Profile
Temperature
60-150 sec.
20-40 sec.
260°C
250°C
3°C/sec max
217°C
6°C/sec max
200°C
150°C
25°C
Time
60-180 sec. max
8 min. max
Figure 7-4: Maximum Pb-free Solder Reflow Profile
7.6 Ordering Information
Table 7-2: Ordering Information
Minimum Order
Part Number
Format
Quantity
GS12190-INE3
GS12190-INTE3
GS12190-INTE3Z
490
250
Tray
Tape and Reel
Tape and Reel
2500
GS12190
Final Data Sheet
PDS-061916
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Rev.3
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IMPORTANT NOTICE
Information relating to this product and the application or design described herein is believed to be reliable, however such information is
provided as a guide only and Semtech assumes no liability for any errors in this document, or for the application or design described herein.
Semtech reserves the right to make changes to the product or this document at any time without notice. Buyers should obtain the latest relevant
information before placing orders and should verify that such information is current and complete. Semtech warrants performance of its
products to the specifications applicable at the time of sale, and all sales are made in accordance with Semtech’s standard terms and conditions
of sale.
SEMTECH PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS,
DEVICES OR SYSTEMS, OR IN NUCLEAR APPLICATIONS IN WHICH THE FAILURE COULD BE REASONABLY EXPECTED TO RESULT IN PERSONAL
INJURY, LOSS OF LIFE OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. INCLUSION OF SEMTECH PRODUCTS IN SUCH APPLICATIONS IS
UNDERSTOOD TO BE UNDERTAKEN SOLELY AT THE CUSTOMER’S OWN RISK. Should a customer purchase or use Semtech products for any such
unauthorized application, the customer shall indemnify and hold Semtech and its officers, employees, subsidiaries, affiliates, and distributors
harmless against all claims, costs damages and attorney fees which could arise.
The Semtech name and logo are registered trademarks of the Semtech Corporation. All other trademarks and trade names mentioned may be
marks and names of Semtech or their respective companies. Semtech reserves the right to make changes to, or discontinue any products
described in this document without further notice. Semtech makes no warranty, representation or guarantee, express or implied, regarding the
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© Semtech 2020
Contact Information
Semtech Corporation
200 Flynn Road, Camarillo, CA 93012
Phone: (805) 498-2111, Fax: (805) 498-3804
www.semtech.com
GS12190
Final Data Sheet
PDS-061916
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121Proprietary & Confidential
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