SC2446AEVB [SEMTECH]
Dual-Phase, Single or Dual Output Synchronous Step-Down Controller; 双相，单或双输出同步降压型控制器
| 型号： | SC2446AEVB |
| 厂家： | 
SEMTECH CORPORATION |
| 描述： | Dual-Phase, Single or Dual Output Synchronous Step-Down Controller |
| 文件： | 总27页 (文件大小：525K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SC2446A
Dual-Phase, Single or Dual Output
Synchronous Step-Down Controller
POWER MANAGEMENT
Features
Description
2-Phase synchronous continuous conduction mode
for high efficiency step-down converters
Out of phase operation for low input current ripples
Output source and sink currents
Fixed frequency peak current-mode control
50mV/-75mV maximum current sense voltage
Inductive current-sensing for low-cost applications
Optional resistor current-sensing for precise cur-
rent-limit
Dual outputs or 2-phase single output operation
Excellent current sharing between individual phases
Wide input voltage range: 4.7V to 16V
Individual soft-start, overload shutdown and enable
Duty cycle up to 88%
0.5V feedback voltage for low-voltage outputs
External reference input for DDR applications
Programmable frequency up to 1MHz per phase
External synchronization
The SC2446A is a high-frequency dual synchronous step-
down switching power supply controller. It provides out-
of-phase output gate signals. The SC2446A operates in
synchronous continuous-conduction mode. Both phases
are capable of maintaining regulation with sourcing or
sinking load currents, making the SC2446A suitable for
generating both VDDQ and the tracking VTT for DDR appli-
cations.
The SC2446A employs fixed frequency peak current-
mode control for the ease of frequency compensation
and fast transient response.
The dual-phase step-down controllers of the SC2446A
can be configured to provide two individually controlled
and regulated outputs or a single output with shared
current in each phase. The Step-down controllers oper-
ate from an input of at least 4.7V and are capable of
regulating outputs as low as 0.5V
The step-down controllers in the SC2446A have the pro-
vision to sense inductor RDC voltage drop for current-mode
control. This sensing scheme eliminates the need of the
current-sense resistor and is more noise-immune than
direct sensing of the high-side or the low-side MOSFET
voltage. Precise current-sensing with sense resistor is
optional.
Individual soft-start and overload shutdown timer is in-
cluded in each step-down controller. The SC2446A imple-
ments hiccup overload protection. In two-phase single-
output configuration, the master timer controls the soft-
start and overload shutdown functions of both control-
lers.
Industrial temperature range
28-lead TSSOP lead free package. This product is
fully WEEE and RoHS compliant
Applications
Telecommunication power supplies
DDR memory power supplies
Graphic power supplies
Servers and base stations
Typical Application Circuit
V IN (12V)
VING ND
C6
C7
R55
R49
23
19
20
PVCC
BST2
GDH2
VO1
U10
U9
VO2
13
26
25
13
VDDC
VDDC
BST1
C68
1
C67
1
VDDO
VDDO
GDH1
L6
L5
C23
10
10
VO
CB
VO
CB
C45
R53
0
C65
R52
C62
16
9
16
9
R46
VI
VI
C74
R14
C75
11
28
11
28
24
22
27
1
21
0
GD L1
PGND
VPN 1
CS1+
CS1-
GD L2
VSSO
VSSC
VSSC
VSSO
R13
18
14
13
12
11
10
17
6
VPN 2
CS2+
R50
Integrated M O SFET/D river
Integrated M O SFET/D river
RCS-5
RCS-6
2
CS2-
VO2GND
VO1GND
4
IN1-
IN2-
5
COMP1
RE F
COMP2
RE FIN
VIN 2
R28
8
REFOUT (0. 5V)
REFOUT (0. 5V)
R48
7
R29
C40
AGND
Rosc
AVCC
C63
R45
C29
R51
3
SYNC
SS1/EN1
TP11
R47
C64
16
9
28
15
C70
VIN
REFOUT SS2/EN2
C72
C73
C71
U3
SC2446A
REFOUT (0. 5V)
Figure 1
1
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Revision: November 9, 2005
SC2446A
POWER MANAGEMENT
Absolute Maximum Rating
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified
in the Electrical Characteristics section is not implied. Exposure to Absolute Maximum rated conditions for extended periods of time may affect device
reliability.
Parameter
Supply Voltage
Gate Outputs GDH1, GDH2, GDL1, GDL2 voltages
Symbol
AVCC
VGDH1, VGDH2,VGDL1, VGDL2
Maximum Ratings
-0.3 to 16
Units
V
V
-0.3 to 6
IN1-, IN2- Voltages
REFOUT Voltages
VIN1-,VIN2-
-0.3 to AVCC+0.3
-0.3 to 6
V
V
VREF ,VREFOUT
REF, REFIN Voltage
COMP1, COMP2 Voltages
CS1+, CS1-, CS2+ and CS2- Voltages
VREFIN
VCOMP1,VCOMP2
VCS1+,VCS1-,VCS2+,VCS2-
-0.3 to AVCC+0.3
-0.3 to AVCC+0.3
-0.3 to AVCC+0.3
V
V
V
SYNC Voltage
SS1/EN1 AND SS2/EN2 Voltages
Ambient Temperature Range
Thermal Resistance Junction to Case (TSSOP-28)
Thermal Resistance Junction to Ambient (TSSOP-28)
Storage Temperature Range
Lead Temperature (Soldering) 10 sec
Maximum Junction Temperature
VSYNC
VSS1,VSS2
TA
-0.3 to AVCC+0.3
V
V
°C
°C/W
°C/W
°C
-0.3 to 6
-40 to 125
13
θJC
84
θJA
TSTG
TLEAD
TJ
-60 to 150
260
°C
°C
150
Electrical Characteristics
Unless specified: AVCC = 12V, SYNC = 0, ROSC = 51.1kΩ, -40°C < TA = TJ < 125°C
Parameter
Undervoltage Lockout
Symbol
Conditions
Min
Typ
Max
4.7
15
Units
AVCC Start Threshold
AVCCTH AVCC Increasing
AVCCHYST
4.5
V
AVCC Start Hysteresis
AVCC Operating Current
0.2
8
V
mA
ICC
AVCC= 12V
AVCC Quiescent Current in UVLO
Channel 1 Error Amplifier
AVCC = AVCCTH - 0.2V
2.5
mA
Input Common-Mode Voltage Range
Inverting Input Voltage Range
(Note 1)
(Note 1)
0 ~ 70° C
0
0
3
V
V
AVCC
±3
Input Offset Voltage
1
-100
-100
260
65
mV
nA
nA
Non-Inverting Input Bias Current
Inverting Input Bias Current
IREF
-250
-250
I
IN1-
µΩ−1
Amplifier Transconductance
GM1
aOL1
Amplifier Open-Loop Gain
dΒ
Amplifier Unity Gain Bandwidth
Minimum COMP1 Switching Threshold
5
MHz
V
V
= VCS1- = 0
2.2
VCSSS11+Increasing
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SC2446A
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Unless specified: AVCC = 12V, SYNC = 0, ROSC = 51.1kΩ, -40°C < TA = TJ < 125°C
Parameter
Symbol
Conditions
Min
Typ
16
Max
Units
µA
Amplifier Output Sink Current
Amplifier Output Source Current
V
IN1- = 1V, VCOMP1 = 2.5V
VIN1- = 0, VCOMP1 = 2.5V
12
µA
Channel 2 Error Amplifier
Input Common-mode Voltage Range
Inverting Input Voltage Range
Input Offset Voltage
Non-inverting Input Bias Current
Inverting Input Bias Current
(Note 1)
(Note 1)
0 ~ 70° C
0
0
3
V
V
mV
nA
nA
AVCC
±3
-380
-250
1.5
-150
-100
I
IN2+
I
IN2-
Inverting Input Voltage for 2-Phase Single
2.5
V
Output Operation
µΩ−1
Amplifier Transconductance
Amplifier Open-Loop Gain
Amplifier Unity Gain Bandwidth
GM2
aOL2
260
65
5
dΒ
MHz
V
= VCS2- = 0
VCSSS22+Increasing
VCOMP2 = 2.5V
VCOMP2 = 2.5V
Minimum COMP2 Switching Threshold
2.2
V
Amplifier Output Sink Current
Amplifier Output Source Current
Oscillator
16
12
µA
µA
Channel Frequency
f
CH1, fCH2
0 ~ 70° C
(Note 1)
450
2.1fCH
1.5
500
88
550
0.5
KHz
KHz
V
V
µA
Synchronizing Frequency
SYNC Input High Voltage
SYNC Input Low Voltage
SYNC Input Current
ISYNC
VSYNC = 0.2V
VSYNC = 2V
1
50
Channel Maximum Duty Cycle
Channel Minimum Duty Cycle
Current-limit Comparators
Input Common-Mode Range
D
MAX1, DMAX2
%
%
D
MIN1, DMIN2
0
0
AVCC - 1
60
V
VILIM1+,
VILIM2+
VCS1- = V
= 0.5V,
SourcingCMS2o- de, 0 ~ 70° C
Cycle-by-cycle Peak Current Limit
40
50
-75
-0.7
-0.7
mV
Valley Current Overload Shutdown
Threshold
VCS1- = VCS2- = 0.5V,
VILIM1-, VILIM2-
ICS1+, ICS2+
ICS1-, ICS2-
-60
-90
-2
mV
µA
µA
Sinking Mode, 0 ~ 70° C
V
=VCS1- = 0
VCCSS21+- =VCS2- = 0
Positive Current-Sense Input Bias Current
Negative Current-Sense Input Bias
Current
V
=VCS1- = 0
VCCSS21++ =VCS2- = 0
-2
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SC2446A
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Unless specified: AVCC = 12V, SYNC = 0, ROSC = 51.1kΩ, -40°C < TA = TJ < 125°C
Parameter
Symbol
Conditions
Min
Typ
Max
Units
PWM Outputs
Peak Source Current
G
DL1, GDL2,
AVCC = 12V
AVCC = 12V
4
3
mA
mA
GDH1, GDH2
Peak Sink Current
GDL1, GDL2,
GDH1, GDH2
Output High Voltage
Output Low Voltage
Source IO = 1.2mA, 0 ~ 70° C
Sink IO = 1mA
3.95
0
5
V
V
0.4
Minimum On-Time
TA = 25°C
120
ns
Soft-Start, Overload Latchoff and Enable
Soft-Start Charging Current
ISS1, ISS2
VSS1 = VSS2 = 1.5V
1.8
3.2
µA
Overload Latchoff Enabling
VSS1 and VSS2 Increasing
V
Soft-Start Voltage
Overload Latchoff
IN1- Threshold
V
SS1 = 3.8V, VIN1-Decreasing
SS2 = 3.8V, VIN2-Decreasing
0.5VREF
V
V
Overload Latchoff
0.5 X
VREFIN
V
V
IN2- Threshold
= 0.5VREF
,
Soft-Start Discharge Current
I
SS1(DIS), ISS2(DIS) VIINN12--=0.5V
,
1.2
µA
REFIN
VSS1 = VSS2 = 3.8V
Overload Latchoff Recovery
Soft-Start Voltage
VSSRCV1,
VSSRCV2
VSS1 and VSS2 Decreasing
0.3
0.7
0.5
0.8
1.2
0.7
V
V
V
PWM Output Disable SS/EN
Voltage
PWM Output Enable SS/EN
Voltage
Internal 0.5V Reference Buffer
1.5
505
Output Voltage
VREFOUT
IREFOUT = -1mA, 0°C < T = T < 70°C
495
500
mV
-
A
J
Load Regulation
0 < IREFOUT < -5mA
AVCCTH < AVCC < 15V, IREFOUT = -1mA
0.05
%/mA
%V
Line Regulation
0.02%
Notes:
(1) Guaranteed by design not tested in production.
(2) This device is ESD sensitive. Use of standard ESD handling precautions is required.
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SC2446A
POWER MANAGEMENT
Ordering Information
Pin Configurations
Device
Package
Temp. Range( TA)
TOP VIEW
SC2446AITSTRT(1)(2) TSSOP-28
-40 to 125°C
SC2446AEVB
Evaluation Board
CS1+
CS1-
ROSC
IN1-
1
2
3
4
5
6
7
8
28
27
26
25
24
23
22
21
20
19
18
17
16
15
SS1/EN1
VPN1
BST1
GDH1
GDL1
PVCC
PGND
GDL2
GDH2
BST2
Notes:
(1) Only available in tape and reel packaging. A reel
contains 2500 devices for TSSOP package.
(2) Lead free product. This product is fully WEEE and
RoHS compliant.
COMP1
SYNC
AGND
REF
REFOUT
REFIN
COMP2
IN2-
9
10
11
12
13
14
VPN2
VIN2
CS2-
CS2+
AVCC
SS2/EN2
(28 Pin TSSOP)
Figure 2
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SC2446A
POWER MANAGEMENT
Pin Descriptions
TSSOP Package
Pin
Pin Name
Pin Function
1
CS1+
The Non-inverting Input of the Current-sense Amplifier/Comparator for the Controller 1.
The Inverting Input of the Current-sense Amplifier/Comparator for the Controller 1. Normally
tied to the output of the converter.
2
3
4
5
CS1-
ROSC
IN1-
An external resistor connected from this pin to GND sets the oscillator frequency.
Inverting Input of the Error Amplifier for the Step-down Controller 1. Tie an external resistive
divider between OUTPUT1 and the ground for output voltage sensing.
COMP1
The Error Amplifier Output for Step-down Controller 1. This pin is used for loop compensation.
Edge-triggered Synchronization Input. When not synchronized, tie this pin to a voltage above
1.5V or the ground. An external clock (frequency > frequency set with ROSC) at this pin
synchronizes the controllers.
6
SYNC
7
8
9
AGND
REF
Analog Signal Ground.
The non-inverting input of the error amplifier for the step down converter 1.
Buffered output of the internal reference voltage 0.5V.
REFOUT
An external Reference voltage is applied to this pin.The non-inverting input of the error
amplifier for the step-down converter 2 is internally connected to this pin.
10
11
REFIN
COMP2
The Error Amplifier Output for Step-down Controller 2. This pin is used for loop compensation.
Inverting Input of the Error Amplifier for the Step-down Controller 2. Tie an external resistive
divider between output2 and the ground for output voltage sensing. Tie to AVCC for two-phase
single output applications
12
IN2-
The Inverting Input of the Current-sense Amplifier/Comparator for the Controller 2. Normally
tied to the output of the converter.
13
14
CS2-
CS2+
The Non-inverting Input of the Current-sense Amplifier/Comparator for the Controller 2
An external capacitor tied to this pin sets (i) the soft-start time (ii) output overload latch off time
for step-down converter 2. Pulling this pin below 0.7V shuts off the gate drivers for the second
controller. Leave open for two-phase single output applications.
15
SS2/EN2
16
17
18
19
20
AVCC
VIN2
Power Supply Voltage for the Analog Portion of the Controllers.
No connection.
No connection.
VPN2
BST2
GDH2
No connection.
PWM Output for the High-side N-channel MOSFET of Output 2.
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SC2446A
POWER MANAGEMENT
Pin Descriptions
Pin
Pin Name
Pin Function
Logic Enable gate drive signal for Output 2.
No connection.
21
22
23
24
25
26
27
GDL2
PGND
PVCC
GDL1
GDH1
BST1
VPN1
No connection.
Logic Enable gate drive signal for Output 1.
PWM Output for the High-side N-channel MOSFET of Output 1.
No connection.
No connection.
An external capacitor tied to this pin sets (i) the soft-start time (ii) output overload latch off time
for buck converter 1. Pulling this pin below 0.7V shuts off the gate drivers for the first controller.
28
SS1/EN1
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SC2446A
POWER MANAGEMENT
Block Diagram
SYNC
6
ROSC
3
COMP1
5
CLK2
CLK1
AVCC
16
FREQUENCY
DIVIDER
CLK
1.25V
REFERENCE
0.5V
OSCILLATOR
BST1
26
SLOPE COMP
SLOPE2
GDH1
25
IN1-
4
-
R
S
REF
EA1
-
+
Q
+
PWM1
8
VPN1
27
SLOPE1
CS1+
1
CS1-
2
UV
GDL1
24
+
+
+
ISEN1
Σ
-
OL1
DSBL1
Soft-Start
And
PGND
22
SS1/EN1
+
ILIIM1+
Overload
Hiccup
OCN1
-
50mV
75mV
Control 1
28
-
ILIM1-
VIN2
17
0.5 (REFOUT)
+
REFOUT
9
0.5V
+
-
PVCC
23
UVLO
4.3/4.5V
-
+
AGND
7
COMP2
11
B
A
BST2
19
SEL
1.8V
-
Y
CLK2
SEL
0.5 (REFIN)
R
+
GDH2
20
ANALOG
SWITCH
IN2-
12
REFIN
10
-
+
EA2
-
+
Q
PWM2
S
VPN2
18
SLOPE2
CS2+
14
CS2-
UV
GDL2
21
+
+
+
ISEN2
Σ
-
13
OL2
Soft-Start
And
+
DSBL2
ILIM2
I
Overload
Hiccup
OCN2
SS2/EN2
15
-
50mV
75mV
Control 2
-
ILIM2-
+
0.5 (REFIN)
Figure 3. SC2446A Block Diagram
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SC2446A
POWER MANAGEMENT
Block Diagram
OCN
IN-
-
S
R
0.5(VREFOUT
/ 0.5(VREFIN
)
)
+
OL
Q
1.8µΑ
SS/EN
0.5V/3.2V
0.8V/1.2V
DSBL
UVLO
3µΑ
Figure 4. Soft-Start and Overload Hiccup Control Circuit
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SC2446A
POWER MANAGEMENT
Application Information
SC2446A consists of two current-mode synchronous For a given output power, the sizes of the passive
buck controllers with many integrated functions. By components are inversely proportional to the switching
proper application circuitry configuration, SC2446A can frequency, whereas MOSFETs/Diodes switching losses
be used to generate
are proportional to the operating frequency. Other issues
1) two independent outputs from a common input or such as heat dissipation, packaging and the cost issues
two different inputs or
2) dual phase output with current sharing,
are also to be considered. The frequency bands for signal
transmission should be avoided because of EM
3) current sourcing/sinking from common or separate interference.
inputs as in DDR (I and II) memory application.
The application information related to the converter Minimum Switch On Time Consideration
design using SC2446A is described in the following.
In the SC2446A the falling edge of the clock turns on
Step-down Converter
the top MOSFET gate. The inductor current and the
sensed voltage ramp up. After the sensed voltage crosses
Starting from the following step-down converter a threshold determined by the error amplifier output, the
specifications,
top MOSFET gate is turned off. The propagation delay
time from the turn-on of the controlling FET to its turn-
off is the minimum switch on time. The SC2446A has a
minimum on time of about 120ns at room temperature.
This is the shortest on interval of the controlling FET. The
controller either does not turn on the top MOSFET at all
or turns it on for at least 120ns.
Input voltage range: V
Input voltage ripple (peak-to-peak): ∆Vin
Output voltage: Vo
[Vin,min ,Vin,max ]
in
Output voltage accuracy: ε
Output voltage ripple (peak-to-peak): ∆Vo
Nominal output (load) current: Io
Maximum output current limit: Io,max
Output (load) current transient slew rate: dIo (A/s)
Circuit efficiency: η
Selection criteria and design procedures for the following
are described.
1) output inductor (L) type and value,
2) output capacitor (Co) type and value,
3) input capacitor (Cin) type and value,
4) power MOSFET’s,
For a synchronous step-down converter, the operating
duty cycle is VO/VIN. So the required on time for the top
MOSFET is VO/(VINfs). If the frequency is set such that
the required pulse width is less than 120ns, then the
converter will start skipping cycles. Due to minimum on
time limitation, simultaneously operating at very high
switching frequency and very short duty cycle is not
practical. If the voltage conversion ratio VO/VIN and hence
the required duty cycle is higher, the switching frequency
can be increased to reduce the sizes of passive
components.
There will not be enough modulation headroom if the on
time is simply made equal to the minimum on time of the
SC2446A. For ease of control, we recommend the
required pulse width to be at least 1.5 times the minimum
on time.
5) current sensing and limiting circuit,
6) voltage sensing circuit,
7) loop compensation network.
Operating Frequency (fs)
The switching frequency in the SC2446A is user-
programmable. The advantages of using constant
frequency operation are simple passive component
selection and ease of feedback compensation. Before
setting the operating frequency, the following trade-offs
should be considered.
1) Passive component size
2) Circuitry efficiency
3) EMI condition
4) Minimum switch on time and
5) Maximum duty ratio
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SC2446A
POWER MANAGEMENT
Application Information (Cont.)
Setting the Switching Frequency
The followings are to be considered when choosing
inductors.
The switching frequency is set with an external resistor
connected from Pin 3 to the ground. The set frequency
is inversely proportional to the resistor value (Figure 5).
a) Inductor core material: For high efficiency applications
above 350KHz, ferrite, Kool-Mu and polypermalloy
materials should be used. Low-cost powdered iron cores
can be used for cost sensitive-applications below 350KHz
but with attendant higher core losses.
b) Select inductance value: Sometimes the calculated
inductance value is not available off-the-shelf. The
designer can choose the adjacent (larger) standard
inductance value. The inductance varies with
temperature and DC current. It is a good engineering
practice to re-evaluate the resultant current ripple at
the rated DC output current.
800
700
600
500
400
300
200
100
0
c) Current rating: The saturation current of the inductor
should be at least 1.5 times of the peak inductor current
under all conditions.
0
50
100
150
200
250
Rosc (k Ohm)
Output Capacitor (Co) and Vout Ripple
Figure 5. Free running frequency vs. ROSC
.
The output capacitor provides output current filtering in
steady state and serves as a reservoir during load
transient. The output capacitor can be modeled as an
ideal capacitor in series with its parasitic ESR (Resr) and
ESL (Lesl) (Figure 6).
Inductor (L) and Ripple Current
Both step-down controllers in the SC2446A operate in
synchronous continuous-conduction mode (CCM)
regardless of the output load. The output inductor
selection/design is based on the output DC and transient
requirements. Both output current and voltage ripples
are reduced with larger inductors but it takes longer to
change the inductor current during load transients.
Conversely smaller inductors results in lower DC copper
losses but the AC core losses (flux swing) and the winding
AC resistance losses are higher. A compromise is to
choose the inductance such that peak-to-peak inductor
ripple-current is 20% to 30% of the rated output load
current.
Co
Lesl
Resr
Figure 6. An equivalent circuit of Co.
Assuming that the inductor current ripple (peak-to-peak)
value is δ*Io, the inductance value will then be
If the current through the branch is ib(t), the voltage
across the terminals will then be
Vo (1− D)
δIofs
t
L =
.
dib(t)
dt
1
Co
vo (t) = Vo +
ib(t)dt + Lesl
+ Resrib(t).
∫
0
The peak current in the inductor becomes (1+δ/2)*Io
and the RMS current is
This basic equation illustrates the effect of ESR, ESL
and Co on the output voltage.
δ2
IL,rms = Io 1+
.
12
The first term is the DC voltage across Co at time t=0.
The second term is the voltage variation caused by the
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SC2446A
POWER MANAGEMENT
Application Information (Cont.)
The voltage rating of aluminum capacitors should be at
least 1.5Vo. The RMS current ripple rating should also be
greater than
charge balance between the load and the converter
output. The third term is voltage ripple due to ESL and
the fourth term is the voltage ripple due to ESR. The
total output voltage ripple is then a vector sum of the
last three terms.
δIo
.
2 3
Usually it is necessary to have several capacitors of the
same type in parallel to satisfy the ESR requirement. The
voltage ripple cause by the capacitor charge/discharge
should be an order of magnitude smaller than the voltage
ripple caused by the ESR. To guarantee this, the
capacitance should satisfy
Since the inductor current is a triangular waveform with
peak-to-peak value δ*Io, the ripple-voltage caused by
inductor current ripples is
δIo
∆vC ≈
,
8Cofs
the ripple-voltage due to ESL is
10
2πfsResr
Co >
.
δIo
D
∆vESL = Leslfs
,
In many applications, several low ESR ceramic capacitors
are added in parallel with the aluminum capacitors in
order to further reduce ESR and improve high frequency
decoupling. Because the values of capacitance and ESR
are usually different in ceramic and aluminum capacitors,
the following remarks are made to clarify some practical
issues.
and the ESR ripple-voltage is
∆vESR = Resr δIo.
Aluminum capacitors (e.g. electrolytic, solid OS-CON,
POSCAP, tantalum) have high capacitances and low
ESL’s. The ESR has the dominant effect on the output
ripple voltage. It is therefore very important to minimize
the ESR.
When determining the ESR value, both the steady state
ripple-voltage and the dynamic load transient need to be
considered. To keep the steady state output ripple-voltage
< ∆Vo, the ESR should satisfy
Remark 1: High frequency ceramic capacitors may not
carry most of the ripple current. It also depends on the
capacitor value. Only when the capacitor value is set
properly, the effect of ceramic capacitor low ESR starts
to be significant.
For example, if a 10µF, 4mΩ ceramic capacitor is
connected in parallel with 2x1500µF, 90mΩ electrolytic
capacitors, the ripple current in the ceramic capacitor is
only about 42% of the current in the electrolytic
capacitors at the ripple frequency. If a 100µF, 2mΩ
ceramic capacitor is used, the ripple current in the
ceramic capacitor will be about 4.2 times of that in the
electrolytic capacitors. When two 100µF, 2mΩ ceramic
capacitors are used, the current ratio increases to 8.3.
In this case most of the ripple current flows in the
ceramic decoupling capacitor. The ESR of the ceramic
capacitors will then determine the output ripple-voltage.
∆Vo
δIo
Resr1
<
.
To limit the dynamic output voltage overshoot/
undershoot within α (say 3%) of the steady state output
voltage) from no load to full load, the ESR value should
satisfy
αVo
Io
Resr2
<
.
Then, the required ESR value of the output capacitors
should be
Resr = min{Resr1,Resr2 }.
Remark 2: The total equivalent capacitance of the filter
bank is not simply the sum of all the paralleled capacitors.
The total equivalent ESR is not simply the parallel
combination of all the individual ESR’s either. Instead
they should be calculated using the following formulae.
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SC2446A
POWER MANAGEMENT
Application Information (Cont.)
2
2
(R1a + R1b )2 ω2C1a C1b + (C1a + C1b )2
Ceq(ω) :=
Req(ω) :=
2
2
(R1a C1a + R1b C1b )ω2C1aC1b + (C1a + C1b )
2
2
2
2
R1aR1b(R1a + R1b )ω2C1a C1b + (R1bC1b + R1aC1a
)
2
2
(R1a + R1b )2 ω2C1a C1b + (C1a + C1b )2
where R1a and C1a are the ESR and capacitance of
electrolytic capacitors, and R1b and C1b are the ESR and
capacitance of the ceramic capacitors respectively.
(Figure 7)
Figure 8. A simple model for the converter input
In Figure 8 the DC input voltage source has an internal
impedance Rin and the input capacitor Cin has an ESR of
Resr. MOSFET and input capacitor current waveforms, ESR
voltage ripple and input voltage ripple are shown in Figure
9.
C1a
C1b
Ceq
R1a
R1b
Req
Figure 7. Equivalent RC branch.
Req and Ceq are both functions of frequency. For rigorous
design, the equivalent ESR should be evaluated at the
ripple frequency for voltage ripple calculation when both
ceramic and electrolytic capacitors are used. If R1a = R1b
= R1 and C1a = C1b = C1, then Req and Ceq will be frequency-
independent and
Req = 1/2 R1 and Ceq = 2C1.
Input Capacitor (Cin)
The input supply to the converter usually comes from a
pre-regulator. Since the input supply is not ideal, input
capacitors are needed to filter the current pulses at the
switching frequency. A simple buck converter is shown in
Figure 8.
Figure 9. Typical waveforms at converter input.
It can be seen that the current in the input capacitor
pulses with high di/dt. Capacitors with low ESL should be
used. It is also important to place the input capacitor
close to the MOSFETs on the PC board to reduce trace
inductances around the pulse current loop.
The RMS value of the capacitor current is approximately
δ2
ICin = Io D[(1+ )(1− )2 +
D
D
(1−D)].
η2
12
η
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SC2446A
POWER MANAGEMENT
Application Information (Cont.)
The power dissipated in the input capacitors is then
Let the duty ratio and output current of Channel 1 and
Channel 2 be D1, D2 and Io1, Io2, respectively.
2
PCin = ICin Resr.
If D1<0.5 and D2<0.5, then
For reliable operation, the maximum power dissipation
in the capacitors should not result in more than 10oC of
temperature rise. Many manufacturers specify the
maximum allowable ripple current (ARMS) rating of the
capacitor at a given ripple frequency and ambient
temperature. The input capacitance should be high
enough to handle the ripple current. For higher power
applications, multiple capacitors are placed in parallel to
increase the ripple current handling capability.
2
2
ICin ≈ D1Io1 + D2Io2
.
Choosing Power MOSFETs
The power devices with integrated gate drivers such as
PIP212, R2J20601NP, PIP202, PIP201 and IP2001,
IP2002 are suitable for SC2446A application.
Sometimes meeting tight input voltage ripple
specifications may require the use of larger input
capacitance. At full load, the peak-to-peak input voltage
ripple due to the ESR is
Current Sensing
Inductor current sensing is required for the current-mode
control. Although the inductor current can be sensed with
a precision resistor in series with the inductor, the lossless
inductive current sense technique is used in the
SC2446A. This technique has the advantages of
δ
∆vESR = Resr (1+ )Io.
2
The peak-to-peak input voltage ripple due to the capacitor
is
DIo
Cinfs
1) lossless current sensing,
2) lower cost compared to resistive sense
3) more accurate compared to the RDS(ON) sense
∆vC
≈
,
From these two expressions, CIN can be found to meet
the input voltage ripple specification. In a multi-phase
converter, channel interleaving can be used to reduce
ripple. The two step-down channels of the SC2446A
operate at 180 degrees from each other. If both step-
down channels in the SC2446A are connected in parallel,
both the input and the output RMS currents will be
reduced.
The basic arrangement of the inductive current sense is
shown in Figure 10.
Where, RL is the equivalent series resistance of the output
inductor. The added Rs and Cs form a RC branch for
inductor current sensing.
Vin
Ripple cancellation effect of interleaving allows the use
of smaller input capacitors. When converter outputs are
connected in parallel and interleaved, smaller inductors
and capacitors can be used for each channel. The total
output ripple-voltage remains unchanged. Smaller
inductors speeds up output load transient.
Q1
iL(t)
L
RL
Cs
Cin
Rs
Vo
Q2
Cout
Rload
vC(t)
When two channels with a common input are interleaved,
the total DC input current is simply the sum of the
individual DC input currents. The combined input current
waveform depends on duty ratio and the output current
waveform. Assuming that the output current ripple is
small, the following formula can be used to estimate the
RMS value of the ripple current in the input capacitor.
Figure 10. The basic structure of inductive current
sense.
In steady state, the DC value,
VCS = RL IO
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SC2446A
POWER MANAGEMENT
Application Information (Cont.)
when the load is sourcing current from the converter and
It is noted that the DC value of VCs is independent of the
value of L, Rs and Cs. This means that, if only the average
load current information is needed (such as in average
current mode control), this current sensing method is
effective without time constant matching requirement.
In the current mode control as implemented in SC2446A,
the voltage ripple on Cs is critical for PWM operation. In
fact, the AC voltage ripple peak-to-peak value of VCs
(denoted as ∆VCs) directly effects the signal-to-noise ratio
of the PWM operation. In general, smaller ∆VCs leads to
lower signal-to-noise ratio and more noise sensitive
operation. Larger ∆VCs leads to more circuit (power stage)
parameter sensitive operation. A good engineering
compromise is to make
75mV
RL
ILMcn = −
,
when the load is forcing current back to the input power
source. If RL = 1.8mΩ, then ILM = 27.8 / -41.7A. The circuit
in Figure 11 allows the user to scale the equivalent
current limit with the same RL.
In the following design steps, the capacitor CS in the
current sensing part is commonly selected in the range
of 22nF ~ 100nF.
∆VCs~ RL δIo.
Vin
The pre-requisite for such relation is the so called time
constant matching condition
Q1
Vgs1
iL(t)
L
RL
Rs1
PN
Cin
L
Rs
≈ RsCs.
RL
Vo
Q2
Cs
Cout
Rload
Vgs2
vC(t)
For an example of application circuit, L = 1µH,
RL = 1.8mΩ, the time constant RsCs should be set as
555.6µs. If one selects Cs = 33nF, then Rs = 16.9 kΩ.
Scaling the Current Limit
1
2
+
-
Rs2
ISEN
Rs3
Over-current is handled differently in the SC2446A
depending on the direction of the inductor current. If the
differential sense voltage between CS+ and CS- exceeds
+50mV, the top MOSFET will be turned off and the bottom
MOSFET will be turned on to limit the inductor current.
This +50mV is the cycle-by-cycle peak current limit when
the load is drawing current from the converter. There is
no cycle-by-cycle current limit when the inductor current
flows in the reverse direction. If the voltage between
CS1+ and CS- falls below -75mV, the controller will
undergo overload shutdown and time-out with both the
top and the bottom MOSFETs shut off. (See the section
Overload Protection and Hiccup).
Figure 11. Scaling the equivalent current limit.
a) When the required current limit value ILM is greater
than ILMcp, one just needs to remove Rs3, and solve the
following equations
L
RL
(Rs //Rs1) Cs =
,
Rs1
ILMR
= 50mV,
L Rs + Rs1
In the circuit of Figure 11, the equivalent inductor current
limits are set according to
and
for
Rs2 = Rs //Rs1 .
50mV
RL
ILMcp
=
,
Rs,Rs1 and Rs2.
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15
SC2446A
POWER MANAGEMENT
Application Information (Cont.)
Note that RS2 is selected as RS//RS1 in order to reduce
the bias current effect of the current amplifier in
SC2446A.
a) The time taken to discharge the capacitor from 3.2V
to 0.5V
(3.2 − 0.5)V
tssf = C32
.
b) When the required current limit ILM is less than ILMcp
,
1.2µA
one just needs to remove Rs1 and solve
If C32 = 0.1µF, tssf is calculated as 225ms.
b) The soft start time from 0.5V to 3.2V
L
RL
RsCs =
,
(3.2 − 0.5)V
tssr = C32
.
1.8µA
Rs
Rs3
ILMRL +
VO = 50mV,
When C32 = 0.1µF, tssr is calculated as 150ms. Note that
during soft start, the converter only starts switching when
the voltage at SS/EN exceeds 1.2V.
for Rs and RS3.
c) The effective start-up time is
Rs2 is then obtained from
Rs3Rs
.
(3.2 −1.2)V
Rs2
=
tsso = C32
.
Rs3 − Rs
1.8µA
Similar steps and equations apply to the current limit
setting and scaling for current sinking mode.
The average inductor current is then
tsso
tssf + tssr
ILeff = ILMcp
.
Overload Protection and Hiccup
During start-up, the capacitor from the SS/EN pin to
ground functions as a soft-start capacitor. After the
converter starts and enters regulation, the same
capacitor operates as an overload shutoff timing
capacitor. As the load current increases, the cycle-by-
cycle current-limit comparator will first limit the inductor
current. Further increase in loading will cause the output
voltage (hence the feedback voltage) to fall. If the
feedback voltage falls to less than (50% for Ch1, 50%
for Ch2) of the reference voltage, the controller will shut
off both the top and the bottom MOSFETs. Meanwhile
an internal net 1.2µA current source discharges the soft-
start capacitor C32(C33) connected to the SS/EN pin.
ILeff ≈ 0.30 ILMcp and is independent of the soft start
capacitor value. The converter will not overheat in hiccup.
Setting the Output Voltage
The non-inverting input of the channel-one error amplifier
is internally tied the 0.5V voltage reference output (Pin
8). The non-inverting input of the channel-two error
amplifier is brought out as a device pin (Pin 10) to which
the user can connect Pin 8 or an external voltage
reference. A simple voltage divider (Ro1 at top and Ro2 at
bottom) sets the converter output voltage. The voltage
feedback gain h=0.5/Vo is related to the divider resistors
value as
When the capacitor is discharged to 0.5V, a 1.8µA current
source recharges the SS/EN capacitor and converter
restarts. If overload persists, the controller will shut down
the converter when the soft start capacitor voltage
exceeds 3.2V. The converter will repeatedly start and shut
off until it is no longer overloaded. This hiccup mode of
overload protection is a form of foldback current limiting.
The following calculations estimate the average inductor
current when the converter output is shorted to the
ground.
h
1− h
Ro2
=
Ro1.
Once either Ro1 or Ro2 is chosen, the other can be
calculated for the desired output voltage Vo. Since the
number of standard resistance values is limited, the
calculated resistance may not be available as a standard
value resistor. As a result, there will be a set error in the
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SC2446A
POWER MANAGEMENT
Application Information (Cont.)
converter output voltage. This non-random error is
caused by the feedback voltage divider ratio. It cannot
be corrected by the feedback loop.
The inner current-loop is unstable (sub-harmonic
oscillation) unless the inductor current up-slope is steeper
than the inductor current down-slope. For stable
operation above 50% duty-cycle, a compensation ramp
is added to the sensed-current. In the SC2446A the
compensation ramp is made duty-ratio dependent. The
compensation ramp is approximately
The following table lists a few standard resistor
combinations for realizing some commonly used output
voltages.
Iramp = De1.76D * 30µA.
Vo (V)
(1-h)/h
0.6
0.2
0.9
0.8
1.2
1.4
1.5
2
1.8
2.6
2.5
4
3.3
5.6
The slope of the compensation ramp is then
Se = (1+1.76D)e1.76Dfs * 30µA.
Ro1 (Ohm) 200 806 1.4K 2K
Ro2 (Ohm) 1K 1K 1K 1K
2.61K 4.02K 5.62K
1K 1K 1K
The slope of the internal compensation ramp is well above
the minimal slope requirement for current loop stability
and is sufficient for all the applications.
With the inner current loop stable, the output voltage is
then regulated with the outer voltage feedback loop. A
simplified equivalent circuit model of the synchronous
Buck converter with current mode control is shown in
Figure 12.
Only the voltages in boldface can be precisely set with
standard 1% resistors.
From this table, one may also observe that when the
value
Vo − 0.5
0.5
1− h
h
=
and its multiples fall into the standard resistor value
chart (1%, 5% or so), it is possible to use standard value
resistors to exactly set up the required output voltage
value.
The input bias current of the error amplifier also causes
an error in setting the output voltage. The maximum
inverting input bias currents of error amplifiers 1 and 2
is -250nA. Since the non-inverting input is biased to 0.5V,
the percentage error in the second output voltage will be
k
–100% · (0.25µA) · R
R
/[0.5 · (R +R ) ]. To keep
< 4kΩ.
o1 o2
o1 o2
this error below 0.2%, R
o2
Loop Compensation
SC2446A uses current-mode control for both step-down
channels. Current-mode control is a dual-loop control
system in which the inductor peak current is loosely
controlled by the inner current-loop. The higher gain outer
loop regulates the output voltage. Since the current loop
makes the inductor appear as a current source, the
complex high-Q poles of the output LC networks is split
into a dominant pole determined by the output capacitor
and the load resistance and a high frequency pole. This
pole-splitting property of current-mode control greatly
simplifies loop compensation.
Figure 12. A simple model of synchronous buck converter
with current mode control.
The transconductance error amplifier (in the SC2446A)
has a gain gm of 260µA/V. The target of the compensation
design is to select the compensation network consisting
of C2, C3 and R2, along with the feedback resistors Ro1,
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SC2446A
POWER MANAGEMENT
Application Information (Cont.)
The loop transfer function is then
T(s)=Gvc(s)C(s).
Ro2 and the current sensing gain, such that the converter
output voltage is regulated with satisfactory dynamic
performance.
With the output voltage Vo known, the feedback gain h
and the feedback resistor values are determined using
the equations given in the “Output Voltage Setting”
section with
To simplify design, we assume that C3<<C2, Roesr<<Ro,
selects Sp1=Sz2 and specifies the loop crossover
frequency fc. It is noted that the crossover frequency
determines the converter dynamic bandwidth. With these
assumptions, the controller parameters are determined
as following.
0.5
Vo
h =
.
For the rated output current Io, the current sensing gain
k is first estimated as
gmhkRo
2πfc
C2 =
,
Io
2.1
k =
.
RoCo
C2
R2 =
,
From the transfer function from the voltage error
amplifier output vc to the converter output vo is
and
Roesr
R2
C
C3 =
o K,
s
1+
Vo (s)
Vc (s)
sz1
s
:= Gvc (s) = kRo
.
with a constant K.
For example, if Vo=2.5V, Io=15A, fs=300kHz, Co=1.68mF,
1+
sp1
Roesr=4.67mΩ, one can calculate that
where, the single dominant pole is
1
sp1
=
,
Vo
Io
(Ro + Roesr )Co
Ro =
= 167mΩ,
and the zero due to the output capacitor ESR is
0.5
Vo
h =
= 0.2,
1
sz1
=
.
RoesrCo
and
The dominant pole moves as output load varies.
The controller transfer function (from the converter
output vo to the voltage error amplifier output vc) is
Io
2.1
k =
= 7.14.
If the converter crossover frequency is set around 1/10
of the switching frequency, fc = 30kHz, the controller
parameters then can be calculated as
s
1+
gmh
s(C2 + C3 )
sz2
s
C(s) =
,
1+
gmhkRo
sp2
C2 =
≈ 0.328nF.
2πfc
where
and
1
where, gm is the error amplifier transconductance gain
(260 µΩ−1).
sz2
=
,
R2C2
If we use C2 = 0.33 nF,
1
sp2
=
.
RoCo
C2C3
R2 =
≈ 848.5kΩ,
R
2 C2 + C3
C2
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SC2446A
POWER MANAGEMENT
Application Information (Cont.)
use R2 = 770kΩ.
With K = 1, it is further calculated that
It is clear that the resulted crossover frequency is about
27.1 kHz with phase margin 91o.
Roesr
R2
C
o K ≈ 10.2pF,
It is noted that the current sensing gain k was first
estimated using the DC value in order to quickly get the
compensation parameter value. When the circuit is
operational and stable, one can further improve the
compensation parameter value using AC current sensing
gain. One simple and practical method is to effectively
measure the output current at two points, e.g. Io1 and Io2
and the corresponding error amplifier output voltage Vc1
and Vc2. Then, the first order AC gain is
C3 =
use C3 = 10pF. The Bode plot of the loop transfer function
(magnitude and phase) is shown in Figure 13
100
69.241
∆Io
Io1 −Io2
=
50
k =
∆Vc Vc1 − Vc2
20⋅log G (f) C(f)
(
)
vc
0
With this k value, one can further calculate the improved
compensator parameter value using the previous
equations.
− 20.73
50
3
4
5
6
.
.
.
.
10
10
100
1 10
1 10
1 10
1 10
For example, if one measured that Io1=1A, Io2=15A and
Vc1=2.139V, Vc2=2.457V. k is then calculated as 44.
Substituting this parameter to the equations before, one
can derive that
5
f
3×10
88
89
90
91
92
93
C2 ≈ 2.024nF. Select C2 = 2.2nF.
R2 ≈ 127.3kΩ. Select R2 = 127kΩ.
C3 ≈ 61.78pF. Select C3 = 47pF
88.78
−
In some initial prototypes, if the circuit noise makes the
control loop jittering, it is suggested to use a bigger C3
value than the calculated one here. Effectively, the
converter bandwidth is reduced in order to reject some
high frequency noises. In the final working circuit, the
loop transfer function should be measured using network
analyzer and compared with the design to ensure circuit
stability under different line and load conditions. The load
transient response behavior is further tested and
measured to meet the specification.
180
⋅
π
argG (f) C(f)
⋅
(
)
vc
92.702
−
3
4
5
6
.
.
.
.
10
10
100
1 10
1 10
1 10
1 10
×
5
f
3 10
Figure 13. The loop transfer function Bode plot of the
example.
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19
SC2446A
POWER MANAGEMENT
Application Information (Cont.)
PC Board Layout Issues
Circuit board layout is very important for the proper
operation of high frequency switching power converters.
A power ground plane is required to reduce ground
bounces. The followings are suggested for proper layout.
Power Stage
1) Separate the power ground from the signal ground. In
SC2446A, the power ground PGND should be tied to the
source terminal of lower MOSFETs. The signal ground
AGND should be tied to the negative terminal of the
output capacitor.
2) Minimize the size of high pulse current loop. Keep the
top MOSFET, bottom MOSFET and the input capacitors
within a small area with short and wide traces. In addition
to the aluminum energy storage capacitors, add multi-
layer ceramic (MLC) capacitors from the input to the
power ground to improve high frequency bypass.
Control Section
3) The frequency-setting resistor Rosc should be placed
close to Pin 3. Trace length from this resistor to the analog
ground should be minimized.
4) Solder the bias decoupling capacitor right across the
AVCC and analog ground AGND.
5) Place the Combi-sense components away from the
power circuit and close to the corresponding CS+ and
CS- pins. Use X7R type ceramic capacitor for the Combi-
sense capacitor because of their temperature stability.
6) Use an isolated local ground plane for the controller
and tie it to the negative side of output capacitor bank.
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SC2446A
POWER MANAGEMENT
Typical Application Schematic
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21
SC2446A
POWER MANAGEMENT
Typical Characteristics
S C2446A + P IP 212 Du al P hase E fficien cy
V in=12V , D ual O utp ut, F sw =500KH z, Tam b =25°C , 0LF M
1
0.98
0.96
0.94
0.92
0.9
Channel 1: Vo1 = 2.5V
Channel 2: Vo2 = 1.2V
0.88
0.86
0.84
0.82
0.8
2. 5V Ef ficiency
1. 2V Ef ficiency
0.78
0.76
0.74
0.72
0.7
2
4
6
8
10
12
14
15
16
18
20
AMP S
D ual P hase Th erm als
V in=12V , D ual O utp ut, F sw =500KH z, Tam b =25°C , 0LF M
7 0
6 0
5 0
4 0
2. 5V t herm als
1. 2V t herm als
2. 5V t herm als
1. 2V t herm als
3 0
2 0
1 0
0
0
2
4
6
8
1 0
1 2
1 4
1 6
1 8
2 0
A M P S
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SC2446A
POWER MANAGEMENT
Typical Characteristics (Cont.)
Ch1 (2.5V) Output voltage ripple = 14.0mV p-p
Ch2 (1.2V) Output voltage ripple = 15.6mV p-p
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SC2446A
POWER MANAGEMENT
Typical Characteristics (Cont.)
Ch1 (2.5V) Full load start-up
Vin = 12V
Io1
Vout1 = 2.5V
Ch1 (2.5V) Shutdown
Vin = 12V
Vout1 = 2.5V
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SC2446A
POWER MANAGEMENT
Typical Characteristics (Cont.)
Ch2 (1.2V) Full load start-up
Vin = 12V
Io2
Vout2 = 1.2V
Ch2 (1.2V) Shutdown
Vin = 12V
Vout2 = 1.2V
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2005 Semtech Corp.
25
SC2446A
POWER MANAGEMENT
Typical Characteristics (Cont.)
Vin = 12V, Dual output, Fsw = 500KHz, Tamb = 25° C, 0LFM 2.5V Output short and release.
VO2
VO1
IO1
Vin = 12V, Dual output, Fsw = 500KHz, Tamb = 25° C, 0LFM 1.2V Output short and release.
VO1
VO2
IO2
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2005 Semtech Corp.
26
SC2446A
POWER MANAGEMENT
Outline Drawing - TSSOP-28
DIMENSIONS
INCHES MILLIMETERS
A
DIM
A
D
E
e
MIN NOM MAX MIN NOM MAX
N
-
-
-
-
-
-
-
-
-
-
-
-
.047
1.20
0.15
1.05
0.30
0.20
A1 .002
A2 .031
.006 0.05
.042 0.80
.012 0.19
.007 0.09
2X E/2
b
c
D
.007
.003
E1
.378 .382 .386 9.60 9.70 9.80
PIN 1
E1 .169 .173 .177 4.30 4.40 4.50
INDICATOR
E
e
.252 BSC
.026 BSC
6.40 BSC
0.65 BSC
L
L1
N
.018 .024 .030 0.45 0.60 0.75
ccc C
2X N/2 TIPS
1 2 3
(.039)
28
-
(1.0)
28
-
e/2
01
aaa
0°
8°
0°
8°
B
.004
.004
.008
0.10
0.10
0.20
bbb
ccc
D
aaa C
A2
A
SEATING
PLANE
C
H
A1
A-B D
bxN
bbb
C
c
GAGE
PLANE
0.25
L
(L1)
01
DETAIL A
SEE DETAIL A
SIDE VIEW
NOTES:
1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H-
3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS
OR GATE BURRS.
4. REFERENCE JEDEC STD MO-153, VARIATION AE.
Land Pattern - TSSOP-28
X
DIMENSIONS
DIM
INCHES
(.222)
.161
MILLIMETERS
(5.65)
4.10
0.65
0.40
1.55
7.20
C
G
P
X
Y
Z
(C)
G
Y
Z
.026
.016
.061
.283
P
NOTES:
1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
Contact Information
Semtech Corporation
Power Management Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805)498-2111 FAX (805)498-3804
www.semtech.com
2005 Semtech Corp.
27
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