SC2602LSTRT [SEMTECH]
Synchronous Voltage Mode Controller for Distributed Power Supply; 同步电压模式控制器的分布式电源
| 型号： | SC2602LSTRT |
| 厂家： | 
SEMTECH CORPORATION |
| 描述： | Synchronous Voltage Mode Controller for Distributed Power Supply |
| 文件： | 总14页 (文件大小：463K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SC2602L
Synchronous Voltage Mode Controller
for Distributed Power Supply
POWER MANAGEMENT
Description
Features
The SC2602L is low-cost, full featured, synchronous volt-
age-mode controller designed for use in single ended
power supply applications where efficiency is of primary
concern. Synchronous operation allows for the elimina-
tion of heat sinks in many applications. The SC2602L is
ideal for implementing DC/DC converters needed to
power advanced microprocessors in low cost systems,
or in distributed power applications where efficiency is
important. Internal level-shift, high-side drive circuitry, and
preset shoot-through control, allows the use of inexpen-
sive N-channel power MOSFETs.
Synchronous operation for high efficiency (95%)
RDS(ON) current sensing
Output voltage can be programmed as low as 0.8V
On-chip power good and OVP functions
Small size with minimum external components
Soft Start
Enable function
SO-14 package is fully WEEE and RoHS compliant
Applications
Microprocessor core supply
Low cost synchronous applications
Voltage Regulator Modules (VRM)
DDR termination supplies
Networking power supplies
Sequenced power supplies
SC2602L features include temperature compensated
voltage reference, triangle wave oscillator and current
sense comparator circuitry. Power good signaling, shut-
down, and over voltage protection are also provided.
The SC2602L operates at a fixed 200kHz which is for
optimum compromise between efficiency, external com-
ponent size, and cost.
Two SC2602L can be used together to sequence two
voltage regulators for power up in telecom systems. The
power good of the first SC2602L connected to the en-
able of the second SC2602L makes this possible.
Typical Application Circuit
V_pullup
5V IN
R1
R2
R3
C1
+
C3
C2
U1
GND
C4
C5
C6
1
14
13
12
11
10
9
SS/SHDN
VCC
GND
2
3
4
5
6
7
PWRGD SS/SHDN
PWRGD
OVP
OVP
COMP
SENSE
BSTH
R4
R5
C7
OCSET
PHASE
DH
Q1
Q2
L1
12V IN
BSTL
C8
2.5VOUT
D1
8
R6
R7
PGND
DL
SC2602L
+
C10
C9
GND
R8
Figure 1. Typical distributed power supply
Revision: January 05, 2006
1
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SC2602L
POWER MANAGEMENT
Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified
in the Electrical Characteristics section is not implied. Exposure to Absolute Maximum rated conditions for extended periods of time may affect device
reliability.
Parameter
Symbol
Maximum
Units
VCC, BST L to GND
VIN
-1.0 to 16 (20V Surge)
V
V
PGND to GND
± 0.5
PHASE to GND(1)
-0.5 to 18 (20V Surge)
V
BST H to PHASE
16 (20V Surge)
V
T hermal Resistance Junction to Case
T hermal Resistance Junction to Ambient
Operating T emperature Range
Maximum Junction T emperature
Storage T emperature Range
Lead T emperature (Soldering) 10 Sec.
45
115
°C/W
°C/W
°C
θJC
θJA
TA
-40 to +85
125
TJ
°C
TST G
TLEAD
ESD
-65 to +150
300
°C
°C
ESD Rating (Human Body Model)
2
kV
Note: (1) -1.5V to 20V for 25ns repetitive every cycle.
Electrical Characteristics
Unless specified: VCC = 4.75V to 12.6V; GND = PGND = 0V; VBSTL = 12V; VBSTH-PHASE = 12V; TJ = 25oC
Parameter
Conditions
Min
Typ
Max
Units
Power Supply
Supply Voltage
Supply Current
VCC
4.2
12.6
10
V
mA
%
EN = VCC
VO = 2.5V
6
Line Regulation
Error Amplifier
Transconductance
Gain (AOL)
0.5
G
1.8
50
5
mS
dB
µA
m
Input Bias
8
Oscillator
Oscillator Frequency
Oscillator Max Duty Cycle
Internal Ramp Peak to Peak
MOSFET Drivers
DH Source/Sink
200
95
1
kHz
%
90
V
BST H - DH = 4.5V,
DH - PHASE = 2V
1
1
A
DL Source/Sink
BST L - DL = 4.5V.
DL - PGND. = 2V
A
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SC2602L
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Unless specified: VCC = 4.75V to 12.6V; GND = PGND = 0V; VBSTL = 12V; VBSTH-PHASE = 12V; TJ = 25oC
Parameter
Conditions
Min
Typ
Max
Units
PROTECTION
OVP T hreshold Voltage
OVP Source Current
Power Good T hreshold
Dead T ime
20
%
mA
%
V
OVP = 3V
10
88
112
100
220
45
nS
µA
Over Current Set (Isink)
Reference
2.0V < VOCSET < 12V
180
200
0.8
O
O
Reference Voltage
Soft Start
0 C to 70 C
0.792
8.0
0.808
12
V
Charge Current
VSS = 1.5V
VSS = 1.5V
10
µA
µA
Discharge Current
Power Good
1.5
Sink Current Capability
Shut Down
Sink 1mA
0.4
V
V
Shut Down T hreshold
0.6
Note:
(1) Specification refers to application circuit (Figure 1).
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SC2602L
POWER MANAGEMENT
Pin Configuration
Ordering Information
Device(2)
Frequency
Package(1)
Top View
SC2602LST RT
SC2602LEVB
200kHz
SO-14
VCC
GND
SS / SHDN
COMP
SENSE
BSTH
Evaluation Board
PWRGD
OVP
Notes:
(1) Only available in tape and reel packaging. A reel contains
OCSET
PHASE
DH
2500 devices.
(2) Lead free product. This product is fully WEEE and RoHS
compliant.
BSTL
PGND
DL
(14-Pin SOIC)
Pin Descriptions
Pin #
Pin Name
Pin Function
1
VCC
Chip supply voltage.
2
PWRGD
OVP
Open collector output. Logic high indicates correct ouput voltage.
Over voltage protection output. Source at least 10mA when Vsense > 1.2 * VBG.
Set the converter over current trip point.
Input from the phase node between the MOSFET s.
High side driver output.
3
4
OCSET
PHASE
DH
5
6
7
PGND
DL
Power ground.
8
Low side driver output.
9
BST L
Bootstrap, low side driver.
10
11
12
13
14
BST H
Bootstrap, high side driver.
SENSE
COMP
SS/SHDN
GND
Voltage sense input.
Compensation pin.
Gate Drive return Ground for the 1.5V GMCH regulator. Connect to Source of bottom FET .
Signal ground.
Note:
(1) All logic level inputs and outputs are open collector TTL compatible.
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SC2602L
POWER MANAGEMENT
Block Diagram
VCC
200uA
Vbg
Over Current
+10%
-10%
Under
Voltage
OCSET
PWRGD
0.8V
+20%
VCC
One Shot
Oscillator
OVP
Error Amp
SENSE
PWM
Vbg
BSTH
DH
DRVH
COMP
S
Cross
Current
Control
VCC
0.8V
PHASE
R
QB
10uA
SS/SHDN
Fault
BSTL
DL
GND
1.5uA
DRVL
0.6V
PGND
Theory of Operation
Synchronous Buck Converter
The output rail is regulated by a synchronous, voltage- As SENSE increases, the output voltage of the error
mode pulse width modulated (PWM) controller. This amplifier decreases. This causes a reduction in the on-
section has all the features required to build a high effi- time of the high-side MOSFET connected to DH, hence
ciency synchronous buck converter, including “Power lowering the output voltage.
Good” flag, shut-down, and cycle-by-cycle current limit.
Under Voltage Lockout
The output voltage of the synchronous converter is set The under voltage lockout circuit of the SC2602L as-
and controlled by the output of the error amplifier. The sures that the high-side MOSFET driver outputs remain
external resistive divider reference voltage is derived from in the off state whenever the supply voltage drops below
an internal trimmed-bandgap voltage reference (See Fig. set parameters. Lockout occurs if VCC falls below 4.1V.
1). The inverting input of the error amplifier receives its Normal operation resumes once VCC rises above 4.2V.
voltage from the SENSE pin.
Over-Voltage Protection
The internal oscillator uses an on-chip capacitor and The over-voltage protection pin (OVP) is high only when
trimmed precision current sources to set the oscillation the voltage at SENSE is 20% higher than the target value
frequency to 200kHz. The triangular output of the oscil- programmed by the external resistor divider. The OVP
lator sets the reference voltage at the inverting input of pin is internally connected to a PNP’s collector.
the comparator. The non-inverting input of the compara-
tor receives it’s input voltage from the error amplifier. Power Good
When the oscillator output voltage drops below the er- The power good function is to confirm that the regulator
ror amplifier output voltage, the comparator output goes outputs are within +/-10% of the programmed level.
high. This pulls DL low, turning off the low-side FET, and PWRGD remains high as long as this condition is met.
DH is pulled high, turning on the high-side FET (once PWRGD is connected to an internal open collector NPN
the cross-current control allows it). When the oscillator transistor.
voltage rises back above the error amplifier output volt-
age, the comparator output goes low. This pulls DH low,
turning off the high-side FET, and DL is pulled high, turn-
ing on the low-side FET (once the cross-current control
allows it).
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SC2602L
POWER MANAGEMENT
Applications Information (Cont.)
Soft Start
Initially, SS/SHDN sources 10µA of current to charge an
external capacitor. The outputs of the error amplifiers
are clamped to a voltage proportional to the voltage on
SS/SHDN. This limits the on-time of the high-side
MOSFETs, thus leading to a controlled ramp-up of the
output voltages.
An over-current condition occurs when the high-side drive
is turned on, but the PHASE node does not reach the
voltage level set at the OCSET pin. The PHASE node is
sampled only once per cycle during the valley of the tri-
angular oscillator. Once an over-current occurs, the high-
side drive is turned off and the low-side drive turns on
and the SS/SHDN pin begins to sink 1.5µA. The soft-
start voltage will begin to decrease as the 1.5µA of cur-
rent discharges the external capacitor. When the soft-
start voltage reaches 0.8V, the SS/SHDN pin will begin
to source 10µA and begin to charge the external capaci-
tor causing the soft-start voltage to rise again. Again,
when the soft-start voltage reaches the level of the in-
ternal oscillator, switching will occur.
RDS(ON) Current Limiting
The current limit threshold is set by connecting an ex-
ternal resistor from the VCC supply to OCSET. The volt-
age drop across this resistor is due to the 200µA inter-
nal sink sets the voltage at the pin. This voltage is com-
pared to the voltage at the PHASE node. This compari-
son is made only when the high-side drive is high to
avoid false current limit triggering due to uncontributing
measurements from the MOSFETs off-voltage. When
the voltage at PHASE is less than the voltage at OCSET,
an overcurrent condition occurs and the soft start cycle
is initiated. The synchronous switch turns off and SS/
SHDN starts to sink 1.5µA. When SS/SHDN reaches
0.8V, it then starts to source 10µA and a new cycle be-
gins.
If the over-current condition is no longer present, nor-
mal operation will continue. If the over-current condition
is still present, the SS/SHDN pin will again begin to sink
1.5µA. This cycle will continue indefinitely until the over-
current condition is removed.
In conclusion, below is shown a typical “12V Application
Circuit” which has a BSTH voltage derived by
bootstrapping input voltage to the PHASE node through
diode D1. This circuit is very useful in cases where only
input power of 12V is available.
Hiccup Mode
During power up, the SS/SHDN pin is internally pulled
low until VCC reaches the undervoltage lockout level of
4.2V. Once V has reached 4.2V, the SS/SHDN pin is
released and CbCegins to source 10µA of current to the
external soft-start capacitor. As the soft-start voltage
rises, the output of the internal error amplifier is clamped
to this voltage. When the error signal reaches the level
of the internal triangular oscillator, which swings from
1V to 2V at a fixed frequency of 200kHz, switching oc-
curs. As the error signal crosses over the oscillator sig-
nal, the duty cycle of the PWM signal continues to in-
crease until the output comes into regulation. If an over-
current condition has not occurred the soft-start voltage
will continue to rise and level off at about 2.2V.
In order to prevent substrate glitching, a small-signal di-
ode should be placed in close proximity to the chip with
cathode connected to PHASE and anode connected to
PGND.
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SC2602L
POWER MANAGEMENT
Application Circuit
Typical 12V Application Circuit with Bootstrapped BSTH
+5V
12V IN
GND
R2
C1
R3
C2
10
R1
5K
1.74K
0.1u
C4
+
C3
1.0u
D1
1N1418
10u
C5
C6
C7
U1
0.1u
0.1u
1.0u
1
2
3
4
5
6
7
14
13
12
11
10
9
PWRGD
SS/SHDN
VCC
GND
C8 1.0u
PWRGD SS/SHDN
R5
C9
OVP
COMP
SENSE
BSTH
R4 1K
9.6K
36n
OCSET
PHASE
DH
Q1
Q2
OVP
L1 4uH
BSTL
D2
1N4148
3.3VOUT
8
R6
R7
PGND
DL
C11
10u
+ C10
SC2602L
GND
R8
2.2
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SC2602L
POWER MANAGEMENT
Typical Characteristics
Output Ripple Voltage
Ch1: Vo_rpl
Gate Drive Waveforms
Ch1: Top FET
Ch2: Bottom FET
1. VIN = 5V; VO = 3.3V; IOUT = 12A
PIN Descriptions
Ch1: Vo_rpl
2. VIN = 5V; VOUT = 1.3V; IOUT = 12A
Ch1: oT p FET
Ch2: Bottom FET
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SC2602L
POWER MANAGEMENT
Typical Characteristics (Cont.)
Ch1: Vo_rpl
2. VIN = 5V; VOUT = 1.3V; IOUT = 12A
Ch1: Top FET
Ch2: Bottom FET
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SC2602L
POWER MANAGEMENT
Typical Characteristics (Cont.)
Hiccup Mode
Ch1: Vin
Ch2: Vss
Ch3: Top Gate
Ch4: Vout
Vin = 5V
Vout = 3.3V
Vbst = 12V
Iout = S.C.
Start Up Mode
Ch1: Vin
Ch2: Vss
Ch3: Top Gate
Ch4: Vout
Vin = 5V
Vout = 3.3V
Iout = 2A
Vbst = 12V
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SC2602L
POWER MANAGEMENT
The task here is to properly choose the compensation
network for a nicely shaped loop-gain Bode plot. The
following design procedures are recommended to ac-
complish the goal:
Gpwm
L
EA
R1
R2
R
Rc
Co
(1) Calculate the corner frequency of the output filter:
Vbg
Vin
Ro
C
0.8Vdc
1
F :=
o
2⋅π⋅ L⋅C
o
Fig. 2. SC2602L small signal model.
(2) Calculate the ESR zero frequency of the output filter
capacitor:
The control model of SC2602L control loop small signal
can be depicted in Fig. 2. This model can also be used in
SPICE kind of simulator to generate loop gain Bode plots.
The bandgap reference is 0.8V and trimmed to +/-1%
accuracy. The desired output voltage can be achieved
by setting the resistive divider network, R1 and R2.
1
F
:=
esr
2⋅π⋅R ⋅C
c
o
(3) Check that the ESR zero frequency is not too high.
F
sw
5
F
<
esr
The error amplifier is transconductance type with fixed
gain of:
If this condition is not met, the compensation structure
may not provide loop stability. The solution is to add
some electrolytic capacitors to the output capacitor bank
to correct the output filter corner frequency and the ESR
zero frequency. In some cases, the filter inductance
may also need to be adjusted to shift the filter corner
frequency. It is not recommended to use only high fre-
quency multi-layer ceramic capacitors for output filter.
1.8.mA
G
m
V
The compensation network includes a resistor and a
capacitor in series, which terminates from the output of
the error amplifier to the ground.
(4) Choose the loop gain cross over frequency (0 dB
frequency). It is recommended that the crossover fre-
quency is always less than one fifth of the switching
frequency :
This device uses voltage mode control with input volt-
age feed forward. The peak-to-peak ramp voltage is
proportional to the input voltage, which results in an ex-
cellent performance to reject input voltage variation. The
PWM gain is inversion of the ramp amplitude, and this
gain is given by:
F
sw
F
≤
x_over
5
1
G
If the transient specification is not stringent, it is better to
choose a crossover frequency that is less than one tenth
of the switching frequency for good noise immunity. The
resistor in the compensation network can then be cal-
culated as:
pwm
V
ramp
where the ramp amplitude (peak-to-peak) is 1.0 volts
when input voltage is 12 volts.
The total control loop-gain can then be derived as
follows:
2
F
F
V
1
esr x_over o
R :=
⋅
⋅
⋅
G
⋅V ⋅G
pwm in
F
F
esr
V
m
o
bg
.
s. R C
c o
1
1
s. R. C
s. R. C
.
.
T(s) T
o
R
R
L
c
2.
.
.
1
s. R C
s L. C
1
c
o
o
when
R
o
o
F
< F
< F
esr x_over
o
V
bg
T
:= G ⋅G
⋅V ⋅R⋅
pwm in
o
m
V
o
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SC2602L
POWER MANAGEMENT
Step 1. Output filter corner frequency
Applications Information (Cont.)
or
F
= 2.516 KHz
o
2
F
F
V
1
o x_over o
Step 2. ESR zero frequency:
R :=
⋅
⋅
⋅
G
⋅V ⋅G
pwm in
F
F
V
esr
bg
m
o
F
= 7.958 KHz
esr
when
Step 3. Check the following condition:
F
< F < F
o x_over
esr
(5) The compensation capacitor is determined by choos-
ing the compensator zero to be about one fifth of the
output filter corner frequency:
F
sw
5
F
<
esr
Which is satisfied in this case.
F
o
F
zero
5
Step 4. Choose crossover frequency and calculate
compensator R:
1
C
2 . . R . F
π
F
20 KHz
x_over =
zero
(6) The final step is to generate the Bode plot, either by
using the simulation model in Fig. 2 or using the equa-
tions provided here with Mathcad. The phase margin
can then be checked using the Bode plot. Usually, this
design procedure ensures a healthy phase margin.
(7) An additional capacitor should be reserved at the
compensation pin to ground to have another high fre-
quency pole.
R
=
4.8 K
Ω
Step 5. Calculate the compensator C:
C
= 65.886 nF
Step 6. Generate Bode plot and check the phase mar-
gin. In this case, the phase margin is about 85oC that
ensures the loop stability.
An example is given below to demonstrate the proce-
dure introduced above. The parameters of the power
supply are given as :
The parameters of the power supply are given as :
V
V
I
12.V
3.3.V
12.A
in
o
o
F
200.KHz
sw
L
C
4.
µH
.
1200µF
o
.
0.02 Ω
R
V
V
c
0.8.V
1.V
bg
ramp
1.8.mA
V
G
m
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SC2602L
POWER MANAGEMENT
Applications Information (Cont.)
Loop Gain Mag (dB)
100
50
mag( i)
0
50
3
.
1 10
0.01
0.1
1
10
100
F
i
kHz
Loop Gain Phase (Degree)
0
45
phase( i)
90
135
180
3
.
1 10
0.01
0.1
1
10
100
F
i
kHz
Bode plot of the control loop
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SC2602L
POWER MANAGEMENT
Outline Drawing - S0-14
DIMENSIONS
INCHES MILLIMETERS
MIN NOM MAX MIN NOM MAX
A
DIM
A
D
E
e
-
-
-
-
-
-
-
-
-
-
.053
.069 1.35
.010 0.10
.065 1.25
.020 0.31
.010 0.17
1.75
0.25
1.65
0.51
0.25
N
A1 .004
A2 .049
2X
E/2
b
c
D
.012
.007
.337 .341 .344 8.55 8.65 8.75
E1 .150 .154 .157 3.80 3.90 4.00
E1
E
e
h
L
.236 BSC
6.00 BSC
1.27 BSC
.050 BSC
-
-
.010
.020 0.25
0.50
1
2
3
ccc C
.016 .028 .041 0.40 0.72 1.04
B
(.041)
14
-
.004
.010
.008
(1.04)
14
-
0.10
0.25
0.20
L1
N
01
aaa
bbb
ccc
2X N/2 TIPS
0°
8°
0°
8°
D
aaa
C
h
A2 A
SEATING
PLANE
h
C
A1
A-B D
H
bxN
bbb
C
c
GAGE
PLANE
0.25
L
01
(L1)
SEE DETAIL A
DETAIL A
SIDE VIEW
NOTES:
1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE
-H-
3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS
OR GATE BURRS.
4. REFERENCE JEDEC STD MS-012, VARIATION AB.
Land Pattern - S0-14
X
DIMENSIONS
DIM
INCHES
(.205)
.118
.050
.024
MILLIMETERS
(5.20)
3.00
1.27
0.60
2.20
7.40
C
G
P
X
Y
Z
(C)
G
Y
Z
.087
.291
P
NOTES:
1. THIS LAND PATERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
2. REFERENCE IPC-SM-782A, RLP NO. 302A.
Contact Information
Semtech Corporation
Power Management Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805)498-2111 FAX (805)498-3804
www.semtech.com
2005 Semtech Corp.
14
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