SC4605IMSTRT [SEMTECH]
Low Input, High Efficiency Synchronous, Step Down Controller; 低投入，高效率同步降压控制器
| 型号： | SC4605IMSTRT |
| 厂家： | 
SEMTECH CORPORATION |
| 描述： | Low Input, High Efficiency Synchronous, Step Down Controller |
| 文件： | 总19页 (文件大小：423K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SC4605
Low Input, High Efficiency
Synchronous, Step Down Controller
POWER MANAGEMENT
Description
Features
BICMOS voltage mode PWM controller
2.8V to 5.5V Input voltage range
Output voltages as low as 0.8V
+/-1% Reference accuracy
Sleep mode (Icc = 10µA typ)
Lossless adjustable short circuit current limiting
Combination pulse by pulse & hiccup mode
current limit
The SC4605 is a voltage mode step down (buck) regula-
tor controller that provides accurate high efficiency power
conversion from a input supply range of 2.8V to 5.5V. A
high level of integration reduces external component
count, and makes it suitable for low voltage applications
where cost, size and efficiency are critical.
The SC4605 drives external N-channel MOSFETs with 1A
peak current. A non-overlap protection is provided for
the gate drive signals to prevent shoot through of the
MOSFET pair. The voltage drop across the high side
MOSFET during its conduction is sensed for lossless short
circuit current limiting.
High efficiency synchronous switching
0% to 97% Duty cycle range
1A Peak current driver
10-Pin MSOP package
The quiescent supply current in sleep mode is typically Applications
lower than 10µA. A 1.8ms soft start is internally provided
to prevent output voltage overshoot during start-up.
Distributed power architecture
Servers/workstations
Local microprocessor core power supplies
DSP and I/O power supplies
Battery powered applications
Telecommunications equipment
Data processing applications
The SC4605 is an ideal choice for 3.3V, 5V or other low
input supply systems. It’s available in 10 pin MSOP pack-
age.
Typical Application Circuit
Vin = 2.8V - 5.5V
C10
C11
D2
C12
1u
C71
22u
22u
220u
M1
M2
C14
0.1u
R13
1
R3
U1
1
2
3
4
5
10
9
BST
DRVH
PHASE
DRVL
L1
C3
4.7u
Vout = 1.5V (as low as 0.8V * ) / 12A
VCC
ISET
COMP
1.8u
8
7
C6
C5
C4
GND
C9
4.7n
C20
2.2n
6
C2
22u
C1
330u
22u
R7
FS/SYNC
VSENSE
10k
470pF
180p
R8
SC4605
200
R1
14.3k
R9
11.5k
* External components can be modified to provide a Vout as low as 0.8V.
Revision: October 14, 2004
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SC4605
POWER MANAGEMENT
Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified
in the Electrical Characteristics section is not implied.
Parameter
Symbol
Maximum
Units
Supply Voltage (VCC)
7
V
A
Output Drivers (DRVH, DRVL) Currents
+/-0.25
Continuous
Peak
+/-1.00
A
Inputs (VSENSE, COMP, FS/SYNC, ISET)
PHASE
-0.3 to 7
-0.3 to 5.5
-2 to 7
V
V
PHASE Pulse tpulse < 100ns
Operating Ambient Temperature Range
Storage Temperature Range
Junction Temperature Range
Lead Temperature (Soldering) 10 Sec.
V
TA
TSTG
TJ
-40 to +85
-65 to +150
-55 to +150
+300
°C
°C
°C
°C
TLEAD
All voltages with respect to GND. Currents are positive into, negative out of the specified terminal.
Electrical Characteristics
Unless otherwise specified, VCC = 5V, CT = 470pF, TA = -40°C to 85°C, TA = TJ.
Parameter
Test Conditions
Min
Typ
Max
Unit
Overall
Supply Voltage
2.8
5.5
15
3
V
Supply Current, Sleep
Supply Current, Bias
VCC Turn-on Threshold
VCC Turn-off Hysteresis
Error Amplifier
FS/SYNC = 0V
VCC = 5.5V
10
1
µA
mA
V
2.7
125
2.8
mV
Input Voltage
TA = 25°C
0.792
0.8
0.808
(Internal Reference)
V
VCC = 2.8V ~ 5.5V, TA = 25°C
Temperature
0.788
0.786
0.8
0.812
0.814
0.8
VSENSE Bias Current
Open Loop Gain (1)
Unity Gain Bandwidth (1)
Slew Rate (1)
25
nA
dB
VCOMP = 0.5 to 2.5V
80
4
2
MHz
V/µs
V
VOUT High
ICOMP = -2mA
VCC - 0.5
VCC - 0.2
0.1
VOUT Low
ICOMP = 2mA
0.25
V
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SC4605
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Unless otherwise specified, VCC = 5V, CT = 470pF, TA = -40°C to 85°C, TA = TJ.
Parameter
Test Conditions
Min
Typ
Max
Unit
Oscillator
Initial Accuracy
TA = 25°C
255
300
100
600
1.5
345
kHz
kHz
kHz
V
Minimum Operation Frequency (1)
Maximum Operation Frequency (1)
Ramp Peak to Valley (1)
Ramp Peak Voltage (1)
Ramp Valley Voltage (1)
Sleep, Soft Start, Current Limit
Sleep Threshold
2.0
V
0.5
V
Measured at FS
TJ = 25°C
0.2
-57
V
Soft Start Time (1)
1.8
-50
150
ms
µA
ns
ISET Bias Current
-43
0
Current Limit Blank Time (1)
Gate Drive
Duty Cycle
97
3
%
Ω
Peak Source (DRVH) (2)
Peak Sink (DRVH) (2)
Peak Source (DRVL) (2)
Peak Sink (DRVL) (2)
Output Rise Time (2)
Output Fall Time (2)
Vgs = 5V, ISOURCE = 100mA
Vgs = 5V, ISINK = 100mA
Vgs = 5V, ISOURCE = 100mA
Vgs = 5V, ISINK = 100mA
Vgs = 5V, COUT = 4.7nF
Vgs = 5V, COUT = 4.7nF
3
Ω
3
Ω
3
Ω
35
35
40
ns
ns
ns
(1)
Minimum Non-Overlap
30
Notes:
(1). Guaranteed by design.
(2). Guaranteed by characterization.
(3) This device is ESD sensitive. Use of standard ESD handling precautions is required.
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SC4605
POWER MANAGEMENT
Pin Configuration
Ordering Information
Part Number (1)
SC4605IMSTR
SC4605IMSTRT(2)
Notes:
(1) Only available in tape and reel packaging. A reel
contains 2500 devices.
(2) Lead free product. This product is fully WEEE and
RoHS compliant.
Device
MSOP-10
TOP VIEW
BST
VCC
ISET
1
2
3
4
5
10
9
8
7
6
DRVH
PHASE
DRVL
GND
VSENSE
COMP
FS/SYNC
(MSOP-10)
Pin Descriptions
VCC: Positive supply rail for the IC. Bypass this pin to ISET / PHASE: PHASE is connected to the junction be-
GND with a 0.1 to 4.7µF low ESL/ESR ceramic capaci- tween the two external power MOSFET transistors. The
tor.
voltage drop across the high side MOSFET during its con-
duction is compared with the voltage drop generated by
GND: All voltages are measured with respect to this pin. the internal 50µA current source and the external cur-
All bypass and timing capacitors connected to GND should rent limit resistor connected between PHASE and Vin,
have leads as short and direct as possible.
and forms the current limit comparator and logic sets
the PWM latch and terminates the output pulse. If the
FS/SYNC: A capacitor from FS pin to GND sets the PWM converter output voltage drops below 68.75% of its nomi-
oscillator frequency. Use a high quality ceramic capacitor nal voltage, the controller stops switching and goes
with low ESL and ESR for best result. A minimum capaci- through a soft start sequence. This prevents excess
tor value of 200pF ensures good accuracy and less sus- power dissipation in the low side MOSFET during a short
ceptibility to circuit layout parasitics. When the FS is pulled circuit. The current limit threshold is set by the external
and held below 0.2V, its sleep mode operation is invoked. resistor between VCC and ISET.
The Sleepmode supply current is 10µA typical. The oscil-
lator and PWM are designed to provide practical opera- BST: This pin connects the external charge pump, and
tion up to 600kHz. In synchronous mode operation, a powers the high side MOSFET gate drive.
low value resistor has to be connected between ground
and the timing capacitor. An external clock is then feed DRVH, DRVL: The output drivers are rated for 1A peak
into the resistor capacitor junction to override the inter- currents. The PWM circuitry provides complementary drive
nal clock.
signals to the output stages. The cross conduction of
the external MOSFETs is prevented by monitoring the
VSENSE: This pin is the inverting input of the voltage voltage on the driver pins of the MOSFET pair in conjunc-
amplifier and serves as the output voltage feedback point tion with a time delay optimized for FET turn-off charac-
for the Buck converter. It senses the output voltage through teristics.
an external divider.
COMP: This is the output of the voltage amplifier. The
voltage at this output is inverted internally and connected
to the non-inverting input of the PWM comparator. A lead-
lag network around the voltage amplifier compensates for
the two pole LC filter characteristic inherent to voltage mode
control and is required in order to optimize the dynamic
performance of the voltage mode control loop.
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SC4605
POWER MANAGEMENT
Block Diagram
Marking Information
yyww = Datecode (Example: 0012)
xxxx = Semtech Lot # (Example: E901
xxxx
01-1)
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SC4605
POWER MANAGEMENT
Applications Information
Enable
Soft Start
Pulling and holding the FS/SYNC pin below 0.2V initial-
izes the SLEEP mode of the SC4605 with its typical SLEEP
mode supply current of 10µA. During the SLEEP mode,
the high side and low side MOSFETs are turned off and
the internal soft start voltage is held low.
The soft start function is required for step down control-
lers to prevent excess inrush current through the DC bus
during start up. Generally this can be done by sourcing a
controlled current into a timing capacitor and then using
the voltage across this capacitor to slowly ramp up the
error amp reference. The closed loop creates narrow
width driver pulses while the output voltage is low and
allows these pulses to increase to their steady state duty
cycle as the output voltage reaches its regulated value.
With this, the inrush current from the input side is con-
trolled. The duration of the soft start in the SC4605 is
controlled by an internal timing circuit which is used dur-
ing start up and over current to set the hiccup time. The
soft start time can be calculated by:
Oscillator
The oscillator uses an external capacitor between FS and
GND to set the oscillation frequency. The ramp wave-
form is a triangle at the PWM frequency with a peak volt-
age of 2V and a valley voltage of 0.5V. The PWM duty
ratio is limited to a maximum of 97%, which allows the
bootstrap capacitor to be charged during each cycle. The
capacitor tolerance adds to the accuracy of the oscilla-
tor frequency. The approximate operating frequency is
determined by the external capacitor connected to the
FS/SYNC pin as shown below:
720
=
TSOFT _START
fs
As can be seen here, the soft start time is switching fre-
quency dependant. For example, if fs = 300kHz,
TSOFT_START = 720/300k = 2.4ms. But if fs = 600kHz,
TSOFT_START = 720/600k = 1.2ms.
−4
1.55 10
fs =
CT
In its synchronous mode, a low value resistor needs to
be connected between ground and the frequency set-
ting capacitor, CT. Then an external clock connects to
the junction of the resistor and the capacitor to activate
its synchronous mode. The frequency of the clock can
be used up to 700kHz. This external clock signal should
have a duty cycle from 5% to 10% and the peak voltage
at the junction from the clock signal should be about
0.2V.
The SC4605 implements its soft start by ramping up the
error amplifier reference voltage providing a controlled
slew rate of the output voltage, then preventing over-
shoot and limiting inrush current during its start up.
Over Current Protection
Over current protection for the SC4605 is implemented
by detecting the voltage drop of the high side N-MOSFET
during its conduction, also known as high side RDS(ON)
detection. This loss-less detection eliminates the sense
resistor and its loss. The overall efficiency is improved
and the number of components and cost of the con-
verter are reduced. RDS(ON) sensing is by default inac-
curate and is mainly used to protect the power supply
during a fault case. The over current trigger point will
vary from unit to unit as the RDS(ON) of N-MOSFET var-
ies. Even for the same unit, the over current trigger point
will vary as the junction temperature of N-MOSFET var-
ies. The SC4605 provides a built-in 50µA current source,
which is combined with RSET (connected between VCC
and ISET) to determine the current limit threshold. The
value of RSET can be properly selected according to the
desired current limit point IMAX and the internal 50µA
pull down current available on the ISET pin based on the
following expression:
UVLO
When the FS/SYNC pin is not pulled and held below 0.2V,
the voltage on the Vcc pin determines the operation of
the SC4605. As Vcc increases during start up, the UVLO
block senses Vcc and keeps the high side and low side
MOSFETs off and the internal soft start voltage low until
Vcc reaches 2.8V. If no faults are present, the SC4605
will initiate a soft start when Vcc exceeds 2.8V. A hyster-
esis (150mV) in the UVLO comparator provides noise
immunity during its start up.
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SC4605
POWER MANAGEMENT
Applications Information (Cont.)
Power MOSFET Drivers
IMAX RDS(ON)
The SC4605 has two drivers for external power N-
MOSFETs. The driver block consists of one high side N-
MOSFET, 1A driver, DRVH, and one low side 1A, N-MOSFET
driver, DRVL, which are optimized for driving external
power MOSFETs in a synchronous buck converter. The
output drivers also have gate drive non-overlap mecha-
nism that gives a dead time between DRVH and DRVL
transitions to avoid potential shoot through problems in
the external MOSFETs. By using the proper design and
the appropriate MOSFETs, a 12A converter can be
achieved. As shown in Figure 2, td1, the delay from the
top MOSFET off to the bottom MOSFET on is adaptive by
detecting the voltage of the phase node. td2, the delay
from the bottom MOSFET off to the top MOSFET on is
fixed, is 50ns for the SC4605. This control scheme guar-
antees avoiding the cross conduction or shoot through
between two MOSFETs and minimizes the conduction loss
in the bottom diode for high efficiency applications.
RSET
=
50µA
Kelvin sensing connections should be used at the drain
and source of N-MOSFET. R needs to be adjusted if
the input of the application changes significantly, say from
3.3V to 5V for the same load and same output voltage.
A 0.1µA ceramic capacitor paralled to this resistor should
be used to decouple the noise.
SET
The RDS(ON) sensing used in the SC4605 has an addi-
tional feature that enhances the performance of the over
current protection. Because the RDS(ON) has a positive
temperature coefficient, the 50µA current source has a
positive coefficient of about 0.17%/C° providing first order
correction for current sensing vs temperature. This com-
pensation depends on the high amount of thermal trans-
ferring that typically exists between the high side N-
MOSFET and the SC4605 due to the compact layout of
the power supply.
TOP MOSFET Gate Drive
When the converter detects an over current condition (I
> IMAX) as shown in Figure 1, the first action the SC4605
takes is to enter the cycle by cycle protection mode (Point
B to Point C), which responds to minor over current cases.
Then the output voltage is monitored. If the over current
and low output voltage (set at 68.75% of nominal out-
put voltage) occur at the same time, the Hiccup mode
operation (Point C to Point D) of the SC4605 is invoked
and the internal soft start capacitor is discharged. This is
like a typical soft start cycle.
BOTTOM MOSFET Gate Drive
Ground
Phase node
td2
td1
Figure 2. Timing Waveforms for Gate Drives and Phase
Node
Inductor Selection
The factors for selecting the inductor include its cost,
efficiency, size and EMI. For a typical SC4605 applica-
tion, the inductor selection is mainly based on its value,
saturation current and DC resistance. Increasing the in-
ductor value will decrease the ripple level of the output
voltage while the output transient response will be de-
graded. Low value inductors offer small size and fast tran-
sient responses while they cause large ripple currents,
poor efficiencies and more output capacitance to smooth
out the large ripple currents. The inductor should be able
to handle the peak current without saturating and its
copper resistance in the winding should be as low as
possible to minimize its resistive power loss. A good trade-
off among its size, loss and cost is to set the inductor
ripple current to be within 15% to 30% of the maximum
output current.
A
B
VO−nom
0.6875⋅VO−nom
0.125⋅VO−nom
C
D
VO
IMAX
IO
Figure 1. Over current protection characteristic of
SC4605
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SC4605
POWER MANAGEMENT
Applications Information (Cont.)
the additional current needed by the load. The ESR and
ESL of the output capacitor, the loop parasitic inductance
between the output capacitor and the load combined
with inductor ripple current are all major contributors to
the output voltage ripple. Surface mount speciality poly-
mer aluminum electrolytic chip capacitors in UE series
from Panasonic provide low ESR and reduce the total
capacitance required for a fast transient response.
POSCAP from Sanyo is a solid electrolytic chip capacitor
that has a low ESR and good performance for high fre-
quency with a low profile and high capacitance. Above
mentioned capacitors are recommended to use in
SC4605 applications.
The inductor value can be determined according to its
operating point and the switching frequency as follows:
VO (V − VO )
I
L =
V fs ∆I IOMAX
I
Where:
fs = switching frequency and
DI = ratio of the peak to peak inductor current to the
maximum output load current.
The peak to peak inductor current is:
IP−P = ∆I• IOMAX
Boost Capacitor Selection
After the required inductor value is selected, the proper
selection of the core material is based on the peak in-
ductor current and efficiency requirements. The core
must be able to handle the peak inductor current IPEAK
without saturation and produce low core loss during the
high frequency operation.
The boost capacitor selection is based on its discharge
ripple voltage, worst case condition time and boost cur-
rent. The worst case conduction time T can be estimated
W
as follows:
1
fs
Tw =
Dmax
Ip−p
IPEAK = IOMAX
+
2
Where:
The power loss for the inductor includes its core loss and
copper loss. If possible, the winding resistance should
be minimized to reduce inductor’s copper loss. The core
loss can be found in the manufacturer’s datasheet. The
inductor’ copper loss can be estimated as follows:
f = the switching frequency and
Dmax = maximum duty ratio, 0.97 for the SC4605.
S
The required minimum capacitance for boost capacitor
will be:
PCOPPER = I2
RWINDING
LRMS
IB
VD
Cboost
=
TW
Where:
Where:
ILRMS is the RMS current in the inductor. This current
can be calculated as follows:
I = the boost current and
V = discharge ripple voltage
B
D
1
3
ILRMS = IOMAX 1+
∆I2
With f = 300kH, V = 0.3V and I = 50mA, the required
D
B
capacSitance for the boost capacitor is:
IB
VD fs
1
0.05
0.3 300k
1
Output Capacitor Selection
Cboost
=
Dmax
=
0.97 = 540nF
Basically there are two major factors to consider in se-
lecting the type and quantity of the output capacitors.
The first one is the required ESR (Equivalent Series Re-
sistance) which should be low enough to reduce the volt-
age deviation from its nominal one during its load changes.
The second one is the required capacitance, which should
be high enough to hold up the output voltage. Before the
SC4605 regulates the inductor current to a new value
during a load transient, the output capacitor delivers all
Input Capacitor Selection
The input capacitor selection is based on its ripple cur-
rent level, required capacitance and voltage rating. This
capacitor must be able to provide the ripple current by
the switching actions. For the continuous conduction
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SC4605
POWER MANAGEMENT
Applications Information (Cont.)
ITOP _PEAK V fs
I
PTOP _TOTAL = I2
RTOP_ON
+
mode, the RMS value of the input capacitor can be cal-
culated from:
TOP _RMS
V
GATE RG
(QGD + QGS2 ) + QGT VGATE fs + (QOSS + Qrr ) V fs
VO (V − VO )
I
I
ICIN
= IOMAX
(RMS)
V2
I
Where:
This current gives the capacitor’s power loss as follows:
RG = gate drive resistor,
QGD = the gate to drain charge of the top MOSFET,
QGS2 = the gate to source charge of the top MOSFET,
QGT = the total gate charge of the top MOSFET,
QOSS = the output charge of the top MOSFET and
Qrr = the reverse recovery charge of the bottom diode.
PCIN = I2
RCIN(ESR)
CIN(RMS)
This capacitor’s RMS loss can be a significant part of the
total loss in the converter and reduce the overall con-
verter efficiency. The input ripple voltage mainly depends
on the input capacitor’s ESR and its capacitance for a
given load, input voltage and output voltage. Assuming
that the input current of the converter is constant, the
required input capacitance for a given voltage ripple can
be calculated by:
For the top MOSFET, it experiences high current and high
voltage overlap during each on/off transition. But for the
bottom MOSFET, its switching voltage is the bottom
diode’s forward drop during its on/off transition. So the
switching loss for the bottom MOSFET is negligible. Its
total power loss can be determined by:
D (1−D)
fs (∆V −IOMAX RCIN
PBOT _TOTAL = I2
RBOT _ON + QGB VGATE fs +ID _AVG VF
BOT _RMS
CIN = IOMAX
)
I
(ESR)
Where:
D = VO/VI , duty ratio and
DVI = the given input voltage ripple.
Where:
QGB = the total gate charge of the bottom MOSFET and
VF = the forward voltage drop of the bottom diode.
Because the input capacitor is exposed to the large surge
current, attention is needed for the input capacitor. If
tantalum capacitors are used at the input side of the
converter, one needs to ensure that the RMS and surge
ratings are not exceeded. For generic tantalum capaci-
tors, it is wise to derate their voltage ratings at a ratio of
2 to protect these input capacitors.
For a low voltage and high output current application such
as the 3.3V/1.5V@12A case, the conduction loss is of-
ten dominant and selecting low RDS(ON) MOSFETs will
noticeably improve the efficiency of the converter even
though they give higher switching losses.
The gate charge loss portion of the top/bottom MOSFET’s
total power loss is derived from the SC4605. This gate
charge loss is based on certain operating conditions (fs,
VGATE, and IO).
Power Mosfet Selection
The SC4605 can drive an N-MOSFET at the high side
and an N-MOSFET synchronous rectifier at the low side.
The use of the high side N-MOSFET will significantly re-
duce its conduction loss for high current. For the top
MOSFET, its total power loss includes its conduction loss,
switching loss, gate charge loss, output capacitance loss
and the loss related to the reverse recovery of the bot-
tom diode, shown as follows:
The thermal estimations have to be done for both
MOSFETs to make sure that their junction temperatures
do not exceed their thermal ratings according to their
total power losses PTOTAL, ambient temperature Ta and
their thermal resistance Rθja as follows:
PTOTAL
Tj(max) < Ta +
Rθja
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SC4605
POWER MANAGEMENT
Applications Information (Cont.)
Loop Compensation Design
Where:
For a DC/DC converter, it is usually required that the
converter has a loop gain of a high cross-over frequency
for fast load response, high DC and low frequency gain
for low steady state error, and enough phase margin for
its operating stability. Often one can not have all these
properties at the same time. The purpose of the loop
compensation is to arrange the poles and zeros of the
compensation network to meet the requirements for a
specific application.
R = load resistance and
RC = C4’s ESR.
The compensation network will have the characteristic
as follows:
s
ωZ1
s
s
ωZ2
s
1+
1+
1+
1+
ωI
GCOMP (s) =
s
ωP1
ωP2
The SC4605 has an internal error amplifier and requires
the compensation network to connect among the COMP
pin and VSENSE pin, GND, and the output as shown in
Figure 3. The compensation network includes C1, C2,
R1, R7, R8 and C9. R9 is used to program the output
voltage according to:
Where;
1
ωI =
R7 (C1 + C2 )
1
ωZ1
=
R1 C2
R7
R9
VO = 0.8 (1+
)
1
ωZ2
=
(R7 + R8 ) C9
C1 + C2
=
SC4605
1
2
3
4
10
9
BST
DRVH
ωP1
L1
+VO
R1 C1 C2
VCC
PHASE
DRVL
8
ISET
7
C9
COMP
FSET
GND
C4
1
ωP2 =
5
6
C2
C1
VSENSE
R8 C9
R7
After the compensation, the converter will have the
following loop gain:
R8
R1
R9
T(s) = GPWM GCOMP (s) GVD (s) =
s
1+
1
VM
s
ωZ1
s
s
ωZ2
s
1
ωI V 1+
1+
1+
Figure 3. Compensation network provides 3
poles and 2 zeros.
I
RC C4
1+ s + s2LC
L
R
s
1+
ωP1
ωP2
For voltage mode step down applications as shown in
Figure 3, the power stage transfer function is:
Where:
GPWM = PWM gain
VM = 1.5V, ramp peak to valley voltage of SC4605
s
1
1+
RC C4
GVD (s) = V
I
L1
1+ s + s2L1C4
R
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SC4605
POWER MANAGEMENT
Layout Guideline
Applications Information (Cont.)
The design guidelines for the SC4605 applications are
as following:
In order to achieve optimal electrical, thermal and noise
performance for high frequency converters, special at-
tention must be paid to the PCB layouts. The goal of lay-
out optimization is to identify the high di/dt loops and
minimize them. The following guideline should be used to
ensure proper functions of the converters.
1. A ground plane is recommended to minimize noises
and copper losses, and maximize heat dissipation.
2. Start the PCB layout by placing the power compo-
nents first. Arrange the power circuit to achieve a
clean power flow route. Put all the connections on
one side of the PCB with wide copper filled areas if
possible.
1. Set the loop gain crossover corner frequency ωC for
given switching corner frequency ωS =2πfs,
2. Place an integrator at the origin to increase DC and
low frequency gains,
3. Select ωZ1 and ωZ2 such that they are placed near
ωO to damp the peaking and the loop gain has a
-20dB/dec rate to go across the 0dB line for
obtaining a wide bandwidth,
4. Cancel the zero from C4’s ESR by a compensator
pole ωP1 ( ωP1 = ωESR = 1/( RCC4)),
5. Place a high frequency compensator pole
ωp2 ( ωp2 = πfs) to get the maximum attenuation of
the switching
3. The Vcc bypass capacitor should be placed next to
the Vcc and GND pins.
4. The trace connecting the feedback resistors to the
output should be short, direct and far away from the
noise sources such as switching node and switching
components.
ripple and high frequency noise with the adequate
phase lag at ωC.
5. Minimize the traces between DRVH/DRVL and the
gates of the MOSFETs to reduce their impedance to
drive the MOSFETs.
The compensated loop gain will be as given in Figure 4:
6. Minimize the loop including input capacitors, top/bot-
tom MOSFETs. This loop passes high di/dt current.
Make sure the trace width is wide enough to reduce
copper losses in this loop.
7. ISET and PHASE connections to the top MOSFET for
current sensing must use Kelvin connections.
8. Maximize the trace width of the loop connecting the
inductor, bottom MOSFET and the output capacitors.
9. Connect the ground of the feedback divider and the
compensation components directly to the GND pin
of the SC4605 by using a separate ground trace.
Then connect this pin to the ground of the output
capacitor as close as possible.
T
ωZ1
Loop gain T(s)
o
ω
ωZ2
-20dB/dec
Gvd
0dB
c
ω
ω
p1
ω
p2
Power stage GVD(s)
ωESR
-40dB/dec
Figure 4. Asymptotic diagrams of power stage and its
loop gain
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SC4605
POWER MANAGEMENT
Applications Information (Cont.)
Design Example 1: 3.3V to 1.5V @ 12A application with SC4605 (NH020 footprint)
GND
1
2
3
4
5
6
+VIN
C10
D2
C12
22u
1u
C71
330u
ON/OFF
M1
M2
R13
1
C14
0.1u
R6
1.0
R3
J1
U1
2.26k
1
2
3
4
5
10
9
BST
DRVH
PHASE
DRVL
L1
1
2
3
4
5
C3
4.7u
+VOUT
VCC
1.8u
8
ISET
COMP
FSET
7
C6
C7
C5
C4
22u
GND
C9
4.7n
C20
470pF
R12
100
2.2n
6
C2
C1
150u
150u
22u
R7
J2
VSENSE
R5
1.0
10k
180p
R8
SC4605
200
R1
R10
14.3k
TRIM
100
R9
R11
100
11.5k
ON/OFF
Figure 5. Schematic for 3.3V/1.5V@12A with SC4605 application
Design Example 2: 5V to 1.5V @ 12A application with SC4605 (NH020 footprint)
GND
1
2
3
4
5
6
+VIN
C10
D2
C12
22u
1u
C71
330u
ON/OFF
M1
M2
R13
1
C14
0.1u
R6
1.0
R3
J1
U1
2.8k
1
2
3
4
5
10
9
BST
DRVH
PHASE
DRVL
L1
1
C3
4.7u
+VOUT
2
3
4
5
VCC
1.8u
8
ISET
COMP
FSET
7
C6
150u
C7
C5
C4
GND
C9
4.7n
C20
470pF
R12
100
2.2n
6
C2
C1
150u
22u
22u
R7
J2
VSENSE
R5
1.0
10k
180p
R8
SC4605
200
R1
R10
100
14.3k
TRIM
R9
11.5k
R11
100
ON/OFF
Figure 6. Schematic for 5V/1.5V@12A with SC4605 application
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POWER MANAGEMENT
Applications Information (Cont.)
Design Example 3: 3.3V to 1.5V @ 15A application with SC4605 and its typical efficiency characteristics.
U3
Vin=3.3V
1
2
3
4
8
7
6
5
Vin
Vin
Vin
Vin
C10
C11
C13
22u
C14
22u
C12
22u
GND
GND
GND
GND
330u
330u
D2
1u
J8
C17
C18
0.1u
R13
1
R3
2.43k
M12
M11
U1
R6
1
1
2
3
4
5
10
9
BST
DRVH
PHASE
DRVL
U2
HC2-2R2
C3
4.7u
Vout=1.5V 15A
1
12
11
10
9
VCC
ISET
COMP
FSET
Vout
Vout
Vout
GND
GND
GND
Vout
Vout
Vout
GND
GND
GND
2
3
4
5
6
2.2u
R5
8
1
C5
22u
7
C7
C4
8
C9
M21
M22
GND
7
C16
470pF
470u
2.2n
6
22u
C2
C1
R7
5.62k
8.2n
VSENSE
J12
270p
R8
115
SC4605
R1
4 x Si7882
15.8k
R9
6.49k
Figure 7. Schematic for 3.3V/1.5V @ 15A with SC4605 application
Efficiency vs Load current
0.93
0.92
0.91
0.9
Vin=3.3V
0.89
0.88
Vo=1.5V
3
6
9
12
15
Load current (A)
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SC4605
POWER MANAGEMENT
Applications Information (Cont.)
Design Example 4: 5V to 3.3V @ 5A application with SC4605 and its typical efficiency characteristics.
GND
1
2
3
4
5
2
x Si7882
VIN=5V
C10
22u
C12
22u
D2
1u
C71
ON/OFF
6
C14
0.1u
M1
R13
1
R6
1.0
R3
2.87k
J1
U1
1
2
3
4
5
10
9
BST
DRVH
PHASE
DRVL
ETQ P6F2R5
1
2
3
4
5
C3
4.7u
VO UT=3.3V/5A
VCC
2.5u
8
ISET
COMP
FSET
C9
7
C6
C7
150u
C5
C4
GND
C20
R12
100
2.2n
6
C2
C1
150u
M2
22u
22u
R7
4.7k
J2
10n
R8
97.6
VSENSE
R5
1.0
470pF
220p
SC4605
R1
R10
100
14.3k
TRIM
R9
1.5k
R11
100
ON/OFF
Figure 8. Schematic for 5V/3.3V@ 5A with SC4605 application
Efficiency vs Load current
0.98
0.97
0.96
0.95
0.94
0.93
0.92
0.91
0.9
Vin=5V
Vo=3.3V
1
2
3
4
5
Load current (A)
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SC4605
POWER MANAGEMENT
Bill of Materials - 3.3V to 1.5V @ 12A
Item
Qty
1
Reference
Value
Part No./Manufacturer
1
2
C1
180pF
2.2nF
1
C2
3
4
1
1
3
2
1
1
1
1
1
C3
4.7uF, 0805
1uF
C71
5
C4, C5, C12
C6, C7
C9
22uF, 1210
150uF, 2870
4.7nF
TDK P/N: C3225X5R0J226M
Sanyo P/N: 4TPB150ML
6
7
8
C10
330uF, 2870
0.1uF
Sanyo P/N: 6TPB330ML
9
C14
10
11
C20
470pF
D2
MBR0520LT1, SOD-123
ON Semiconductor
Panasonic. P/N:
ETQP6F1R8BFR
14
1
L1
Inductor, 1.8uF
15
16
17
18
19
20
21
22
23
24
2
1
1
2
1
1
1
3
1
1
M1, M2
Powerpack, SO-8
Vishay P/N: Si7858DP
R1
14.3k
2.32k
1.0
R3
R5, R6
R7
10k
R8
200
R9
11.5k
100
R10, R11, R12
R13
U1
1
SC4605
Semtech P/N: SC4605IMSTR
Unless specified, all resistors have 1% precision with 0603 package.
Capacitors will have 20% percision with 0603 package.
For R9, there are 3 kinds of values for different output cases.
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SC4605
POWER MANAGEMENT
PCB Layout - 3.3V to 1.5V @ 12A
Top
Bottom
Top
Bottom
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SC4605
POWER MANAGEMENT
Applications Information (Cont.)
Over current protection characteristic of SC4605 for 3.3V to 1.5V @12A application
The over current protection curve below is obtained by applying a gradually increased load while the load current
and the output voltage are monitored and measured. When the load current is increased from 0 to 16.2A (over
current trigger point), the output voltage is 1.5V, corresponding from Point A to Point B. As the load current in-
creases further from 16.2A to 16.3A, the output voltage drops significantly from 1.5V (Point B) to 0.88V (Point C).
Because an over current and a lower output voltage (0.88V<68.75%*1.5V=1.03V) are present at Point C, the
SC4605 enters its HICCUP mode. Then the locus of the output current and the output voltage follows Line CD as
shown in the curve. Due to the over current applied, the HICCUP protection will go back and forth on Line CD. This
prevents excess power dissipation in the TOP MOSFET during a short output condition.
Over current protection
3
2.5
A
B
2
1.5
D
1
0.5
0
C
0
5
10
15
20
Io (A)
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SC4605
POWER MANAGEMENT
Typical Characteristics
Oscillator Internal Accuracy
Oscillator Internal Accuracy
vs
vs
Input Voltage
Temperature
314
312
310
308
306
304
302
300
298
318
316
314
312
310
308
306
304
Vcc = 5V
TA = 25°C
-40
-20
0
20
40
60
80
100
120
2.5
3
3.5
4
4.5
5
5.5
Temperature (°C)
Vcc (V)
Sense Voltage
vs
Temperature
Sense Voltage
vs
Input Voltage
0.804
0.802
0.800
0.798
0.796
0.794
0.792
0.804
0.803
0.803
0.802
0.802
0.801
Vcc = 5V
A
T
= 25°C
-40
-20
0
20
40
60
80
100
120
2.5
3
3.5
4
4.5
5
5.5
Temperature (°C)
Vcc (V)
Current Limit Bias Current
Current Limit Bias Current
vs
vs
Temperature
Input Voltage
51.0
50.5
50.0
49.5
49.0
48.5
48.0
47.5
60.0
A
T
= 25°C
Vcc = 5V
55.0
50.0
45.0
40.0
35.0
30.0
2.5
3
3.5
4
4.5
5
5.5
-40
-20
0
20
40
60
80
100
120
Vcc (V)
Temperature (°C)
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SC4605
POWER MANAGEMENT
Outline Drawing - MSOP-10
DIMENSIONS
INCHES MILLIMETERS
e
DIM
A
A
MIN NOM MAX MIN NOM MAX
D
E
-
-
-
-
-
-
-
-
-
-
-
-
.043
1.10
0.15
0.95
0.27
0.23
N
A1 .000
A2 .030
.006 0.00
.037 0.75
.011 0.17
.009 0.08
b
c
D
.007
.003
2X
E/2
.114 .118 .122 2.90 3.00 3.10
E1
E1 .114 .118 .122 2.90 3.00 3.10
PIN 1
E
e
.193 BSC
.020 BSC
4.90 BSC
0.50 BSC
INDICATOR
L
L1
N
.016 .024 .032 0.40 0.60 0.80
ccc
C
1 2
(.037)
10
-
(.95)
10
-
2X N/2 TIPS
B
01
aaa
0°
8°
0°
8°
.004
.003
.010
0.10
0.08
0.25
bbb
ccc
D
aaa
C
H
A2
A
SEATING
PLANE
c
GAGE
A1
bxN
bbb
C
PLANE
C
A-B D
0.25
L
01
(L1)
DETAIL A
SEE DETAIL A
SIDE VIEW
NOTES:
1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H-
3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS
OR GATE BURRS.
4. REFERENCE JEDEC STD MO-187, VARIATION BA.
Land Pattern - MSOP-10
X
DIMENSIONS
DIM
INCHES
(.161)
.098
MILLIMETERS
(4.10)
2.50
0.50
0.30
1.60
5.70
C
G
P
X
Y
Z
(C)
G
Y
Z
.020
.011
.063
.224
P
NOTES:
1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
Contact Information
Semtech Corporation
Power Management Products Division
2OO Flynn Road, Camarillo, CA. 93012
Phone: (805)498-2111 FAX (805)498-3804
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