SC4612MLTRT [SEMTECH]
Wide Input Range High Performance Synchronous Buck Switching Controller; 宽输入范围的高性能同步降压开关控制器
| 型号： | SC4612MLTRT |
| 厂家： | 
SEMTECH CORPORATION |
| 描述： | Wide Input Range High Performance Synchronous Buck Switching Controller |
| 文件： | 总24页 (文件大小：426K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SC4612
Wide Input Range High Performance
Synchronous Buck Switching Controller
POWER MANAGEMENT
Description
Features
SC4612 is a high performance synchronous buck controller
that can be configured for a wide range of applications.
The SC4612 utilizes synchronous rectified buck topology
where high efficiency is the primary consideration. SC4612
is optimized for applications requiring wide input supply
range and low output voltages down to 500mV.
Wide voltage range, VDD = 28V, VPWRIN = 40V
Internally regulated DRV
Output voltage as low as 0.5V
1.7A gate drive capability
Asynchronous start up mode
Low side RDS-ON sensing with hiccup mode current
limit
Programmable current limit
Programmable frequency up to 1.2 MHz
Available in MLPD-12 and SOIC-14 Lead-free
packages. This product is fully WEEE and RoHS
compliant
SC4612 implements an asynchronous soft-start mode,
which keeps the lower side MOSFET off during soft-start, a
desired feature when a converter turns on into a preset
external voltage or pre-biased output voltage. With the lower
MOSFET off, the external bus is not discharged, preventing
any disturbances in the start up slope and any latch-up of
modern day ASIC circuits.
Applications
Distributed power architectures
Telecommunication equipment
Servers/work stations
Mixed signal applications
Base station power management
Point of use low voltage high current applications
SC4612 comes with a rich set of features such as regulated
DRV supply, programmable soft-start, high current gate
drivers, internal bootstrapping for driving high side
N-channel MOSFET, shoot through protection, RDS-ON sensing
with hiccup over current protection, and asynchronous start
up with over current protection.
Typical Application Circuit
+
C9
Vin
_
U1
R1
R2
SC4612MLP
1
2
3
4
5
6
12
11
10
9
ILIM
OSC
SS/EN
EAO
FB
PHASE
C1
DH
BST
DRV
DL
D1
C2
R3
Q1
C8
L1
C7
C3
C4
+
8
C10
Vout
Q2
7
VDD
GND
C5
_
R5
R4
R6
C6
Revision: January 31, 2007
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SC4612
POWER MANAGEMENT
Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in
the Electrical Characteristics section is not implied.
Parameter
Symbol
Maximum
Units
Bias Supply Voltage to GND
DRV to GND
VDD
-0.3 to 30
-0.3 to 10
100
V
V
DRV Source Current (peak)
ILIM, to GND
mA
V
-0.3 to 10
-0.3 to +5
-0.3 to +10
-0.3 to +10
-2 to +40
-0.3 to +10
45.3
EAO, SS/EN, FB, OSC to GND
DL to GND
V
V
BST to PHASE
V
PHASE to GND
VIN
V
DH to PHASE
V
Thermal Resistance Junction to Ambient (MLPD) (1)
Thermal Resistance Junction to Case (MLPD)
Thermal Resistance Junction to Ambient (SOIC)
Thermal Resistance Junction to Case (SOIC)
Operating Junction Temperature Range
Storage Temperature Range
Peak IR Reflow Temperature (10-40s)
Lead Temperature (10s), (SOIC-14)
ESD Rating (Human Body Model)
°C/W
°C/W
°C/W
°C/W
°C
θJA
θJC
11
115
θJA
45
θJC
TJ
-40 to +125
-65 to +150
260
TSTG
TIR Reflow
TLEAD
ESD
°C
°C
300
°C
2
kV
All voltages with respect to GND. Positive currents are into, and negative currents are out of the specified terminal. Pulsed
is defined as a less than 10% duty cycle with a maximum duration of 500ns. Consult Packaging Section of Data sheet for
thermal limitations and considerations of packages.
Note:
(1). 1 sq. inch of FR-4, double-sided, 1 oz copper weight.
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SC4612
POWER MANAGEMENT
Electrical Characteristics
Unless otherwise specified:
VIN = VDD = 12V, FOSC = 600kHz, TA = TJ = -40°C to 125°C.
Parameter
Bias Supply
VDD
Test Conditions
Min
Typ
Max
Units
28
7
V
Quiescent Current
VDD = 28V, No load, SS/EN = 0
5
mA
VDD Undervoltage Lockout
Start Threshold
4.20
7.3
4.50
400
4.75
V
UVLO Hysteresis
mV
Drive Regulator
DRV
10V ≤ VDD ≤ 28V, IOUT ≤ 1mA
1mA ≤ IO ≤ 100mA
7.8
8.3
V
Load Regulation
100
mV
Oscillator
Operation Frequency Range
Initial Accuracy(1)
100
540
85
1200
660
kHz
kHz
%
COSC = 160pF (Ref only)
600
850
Maximum Duty Cycle(2)
Ramp Peak to Valley (1)
Oscillator Charge Current
Current Limit (Low Side Rdson)
Current Limit Threshold Voltage
Error Amplifier
mV
µA
90
110
VOUT = 500mV, 3.3V, 5V
100
mV
Feedback Voltage
TJ = 0 to +70°C
TJ = -40 to +85°C
TJ = -40 to +125°C
FB = 0.5V
0.495
0.492
0.488
0.500
0.500
0.500
0.505
0.508
0.512
200
V
V
V
Input Bias Current
nA
dB
MHz
µA
µA
V/µs
(1)
Open Loop Gain
60
10
Unity Gain Bandwidth (1)
Output Sink Current
Output Source Current
Slew Rate (1)
7
Open Loop, FB = 0V
Open Loop, FB = 0.6V
900
1100
1
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SC4612
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Unless otherwise specified:
VIN = VDD = 12V, FOSC = 600kHz, TA = TJ = -40°C to 125°C.
Parameter
Test Conditions
Min
Typ
Max
Units
SS/EN
Disable Threshold Voltage
Soft Start Charge Current
Soft Start Discharge Current (1)
Disable Low to Shut Down (1)
Hiccup
500
mV
µA
µA
ns
25
1
50
C
= 0.1,
current SliSmit condition
Hiccup duty cycle
1
%
Gate Drive
Gate Drive On-Resistance (H)(2)
Gate Drive On-Resistance (L)(2)
DL Source/Sink Peak Current(2)
DH Source/Sink Peak Current(2)
Output Rise Time
ISOURCE = 100mA
ISINK = 100mA
3
4
4
Ω
Ω
3
COUT = 2000pF
COUT = 2000pF
COUT = 2000pF
COUT = 2000pF
±1.4
±1.4
1.7
1.7
20
20
30
A
A
ns
ns
ns
ns
Output Fall Time
Minimum Non-Overlap (1)
Minimum On Time(2)
110
Notes:
(1) Guaranteed by design.
(2) Guaranteed by characterization.
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SC4612
POWER MANAGEMENT
Timing Diagrams
No fault start up sequence
VCC
Vcc
UVLO
4.58V
SS/EN
2.75V
1.3V
0.8V
0.5V
EAO
DH
Soft Start Duration
DL
Asynchronous
Operation
Over current fault at Asynchronous start up sequence
VCC
Vcc
UVLO
4.58V
Fault removed,
Fault
SS/EN
normal operation resumed
occur
2.75V
1.3V
0.8V
0.5V
EAO
DH
EOA<FB+0.7V
Soft Start Duration
Fault
present for
10 cycles
DL
Asynchronous
Operation
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SC4612
POWER MANAGEMENT
Pin Configurations
Ordering Information
(3)
Part Number
SC4612MLTRT
SC4612STRT
SC4612EVB(1)
Package(2)
Temp. Range (TJ)
TOP VIEW
MLPD-12
SOIC-14
-40°C to +125°C
1
2
3
4
5
6
ILIM
OSC
SS/EN
EAO
FB
12
11
10
9
8
7
PHASE
DH
BST
DRV
DL
EVALUATION BOARD
Notes:
(1) When ordering please specify MLPD or SOIC
package.
(2) Only available in tape and reel packaging. A reel
contains 3000 devices for MLPD package and 2500 for
SOIC package..
VDD
GND
(12 Pin MLPD)
TOP VIEW
(3) Lead-free product. This product is fully WEEE and
RoHS compliant.
NC
ILIM
1
2
3
4
5
6
7
14
13
12
11
10
9
PHASE
DH
BST
DRV
DL
OSC
SS/EN
EAO
VDD
NC
GND
FB
8
(14 Pin SOIC)
Marking Information - MLPD
Marking Information - SOIC
Top Mark
Top Mark
SC4612
yyww
4612
yyww
xxxxx
xxxxxxxxx
nnnnnn = Part Number (Example: SC4612)
nnnn
yyww
= Part Number (Example: 1531)
= Date Code (Example: 0012)
yyww
= Date Code (Example: 0552)
xxxxxxxxx = Semtech Lot No.
(Example: A01E90101)
xxxxx = Semtech Lot No. (Example:E9010)
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SC4612
POWER MANAGEMENT
Pin Descriptions
Pin #
Pin#
Pin Name Pin Function
MLPD
SOIC
1, 7
2
NC
No connection.
1
ILIM
The current limit programing resistors (R2 & R3) in conjunction with an internal current
source, program the current limit threshold for the low side MOSFET RDS-ON
sensing. Once the voltage drop across the Low side MOSFET is larger than the drop
across the programmed value, current limit conditionoccurs, and the hiccup current limit
protection is activated.
2
3
3
4
OSC
Oscillator Frequency set pin. An external capacitor to GND will program the oscillator
frequency. See Table "Frequency vs. COSC" on page 14 to determine oscillator
frequency.
SS/EN
Soft start pin. Internal current source connected to a single external capacitor will
determine the soft-start duration for the output. Inhibits the chip if pulled down.
CSS X 1.2
TSS
≈
ISS
4
5
5
8
EAO
FB
Error Amplifier output. A compensation network is connected from this pin to FB.
The inverting input of the error amplifier. Feedback pin is used to sense the output
voltage via a resistive divider.
6
6
VDD
Bias supply ranging from 4.5V to 28V, VDD pin is initially used to provide the base
drive to the internal pass transistor to regulate the DRV.
7
8
9
9
GND
DL
Ground.
10
11
DL signal (Drive Low). Gate drive for bottom MOSFET.
DRV
DRV supplies the output MOSFETs gate drive, and the chip analog circuitry. This pin
should be bypassed witha 2.2µF ceramic capacitor to GND. DRV is internallyregulated
from the external supply connected to VDD. If VDD is below 10V , the supply could be
directly connected to the DRV pin.
10
12
BST
BST signal. Supply for high side driver; can be directly connected to an external supply
or to a bootstrap circuit.
11
12
13
14
DH
DH signal (Drive High). Gate drive for top MOSFET.
PHASE
The return path for the high side gate drive, also used to sense the voltage at the phase
node for adaptive gate drive protection, and the low-side RDS-ON voltage sensing.
THERMAL Pad for heatsinking purposes. Connect to ground plane using multiple vias.
PAD (GND)
X
-
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SC4612
POWER MANAGEMENT
Block Diagram
VDD
DRV
GND
BST
DH
TOP Side
Gate Driver
INTERNAL REGULATOR
&
BST
DH
BANDGAP GENERATOR
PWM
OVP
PHASE
OVP
OCP
PWM Control
OCP
EN
SYNC
Oscillator
900mV
Low Side
PHASE
DL
Q
Gate Driver
S
R
VCC
PWM
OSC
DL
-
+
Synchronous
Mode
GND
Error
Amp.
-
Current
Limit
ILIM
FB
+
FB
SOFT START
SS
REF
SS
&
SS/EN
EAO
Enable
Over Voltage Protection
OCP @ Asynchronous Start up
FB
+
-
Low Side 100% on
S
R
Q
False
600mV
EAO > FB + 0.7
Top Side off
20% OVP
for more than 10
cycles
PWM
Enable
Soft Start
True
Cycle
Vcc UVLO
Allow
Synchronous
mode
PWM
PWM
SS
Enable
Disable
+
-
Vcc
UVLO
800mV
Synchronous
Mode
FB
+
-
S
R
Q
Vref
PWM
Low Side
Enable
S
R
Q
Rdson OCP
PWM
Enable
PWM
Disable
SS
+
-
Vref+0.5
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SC4612
POWER MANAGEMENT
Applications Information
INTRODUCTION
START UP SEQUENCE
The SC4612 is a versatile voltage mode synchronous
rectified buck PWM convertor, with an input supply (VIN)
ranging from 4.5V to 28V designed to control and drive
N-channel MOSFETs.
The power dissipation is controlled using a novel low volt-
age supply technique, allowing high speed and integra-
tion with the high drive currents to ensure low MOSFET
switching loss. The synchronous buck configuration also
allows converter sinking current from load without losing
output regulation.
Start up is inhibited until VDD input reaches its UVLO
threshold. The UVLO limit is 4.5V (TYP).
Meanwhile, the high side and low side gate drivers DH,
and DL, are kept low. Once VDD exceeds the UVLO
threshold, the external soft-start capacitor starts to be
charged by a 25µA current source. If an over current
condition occurs, the SS/EN pin will discharge to 500mV
by an internal switch. During this time, both DH and DL
will be turned off.
When the SS pin reaches 0.8V, the converter will start
switching. The reference input of the error amplifier is
ramped up with the soft-start signal. Initially only the high
side driver is enabled. Keeping the low side MOSFET off
during start up is useful where multiple convertors are
operating in parallel. It prevents forward conduction in the
freewheeling MOSFET which might otherwise cause a dip
in the common output bus.
The internal reference is trimmed to 500mV with ± 1%
accuracy, and the output voltage can be adjusted by two
external resistors.
A fixed oscillator frequency (up to 1.2MHz) can be
programmed by an external capacitor for an optimized
design.
During the Asynchronous start up, the SC4612 provides a
top MOSFET shut down over current protection, while under
normal operating conditions a low side MOSFET RDS-ON
current sensing with hiccup mode over current protection,
minimizes power dissipation and provides further
protection.
In case of over current condition which is longer than 10
cycles during the asynchronous start up, SC4612 will turn
off the high side MOSFET gate drive, and the soft-start
sequence will repeat.
When the SS pin reaches 1.3V, the low side MOSFET will
begin to switch and the convertor is fully operational in
the synchronous mode. The soft-start duration is
controlled by the value of the SS cap. If the SS pin is pulled
below 0.5V, the SC4612 is disabled and draws a typical
quiescent current of 5mA.
Other features of the SC4612 include:
Wide input power voltage range (from 4.5V to 28V), low
output voltages down to 500mV, externally programmable
soft-start, hiccup over current protection, wide duty cycle
range, thermal shutdown, asynchronous start-up
protection, and a -40 to 125°C junction operating
temperature range.
Bias Generation
A 4.5V to 10V (MAX) supply voltage is required to power
up the SC4612. This voltage could be provided by an ex-
ternal power supply or derived from VDD (VDD >10V)
through an internal pass transistor.
THEORY OF OPERATION
SUPPLIES
Two pins (VDD and DRV) are used to power up the SC4612.
If input supply (VDD) is less than 10V (MAX), tie DRV and
VDD together.
The internal pass transistor will regulate the DRV from an
external supply >10V connected to VDD to produce 7.8V
(TYP) at the DRV pin.
This supply should be bypassed with a low ESR 2.2uF (or
greater) ceramic capacitor directly at the DRV to GND pins
of the SC4612.
Soft start / Shut down
An external capacitor at the SS/EN pin is used to set up
the soft-start duration. The capacitor value in conjunction
with the internal current source, controls the duration of
soft-start time. If the SS/EN pin is pulled down to GND,
the SC4612 is disabled. The soft-start pin is charged by a
25µA current source and discharged by an internal switch.
When SS/EN is released it charges up to 0.5V as the con-
trol circuit starts up.
The DRV supply also provides the bias for the low and the
high side MOSFET gate drive.
The maximum rating for DRV supply is 10V and for
applications where input supply is below 10V, it may be
connected directly to VDD.
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SC4612
POWER MANAGEMENT
Applications Information (Cont.)
The reference input of the error amplifier is effectively
ramped up with the soft-start signal. The error amp output
will vary between 100mV and 1.2V, depending on the duty
cycle. The error amp will be off until SS/EN reaches 0.7V
(TYP) and will move the output up to its desired voltage by
the time SS/EN reaches 1.3V. The gate drivers will be in
asynchronous mode until the FB pin reaches 500mV.
OVERCURRENT PROTECTION
SC4612 features low side MOSFET on-state Rds current
sensing and hiccup mode over current protection. ILIM pin
would be connected to DRV or PHASE via programming
resistors to adjust the over current trip point to meet
different customer requirements.
The sampling of the current thru the bottom FET is set at
~150ns after the bottom FET drive comes ON. It is done to
prevent a false tripping of the current limit circuit due to
the ringing at the phase node when the top FET is turned
OFF.
Internally overcurrent threshold is set to 100mV_typ. If
voltage magnitude at the phase node during sampling is
such that the current comparator meets this condition then
the OCP occurs.
Connecting a resistor from external voltage source such
as VDD, DRV, etc. to ILIM increases the current limit.
Connecting a resistor from ILIM to PHASE lowers the current
limit (see the block diagram in page 9).
The intention for the asynchronous start up is to keep the
low side MOSFET from being switched on which forces the
low side MOSFETs body diode or the parallel Schottky di-
ode to conduct. The conduction by the diode prevents any
dips in an existing output voltage that might be present,
allowing for a glitch free start up in applications that are
sensitive to any bus disturbances.
During the asynchronous start up SC4612 monitors the
output and if within 10 cycles the FB has not reached the
internal soft start ramp level, the device switches to syn-
chronous mode. This provides an added protection in case
of short circuit at the output during the asynchronous start
when the bottom MOSFET is not being switched to provide
the RDS-ON sensing current limit protection.
Internal current source at ILIM node is ~20µA. External
programming resistors add to or subtract from that source
and hence vary the threshold.
In case of a current limit, the gate drives will be held off
until the soft-start is initiated. The soft-start cycle defined
by the SS cap being charged from 800mV to 1.3V and
slowly discharged to achieve an approximate hiccup duty
cycle of 1% to minimize excessive power dissipation.
The tolerance of the collective current sink at ILIM node is
fairly loose when combined with variations of the FET’s
Rds(on). Therefore when setting current limit some iteration
might be required to get to the wanted trip point.
Nonetheless, this circuit does serve the purpose of a hard
fault protection of the power switches. When choosing the
current limit one should consider the cumulative effect of
the load and inductor ripple current. As a rule of thumb,
the limit should be set at least x10 greater then the pk-pk
ripple current. Whenever a high current peak is detected,
SC4612 would first block the driving of the high side and
low side MOSFET, and then discharge the soft-start
capacitor. Discharge rate of the SS capacitor is 1/25 of
the charge rate.
The part will try to restart on the next softstart cycle. If the
fault has cleared, the outputs will start . If the fault still
remains, the part will repeat the soft-start cycle above in-
definitely until the fault has been removed.
The soft-start time is determined by the value of the
softstart capacitor (see formula below).
CSS X 1.2
≈
TSS
ISS
Oscillator Frequency Selection
Under Voltage Lock Out
The internal oscillator sawtooth signal is generated by
charging an external capacitor with a current source of
100µA charge current.
Under Voltage Lock Out (UVLO) circuitry senses the VDD
through a voltage divider. If this signal falls below 4.5V (typi-
cal) with a 400mV hysteresis (typical), the output drivers
are disabled . During the thermal shutdown, the output
drivers are disabled.
See Table 1 “Frequency vs. COSC” on page 14 to determine
oscillator frequency.
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SC4612
POWER MANAGEMENT
Applications Information (Cont.)
Below are examples of calculating the OCP trip voltages.
Low Side RDS_ON Current Limit
SC4612
2.75V
DRV pin
R3
R4
130k
260k
Vin
Ra
R1
2k
ILIM pin
OCP
COMP
Rb
R2
10k
+100mV
L
PHASE pin
R
C1
C2
Iload@Toff
R5
load
2pF
5pF
10k
1. Ra, Rb - Not installed:
2.75V −100mV 100mV − Vphase
=
R3
R2
solving for: VPHASE = -100mV, therefore the circuit will trip @ RDS_ON x ILOAD = 100mV
2. To lower trip voltage - install Rb. For example: Rb = 13k
2.75V −100mV 100mV − Vphase
=
R3
R2|| (Rb + R1)
solving for: VPHASE = -20mV, obviously more sensitive! RDS_ON x ILOAD = 20mV
3. To increase trip voltage - install Ra. For example: Ra = 800k; VDRIVE = 7.8V typ.
2.75V −100mV Vdrive 100mV − Vphase
+
=
R3
Ra + R1
R2
solving for: VPHASE = -200mV. Current limit has doubled compared to original conditions.
NOTE! Allow for tempco and RDS_ON variation of the MOSFET - see “overcurrent protection” information on page 11 in the
datasheet.
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SC4612
POWER MANAGEMENT
Applications Information (Cont.)
Gate Drive/Control
where,
VIN – Input voltage
RL – Load resistance
C – Output capacitance
The SC4612 also provides integrated high current gate
drives for fast switching of large MOSFETs. The high side
and low side MOSFET gates could be switched with a peak
gate current of 1.7A. The higher gate current will reduce
switching losses of the larger MOSFETs.
L – Output inductance
ESRC – Output capacitor ESR
VS – Peak to peak ramp voltage
The low side gate drives are supplied directly from the DRV.
The high side gate drives could be provided with the clas-
sical bootstrapping technique from DRV.
The classical Type III compensation network can be built
Cross conduction prevention circuitry ensures a non over- around the error amplifier as shown below:
lapping (30ns typical) gate drive between the top and bot-
tom MOSFETs. This prevents shoot through losses which
provides higher efficiency. Typical total minimum off time
for the SC4612 is about 30ns which will cause the maxi-
mum duty cycle at higher frequencies to be limited to lower
than 100%.
C3
C2
R1
R3
R2
C1
-
+
OVERVOLTAGE PROTECTION
Vref
If the FB pin ever exceeds 600mV, the top side driver is
latched OFF, and the low side driver is latched ON. This
mode can only be reset by power supply cycling.
Figure 1. Voltage mode buck converter compensation
network
ERROR AMPLIFIER DESIGN
The SC4612 is a voltage mode buck controller that utilizes
an externally compensated high bandwidth error amplifier
to regulate output voltage. The power stage of the
synchronous rectified buck converter control-to-output
transfer function is as shown below:
The transfer function of the compensation network is as
follows:
s
s
ωZ2
s
(1+
(1+
)(1+
)(1+
)
)
ωI
ωZ1
s
GCOMP(s) =
s
ωP1
ωP2
where,
V
V
1+ sESR C
IN
×
S
C
G
(s) =
VD
L
2
1
R2C1
1
1
1+ s
+ s LC
ωZ1
=
, ωZ2
=
, ωo =
R
(R1 + R3 )C2
Lout × Cout
L
1
1
R3C2
1
ωI =
,
ωP1
=
,
ωP2
=
C1C3
R1(C1 + C3 )
R
2 C1 + C3
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SC4612
POWER MANAGEMENT
Application Information (Cont.)
The design guidelines are as following:
T
ωZ1
1. Set the loop gain crossover frequency wC for given
switching frequency.
Loop gain T(s)
ω o
ωZ2
2. Place an integrator at the origin to increase DC and low
frequency gains.
Gd
ωc
0dB
ω
p1
3. Select wZ1 and wZ2 such that they are placed near wO to
dampen peaking; the loop gain should cross 0dB at a rate
of -20dB/dec.
ω
p2
4. Cancel wESR with compensation pole wP1 (wP1 = wESR ).
ω ESR
5. Place a high frequency compensation pole wP2 at half
the switching frequency to get the maximum attenuation
of the switching ripple and the high frequency noise with
adequate phase lag at wC.
Figure 2. Simplified asymptotic diagram of buck power
stage and its compensated loop gain.
Switching Frequency, FSW vs. COSC
.
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
0
100
200
300
400
500
600 700
800
900 1000 1100 1200
Frequency, (kHz)
Table 1
2007 Semtech Corp.
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SC4612
POWER MANAGEMENT
Application Information (Cont.)
PCB LAYOUT GUIDELINES
Careful attention to layout is necessary for successful
implementation of the SC4612 PWM controller. High
switching currents are present in the application and their
effect on ground plane voltage differentials must be
understood and minimized.
VIN
I (Input Capacitor)
Vphase
Vout
Ids (Top Fet)
I (Inductor)
1) The high power section of the circuit should be laid out
first. A ground plane should be used. The number and
position of ground plane interruptions should not
unnecessarily compromise ground plane integrity. Isolated
or semi-isolated areas of the ground plane may be
deliberately introduced to constrain ground currents to
particular areas; for example, the input capacitor and
bottom FET ground.
+
Vout
I (Output Capacitor)
+
2) The loop formed by the Input Capacitor(s) (Cin), the Top
FET (M1), and the Bottom FET (M2) must be kept as small
as possible. This loop contains all the high current, fast
transition switching. Connections should be as wide and
as short as possible to minimize loop inductance.
Minimizing this loop area will a) reduce EMI, b) lower ground
injection currents, resulting in electrically “cleaner” grounds
for the rest of the system and c) minimize source ringing,
resulting in more reliable gate switching signals.
Ids (Bottom Fet)
Voltage and current waveforms of buck power stage .
3) The connection between the junction of M1, M2 and
the output inductor should be a wide trace or copper region.
It should be as short as practical. Since this connection
has fast voltage transitions, keeping this connection short
will minimize EMI. Also keep the Phase connection to the
IC short. Top FET gate charge currents flow in this trace.
4) The Output Capacitor(s) (Cout) should be located as
close to the load as possible. Fast transient load currents
are supplied by Cout only, and therefore, connections
between Cout and the load must be short, wide copper
areas to minimize inductance and resistance.
5) The SC4612 is best placed over a quiet ground plane
area. Avoid pulse currents in the Cin, M1, M2 loop flowing
in this area. GND should be returned to the ground plane
close to the package and close to the ground side of (one
of) the output capacitor(s). If this is not possible, the GND
pin may be connected to the ground path between the
Output Capacitor(s) and the Cin, M1, M2 loop. Under no
circumstances should GND be returned to a ground inside
the Cin, M1, M2 loop.
6) Allow adequate heat sinking area for the power
components. If multiple layers will be used, provide
sufficent vias for heat transfer
2007 Semtech Corp.
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SC4612
POWER MANAGEMENT
Application Information (Cont.)
COMPONENT SELECTION:
The maximum inductor value may be calculated from:
RESR
It
C
L ≤
VIN − VO
( )
SWITCHING SECTION
The calculated maximum inductor value assumes 100%
duty cycle, so some allowance must be made. Choosing
an inductor value of 50 to 75% of the calculated maximum
will guarantee that the inductor current will ramp fast
enough to reduce the voltage dropped across the ESR at a
faster rate than the capacitor sags, hence ensuring a good
recovery from transient with no additional excursions. We
must also be concerned with ripple current in the output
inductor and a general rule of thumb has been to allow
10% of maximum output current as ripple current. Note
that most of the output voltage ripple is produced by the
inductor ripple current flowing in the output capacitor ESR.
Ripple current can be calculated from:
OUTPUT CAPACITORS - Selection begins with the most
critical component. Because of fast transient load current
requirements in modern microprocessor core supplies, the
output capacitors must supply all transient load current
requirements until the current in the output inductor ramps
up to the new level. Output capacitor ESR is therefore one
of the most important criteria. The maximum ESR can be
simply calculated from:
Vt
It
RESR
≤
Where
Vt = Maximum transient voltage excursion
It = Transient current step
VIN
IL
=
RIPPLE
4 L fOSC
Ripple current allowance will define the minimum permitted
inductor value.
For example, to meet a 100mV transient limit with a 10A
load step, the output capacitor ESR must be less than
10mΩ. To meet this kind of ESR level, there are three
available capacitor technologies.
POWER FETS - The FETs are chosen based on several
criteria with probably the most important being power
dissipation and power handling capability.
Each
Total
TOP FET - The power dissipation in the top FET is a
combination of conduction losses, switching losses and
bottom FET body diode recovery losses.
Capacitor
Qty
Technology
Rqd.
C
ESR
C
ESR
(uF) (mΩ)
(uF)
(mΩ)
10
a) Conduction losses are simply calculated as:
Low ESR Tantalum
OS-CON
330
330
60
25
44
6
3
5
2000
990
PCOND = IO2 RDS(on)
D
8.3
8.8
where
Low ESR Aluminum 1500
7500
VO
IN
D = duty cycle ≈
The choice of which to use is simply a cost/performance
issue, with low ESR Aluminum being the cheapest, but
taking up the most space.
V
b) Switching losses can be estimated by assuming a
switching time, If we assume 100ns then:
100ns
TSW
INDUCTOR - Having decided on a suitable type and value
of output capacitor, the maximum allowable value of
inductor can be calculated. Too large an inductor will
produce a slow current ramp rate and will cause the output
capacitor to supply more of the transient load current for
longer - leading to an output voltage sag below the ESR
excursion calculated above.
PSW = IO
V
IN
or more generally,
IO
=
V
(tr + tf ) fOSC
2
IN
PSW
c) Body diode recovery losses are more difficult to estimate,
but to a first approximation, it is reasonable to assume
2007 Semtech Corp.
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SC4612
POWER MANAGEMENT
Application Information (Cont.)
mount packages on double sided FR4, 2 oz printed circuit
board material, thermal impedances of 40oC/W for the
D2PAK and 80oC/W for the SO-8 are readily achievable.
The corresponding temperature rise is detailed below:
that the stored charge on the bottom FET body diode will
be moved through the top FET as it starts to turn on. The
resulting power dissipation in the top FET will be:
P RR = Q
V
fOSC
RR
IN
Temperature rise ( 0C)
To a first order approximation, it is convenient to only
consider conduction losses to determine FET suitability.
For a 5V in, 2.8V out at 14.2A requirement, typical FET
losses would be:
FET Type
IRL3402S
IRL2203
Si4410
Top FET
67.6
Bottom FET
53.2
47.6
37.2
FET Type
IRL3402S
IRL2203
Si4410
RDS(on) (mΩ)
PD(W)
1.69
Package
D2PAK
D2PAK
SO-8
180.8
141.6
15
10.5
20
1.19
It is apparent that single SO-8 Si4410 are not adequate for
this application, By using parallel pairs in each position,
power dissipation will be approximately halved and
temperature rise reduced by a factor of 4.
2.26
Using 1.5X Room temp RDS(ON) to allow for temperature rise.
INPUT CAPACITORS - Since the RMS ripple current in the
input capacitors may be as high as 50% of the output
current, suitable capacitors must be chosen accordingly.
Also, during fast load transients, there may be restrictions
on input di/dt. These restrictions require useable energy
storage within the converter circuitry, either as extra output
capacitance or, more usually, additional input capacitors.
Choosing low ESR input capacitors will help maximize ripple
rating for a given size.
BOTTOM FET - Bottom FET losses are almost entirely due
to conduction. The body diode is forced into conduction at
the beginning and end of the bottom switch conduction
period, so when the FET turns on and off, there is very little
voltage across it resulting in very low switching losses.
Conduction losses for the FET can be determined by:
PCOND = I2O RDS(on) (1−D)
For the example above:
FET Type
IRL3402S
IRL2203
Si4410
RDS(on) (mΩ)
PD(W)
1.33
0.93
1.77
Package
D2PAK
D2PAK
SO-8
15
10.5
20
Each of the package types has a characteristic thermal
impedance, for the TO-220 package, thermal impedance
is mostly determined by the heatsink used. For the surface
2007 Semtech Corp.
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SC4612
POWER MANAGEMENT
Application Information (Cont.)
Application Circuit 1: Vin = 36V; Vout = 5V @ 20A, Fsw = 250kHz.
+
Vin=36V
C14A
330/50V_AL
C14B
330/50V_AL
_
R 1
560k
U1
SC4612MLP
1
2
3
4
5
6
12
11
10
9
ILIM
OSC
SS/E N
EAO
FB
PHASE
C2
430p
DH
BST
DRV
DL
D 1
MBR0540
C3
0.1
C4
9.1n
Q1
C10
0.1
R 3
10k
HAT2172H
L1
4.7uH@ 22A
Q 2
HAT2172H
C5
1.3n
+
8
C8
2.2/10V
R4*
Vout=5@20A
7
C12A
C12B
C13A
C13B
10/6.3V_cer
VDD
GND
C9
330/6.3V 330/6.3V 330/6.3V
10/50V_cer
Z1*
C6
1_cer
_
R 6
48.7k
R 5
5.36k
Fsw=250kHz
C7
1.3n
R 7
910
R4*: if Vin > 28V, then R4 & Z1 provide VDDclamping
Efficiency:
SC4612: 36Vin, 5Vout @ 20A
100%
98%
96%
94%
92%
90%
88%
86%
84%
82%
80%
0
2
4
6
8
10 12 14 16 18 20 22
Current, (A)
2007 Semtech Corp.
17
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SC4612
POWER MANAGEMENT
Application Information (Cont.)
Application Circuit 2: Vin = 24V; Vout = 3.3V @ 20A, Fsw = 500kHz.
+
Vin=24V
C14A
C14B
470/35V_AL 470/35V_AL
_
R1
560k
U1
SC4612MLP
1
2
3
4
5
6
12
11
10
9
ILIM
OSC
SS/EN
EAO
FB
PHASE
C2
200p
DH
BST
DRV
DL
D1
MBR0540
C3
0.1
C4
3.9n
C10
0.1
R3
R8
0
Q1
10k
HAT2168H
L1
1.5uH@22A
C8
2.2/10V
R9
Q2
C5
300p
0
HAT2165H
+
8
R4opt
Vout=3.3@20A
7
C12A
C12B
C13A
C13B
10/6.3V_cer
VDD
GND
C9
22/25V_cer
180/4V_PosCap 180/4V 180/4V
C6
1/125V
_
R6
39.2k
R5
6.98k
Fsw=500kHz
C7
750p
R7
887
Efficiency:
SC4612: 24Vin, 3.3Vout @ 20A
100%
98%
96%
94%
92%
90%
88%
86%
84%
82%
80%
0
2
4
6
8
10 12 14 16 18 20 22
Current, (A)
2007 Semtech Corp.
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SC4612
POWER MANAGEMENT
Application Information (Cont.)
Application Circuit 3: Vin = 12V; Vout = 2.5V @ 12A, Fsw = 800kHz
+
Vin=12V
C14A
47/16V_AL
C14B
47/16V_AL
R1
825k
_
U1
SC4612MLP
1
2
3
4
5
6
12
11
10
9
ILIM
OSC
SS/EN
EAO
FB
PHASE
C2
120p
DH
D1
SD107WS
C3
0.1
BST
C4
3.3n
C10
0.1
R3
R8
0
Q1
10k
HAT2168H
DRV
DL
L1
1.4uH@14A
C8
R9
Q2
C5
300p
2.2/10V
0
HAT2165H
+
8
R4opt
20
Vout=2.5@12A
10/6.3V_cer
7
C12A
C12B
C13A
N/A
C13B
VDD
GND
C9
22/16V_cer
220/4V_PosCap 220/4V
C6
1/16V
_
R6
11.0k
R5
2.74k
Fsw=800kHz
C7
2.2n
R7
178
Efficiency:
SC4612: 12Vin, 2.5Vout @ 12A
100%
98%
96%
94%
92%
90%
88%
86%
84%
82%
80%
0
1
2
3
4
5
6
7
8
9
10 11 12
Current, (A)
2007 Semtech Corp.
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SC4612
POWER MANAGEMENT
Application Information (Cont.)
Application Circuit 4: Vin = 5V; Vout = 1.35V @ 12A, Fsw = 1MHz.
+
Vin=5V
D1
SD107WS
_
R2
825k
U1
SC4612MLP
1
2
3
4
5
6
12
11
10
9
ILIM
OSC
SS/EN
EAO
FB
PHASE
C2
82p
DH
BST
DRV
DL
C3
0.1
C10
0.1
R3
10k
C4
1n
Q1
HAT2168H
L1
0.47uH@15A
C8
2.2
Q2
HAT2168H
C5
33p
+
8
C11
Vout=1.35@12A
7
VDD
GND
C9
100/6.3_1210_cer
100/6.3_1210_cer
C6
1
_
R6
13.3k
R5
8.87k
Fsw=1MHz
C7
510p
R7
649
Efficiency:
SC4612: 5Vin, 1.35Vout @ 12A
100%
98%
96%
94%
92%
90%
88%
86%
84%
82%
80%
0
1
2
3
4
5
6
7
8
9
10 11 12 13
Current, (A)
2007 Semtech Corp.
20
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SC4612
POWER MANAGEMENT
Application Information (Cont.)
Evaluation Board 1:
Top layer and components view
Bottom Layer:
2007 Semtech Corp.
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SC4612
POWER MANAGEMENT
Application Information (Cont.)
Evaluation Board 2 (actual size):
Top layer:
Bottom layer:
2007 Semtech Corp.
22
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SC4612
POWER MANAGEMENT
Outline Drawing - MLPD - 12
B
E
D
A
DIMENSIONS
INCHES MILLIMETERS
DIM
A
MIN NOM MAX MIN NOM MAX
.031
.040
0.90 1.00
.035
.001
0.80
PIN1
INDICATOR
0.02
A1 .000
.002 0.00
0.05
-
-
-
-
(.008)
(0.20)
A2
(LASER MARK)
b
D
0.25 0.30
.007
.010 .012 0.18
.154 .157 .161 3.90 4.00 4.10
D1
E
.124 .130 .134 3.15
3.40
3.30
.114 .118 .122 2.90 3.00 3.10
1.70
E1
e
.061
1.80
.067 .071 1.55
A2
C
.020 BSC
0.50 BSC
L
N
0.40
12
.012 .016 .020 0.30
0.50
12
A
SEATING
PLANE
aaa
.003
.004
0.08
0.10
aaa C
bbb
A1
D1
D1/2
1 2
E1/2
bxN
E1
LxN
N
bbb
C A B
e
NOTES:
1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2.
COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.
Land Pattern - MLPD - 12
DIMENSIONS
DIM
INCHES
MILLIMETERS
(.114)
.087
.067
.138
.020
.012
.028
.142
(2.90)
2.20
1.70
3.50
0.50
0.30
0.70
3.60
C
G
H
K
P
X
Y
Z
NOTES:
1.
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
2007 Semtech Corp.
23
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SC4612
POWER MANAGEMENT
Outline Drawing - SOIC - 14
DIMENSIONS
INCHES MILLIMETERS
A
DIM
A
MIN NOM MAX MIN NOM MAX
D
E
e
-
-
-
-
-
-
-
-
-
-
.053
.069 1.35
.010 0.10
.065 1.25
.020 0.31
.010 0.17
1.75
0.25
1.65
0.51
0.25
N
1
A1 .004
A2 .049
2X
E/2
b
c
D
.012
.007
.337 .341 .344 8.55 8.65 8.75
E1
E1 .150 .154 .157 3.80 3.90 4.00
E
e
.236 BSC
6.00 BSC
1.27 BSC
.050 BSC
-
-
h
L
.010
.020 0.25
0.50
2
3
ccc
C
.016 .028 .041 0.40 0.72 1.04
B
(.041)
(1.04)
L1
N
2X N/2 TIPS
14
14
-
-
01
aaa
0°
8°
0°
8°
.004
.010
.008
0.10
0.25
0.20
bbb
ccc
D
aaa
SEATING
C
h
A2 A
PLANE
h
C
A1
A-B D
H
bxN
bbb
C
c
GAGE
PLANE
0.25
L
(L1)
01
SEE DETAIL A
DETAIL A
SIDE VIEW
NOTES:
1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H-
3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS
OR GATE BURRS.
4. REFERENCE JEDEC STD MS-012, VARIATION AB.
Land Pattern - SOIC - 14
X
DIMENSIONS
DIM
INCHES
(.205)
.118
MILLIMETERS
(5.20)
3.00
1.27
0.60
2.20
7.40
C
G
P
X
Y
Z
(C)
G
Y
Z
.050
.024
.087
.291
P
NOTES:
1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
2. REFERENCE IPC-SM-782A, RLP NO. 302A.
Contact Information
Semtech Corporation
Power Management Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805)498-2111 FAX (805)498-3804
2007 Semtech Corp.
24
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相关型号：
SC4620
Low Input Voltage, High Efficiency, 2.5A Integrated FET Synchronous Step down DC/DC Regulator
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