SK100LVE111EPJT [SEMTECH]

Low Skew Clock Driver, 100LVE Series, 9 True Output(s), 0 Inverted Output(s), ECL, PQCC28, PLASTIC, LCC-28;


型号：	SK100LVE111EPJT
厂家：	SEMTECH CORPORATION
描述：	Low Skew Clock Driver, 100LVE Series, 9 True Output(s), 0 Inverted Output(s), ECL, PQCC28, PLASTIC, LCC-28 驱动逻辑集成电路
文件：	总6页 (文件大小：131K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SK100LVE111E

1:9 Differential LVECL/LVPECL

Clock Driver w/Enable Input

HIGH-PERFORMANCE PRODUCTS

Description

the device. The VBB output pin should be used only as a

DC bias for the LVE111E as its current sink/

sourcecapability is limited. Whenever used, the VBB pin

should be bypassed to VCC via a 0.01 µF capacitor.

The SK100LVE111E is a low skew 1-to-9 differential

driver designed with clock distribution in mind. The

SK100LVE111E’s function and performance are similar

to the SK100E111, with the added feature of low

voltage operation and the enable input. It accepts

one signal input which can be either differential or

ꢀeatures

single-ended if the V

output is used. The signal is

• 200 ps Part-to-Part Skew

• 35 ps Output-to-Output Skew

• Differential Design

fanned out to 9 identical differential outputs. An enable

input is also provided. A PECL High logic level disables

the device by forcing all Q outputs Low and all Q*

outputs High.

• V Output

• Enable Input

• Voltage and Temperature Compensated Outputs

The device is specifically designed, modeled, and produced

with low skew as the key goal. Optimal design and layout

serve to minimize gate-to-gate skew within a device, and

characterization is used to determine process control limits

that ensure consistent tpd distributions from lot to lot.

The net result is a dependable, guaranteed low skew

device.

• Low Voltage V Range of –3.0V to –3.8V

• 75KΩ Internal Input Pulldown Resistors

• Fully Compatible with MC100LVE111

• Specified Over Industrial Temperature Range:

–40^oC to +85^oC

• ESD Protection of >4000V

• Available in 28 Pin PLCC Package

To ensure that the tight skew specification is met, it is

necessary that both sides of the differential output are

terminated into 50Ω, even if only one side is being used.

In most applications, all nine differential pairs will be used

and therefore terminated. In the case where fewer than

nine pairs are used, it is necessary to terminate at least

the output pairs on the same package side as the pair(s)

being used on that side in order to maintain minimum

skew. Failure to do so will result in small degradations of

propagation delay (on the order of 10–20ps) of the

output(s) being used which, while not being catastrophic

to most designs, will mean a loss of skew margin.

ꢀunctional Block Diagram

Q0*

Q1*

Q2*

Q3*

The SK100LVE111E, as with most other ECL devices,

can be operated from a positive VCC supply in PECL mode.

This allows the LVE111E to be used for high performance

clock distribution in +3.3V systems. Designers can take

advantage of the LVE111E’s performance to distribute low

skew clocks across the back plane or the board. In a

PECL environment, series or Thevenin line terminations

are typically used as they require no additional power

supplies. For systems incorporating GTL, parallel

termination offers the lowest power by taking advantage

of the 1.2V supply as a terminating voltage.

Q4*

IN*

Q5*

EN*

Q6*

Q7*

Q8*

The SK100LVE111 provides VBB output for either

single-ended use or as a DC bias for AC coupling to

Revision 2/ April 30, 2002

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SK100LVE111E

HIGH-PERFORMANCE PRODUCTS

Pin Description

Pin Names

Function

IN, IN*

Differential Input Pair

Enable

EN*

Q0, Q0* - Q8, Q8*

VBB

Differential Outputs

Reference Output Voltage

Positive Supply

VCC, VCCO

VEE

Negative Supply

Pinout

VEE

EN*

Q3*

28 Lead PLCC

VCC

IN*

VCC0

Q4*

(Top View)

VBB

N/C

Q5*

Revision 2/ April 30, 2002

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SK100LVE111E

HIGH-PERFORMANCE PRODUCTS

Package Information

28 Pin PLCC Package

Y BRK

–N–

0.007 (0.180)

L - M

0.007 (0.180)

L - M

PIN Descriptions

–L–

– M –

0.010 (0.250) T L - M

0.007(0.180)

L – M

0.007 (0.180) ^MT L – M

0.007 (0.180)

L – M

View S

0.004 (0.100)

–T– SEATING PLANE

VIEW S

0.010 (0.250)

L – M

0.007 (0.180)

T L – M

NOTES:

INCHES

MILLIMETERS

1. Datums -L-, -M-, and -N- determined where top of lead

shoulder exits plastic body at mold parting line.

2. DIM G1, true position to be measured at Datum -T-,

Seating Plane.

3. DIM R and U do not include mold flash. Allowable mold flash

is 0.010 (0.250) per side.

DIM

MIN

MAX

0.495

0.180

0.110

0.019

MIN

12.32

4.20

MAX

12.57

4.57

0.485

0.165

0.090

0.013

2.29

2.79

0.33

0.48

4. Dimensioning and tolerancing per ANSI Y14.5M, 1982.

5. Controlling Dimension: Inch.

6. The package top may be smaller than the package bottom by

0.050 BSC

1.27 BSC

0.026

0.020

0.025

0.450

0.042

0.032

0.66

0.51

0.64

11.43

1.07

0.81

up to 0.012 (0.300). Dimensions R and U are determined at

the outermost extremes of the plastic body exclusive of mold

flash, tie bar burrs, gate burrs and interlead flash, but

including any mismatch between the top and bottom of the

plastic body.

0.456

0.048

0.056

0.020

10^o

11.58

1.21

1.42

0.50

10^o

7. Dimension H does not include Dambar protrusion or

intrusion. The Dambar protrusion(s) shall not cause the H

dimension to be greater than 0.037 (0.940). The Dambar

intrusion(s) shall not cause the H dimension to be smaller

than 0.025 (0.635).

2^o

0.410

0.040

0.430

10.42

1.02

10.92

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Revision 2/ April 30, 2002

SK100LVE111E

HIGH-PERFORMANCE PRODUCTS

DC Characteristics

SK100LVE111E LVPECL DC Electrical Characteristics (Note 1)

(V – V

= 3.0V to 3.8V; VOUT Loaded 50Ω to V – 2.0V)

TA = - 40 C

TA = 0 C

TA = 25 C

TA = 85 C

Symbol

Characteristic

Min

Typ

Max

2420

1745

2420

1825

2.04

Min

Typ

Max

2420

1680

2420

1825

2.04

Min

Typ

Max

2420

1680

2420

1825

2.04

Min

Typ

Max

2420

1680

2420

1825

2.04

Unit

Output HIGH Voltage

2215

1470

2135

1490

2345

1595

2275

1490

2135

1490

2345

1595

2275

1490

2135

1490

2345

1595

2275

1490

2135

1490

2345

1595

Output LOW Voltage

Input HIGH Voltage

Input LOW Voltage

Output Reference Voltage

1.92

-150

1.92

-150

1.92

-150

1.92

-150

Input Current (Diff)

(SE)

150

µA

Power Supply Current

AC Characteristics

SK100LVE111E AC Electrical Characteristics

(V – V

= 3.0V to 3.8V; VOUT Loaded 50Ω to V – 2.0V)

TA = - 40 C

TA = 0 C

TA = + 25 C

TA = + 85 C

Symbol

Characteristic

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

3, 4

Propagation Delay to Output

IN (Differential)

IN (Single-Ended)

EN*

400

440

490

450

580

610

720

400

440

490

460

590

580

630

740

670

410

470

500

480

600

620

630

760

730

470

550

530

555

665

645

695

790

750

PLH

PHL

Within-Device Skew

Part-to-Part Skew (Diff)

200

skew

Minimum Input Swing

500

1000

500

1000

500

1000

500

1000

VEE +

1.5

VCC – VEE +

0.4

VCC – VEE +

0.4

VCC – VEE +

0.4

VCC –

0.4

Common Mode Range

CMR

1.5

t , t

Rise/Fall Time (20% to 80%)

290

425

550

280

400

540

250

385

520

230

320

400

Revision 2/ April 30, 2002

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SK100LVE111E

HIGH-PERFORMANCE PRODUCTS

AC Characteristics

1. 100LVE111E circuits are designed to meet the DC specifications shown in the table where transverse

airflow greater than 500 lfpm is maintained.

2. These values are for VCC = 3.3V. Level Specifications will vary 1:1 with VCC.

3. The differential propagation delay is defined as the delay from the crossing points of the differential

input signals to the crossing point of the differential output signals.

4. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to

the 50% point of the output signal.

5. The within-device skew is defined as the worst case difference between any two similar delay paths

within a single device.

6. V (min) is defined as the minimum input differential voltage which will cause no increase in the

propagation delay. The V (min) is AC limited for the LVE111E as a differential input as low as 500

mV will still produce full ECL levels at the output.

7. CMR range is referenced to the most positive side of the differential input signal. Normal operation is

obtained if the high level falls within the specified range and the peak-to-peak voltage lies between

VPP

and 1V. The lower end of the CMR range varies 1:1 with VEE and is equal to VEE + 1.5V.

(min)

8. For part ordering description, see HPP Part Ordering Information Data Sheet.

Application Notes

AN1002 - Interfacing Between ECL / LVECL / PECL / LVPECL - to - TTL / LVTTL / CMOS / LVCMOS

AN1003 - Termination Techniques for ECL / LVECL / PECL / LVPECL Devices

AN1004 - Interfacing Between LVDS and ECL / LVECL / PECL / LVPECL

AN1005 - Using ECL / LVECL Devices as PECL / LVPECL

AN1006 - Designing with 10K and 100K ECL / PECL Devices

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Revision 2/ April 30, 2002

SK100LVE111E

HIGH-PERFORMANCE PRODUCTS

Ordering Information

Ordering Code

Package ID

28-PLCC

SK100LVE111EPJ

SK100LVE111EPJT

28-PLCC

Contact Information

Semtech Corporation

High-Performance Products Division

Division Headquarters

10021 Willow Creek Road

San Diego, CA 92131

Phone: (858) 695-1808

Marketing Group

1111 Comstock Street

Santa Clara, CA 95054

Phone: (408) 566-8776

FAX:

(858) 695-2633

FAX: (408) 566-8759

Revision 2/ April 30, 2002

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SK100LVE111EPJT [SEMTECH]

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