SK10E111 [SEMTECH]
1:9 Differential Clock Driver; 1 ： 9差分时钟驱动器
| 型号： | SK10E111 |
| 厂家： | 
SEMTECH CORPORATION |
| 描述： | 1:9 Differential Clock Driver |
| 文件： | 总6页 (文件大小：155K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SK10/100E111
1:9 Differential
Clock Driver
HIGH-PERꢀORMANCE PRODUCTS
ꢀeatures
Description
• Low Skew
• Guaranteed Skew Spec
• Differential Design
The SK10E/100E111 is a low skew 1-to-9 differential
driver designed with clock distribution in mind. It accepts
one signal input which can be either differential or single-
ended if the VBB output is used. The signal is fanned
out to 9 identical differential outputs. An enable input
is also provided. A HIGH disables the device by forcing
all Q outputs LOW and all Q* outputs HIGH.
• V Output
BB
• Enable Input
• Extended 100E V Range of –4.2 to –5.5V
• 75KΩ Internal Input Pulldown Resistors
• Fully Compatible with MC10E111 and
MC100E111
EE
The device is specifically designed, modeled, and
produced with low skew as the key goal. Optimal design
and layout serve to minimize gate-to-gate skew within-
device,and characterization is used to determine process
control limits that ensure consistent tpd distributions
from lot to lot. The net result is a dependable, guaranteed
low skew device.
• Specified Over Industrial Temperature Range:
–40oC to 85oC
• ESD Protection of >4000V
• Available in 28-pin PLCC Package
ꢀunctional Block Diagram
To ensure that the tight skew specification is met, it is
necessary that both sides of the differential output are
terminated into 50Ω,even if only one side is being used.
In most applications, all nine differential pairs will be
used and therefore terminated. In the case where fewer
than nine pairs are used, it is necessary to terminate at
least the output pairs on the same package side (i.e.
Q0
Q0*
Q1
Q1*
sharing the same V
) as the pair(s) being used on
CCO
Q2
that side in order to maintain minimum skew. Failure to
do this will result in small degradations of propagation
delay (on the order of 10–20ps) of the output(s) being
used which, while not being catastrophic to most designs,
will mean a loss of skew margin.
Q2*
Q3
Q3*
Q4
Q4*
IN
Q5
Q5*
Q6
Q6*
Q7
Q7*
Q8
V
BB
Q8*
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Revision 1 /ꢀebruary 13, 2001
1
SK10/100E111
HIGH-PERꢀORMANCE PRODUCTS
PIN Description
Pinout
25
24
23
22
21
20
19
VEE
EN*
IN
26
27
28
18
17
16
15
14
13
12
Q3
Q3*
Q4
28 Lead PLCC
VCC
IN*
1
2
3
4
VCC0
Q4*
Q5
(Top View)
VBB
N/C
Q5*
5
6
7
8
9
10
11
Pin Names
Pin
ꢀunction
IN, IN*
EN*
Differential Input Pair
Enable
Q0, Q0* - Q8, Q8* Differential Outputs
VBB VBB Output
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2
Revision 1 /ꢀebruary 13, 2001
SK10/100E111
HIGH-PERꢀORMANCE PRODUCTS
Package Information
Y BRK
NOTES:
–N–
1. Datums –L–, –M–, and –N– determined where top of
lead shoulder exits plastic body at mold parting line.
2. DIM G1, true position to be measured at Datum –T–,
Seating Plane.
3. DIM R and U do not include mold flash. Allowable
mold flash is 0.010 (0.250) per side.
D
–L–
PIN Descriptions
– M –
4. Dimensioning and tolerancing per ANSI Y14.5M,
1982.
5. Controlling Dimension: Inch.
D
W
6. The package top may be smaller than the package
bottom by up to 0.012 (0.300). Dimensions R and U
are determined at the outermost extremes of the
plastic body exclusive of mold flash, tie bar burrs, gate
burrs and interlead flash, but including any mismatch
betweeen the top and bottom of the plastic body.
7. Dimension H does not include Dambar protrusion or
intrusion. The Dambar protrusion(s) shall not cause
the H dimension to be greater than 0.037 (0.940).
The Dambar intrusion(s) shall not cause the H
dimension smaller than 0.025 (0.635).
V
28
1
S
S
N
A
R
0.007 (0.180)
0.007 (0.180)
M
M
T
L – M
L – M
Z
S
S
N
T
C
E
0.004 (0.100)
G
–T– SEATING PLANE
J
G1
VIEW S
S
S
S
N
0.010 (0.250)
T
L – M
B
M
S
S
0.007 (0.180)
T
L - M
N
INCHES
MIN
MILLIMETERS
U
M
S
S
N
0.007 (0.180)
+
T
L - M
DIM
A
MAX
0.495
0.495
0.180
0.110
0.019
MIN
12.32
12.32
4.20
MAX
12.57
12.57
4.57
Z
0.485
0.485
0.165
0.090
0.013
B
C
E
2.29
2.79
+
&
0.33
0.48
0.010 (0.250)S T L - M
S
N
S
G1
X
G
H
J
0.050 BSC
0.032
1.27 BSC
0.026
0.020
0.025
0.450
0.450
0.042
0.042
0.042
--
0.66
0.51
0.64
11.43
11.43
1.07
1.07
1.07
--
0.81
--
--
K
--
--
0.007(0.180)
M
T
L – M
S
N
S
R
0.456
0.456
0.048
0.048
0.056
0.020
10o
11.58
11.58
1.21
1.21
1.42
0.50
10o
H
U
V
W
X
K1
Y
2o
2o
K
Z
G1
K1
0.410
0.040
0.430
--
10.42
1.02
10.92
--
S
S
0.007 (0.180)
M
T L – M
N
F
VIEW S
Revision 1 /ꢀebruary 13, 2001
3
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SK10/100E111
HIGH-PERꢀORMANCE PRODUCTS
DC Characteristics
SK10/100E111 DC Electrical Characteristics (Notes 1, 2)
(V
CC
– V
= 4.2V to 5.5V; VOUT Loaded 50Ω to V
– 2.0V)
CC
EE
TA = –40oC
TA = 0oC
TA = +25oC
TA = +85oC
Symbol
Characteristic
Min
Max
Min
Max
Min
Max
Min
Max
Unit
13
Output Reference Voltage
10EL
V
-1.43
-1.38
-1.30
-1.26
-1.38
-1.38
-1.27
-1.26
-1.35
-1.38
-1.25
-1.26
-1.31
-1.38
-1.19
-1.26
V
V
BB
100EL
Input Current (Diff)
(SE)
-150
150
150
-150
150
150
-150
150
150
-150
150
150
µA
µA
I
IN
I
Power Supply Current
64
64
64
64
mA
EE
AC Characteristics
SK10/100E111 AC Electrical Characteristics
(V
– V
= 4.2V to 5.5V; VOUT Loaded 50Ω to V
– 2.0V)
CC
EE
CC
TA = –40oC
TA = 0oC
TA = +25oC
Min Typ
TA = +85oC
Symbol Characteristic
Min
Typ
Max
Min
Typ
Max
Max
Min
Typ
Max Unit
t
t
Propagation Delay to
Output
PLH
PHL
5
IN (Diff)
IN (SE)
475
280
400
400
630
780
900
900
490
330
450
450
655
730
850
850
500
330
450
450
660
730
850
850
520
330
450
450
655
730
850
850
ps
ps
ps
ps
6
7
Enable
Disable
9
t
t
Setup Time
EN to IN
s
250
50
0
20
0
0
0
20
0
0
0
20
0
0
0
p
s
10
Hold Time
IN to EN
H
-200
0
-
20
0
-
20
0
-
20
ps
11
Release Time
EN* to IN
t
t
R
350
100
25
300
100
25
300
100
25
300
25
100
50
ps
ps
8
Within-Device Skew
75
50
50
skew
Minimum Input
12
Swing
V
V
250
1000 250
1000 250
1000 250
1000 mV
PP(AC)
CMR
VEE
+
1.6
VEE
VEE
VEE
Common Mode
4
VCC
+
VCC
+
VCC
+
VCC
V
0.4
Range
0.4
1.6
0.4
1.6
0.4
1.6
Rise/&all Time
20% to 80%
t , t
r
215
450
545
225
375
570
230
375
545
240
375
475
ps
f
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4
Revision 1 /ꢀebruary 13, 2001
SK10/100E111
HIGH-PERꢀORMANCE PRODUCTS
AC Characteristics (continued)
IN
IN
IN
IN*
IN*
IN*
t
t
r
s
t
h
EN*
EN*
50%
50%
50%
EN*
≤75 mV
≤75 mV
Q*
Q*
Q*
Q
Q
Q
≤75 mV
≤75 mV
Figure 3. Release Time
Figure 1. Setup Time
Figure 2. Hold Time
Notes:
1. 10E circuits are designed to meet the DC specifications shown in the table after thermal equilibrium has
been established. The circuit is in a test socket or mounted on a printed circuit board and transverse
airflow greater than 500 lfpm is maintained.
2. 100E circuits are designed to meet the DC specifications shown in the table where transverse airflow
greater than 500 lfpm is maintained.
3. Differential input voltage required to obtain a full ECL swing on the outputs.
4. V
range is referenced to the most positive side of the differential input signal. Normal operation is
CMR
obtained if the high level falls within the specified range and the peak-to-peak voltage lies between
VPP(min) and 1V. The lower end of VCMR range varies 1:1 with VEE and is equal to VEE+1.6V.
5. The differential propagation delay is defined as the delay from the crossing points of the differential
input signals to the crossing point of the differential output signals.
6. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to
the 50% point of the output signal.
7. Enable is defined as the propagation delay from the 50% point of a negative transition on EN* to the
50% point of a positive transition on Q (or a negative transition on Q). Disable is defined as the
propagation delay from the 50% point of a positive transition on EN* to the 50% point of a negative
transition on Q (or a positive transition on Q).
8. The within-device skew is defined as the worst case difference between any two similar delay paths
within a single device.
9. The setup time is the minimum time that EN must be asserted prior to the next transition of IN/IN to
prevent an output response greater than 75 mV to that IN/IN transition (see Figure 1).
10. The hold time is the minimum time that EN must remain asserted after a negative going IN or a positive
going IN* to prevent an output response greater than 75 mV to the IN/IN transition (see Figure 2).
11. The release time is the minimum time that EN must be deasserted prior to the next IN/IN* transition to
ensure an output response that meets the specified IN to Q propagation delay and output transition times
(see Figure 3).
12. V (min) is defined as the minimum input differential voltage which will cause no increase in the
PP
propagation delay. The V (min) is AC limited for the E111 as a differential input as low as 250 mV
PP
will still produce full ECL levels at the output.
13. Voltages referenced to VCC = 0V.
14. For standard ECL DC specifications, refer to the ECL Logic Family Standard DC Specifications Data
Sheet.
15. For part ordering descriptions, see HPP Part Ordering Information Data Sheet.
Revision 1 /ꢀebruary 13, 2001
5
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SK10/100E111
HIGH-PERꢀORMANCE PRODUCTS
Ordering Information
Ordering Code
SK10E111PJ
Package ID
28-PLCC
28-PLCC
28-PLCC
28-PLCC
Temperature Range
Industrial
SK10E111PJT
SK100E111PJ
SK100E111PJT
Industrial
Industrial
Industrial
Contact Information
Semtech Corporation
High-Performance Products Division
Division Headquarters
10021 Willow Creek Road
San Diego, CA 92131
Marketing Group
1111 Comstock Street
Santa Clara, CA 95054
Phone: (408) 566-8776
Phone: (858) 695-1808
FAX:
(858) 695-2633
FAX: (408) 727-8994
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6
Revision 1 /ꢀebruary 13, 2001
相关型号：
SK10E142JT
Parallel In Parallel Out, 10E Series, 9-Bit, Right Direction, True Output, ECL, PQCC28, PLASTIC, LCC-28
SEMTECH
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