SGM61630 [SGMICRO]
60V, 3A Buck Converter with 50μA IQ;
| 型号： | SGM61630 |
| 厂家： | 
Shengbang Microelectronics Co, Ltd |
| 描述： | 60V, 3A Buck Converter with 50μA IQ |
| 文件： | 总23页 (文件大小：1673K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SGM61630
60V, 3A Buck Converter with 50μA IQ
GENERAL DESCRIPTION
FEATURES
The SGM61630 is a current mode controlled Buck
regulator with 4.3V to 60V input range and 3A
continuous output current. The device suits various
applications of industry, which demands power
conditioning from unregulated sources. A 140mΩ RDSON
MOSFET is integrated as high-side switch. The ultra-low
50μA (TYP) quiescent current and low shutdown current
of only 2μA (TYP) make it a suitable choice for
battery-powered applications. Switching frequency can
be selected over a wide range (200kHz to 2500kHz) to
allow desired tradeoff between efficiency and
component sizes. There is also the internal loop
compensation that simplifies compensation network
design, and requires less external components, saving
user design time and cost. With precision enable input,
regulator control is simplified, as well as system power
sequencing. Protection against over-voltage transient is
provided to limit the startup or other transient
overshoots. Secure operation in overload conditions is
ensured by thermal shutdown protection and cycle-by-
cycle current limit.
● 4.3V to 60V Input Range
● 3A Continuous Output Current
● Ultra-Low 50μA Operating Quiescent Current
● 140mΩ High-side MOSFET
● Minimum Switching-On Time: 100ns
● Current Mode Control
● SGM61630A: Soft-Start Version
● SGM61630B: Power-Good Version
● Adjustable Switching Frequency from 200kHz to
2500kHz
● Frequency Synchronization to External Clock
● Easy-to-Use Internal Compensation
● Support High Duty Cycle Operation
● Precision Enable Input
● 2μA Shutdown Current
● Thermal, Over-Voltage and Short Protection
● Available in a Green SOIC-8 (Exposed Pad) Package
APPLICATIONS
Industrial Power Supplies
Telecom and Datacom Systems
The SGM61630 is available in a Green SOIC-8 (Exposed
General Purpose Wide Input Voltage Regulation
Pad) package.
TYPICAL APPLICATION
4.3V to 60V
VIN
EN
BOOT
CIN
CBOOT
L
5V/3A
SW
D
SGM61630A
RFBT
COUT
RT/SYNC
FB
RT
RFBB
SS
GND
CSS
Figure 1. SGM61630A Typical Application
SG Micro Corp
MARCH 2023 - REV.A.1
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SGM61630
60V, 3A Buck Converter with 50μA IQ
PACKAGE/ORDERING INFORMATION
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
DESCRIPTION
ORDERING
NUMBER
PACKAGE
MARKING
PACKING
OPTION
MODEL
SGM
MCLXPS8
XXXXX
SGM
MCMXPS8
XXXXX
SOIC-8
(Exposed Pad)
SGM61630A
SGM61630B
SGM61630AXPS8G/TR
Tape and Reel, 4000
Tape and Reel, 4000
-40℃ to +125℃
-40℃ to +125℃
SOIC-8
(Exposed Pad)
SGM61630BXPS8G/TR
MARKING INFORMATION
NOTE: XXXXX = Date Code, Trace Code and Vendor Code.
X X X X X
Vendor Code
Trace Code
Date Code - Year
Green (RoHS & HSF): SG Micro Corp defines "Green" to mean Pb-Free (RoHS compatible) and free of halogen substances. If
you have additional comments or questions, please contact your SGMICRO representative directly.
OVERSTRESS CAUTION
ABSOLUTE MAXIMUM RATINGS
Input Voltages
Stresses beyond those listed in Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to
absolute maximum rating conditions for extended periods
may affect reliability. Functional operation of the device at any
conditions beyond those indicated in the Recommended
Operating Conditions section is not implied.
VIN, EN to GND ............................................. -0.3V to 65V
BOOT to GND................................................ -0.3V to 71V
SS (SGM61630A) to GND................................ -0.3V to 5V
PGOOD (SGM61630B) to GND....................... -0.3V to 5V
FB to GND..................................................... -0.3V to 6.5V
RT/SYNC to GND ......................................... -0.3V to 6.5V
Output Voltages
BOOT to SW ...............................................................6.5V
SW to GND .................................................... -0.3V to 65V
SW to GND (10ns Transient) ............................ -3V to 65V
Package Thermal Resistance
SOIC-8 (Exposed Pad), θJA ...................................... 41℃/W
Junction Temperature...................................................150℃
Storage Temperature Range.......................-65℃ to +150℃
Lead Temperature (Soldering, 10s)............................+260℃
ESD Susceptibility
ESD SENSITIVITY CAUTION
This integrated circuit can be damaged if ESD protections are
not considered carefully. SGMICRO recommends that all
integrated circuits be handled with appropriate precautions.
Failureto observe proper handlingand installation procedures
can cause damage. ESD damage can range from subtle
performance degradation tocomplete device failure. Precision
integrated circuits may be more susceptible to damage
because even small parametric changes could cause the
device not to meet the published specifications.
HBM.............................................................................6000V
CDM ............................................................................1000V
DISCLAIMER
SG Micro Corp reserves the right to make any change in
RECOMMENDED OPERATING CONDITIONS
Buck Regulator
VIN...................................................................4.3V to 60V
BOOT................................................................65V (MAX)
FB .........................................................................0V to 5V
Control
circuit design, or specifications without prior notice.
EN.......................................................................0V to 60V
RT/SYNC ..............................................................0V to 5V
SS (SGM61630A) to GND.....................................0V to 5V
PGOOD (SGM61630B) to GND............................0V to 5V
Switching Frequency Range
RT Mode ............................................. 200kHz to 2500kHz
SYNC Mode ........................................ 210kHz to 2400kHz
Operating Junction Temperature Range......-40℃ to +125℃
SG Micro Corp
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2
SGM61630
60V, 3A Buck Converter with 50μA IQ
PIN CONFIGURATIONS
SGM61630A (TOP VIEW)
SGM61630B (TOP VIEW)
BOOT
1
8
SW
BOOT
1
8
SW
VIN
EN
2
3
7
6
GND
SS
VIN
EN
2
3
7
6
GND
Exposed
Pad
Exposed
Pad
PGOOD
RT/SYNC
4
5
FB
RT/SYNC
4
5
FB
SOIC-8 (Exposed Pad)
SOIC-8 (Exposed Pad)
PIN DESCRIPTION
PIN
NAME
I/O
DESCRIPTION
SGM61630A
SGM61630B
Bootstrap Input (for N-MOSFET Gate Driver Supply Voltage). Connect this pin to
SW pin with a 0.1μF ceramic capacitor. The MOSFET will be turned off if the BOOT
capacitor voltage drops below its BOOT-UVLO level to get the capacitor voltage
refreshed.
1
1
BOOT
I
Supply Input. Connect VIN to a power source with 4.3V to 60V output voltage
range. Decouple VIN to GND as close as possible to the catch diode anode and
the device with a high frequency, and low ESR ceramic capacitor (X5R or higher
grade is recommended).
Active High Enable Input. Float or pull up to VIN pin to enable, or pull down below
1.12V to disable the device. Input UVLO threshold can be programmed through
using a resistor divider from VIN pin.
2
3
2
3
VIN
EN
P
I
Resistor Timing and External Clock. Setting frequency by the external RT resistor
or external SYNC clock, refer to Synchronization to RT/SYNC Pin for more details.
Feedback Pin for Setting the Output Voltage. The SGM61630 regulates the FB pin
to 0.75V. Connect a feedback resistor divider tap to this pin.
4
5
4
5
RT/SYNC
FB
I
I
SS Pin for Soft-Start Version. Connect an external capacitor (CSS) between this pin
and the GND to set the soft-start time.
6
—
SS
O
PGOOD Pin for Power-Good Version. Open drain output for power-good flag, use
a 10kΩ to 100kΩ pull-up resistor to logic rail or other DC voltage no higher than 5V.
—
6
7
PGOOD
GND
7
G
P
Ground Pin.
Switching Node of the Converter (Source of the Internal MOSFET). Connect it to
the cathode of the external power diode (catch diode), the bootstrap capacitor and
the inductor.
8
8
SW
Exposed
Pad
Exposed Pad. It helps cooling the device junction and must be connected to GND
pin for proper operation.
—
—
G
NOTE: I = input, O = output, G = ground, P = power.
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SGM61630
60V, 3A Buck Converter with 50μA IQ
ELECTRICAL CHARACTERISTICS
(TJ = -40℃ to +125℃, VIN = 4.3V to 60V, typical values are at TJ = +25℃, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Power Supply (VIN Pin)
Operation Input Voltage
VIN
VUVLO
VUVLO_HYS
ISHDN
4.3
3.6
60
V
V
Under-Voltage Lockout Threshold
Under-Voltage Lockout Threshold Hysteresis
Shutdown Supply Current
VIN rising
3.85
300
2
4.1
mV
μA
μA
3
TA = +25℃, VEN = 0V, VIN = 24V
TA = +25℃, VFB = 1.0V, VIN = 24V
Operating Quiescent Current (Non-Switching)
Enable (EN Pin)
IQ
50
VENH
VENL
1.08
1.03
1.17
1.12
-4.7
-1.0
-3.7
1.26
1.20
V
V
EN Threshold Voltage
EN Pin Current
Enable threshold +50mV
IEN_PIN
IEN_HYS
μA
μA
Enable threshold -50mV
EN Hysteresis Current
Soft-Start (SGM61630A Only)
External soft-start version only,
TA = +25℃
For power-good version only
SS Pin Current
ISS
tSS
3
4
μA
Internal Soft-Start Time
ms
Power-Good (SGM61630B Only)
Power-good (% of VFB
)
95
92
%
%
%
%
%
nA
V
PGOOD Flag Under-Voltage Tripping Threshold
PGOOD Flag Over-Voltage Tripping Threshold
VPG_UV
Power-bad (% of VFB
)
)
Power-bad (% of VFB
110
107
3
VPG_OV
Power-good (% of VFB
% of VFB
)
PGOOD Flag Recovery Hysteresis
PGOOD Leakage Current at High Level Output
PGOOD Voltage at Low Level Output
VIN for Valid PGOOD Output at a Minimum
Voltage Reference (FB Pin)
VPG_HYS
IPG
VPG_LOW
VIN_PG_MIN
VPull-Up = 5V
100
0.1
1
IPull-Up = 1mA
VPull-Up < 5V at IPull-Up = 100μA
V
0.745
0.741
0.750
0.750
0.763
0.765
V
V
TJ = +25℃
Feedback Voltage
VFB
TJ = -40℃ to +125℃
High-side MOSFET
On-Resistance
RDSON
VIN = 12V, VBOOT - VSW = 5V
VIN = 12V, open-Loop
140
4.8
255
6.0
mΩ
High-side MOSFET Current Limit
Current Limit
ILIMT
3.5
A
Thermal Performance
Thermal Shutdown Threshold
Hysteresis
TSHDN
THYS
170
20
℃
℃
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SGM61630
60V, 3A Buck Converter with 50μA IQ
ELECTRICAL CHARACTERISTICS (continued)
(TJ = -40℃ to +125℃, VIN = 4.3V to 60V, typical values are at TJ = +25℃, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Switching Characteristics
Switching Frequency
fSW
1666
210
2.0
1940
2209
2400
RT = 11.5kΩ
kHz
kHz
V
Switching Frequency Range at SYNC Mode
SYNC Input Clock High Level
fSYNC
VSYNC_R
SYNC Input Clock Low Level
Minimum SYNC Input Pulse Width
PLL Lock In Time
VSYNC_F
tSYNC_MIN
tLOCK_IN
tON-MIN
0.3
V
Measured at 500kHz
Measured at 500kHz
30
100
100
98
ns
μs
ns
%
Minimum Controllable On Time
Maximum Duty Cycle
DMAX
fSW = 200kHz
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SGM61630
60V, 3A Buck Converter with 50μA IQ
TYPICAL PERFORMANCE CHARACTERISTICS
TA = +25℃, VIN = 12V, VOUT = 5V, fSW = 500kHz, L = 10μH and COUT = 2 × 47μF, unless otherwise noted.
Quiescent Current vs. Input Voltage
Quiescent Current vs. Temperature
70
60
50
40
30
100
80
60
40
20
0
0
0
0
10
20
30
40
50
60
-60
-60
-60
-20
20
60
100
140
140
140
Temperature (℃)
Input Voltage (V)
Shutdown Current vs. Input Voltage
Shutdown Current vs. Temperature
10
8
10
8
6
6
4
4
2
2
0
0
10
20
30
40
50
60
-20
20
60
100
Temperature (℃)
Input Voltage (V)
Frequency vs. Resistance
Current Limit vs. Temperature
3000
2400
1800
1200
600
10
8
6
4
2
0
0
25
50
75
100
125
150
-20
20
60
100
Resistance (kΩ)
Temperature (℃)
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SGM61630
60V, 3A Buck Converter with 50μA IQ
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
TA = +25℃, VIN = 12V, VOUT = 5V, fSW = 500kHz, L = 10μH and COUT = 2 × 47μF, unless otherwise noted.
UVLO Rising vs. Temperature
UVLO Hysteresis vs. Temperature
8
6
4
2
0
500
400
300
200
100
0
-60
-20
20
60
100
140
-60
-20
20
60
100
140
Temperature (℃)
Temperature (℃)
Efficiency vs. Output Current
Load Regulation
100
0.5
0.3
80
60
40
20
0
0.1
-0.1
-0.3
-0.5
— VIN = 12V
— VIN = 24V
— VIN = 48V
— VIN = 12V
— VIN = 24V
— VIN = 48V
VOUT = 5V
0.01
0.1
1
10
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Output Current (A)
Output Current (A)
Voltage Reference vs. Temperature
1.0
0.9
0.8
0.7
0.6
0.5
-60
-20
20
60
100
140
Temperature (℃)
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SGM61630
60V, 3A Buck Converter with 50μA IQ
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
TA = +25℃, VIN = 12V, VOUT = 5V, fSW = 500kHz, L = 10μH and COUT = 2 × 47μF, unless otherwise noted.
PSM Mode
CCM Mode
AC Coupled
IOUT = 0A, Steady State
AC Coupled
IOUT = 3A, Steady State
VOUT
VOUT
VSW
VSW
IL
IL
Time (10ms/div)
DCM Mode
Time (2μs/div)
Load Transient
AC Coupled
IOUT = 200mA, Steady State
AC Coupled
IOUT = 0.6A to 2.4A to 0.6A, 2.5A/μs
VOUT
VOUT
VSW
IOUT
IL
Time (2μs/div)
Time (100μs/div)
Startup by VIN
Startup by VIN
IOUT = 0A
IOUT = 3A
VOUT
VOUT
PG
PG
VSW
VSW
IL
IL
Time (2ms/div)
Time (2ms/div)
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SGM61630
60V, 3A Buck Converter with 50μA IQ
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
TA = +25℃, VIN = 12V, VOUT = 5V, fSW = 500kHz, L = 10μH and COUT = 2 × 47μF, unless otherwise noted.
Shutdown by VIN
Shutdown by VIN
IOUT = 3A
IOUT = 0A
VOUT
VOUT
PG
PG
VSW
VSW
IL
IL
Time (20ms/div)
Time (100μs/div)
Startup by EN
Startup by EN
IOUT = 3A
IOUT = 0A
VOUT
VOUT
EN
EN
VSW
VSW
IL
IL
Time (1ms/div)
Time (1ms/div)
Shutdown by EN
Shutdown by EN
IOUT = 0A
IOUT = 3A
VOUT
VOUT
EN
EN
VSW
VSW
IL
IL
Time (500ms/div)
Time (50μs/div)
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SGM61630
60V, 3A Buck Converter with 50μA IQ
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
TA = +25℃, VIN = 12V, VOUT = 5V, fSW = 500kHz, L = 10μH and COUT = 2 × 47μF, unless otherwise noted.
SCP Entry
SCP Recovery
IOUT = 3A
VOUT
IOUT = 3A
VOUT
VSW
IL
VSW
IL
Time (50μs/div)
Time (1ms/div)
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SGM61630
60V, 3A Buck Converter with 50μA IQ
FUNCTIONAL BLOCK DIAGRAM
SGM61630B Only
PGOOD
EN
VIN
Thermal
Shutdown
UVLO
Logic
Enable
Comparator
Shutdown
Shutdown
Logic
UV
OV
Enable
Threshold
Voltage
Reference
Boot
Charge
Boot
UVLO
Error
Amplifier
PWM
Comparator
FB
BOOT
PWM Control
Logic
Comp
Components
SGM61630A Only
Slope
Compensation
Shutdown
SW
Frequency
Foldback
VFB
SS
Reference
DAC for internal
Soft-Start
Maximum
Clamp
Oscillator
with PLL
GND
RT/SYNC
NOTE: SS pin is for the SGM61630A version and PGOOD pin is for the SGM61630B version.
Figure 2. SGM61630 Block Diagram
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SGM61630
60V, 3A Buck Converter with 50μA IQ
DETAILED DESCRIPTION
Overview
Enable Input and UVLO Adjustment
The SGM61630 is a 60V Buck converter with
integrated high-side N-MOSFET (140mΩ) power switch
and 3A continuous output current capability. The
minimum operating input voltage of the device is 4.3V.
The quiescent current is 50μA (TYP). When the device
is disabled, the shutdown current reduces to 2μA.
An internal current source pull-up keeps the EN pin
voltage at high state by default. The device will enable
if the EN pin voltage exceeds the enable threshold of
1.17V and VIN exceeds its UVLO threshold. The device
will disable if the EN voltage is externally pulled low or
the VIN pin voltage falls below its UVLO threshold.
The SGM61630 uses peak current mode control with
power-save mode at light loads to achieve high
efficiency. The device is internally compensated, which
reduces design time.
If an application requires a higher VIN UVLO threshold,
an external VIN UVLO adjustment circuit is
recommended in Figure 3. Figure 3 shows how UVLO
and hysteresis are increased using REN1 and REN2. A
3.7μA additional current is injected to the divider when
EN pin voltage exceeds VENH (1.17V TYP) to provide
hysteresis and it will be removed when EN pin voltage
is below VENL (1.12V TYP). Use Equations 1 and 2 to
calculate these resistors. VSTART is the input start
(turn-on) threshold voltage and VSTOP is the input stop
(turn-off) threshold voltage.
The EN pin is internally pulled up by a current source
that can keep the device enable if EN pin is floating. It
can also be used to increase the input UVLO threshold
using a resistor divider.
The bootstrap diode is integrated and only a small
capacitor between BOOT and SW pins (CBOOT) is
needed for the N-MOSFET gate driving bias. A
separate UVLO circuit monitors CBOOT voltage and
turns the high-side switch off if this voltage falls below a
preset threshold.
VSTART
(VSTART -VSTOP )-VEN_HYS
×
VENH
REN1
=
1μA
3.7μA+VEN_HYS
×
VENH
(1)
(2)
The switching frequency is adjusted using a resistor to
ground connected to the RT/SYNC pin. It is also can be
synchronized to an external clock signal with 210kHz to
2400kHz.
VENH
VSTART - VENH
REN1
REN2
=
+1μA
Over-voltage protection (OVP) circuit is designed to
minimum the output over-voltage transients. When this
comparator detects an OVP (VFB > 110% × VREF), the
switch is kept off until the VFB falls below 107% of the
VREF. The SS pin internal current source allows
soft-start time adjustments with a small external
capacitor. During startup and over-current, the
frequency is reduced (frequency fold-back) to allow
easy maintenance of low inductor current. The thermal
shutdown provides an additional protection in fault
conditions.
VIN
REN1
1μA
3.7μA
+
-
EN
REN2
1.17V
Minimum Input Voltage (4.3V) and UVLO
The recommended minimum operating input voltage is
4.3V. It may operate with lower voltages that are above
the VIN rising UVLO threshold (3.85V TYP). If VIN falls
below its falling UVLO threshold, the device will stop
switching.
Figure 3. VIN UVLO Adjustment Circuit
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SGM61630
60V, 3A Buck Converter with 50μA IQ
DETAILED DESCRIPTION (continued)
Switching Frequency and Timing Resistor
(RT/SYNC Pin)
When the bootstrap voltage falls below the UVLO
threshold, the high-side switch is turned off, and the
integrated low-side switch is turned on to recharge the
BOOT capacitor. After the recharge, the high-side
switch is turned on again to regulate the output.
The switching frequency can be set from 200kHz to
2500kHz by a timing resistor (RT) placed between the
RT/SYNC and GND pins. There is an internal bias
voltage (0.5V TYP) on the RT/SYNC pin during the RT
mode and must have a resistor to ground to set the
switching frequency. Use Equation 3 to find the RT
resistance for any desired switching frequency (fSW).
External Soft-Start Adjustment
(SGM61630A Only)
The SGM61630A has an external soft-start (SS) pin for
adjustable startup time. It is recommended to add a
soft-start capacitor (CSS) between the SS and GND pins
to set the soft-start time. The internal ISS = 3μA current
charges CSS and provides a linear voltage ramp on the
SS pin. Use Equation 4 to calculate the soft-start time.
-0.918
fSW kHz =17700×R kΩ
(
)
(
)
T
(3)
Synchronization to RT/SYNC Pin
The internal oscillator also can synchronize to an
external logic clock applied to the RT/SYNC pin (see
Figure 4) in the 210kHz to 2400kHz range. The SW
rising edge (switch turn-on) is synchronized with the
SYNC falling edge. The SYNC low and high levels must
be less than 0.3V and more than 2.0V and have a pulse
width larger than 30ns. So when the SYNC source is
removed, the DC resistance seen between the
RT/SYNC and GND pins determines the default
switching frequency (fSYNC).
CSS (nF)× VREF (V)
(4)
tSS (ms) =
ISS (μA)
Power-Good (SGM61630B Only)
The SGM61630B has a power-good (PGOOD) pin for
indicate whether the output voltage in the desired level.
The PGOOD pin is open-drain output that requires 10kΩ
to 100kΩ resistor pulled up to an DC voltage(not
exceeds 5V).
As shown in Figure 5, when the FB voltage is within the
power-good range, the PGOOD switch is turned off and
the PGOOD pin is pulled up to high. When the FB
voltage is outside the power-good range, the PGOOD
switch is turned on and the PGOOD pin is pulled down
to low.
SGM61630
PLL
Logic
Clock
Source
RT/SYNC
RT
Figure 4. Synchronization to External Clock
VREF
110%
107%
Low Dropout Operation and Bootstrap
Gate Driving (BOOT Pin)
95%
92%
An internal regulator provides the bias voltage for gate
driver using a 0.1μF ceramic capacitor. X5R or better
dielectric types are recommended. The capacitor must
have a 10V or higher voltage rating. The BOOT
capacitor is refreshed when the high-side switch is off
and the external low-side diode conducts.
PGOOD
High
Low
The SGM61630 operates at maximum duty cycle when
input voltage is closed to output voltage if the bootstrap
voltage (VBOOT - VSW) is greater than its UVLO threshold.
Figure 5. Power-Good Flag
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SGM61630
60V, 3A Buck Converter with 50μA IQ
DETAILED DESCRIPTION (continued)
Slope Compensation
The natural OCP of the peak current mode control may
not be able to provide a complete protection when an
output short-circuit occurs and an extra protection
mechanism for short-circuit is needed. During an output
short, inductor current may runaway above
over-current limits because of the high input voltage
and the minimum controllable on-time. During the
output short, the inductor current decreases slowly
because a small negative diode forward voltage
appears across the inductor during the off-time, as a
result the inductor current cannot be reset. In these
conditions, current can saturate the inductor and the
current may even increase higher until the device is
damaged. In the SGM61630, this problem is effectively
solved by increasing the off-time during short-circuit by
reducing the switching frequency (frequency fold-back).
As the output voltage drops and the FB pin voltage falls
from 0.75V to 0V, the frequency will be divided by 1, 2,
4 and 8.
Without implementing some slope compensation, the
PWM pulse widths will be unstable and oscillatory at
duty cycles above 50%. To avoid sub-harmonic
oscillations in this device, an internal compensation
ramp is added to the measured switch current before
comparing it with the control signal by the PWM
comparator.
Power-Save Mode
At light loads the SGM61630 enters Pulse-Skipping
Mode (PSM) to keep its high efficiency by lowering the
number of switching pulses. When the peak inductor
current is below PSM current threshold, the
corresponding internal COMP voltage (VCOMP) will be
lower than 410mV. The device will enter PSM in such
conditions. In PSM mode, VCOMP is internally clamped
at 350mV that inhibits the high-side MOSFET switching,
the device draws only 50μA (TYP) input quiescent
current. The device can exit PSM if VCOMP rises above
410mV.
Over-Voltage Transient Protection
When an overload or an output fault condition is
removed, large overshoots may occur on the output.
The SGM61630 includes OVP circuit to reduce such
over-voltage transients. If VFB voltage exceeds 110% of
the VREF threshold, the high-side switch is turned off.
When it returns below 107% of the VREF, the switch is
released again.
Over-Current Protection and Frequency
Fold-back
Over-current protection (OCP) is naturally provided by
current mode control. In each cycle, the HS current
sensing starts a short time (blanking time) after the HS
switch is turned on. The sensed HS switch current is
continuously compared with the current limit threshold
and when the HS current reaches to that threshold, the
HS switch is turned off. If the output is overloaded, VOUT
drops and VCOMP is increases by EA to compensate that.
However, the EA output (VCOMP) is clamped to a
maximum value.
Thermal Shutdown (TSD)
If the junction temperature (TJ) exceeds +170℃, the
TSD protection circuit will stop switching to protect the
device from overheating. The device will automatically
restart with a power up sequence when the junction
temperature drops below +150℃.
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SGM61630
60V, 3A Buck Converter with 50μA IQ
APPLICATION INFORMATION
A typical application circuit for the SGM61630A as a Buck converter is shown in Figure 6. It is used for converting a
6V to 60V supply voltage to a lower voltage level supply voltage (5V) suitable for the system.
Typical Application
C5
0.1μF
VIN = 6V to 60V
VIN
EN
BOOT
SW
VOUT = 5V
R1
310kΩ
L
C1
C3
C2
4.7μF
10μH
IOUT = 3A (MAX)
4.7μF
0.1μF
R2
61.2kΩ
D
C6
47μF
C7
47μF
SGM61630A
R4
(1)
CFF
57.6kΩ
GND
FB
RT/SYNC
R3
49.9kΩ
SS
C4
10nF
R5
EP
10.2kΩ
NOTE: 1. In low input voltage condition, CFF = 33pF is recommended.
Figure 6. 5V Output SGM61630A Design Example
Design Requirements
Switching Frequency Selection
The design parameters given in Table 1 are used for
Several parameters such as losses, inductor and
capacitors sizes and response time are considered in
selection of the switching frequency. Higher frequency
increases the switching and gate charge losses and
lower frequency requires larger inductance and
capacitances and results in larger overall physical size
and higher cost. Therefore, a tradeoff is needed
between losses and component size. If the application
is noise-sensitive to a frequency range, the frequency
should be selected out of that range.
this design example.
Table 1. Design Parameters
Design Parameters
Input Voltage
Example Values
12V (TYP). 6V to 60V
Start Input Voltage (Rising VIN)
Stop Input Voltage (Falling VIN)
Input Ripple Voltage
7V
5.5V
360mV, 3% of VIN_TYP
5V
Output Voltage
Output Voltage Ripple
50mV, 1% of VOUT
3A
For this design, a lower switching frequency of 500kHz
is chosen and a 49.9kΩ resistor can be chosen for R3
according to Equation 3.
Output Current Rating
Transient Response 1.5A to 3A Load Step
Operation Frequency
250mV, 5% of VOUT
500kHz
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SGM61630
60V, 3A Buck Converter with 50μA IQ
APPLICATION INFORMATION (continued)
KIND factor (∆IL/IOUT). The inductor ripple current is
Input Capacitor Design
bypassed and filtered by the output capacitor and the
inductor DC current is passed to the output. Inductor
ripple is selected based on a few considerations. The
peak inductor current (IOUT + ∆IL/2) must have a safe
margin from the saturation current of the inductor in the
worst-case conditions especially if a hard-saturation
core type inductor (such as ferrite) is chosen. For peak
current mode converter, selecting an inductor with
saturation current above the switch current limit is
sufficient. The ripple current also affects the selection of
the output capacitor. COUT RMS current rating must be
higher than the inductor RMS ripple. Typically, a 20% to
40% ripple is selected (KIND = 0.2 ~ 0.4). Choosing a
higher KIND value reduces the selected inductance, but
a too high KIND factor may result in insufficient slope
compensation.
A high-quality ceramic capacitor (X5R or X7R or better
dielectric grade) must be used for input decoupling of
the SGM61630. At least 3μF of effective capacitance
(after derating) is needed on the VIN input. In some
applications additional bulk capacitance may also be
required for the VIN input, for example, when the
SGM61630 is more than 5cm away from the input
source. The VIN capacitor ripple current rating must also
be greater than the maximum input current ripple. The
input current ripple can be calculated using Equation 5
and the maximum value occurs at 50% duty cycle.
Using the design example values, IOUT = 3A, yields an
RMS input ripple current of 1.5A.
V - V
VOUT
(
)
= IOUT × D ×(1−D)
IN
OUT
(5)
ICIN_RMS = IOUT
×
×
V
V
IN
IN
For this design, a ceramic capacitor with at least 100V
voltage rating is required to support the maximum input
voltage. So, two 4.7µF/100V capacitors in parallel are
selected for VIN to cover all DC bias, thermal and aging
deratings. The input capacitance determines the
regulator input voltage ripple. This ripple can be
calculated from Equation 6. In this example, the total
effective capacitance of the two 4.7µF/100V capacitors
is around 8µF at 12V input, and the input voltage ripple
is 200mV.
V
IN_MAX - VOUT
VOUT
VIN_MAX × fSW
(7)
L =
×
IOUT ×KIND
In this example, the calculated inductance will be
10.18μH with KIND = 0.3, so the nearest larger
inductance of 10μH is selected. The ripple, RMS and
peak inductors current calculations are summarized in
Equations 8, 9 and 10 respectively.
VIN_MAX - VOUT
VOUT
VIN_MAX × fSW
(8)
ΔL =
×
L
IOUT ×D ×(1−D)
CIN × fSW
(6)
ΔIL2
ΔV
=
+IOUT ×ESRCIN
IN
IL _RMS = IO2 UT
+
(9)
12
It recommended to place an additional small size 0.1µF
ceramic capacitor right beside the VIN and GND pins
(anode of the diode) for high frequency filtering.
ΔIL
(10)
IL _PEAK = IOUT
+
2
Note that during startup, load transients or fault
conditions the peak inductor current may exceed the
calculated IL_PEAK. Therefore, it is always safer to
choose the inductor saturation current higher than the
current limit.
Inductor Design
Equation 7 is conventionally used to calculate the
output inductance of a Buck converter. Generally, a
smaller inductor is preferred to allow larger bandwidth
and smaller size. The ratio of inductor current ripple (∆IL)
to the maximum output current (IOUT) is represented as
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SGM61630
60V, 3A Buck Converter with 50μA IQ
APPLICATION INFORMATION (continued)
output capacitance that is needed to supply a current
External Diode
step (ΔIOUT) for at least 2 cycles until the control loop
responds to the load change with a maximum allowed
output transient of ΔVOUT (overshoot or undershoot).
An external power diode between the SW and GND
pins is needed for the SGM61630 to complete the
converter. This diode must tolerate the application’s
absolute maximum ratings. The reverse blocking
voltage must be higher than VIN_MAX and its peak
current must be above the maximum inductor current.
Choose a diode with small forward voltage drop for
higher efficiency. Typically, diodes with higher voltage
and current ratings have higher forward voltages. A
diode with a minimum of 60V reverse voltage is
preferred to allow input voltage transients up to the
rated voltage of the SGM61630.
2× ΔIOUT
fSW × ΔVOUT
(11)
COUT
>
where:
ΔIOUT is the change in output current.
ΔVOUT is the allowable change in the output voltage.
For example, if the acceptable transient from 1.5A to 3A
load step is 5%, by inserting ΔVOUT = 0.05 × 5V = 0.25V
and ΔIOUT = 1.5A, the minimum required capacitance
will be 24μF. Note that the impact of output capacitor
ESR on the transient is not considered in Equation 11.
For ceramic capacitors, the ESR is generally small
enough to ignore its impact on the calculation of ΔVOUT
transient. However, for aluminum electrolytic and
tantalum capacitors, or high current power supplies, the
ESR contribution to ΔVOUT must be considered.
Output Capacitor
Three primary criteria must be considered for design of
the output capacitor (COUT):
1. The converter pole location.
2. The output voltage ripple.
3. The transient response to a large change in load
current.
When the load steps down, the excess inductor current
will charge the capacitor and the output voltage will
overshoot. The catch diode current cannot discharge
The selected output capacitor value must satisfy all of
them. The desired transient response is usually
expressed as maximum overshoot, maximum
undershoot, or maximum recovery time of VOUT in
response to a large load step. Transient response is
usually the more stringent criteria in low output voltage
applications. The output capacitor must provide the
increased load current or absorb the excess inductor
current (when the load current steps down) until the
control loop can re-adjust the current of the inductor to
the new load level. Typically, it requires two or more
cycles for the loop to detect the output change and
respond (change the duty cycle). Another requirement
may also be expressed as desired hold-up time in
which the output capacitor must hold the output voltage
above a certain level for a specified period if the input
power is removed. It may also be expressed as the
maximum output voltage drop or rise when the full load
is connected or disconnected (100% load step).
Equation 11 can be used to calculate the minimum
C
OUT, so COUT must be large enough as given in
Equation 12 to absorb the excess inductor energy with
limited over-voltage. The excess energy absorbed in
the output capacitor increases the voltage on the
capacitor. The capacitor must be sized to maintain the
desired output voltage during these transient periods.
Equation 12 calculates the minimum capacitance
required to keep the output-voltage overshoot to a
desired value.
IO2 UT _H -IO2 UT _L
(VOUT + ΔVOUT )2 − VO2UT
(12)
COUT > L×
where:
IOUT_H is the high level of the current step.
IOUT_L is the low level of the current step.
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SGM61630
60V, 3A Buck Converter with 50μA IQ
APPLICATION INFORMATION (continued)
For example, if the acceptable transient from 3A to 1.5A
load step is 5%, by inserting ΔVOUT = 0.05 × 5V = 0.25V,
the minimum required capacitance will be 24.4μF.
UVLO Setting
The VIN UVLO can be programmed using an external
voltage divider on the EN pin of the SGM61630. In this
design R1 is connected between the VIN and EN pins
and R2 is connected between EN and GND (see Figure
6). The UVLO has two thresholds (Hysteresis), one for
power-up (turn-on) when the input voltage is rising and
one for power-down (turn-off) when the voltage is falling.
In this design, the turn-on (enable to start switching)
occurs when VIN rises above 7V (UVLO rising
threshold). When the regulator is working, it will not
stop switching (disabled) until the input voltage falls
below 5.5V (UVLO falling threshold). Equations 1 and 2
are provided to calculate the resistors. For this example,
the nearest standard resistor values are R1 = 310kΩ
and R2 = 61.2kΩ.
ΔIL
(13)
COUT
>
8× fSW × VOUT _RIPPLE
Note that the impact of output capacitor ESR on the
ripple is not considered in Equation 13. For a specific
output capacitance value, use Equation 14 to calculate
the maximum acceptable ESR of the output capacitor
to meet the output voltage ripple requirement.
VOUT _RIPPLE
1
(14)
ESRCOUT
<
−
ΔIL
8× fSW ×COUT
Higher nominal capacitance value must be chosen due
to aging, temperature, and DC bias derating of the
output capacitors. In this example, a 2 × 47μF/25V X5R
ceramic capacitor with 1.5mΩ of ESR is used. The
amount of ripple current that a capacitor can handle
without damage or overheating is limited. The inductor
ripple is bypassed through the output capacitor.
Equation 15 calculates the RMS current that the output
capacitor must support. In this example, it is 265mA.
Feedback Resistors Setting
Use resistor dividers (R4 and R5) to set the output
voltage using Equation 16.
VOUT − VREF
R = R ×
(16)
4
5
VREF
For this example, 57.6kΩ was selected for R4 and
10.2kΩ was selected for R5.
VOUT × VIN_MAX - VOUT
(
)
(15)
ICOUT_RMS
=
12 × VIN_MAX ×L× fSW
Bootstrap Capacitor Selection
It is recommended to use a 0.1μF high-quality ceramic
capacitor (X7R or X5R) with 10V or higher voltage
rating for the bootstrap capacitor (C5).
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SGM61630
60V, 3A Buck Converter with 50μA IQ
APPLICATION INFORMATION (continued)
Connect the device GND pin directly to the thermal
Layout Considerations
pad copper area under the IC device.
PCB is an essential element of any switching power
supply. The converter operation can be significantly
disturbed due to the existence of the large and fast
raising/falling voltages that can couple through stray
capacitances to other signal paths, unless those
interferences are minimized and properly managed in
the layout design. Insufficient conductance in copper
traces for the high current paths results in high resistive
losses in the power paths and voltage errors. Following
the guidelines provided here are necessary to design a
good layout:
Stitch the thermal pad to the internal ground
planes and the back side of the PCB directly under
the IC using multiple thermal vias.
Use a short and wide path for routing the SW pin
to the cathode of the catch diode on the same
layer and to the output inductor.
Keep the SW area minimal and away from
sensitive signals like FB input and divider resistors
or RT/SYNC to avoid capacitive noise coupling.
Top side GND plane that is connected to the
thermal pad provides the best heat removal path
for the IC. It should be large enough for designs
that operate with full rated loads. Thicker copper
planes can improve heat dissipation.
Bypass VIN pin to GND pin with low-ESR ceramic
capacitors (X5R or X7R or better dielectric) placed
as close as possible to VIN pin and the catch
diode anode pin.
Minimize the area and path length of the loop
formed by VIN pin, bypass capacitors connections,
SW pin and the catch diode.
Place the RT resistor (R3) as close as possible to
the RT/SYNC pin with short routes.
Vias
Top Layer
Bottom Layer
SGM61630A
SGM61630B
SW
SW
GND
GND
L1
L1
D1
D1
BOOT
SW
BOOT
SW
CIN1 CIN2
CIN1 CIN2
VIN
EN
GND
SS
VIN
EN
GND
REN1
REN1
VOUT
VOUT
PGOOD
RPG
CSS
RT/SYNC
RT/SYNC
FB
FB
COUT1 COUT2
COUT1 COUT2
RT
RT
RFB2
RFB1
RFB2
RFB1
VIN
VIN
REN2
REN2
GND
GND
Figure 7. Layout
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SGM61630
60V, 3A Buck Converter with 50μA IQ
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
MARCH 2023 - REV.A to REV.A.1
Page
Changed Layout ................................................................................................................................................................................................19
Changes from Original (DECEMBER 2022) to REV.A
Page
Changed from product preview to production data.............................................................................................................................................All
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20
PACKAGE INFORMATION
PACKAGE OUTLINE DIMENSIONS
SOIC-8 (Exposed Pad)
D
e
3.22
E1
E
E2
2.33 5.56
1.91
b
D1
1.27
0.61
RECOMMENDED LAND PATTERN (Unit: mm)
L
ccc
C
A2
A
SEATING PLANE
A1
c
θ
C
Dimensions
In Millimeters
Symbol
MIN
MOD
MAX
1.700
0.150
1.650
0.510
0.250
5.100
3.420
4.000
6.200
2.530
A
A1
A2
b
0.000
1.250
0.330
0.170
4.700
3.020
3.800
5.800
2.130
-
-
-
c
-
D
-
D1
E
-
-
E1
E2
e
-
-
1.27 BSC
L
0.400
0°
-
-
1.270
8°
θ
ccc
0.100
NOTES:
1. This drawing is subject to change without notice.
2. The dimensions do not include mold flashes, protrusions or gate burrs.
3. Reference JEDEC MS-012.
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PACKAGE INFORMATION
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
P2
P0
W
Q2
Q4
Q2
Q4
Q2
Q4
Q1
Q3
Q1
Q3
Q1
Q3
B0
Reel Diameter
P1
A0
K0
Reel Width (W1)
DIRECTION OF FEED
NOTE: The picture is only for reference. Please make the object as the standard.
KEY PARAMETER LIST OF TAPE AND REEL
Reel Width
Reel
Diameter
A0
B0
K0
P0
P1
P2
W
Pin1
Package Type
W1
(mm)
(mm) (mm) (mm) (mm) (mm) (mm) (mm) Quadrant
SOIC-8
(Exposed Pad)
13″
12.4
6.40
5.40
2.10
4.0
8.0
2.0
12.0
Q1
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PACKAGE INFORMATION
CARTON BOX DIMENSIONS
NOTE: The picture is only for reference. Please make the object as the standard.
KEY PARAMETER LIST OF CARTON BOX
Length
(mm)
Width
(mm)
Height
(mm)
Reel Type
Pizza/Carton
13″
386
280
370
5
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