500DBBA62M5000ACH [SILICON]
LVPECL Output Clock Oscillator,;
| 型号： | 500DBBA62M5000ACH |
| 厂家： | 
SILICON |
| 描述： | LVPECL Output Clock Oscillator, |
| 文件： | 总7页 (文件大小：977K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si500D
DIFFERENTIAL OUTPUT SILICON OSCILLATOR
Features
Quartz-free, MEMS-free, and PLL-free all-silicon
oscillator
Any output frequencies from 0.9 to 200 MHz
Short lead times
Excellent temperature stability (±20 ppm)
Highly reliable startup and operation
High immunity to shock and vibration
Low jitter: <1.5 ps rms
0 to 85 °C operation includes 10-year aging in hot
environments
Footprint compatible with industry-
standard 3.2 x 5.0 mm XOs
CMOS, SSTL, LVPECL, LVDS, and HCSL
versions available
Driver stopped, tri-state, or powerdown
operation
RoHS compliant
1.8, 2.5, or 3.3 V options
Low power
More than 10x better fit rate than
competing crystal solutions
Specifications
Parameters
Condition
Min
Typ
Max
Units
Frequency Range
0.9
—
200
MHz
Temperature stability,
0 to +70 °C
—
—
—
—
±10
±20
—
—
—
ppm
ppm
ppm
ppm
Temperature stability,
0 to +85 °C
Frequency Stability
Total stability,
0 to +70 °C operation
±150
±250
1
Total stability,
0 to +85 °C operation
—
2
Commercial
0
—
—
—
—
—
—
70
85
°C
°C
°C
V
Operating Temperature
Storage Temperature
Extended commercial
0
–55
1.71
2.25
2.97
+125
1.98
2.75
3.63
1.8 V option
2.5 V option
3.3 V option
Supply Voltage
V
V
Notes:
1. Inclusive of 25 °C initial frequency accuracy, operating temperature range, supply voltage change, output load change,
first-year aging at 25 °C, shock, vibration, and one solder reflow.
2. Inclusive of 25 °C initial frequency accuracy, operating temperature range, supply voltage change, output load change,
ten-year aging at 85 °C, shock, vibration, and one solder reflow.
3. See “AN409: Output Termination Options for the Si500S and Si500D Silicon Oscillators” for further details regarding
output clock termination recommendations.
4. VTT = .5 x VDD
.
5. VTT = .45 x VDD
.
Rev. 1.1 10/11
Copyright © 2011 by Silicon Laboratories
Si500D
Si500D
Parameters
Condition
LVPECL
Min
—
Typ
34.0
19.3
14.9
25.3
Max
36.0
22.2
16.5
29.3
Units
mA
Low Power LVPECL
LVDS
—
mA
—
mA
HCSL
—
mA
Differential CMOS(3.3 V option,
10 pF on each output, 200 MHz)
—
—
33
16
36
—
mA
mA
Supply Current
Differential CMOS(3.3 V option,
1 pFon each output, 40 MHz)
Differential SSTL-3.3
Differential SSTL-2.5
Differential SSTL-1.8
Tri-State
—
24.5
24.3
22.2
9.7
1.0
—
27.7
26.7
mA
mA
mA
mA
mA
%
—
—
25
—
10.7
Powerdown
—
1.9
Output Symmetry
V
= 0
46 – 13 ns/T
54 + 13 ns/T
460
DIFF
CLK
CLK
LVPECL/LVDS
HCSL/Differential SSTL
Differential CMOS, 15 pF, >80 MHz
Mid-level
—
—
—
—
ps
3
Rise and Fall Times (20/80%)
—
800
ps
1.1
—
1.6
ns
V
– 1.5
V
– 1.34
DD
V
LVPECL Output Option
(DC coupling, 50 to V – 2.0 V)
DD
3
Diff swing
.720
—
.880
V
DD
PK
Low Power LVPECL Output Option
Mid-level
—
N/A
—
V
(AC coupling, 100 Differential
Load)
Diff swing
.68
—
.95
V
3
PK
Mid-level
Diff swing
1.15
0.25
0.85
0.25
0.35
0.65
45
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1.26
0.45
0.96
0.45
0.425
0.82
55
V
LVDS Output Option (2.5/3.3 V)
3
(R
= 100 diff)
V
TERM
PK
Mid-level
V
LVDS Output Option (1.8 V)
3
(R
= 100 diff)
Diff swing
V
TERM
PK
Mid-level
V
3
HCSL Output Option
Diff swing
V
PK
DC termination per pad
V
V
V
, sourcing 9 mA
V
– 0.6
DD
—
OH
3
CMOS Output Voltage
V
, sinking 9 mA
—
0.6
OL
V
V
+ 0.375
—
—
OH
TT
4
4
5
SSTL-1.8 Output Voltage
SSTL-2.5 Output Voltage
SSTL-3.3 Output Voltage
Powerup Time
V
V
V
V
V
– 0.375
—
OL
TT
V
V
+ 0.48
—
OH
TT
V
V
V
– 0.48
—
OL
TT
TT
V
V
+ 0.48
—
OH
TT
V
– 0.48
OL
From time V crosses min spec
DD
—
—
—
—
—
—
—
—
2
ms
ns
ns
µs
supply
OE Deassertion to Clk Stop
250 + 3 x T
250 + 3 x T
CLK
CLK
CLK
Return from Output Driver Stopped
Mode
Return From Tri-State Time
12 + 3 x T
Notes:
1. Inclusive of 25 °C initial frequency accuracy, operating temperature range, supply voltage change, output load change,
first-year aging at 25 °C, shock, vibration, and one solder reflow.
2. Inclusive of 25 °C initial frequency accuracy, operating temperature range, supply voltage change, output load change,
ten-year aging at 85 °C, shock, vibration, and one solder reflow.
3. See “AN409: Output Termination Options for the Si500S and Si500D Silicon Oscillators” for further details regarding
output clock termination recommendations.
4. VTT = .5 x VDD
.
5. VTT = .45 x VDD
.
2
Rev. 1.1
Si500D
Parameters
Condition
Min
Typ
Max
Units
Return From Powerdown Time
—
—
2
ms
ps
RMS
Non-CMOS
—
—
—
—
1
2
3
Period Jitter (1-sigma)
ps
RMS
CMOS, C = 7 pF
1
L
1.0 MHz – min(20 MHz,
ps
RMS
0.6
0.7
1
0.4 x F
),non-CMOS
OUT
Integrated Phase Jitter
1.0 MHz – min(20 MHz,
0.4 x F ),CMOS format
ps
RMS
1.5
OUT
Notes:
1. Inclusive of 25 °C initial frequency accuracy, operating temperature range, supply voltage change, output load change,
first-year aging at 25 °C, shock, vibration, and one solder reflow.
2. Inclusive of 25 °C initial frequency accuracy, operating temperature range, supply voltage change, output load change,
ten-year aging at 85 °C, shock, vibration, and one solder reflow.
3. See “AN409: Output Termination Options for the Si500S and Si500D Silicon Oscillators” for further details regarding
output clock termination recommendations.
4. VTT = .5 x VDD
.
5. VTT = .45 x VDD
.
Rev. 1.1
3
Si500D
Package Specifications
Table 1. Package Diagram Dimensions (mm)
Dimension
Min
0.80
Nom
0.85
0.03
0.64
Max
0.90
0.05
0.69
Dimension
Min
0.00
—
Nom
0.05
—
Max
0.10
0.10
0.10
0.08
A
A1
b
L1
0.00
aaa
bbb
ccc
0.59
—
—
D
3.20 BSC.
—
—
e
E
L
1.27 BSC.
4.00 BSC.
0.95
ddd
eee
—
—
—
—
0.10
0.05
1.00
1.05
Table 2. Pad Connections
Table 3. Tri-State/Powerdown/Driver Stopped
Function on OE (3rd Option Code)
1
2
OE
A
B
C
D
E
F
NC—Make no external
connection to this pin
Open Active Active Active Active Active
Active
3
4
5
6
GND
Output
1
Tri-
State
Power-
down
Driver
Stopped
Active
Active
Active
Level
0
Tri-
State
Power-
down
Driver
Stopped
Complementary Output
VDD
Active
Active
Active
Level
0 C CC CC
T T T T T T
Y YWW
Dimension
(mm)
C1
E
X1
Y1
2.70
1.27
0.75
1.55
0 = Si500
CCCCC = mark code
TTTTTT = assembly manufacturing code
YY = year
WW = work week
Figure 2. Top Mark
Figure 1. Recommended Land Pattern
4
Rev. 1.1
Si500D
Environmental Compliance
Parameter
Conditions/Test Method
MIL-STD-883, Method 2002.4
MIL-STD-883, Method 2007.3 A
MIL-STD-202, 260 C° for 8 seconds
MIL-STD-883, Method 2003.8
IEC 68-2-3
Mechanical Shock
Mechanical Vibration
Resistance to Soldering Heat
Solderability
Damp Heat
Moisture Sensitivity Level
J-STD-020, MSL 3
Ordering Information
The Si500D supports a variety of options including frequency, output format, supply voltage, and tri-
state/powerdown. Specific device configurations are programmed into the Si500D at time of shipment.
Configurations are specified using the figure below. Silicon Labs provides a web-based part number utility that can
be used to simplify part number configuration. Refer to www.silabs.com/SiliconXOPartnumber to access this tool.
The Si500D XO series is supplied in a ROHS-compliant, Pb-free, 6-pad, 3.2 x 4.0 mm package. Tape and reel
packaging is available as an ordering option.
500D
X
X
X
XXMXXXX
A
C
X
R
Frequency
Si500
Differential
Oscillator
R = Tape & Reel
Blank = Cut-Tape
xMxxxxx: fOUT < 10 MHz
xxMxxxx: 10 MHz < fOUT < 100 MHz
xxxMxxx: fOUT > 100 MHz
1st Option Code
VDD Format
LVPECL
3rd Option Code
Oper. Temp Range
A
B
C
D
E
F
G
H
J
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
1.8
1.8
1.8
1.8
1.8
1.8
Tri-State/Powerdown/
Output Driver Stopped
F
*H
0 to 70 °C
0 to 85 °C
Low Power LVPECL
LVDS
HCSL
Dual Output CMOS
Differential CMOS
Dual Output SSTL
Differential SSTL
LVPECL
Low Power LVPECL
LVDS
HCSL
Dual Output CMOS
Differential CMOS
Dual Output SSTL
Differential SSTL
LVDS
A
B
C
D
E
F
OE active high/tristate
OE active low/tristate
OE active high/powerdown
OE active low/powerdown
OE active high/driver stopped
OE active low/driver stopped
Product Revision = C
K
L
2nd Option Code
Package
Stability (ppm, max)
M
N
P
Q
R
S
T
U
V
W
X
A
3.2 x 4.0 mm SMD
A
B
±150
±250
HCSL
Dual Output CMOS
Differential CMOS
Dual Output SSTL
Differential SSTL
*Note: Only +250 ppm is supported.
Rev. 1.1
5
Si500D
DOCUMENT CHANGE LIST
Revision 0.2 to Revision 0.3
Revision B to Revision C updated in Ordering Information
0 to 85 C° Operating Temperature Range option added
Revision 0.3 to Revision 1.0
Clarified SSTL specifications.
Revised Differential CMOS supply current values.
Clarified Differential CMOS supply current loading
conditions.
Revision 1.0 to Revision 1.1
Updated Ordering information for ±250 ppm from 0 to
+85 °C.
Updated jitter from 1.5 ps to 1.5 ps rms.
Updated operating temperature to include extended
commercial at 0 to +85 °C.
Updated features to include LVPECL, LVDS, and HCSL.
6
Rev. 1.1
ClockBuilder Pro
One-click access to Timing tools,
documentation, software, source
code libraries & more. Available for
Windows and iOS (CBGo only).
www.silabs.com/CBPro
Timing Portfolio
www.silabs.com/timing
SW/HW
www.silabs.com/CBPro
Quality
www.silabs.com/quality
Support and Community
community.silabs.com
Disclaimer
Silicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or
intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical"
parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes without
further notice to the product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. Without prior
notification, Silicon Labs may update product firmware during the manufacturing process for security or reliability reasons. Such changes will not alter the specifications or the performance
of the product. Silicon Labs shall have no liability for the consequences of use of the information supplied in this document. This document does not imply or expressly grant any license to
design or fabricate any integrated circuits. The products are not designed or authorized to be used within any FDA Class III devices, applications for which FDA premarket approval is required
or Life Support Systems without the specific written consent of Silicon Labs. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails,
can be reasonably expected to result in significant personal injury or death. Silicon Labs products are not designed or authorized for military applications. Silicon Labs products shall under no
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disclaims all express and implied warranties and shall not be responsible or liable for any injuries or damages related to use of a Silicon Labs product in such unauthorized applications.
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