CY28547LFXCT [SILICON]
Processor Specific Clock Generator, 200MHz, CMOS, 10 X 10 MM, LEAD FREE, MO-220, QFN-72;
| 型号： | CY28547LFXCT |
| 厂家： | 
SILICON |
| 描述： | Processor Specific Clock Generator, 200MHz, CMOS, 10 X 10 MM, LEAD FREE, MO-220, QFN-72 时钟 外围集成电路 晶体 |
| 文件： | 总25页 (文件大小：1213K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY28547
Clock Generator for Intel®CK410M/CK505
• 96/100-MHz low power spreadable differential video
clock
Features
• Compliant to Intel® CK410M and CK505
• Selectable CPU frequencies
• 33-MHz PCI clocks
• Buffered Reference Clock 14.318 MHz
• Low-voltage frequency select inputs
• I2C support with readback capabilities
• Low power differential CPU clock pairs
• 100-MHz low power differential SRC clocks
• 96-MHz low power differential dot clock
• 27-MHz Spread and Non-spread video clock
• 48-MHz USB clock
• Ideal Lexmark Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
• 3.3V power supply
• 72-pin QFN package
• SRC clocks independently stoppable through
CLKREQ#[1:9]
Table 1. Output Confguration Table
CPU
SRC
PCI
x5
REF
x 2
DOT96
x 1
USB_48M
x 1
LCD
x1
27M
x2
x2/x3
x9/11
Block Diagram
Pin Configuration
VDD_REF
REF[1:0]
Xin
Xout
14.318MHz
Crystal
PLL Reference
VDD_CPU
CPUT[1:0]
CPUC[1:0]
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55
CPU_STP#
PCI_STP#
CLKREQ#
PLL1
CPU
VDD_SRC
SRCC_9
SRCT_9
1
2
3
4
5
6
7
8
9
54 VDD_SRC
53 SRCC_2
52 SRCT_2
Divider
VDD_SRC
CPUT2_ITP/SRCT10
CPUC2_ITP/SRCC10
VSS_SRC
51 SRCC_1/SATAC
50 SRCT_1/SATAT
49 VDD_SRC
48 SRCC_0 / LCD100MC
47 SRCT_0 / LCD100MT
46 CLKREQ1#
45 FSB/TEST_MODE
44 DOT96C / 27M_SS
43 DOT96T / 27M_NSS
42 VSS_48
FS[C:A]
ITP_EN
CPUC2_ITP / SRCC_10
CPUT2_ITP / SRCT_10
VDDA
VDD_SRC
Divider
Divider
SRCT [9:1]
SRCC [9:1]
VSSA
* PGMODE
CPUC1_MCH 10
CPUT1_MCH 11
VDD_CPU 12
CPUC0 13
CY28547
VDD_PCI
PCI[4:1]
VDD_PCI
CPUT0 14
VSS_CPU 15
SCLK 16
SDATA 17
VDD_REF 18
41 48M / FSA
40 VDD_48
39 VTT_PWRGD# / PD (CKPWRGD/PD#)
38 CLKREQ7#
37 PCIF0/ITP_SEL
PCIF0
VDD_SRC
PLL3
Graphi
c
LCD_100MT/SRCT0
LCD_100MC/SRCC0
Divider
Divider
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
VDD_48
27_SS
FCTSEL
VDD_48
PLL2
Fixed
DOT96T
DOT96C
VDD_48
USB_48 [1:0]
PLL4
27M
VDD_48
27_NSS
VTTPWR_GD#/PD
I2C
Logic
SDATA
SCLK
.......................Document #: 001-05103 Rev *B Page 1 of 24
400 West Cesar Chavez, Austin, TX 78701 1+(512) 416-8500 1+(512) 416-9669
www.silabs.com
CY28547
Pin Description
Pin No.
Name
Type
Description
1, 49, 54, 65 VDD_SRC
PWR 3.3V power supply for outputs.
2, 3, 52, 53, SRCT/C[2:9]
55, 56, 58,
O, DIF 100-MHz Differential serial reference clocks.
59, 60, 61,
63, 64, 66,
67, 69, 70
4, 68
5, 6
VSS_SRC
GND Ground for outputs.
CPUT2_ITP/SRCT10, O, DIF Selectable differential CPU or SRC clock output.
CPUC2_ITP/SRCC10
ITP_SEL = 0 @ pin 39 assertion = SRC10
ITP_SEL = 1 @ pin 39 assertion = CPU2
7
8
9
VDDA
PWR 3.3V power supply for PLL.
VSSA
GND Ground for PLL.
PGMODE
I, PU 3.3V LVTTL input for selecting the polarity of pin 39
Internal pull-up resistor of 100K to 3.3V, use 10K resistor to pull it low externally
if needed
PGMODE CLK mode Pin 39
0
CK410
VTT_PWRGD#/PD
CK_PWRGD/PD#
1(default) CK505
10, 11
CPUC1_MCH,
CPUT1_MCH
O, DIF Differential CPU clock output to MCH
12
VDD_CPU
CPU[T/C]0
VSS_CPU
SCLK
PWR 3.3V power supply for outputs.
O, DIF Differential CPU clock output
GND Ground for outputs.
13, 14
15
16
I
SMBus-compatible SCLOCK.
17
SDATA
I/O, OD SMBus-compatible SDATA.
PWR 3.3V power supply for outputs.
O, SE 14.318-MHz crystal output.
18
VDD_REF
XOUT
19
20
XIN
I
14.318-MHz crystal input.
21
VSS_REF
REF1
GND Ground for outputs.
22
O
Fixed 14.318-MHz clock output.
23
REF0/FSC_TESTSEL
I/O
Fixed 14.318 clock output/3.3V-tolerant input for CPU frequency
selection/Selects test mode if pulled to VIMFS_C when pin 39 is asserted LOW.
Refer to DC Electrical Specifications table for VILFS_C,VIMFS_C,VIHFS_C specifi-
cations.
24
25
CPU_STP#
PCI_STP#
I
I
I
3.3V LVTTL input for CPU_STP# active LOW
During direct clock off to M1 mode transition, a serial load of BSEL data is driven
on this pin and sampled on the rising edge of PCI_STP#. See Figure 14.for more
information.
3.3V LVTTL input for PCI_STP# active LOW
During direct clock off to M1 mode transition, a serial load of BSEL data is driven
on CPU_STP# and sampled on the rising edge of this pin. See Figure 14. for more
information.
26, 28, 29,
38, 46, 57,
62, 71, 72
CLKREQ[1:9]#
3.3V LVTTL input for enabling assigned SRC clock (active LOW).
27
PCI1
O, SE 33MHz clock output
30, 36
31, 35
VDD_PCI
VSS_PCI
PWR 3.3V power supply for outputs.
GND Ground for outputs.
.......................Document #: 001-05103 Rev *B Page 2 of 24
CY28547
Pin Description (continued)
Pin No.
Name
PCI2/TME
Type
Description
32
I/O, SE 33-MHz clock output/Trusted Mode Enable Strap
Strap at pin 39 assertion to determine if the part is in trusted mode or not.
Internal pull-up resistor of 100K to 3.3V, use 10K resistor to pull it low externally
if needed
0 = Normal mode
1= Trusted mode (default)
33
34
PCI3
O, SE 33-MHz clock output
PCI4/FCTSEL1
I/O
33-MHz clock output/3.3V LVTTL input for selecting pins 47,48 (SRC[T/C]0,
100M[T/C]) and pins 43,44 (DOT96[T/C] and 27M Spread and Non-spread)
(sampled on pin 39 assertion).
Internal pull-down resistor of 100K to GND
FCTSEL1 Pin 43
0 DOT96T
Pin 44
DOT96C
27M_SS
Pin 47
Pin 48
96/100M_T 96/100M_C
1 27M_NSS
SRCT0 SRCC0
37
39
ITP_SEL/PCIF0
I/O,SE 3.3V LVTTL input to enable SRC10 or CPU2_ITP/33-MHz clock output. (sampled
on pin 39 assertion).
Internal pull-down resistor of 100K to GND
1 = CPU2_ITP, 0 = SRC10
VTT_PWRGD#/PD
CKPWRGD/PD#
I
3.3V LVTTL input. This pin is a level sensitive strobe. When asserted, according
to the polarity defined by pin 9 (PGMODE), it latches data on the FSA, FSB, FSC,
FCTSEL1 and ITP_SEL pins. After assertion, it becomes a real time input for
controlling power down.
PGMODE
0
Pin 39
0 = POWER GOOD (VTT_PWRGD#)
0
1
1
1 = POWER DOWN (PD)
0 = POWER DOWN (PD#)
1 = POWER GOOD (CKPWRGD)
40
41
VDD_48
PWR 3.3V power supply for outputs.
48M/FSA
I/O
Fixed 48-MHz clock output/3.3V-tolerant input for CPU frequency selection
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
42
VSS_48
GND Ground for outputs.
43, 44
DOT96T/ 27M_NSS
DOT96C/ 27M_SS
O, DIF Fixed 96-MHz clock output or 27 Mhz Spread and Non-spread output Selected
via FCTSEL1 at pin 39 assertion.
45
FSB/TEST_MODE
I
3.3V-tolerant input for CPU frequency selection. Selects Ref/N or Tri-state when
in test mode
0 = Tri-state, 1 = Ref/N
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
47, 48
50, 51
SRC[T/C]0/
LCD100M[T/C]
O,DIF 100-MHz differential serial reference clock output/Differential 96/100-MHz SS
clock for flat-panel display
Selected via FCTSEL1 at pin 39 assertion.
SRCT_1/SATAT,
SRCC_1/SATAC
O, DIF 100-MHz Differential serial reference clocks.
samples the FSA, FSB, and FSC input values. For all logic
levels of FSA, FSB, and FSC, VTT_PWRGD# employs a
Frequency Select Pins (FSA, FSB, and FSC)
Host clock frequency selection is achieved by applying the
appropriate logic levels to FSA, FSB, FSC inputs prior to
VTT_PWRGD# assertion (as seen by the clock synthesizer).
Upon VTT_PWRGD# being sampled LOW by the clock chip
(indicating processor VTT voltage is stable), the clock chip
one-shot functionality in that once valid LOW on
a
VTT_PWRGD# has been sampled, all further VTT_PWRGD#,
FSA, FSB, and FSC transitions will be ignored, except in test
mode.
.......................Document #: 001-05103 Rev *B Page 3 of 24
CY28547
Serial Data Interface
Data Protocol
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initialize to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface cannot be used during system
operation for power management functions.
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
system controller can access individually indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in Table 3.
The block write and block read protocol is outlined in Table 4
while Table 5 outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h)
Table 2. Frequency Select Table FSA, FSB, and FSC
FSC FSB FSA
CPU
SRC
PCIF/PCI
33 MHz
33 MHz
33 MHz
33 MHz
27MHz
27 MHz
27 MHz
27 MHz
27 MHz
REF
DOT96
96 MHz
96 MHz
96 MHz
96 MHz
USB
1
0
0
0
0
0
1
1
1
1
1
0
100 MHz
133 MHz
166 MHz
200 MHz
100 MHz
100 MHz
100 MHz
100 MHz
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
48 MHz
48 MHz
48 MHz
48 MHz
Table 3. Command Code Definition
Bit
Description
7
0 = Block read or block write operation, 1 = Byte read or byte write operation
(6:0)
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be
'0000000'
Table 4. Block Read and Block Write Protocol
Block Write Protocol
Block Read Protocol
Description
Bit
1
Description
Bit
1
Start
Start
8:2
9
Slave address–7 bits
Write
8:2
9
Slave address–7 bits
Write
10
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
10
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
Repeat start
18:11
19
18:11
19
27:20
Byte Count–8 bits
20
(Skip this step if I2C_EN bit set)
28
36:29
37
Acknowledge from slave
Data byte 1–8 bits
27:21
28
Slave address–7 bits
Read = 1
Acknowledge from slave
Data byte 2–8 bits
29
Acknowledge from slave
Byte Count from slave–8 bits
Acknowledge
45:38
46
37:30
38
Acknowledge from slave
Data Byte/Slave Acknowledges
Data Byte N–8 bits
....
46:39
47
Data byte 1 from slave–8 bits
Acknowledge
....
....
Acknowledge from slave
Stop
55:48
56
Data byte 2 from slave–8 bits
Acknowledge
....
....
Data bytes from slave/Acknowledge
Data Byte N from slave–8 bits
NOT Acknowledge
....
....
.......................Document #: 001-05103 Rev *B Page 4 of 24
CY28547
Table 4. Block Read and Block Write Protocol (continued)
Block Write Protocol
Block Read Protocol
Description
Bit
Description
Bit
....
Stop
Start
Table 5. Byte Read and Byte Write Protocol
Byte Write Protocol
Byte Read Protocol
Description
Bit
1
Description
Bit
1
Start
8:2
9
Slave address–7 bits
Write
8:2
9
Slave address–7 bits
Write
10
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
Data byte–8 bits
10
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
Repeated start
18:11
19
18:11
19
27:20
28
20
Acknowledge from slave
Stop
27:21
28
Slave address–7 bits
Read
29
29
Acknowledge from slave
Data from slave–8 bits
NOT Acknowledge
Stop
37:30
38
39
Control Registers
Byte 0 Control Register 0
Bit
7
@Pup
Name
Description
0
0
0
0
RESEREVD
RESEREVD
RESEREVD
iAMT_EN
RESERVED
RESERVED
RESERVED
6
5
4
Set via SMBus or by combination of PD, CPU_STP and PCI_STP
0 = Legacy mode, 1 = iAMT enable
3
2
1
0
0
0
0
1
RESEREVD
RESEREVD
RESEREVD
PD_Restore
RESERVED
RESERVED
RESERVED
Save configuration in PD
0 = Configuration cleared, 1 = Configuration saved
Byte 1 Control Register 1
Bit
@Pup
Name
Description
7
1
SRC[T/C]7
SRC[T/C]7 Output Enable
0 = Disabled, 1 = Enabled
6
5
4
3
1
1
1
1
SRC[T/C]6
SRC[T/C]5
SRC[T/C]4
SRC[T/C]3
SRC[T/C]6 Output Enable
0 = Disabled, 1 = Enabled
SRC[T/C]5 Output Enable
0 = Disabled, 1 = Enabled
SRC[T/C]4 Output Enable
0 = Disabled, 1 = Enabled
SRC[T/C]3 Output Enable
0 = Disabled, 1 = Enabled
.......................Document #: 001-05103 Rev *B Page 5 of 24
CY28547
Byte 1 Control Register 1 (continued)
Bit
@Pup
Name
Description
2
1
SRC[T/C]2
SRC[T/C]2 Output Enable
0 = Disabled, 1 = Enabled
1
0
1
1
SRC[T/C]1
SRC[T/C]1 Output Enable
0 = Disabled, 1 = Enabled
SRC[T/C]0
/LCD_96_100M[T/C]
SRC[T/C]0/LCD_96_100M[T/C] Output Enable
0 = Disabled, 1 = Enabled
Byte 2 Control Register 2
Bit
@Pup
Name
Description
7
1
PCIF0
PCIF0 Output Enable
0 = Disabled, 1 = Enabled
6
5
4
3
2
1
0
1
1
1
1
1
1
1
27M NSS/DOT_96[T/C] 27M Non-spread and DOT_96 MHz Output Enable
0 = Disable, 1 = Enabled
48M
48-MHz Output Enable
0 = Disabled, 1 = Enabled
REF0
REF0 Output Enable
0 = Disabled, 1 = Enabled
REF1
REF1 Output Enable
0 = Disabled, 1 = Enabled
CPU[T/C]1
CPU[T/C]0
CPU[T/C]1 Output Enable
0 = Disabled, 1 = Enabled
CPU[T/C]0 Output Enable
0 = Disabled, 1 = Enabled
CPU, SRC, PCI, PCIF PLL1 (CPU PLL) Spread Spectrum Enable
Spread Enable
0 = Spread off, 1 = Spread on
Byte 3 Control Register 3
Bit
@Pup
Name
Description
7
1
PCI4
PCI4 Output Enable
0 = Disabled, 1 = Enabled
6
5
4
1
1
1
PCI3
PCI2
PCI1
PCI3 Output Enable
0 = Disabled, 1 = Enabled
PCI2 Output Enable
0 = Disabled, 1 = Enabled
PCI1 Output Enable
0 = Disabled, 1 = Enabled
3
2
1
1
1
1
RESERVED
RESERVED
RESERVED
RESERVED
CPU[T/C]2/SRC[T/C]10 CPU[T/C]2/SRC[T/C]10 Output Enable
0 = Disabled, 1 = Enabled
0
1
RESERVED
RESERVED
Byte 4 Control Register 4
Bit
@Pup
Name
Description
7
0
SRC7
Allow control of SRC[T/C]7 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
6
5
4
0
0
0
SRC6
SRC5
SRC4
Allow control of SRC[T/C]6 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]5 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]4 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
.......................Document #: 001-05103 Rev *B Page 6 of 24
CY28547
Byte 4 Control Register 4 (continued)
Bit
@Pup
Name
Description
3
0
SRC3
Allow control of SRC[T/C]3 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
2
1
0
0
0
0
SRC2
SRC1
SRC0
Allow control of SRC[T/C]2 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]1 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]0 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Byte 5 Control Register 5
Bit
@Pup
Name
Description
7
0
LCD_96_100M[T/C]
LCD_96_100M[T/C] PWRDWN Drive Mode
0 = Driven in PWRDWN, 1 = Tri-state
6
0
DOT96[T/C]
DOT PWRDWN Drive Mode
0 = Driven in PWRDWN, 1 = Tri-state
5
4
3
0
0
0
RESERVED
RESERVED
PCIF0
RESERVED, Set = 0
RESERVED, Set = 0
Allow control of PCIF0 with assertion of SW and HW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
2
1
0
1
1
1
CPU[T/C]2
CPU[T/C]1
CPU[T/C]0
Allow control of CPU[T/C]2 with assertion of CPU_STP#
0 = Free running, 1 = Stopped with CPU_STP#
Allow control of CPU[T/C]1 with assertion of CPU_STP#
0 = Free running, 1 = Stopped with CPU_STP#
Allow control of CPU[T/C]0 with assertion of CPU_STP#
0 = Free running, 1 = Stopped with CPU_STP#
Byte 6 Control Register 6
Bit
@Pup
Name
Description
7
0
SRC[T/C]
SRC[T/C] Stop Drive Mode
0 = Driven when PCI_STP# asserted
1 = Tri-state when PCI_STP# asserted
6
5
4
3
2
1
0
0
0
0
0
0
0
0
CPU[T/C]2
CPU[T/C]1
CPU[T/C]0
SRC[T/C][9:1]
CPU[T/C]2
CPU[T/C]1
CPU[T/C]0
CPU[T/C]2 Stop Drive Mode
0 = Driven when CPU_STP# asserted
1 = Tri-state when CPU_STP# asserted
CPU[T/C]1 Stop Drive Mode
0 = Driven when CPU_STP# asserted
1 = Tri-state when CPU_STP# asserted
CPU[T/C]0 Stop Drive Mode
0 = Driven when CPU_STP# asserted
1 = Tri-state when CPU_STP# asserted
SRC[T/C][9:1] PWRDWN Drive Mode
0 = Driven when PD asserted
1 = Tri-state when PD asserted
CPU[T/C]2 PWRDWN Drive Mode
0 = Driven when PD asserted
1 = Tri-state when PD asserted
CPU[T/C]1 PWRDWN Drive Mode
0 = Driven when PD asserted
1 = Tri-state when PD asserted
CPU[T/C]0 PWRDWN Drive Mode
0 = Driven when PD asserted
1 = Tri-state when PD asserted
.......................Document #: 001-05103 Rev *B Page 7 of 24
CY28547
Byte 7 Control Register 7
Bit
@Pup
Name
Description
7
0
TEST_SEL
REF/N or Tri-state Select
0 = Tri-state, 1 = REF/N Clock
6
5
4
3
0
1
1
1
TEST_MODE
REF1
Test Clock Mode Entry Control
0 = Normal operation, 1 = REF/N or Tri-state mode,
REF1 Output Drive Strength
0 = Low, 1 = High
REF0
REF0 Output Drive Strength
0 = Low, 1 = High
PCI, PCIF and SRC clock SW PCI_STP Function
outputs except those set to 0 = SW PCI_STP assert, 1= SW PCI_STP deassert
free running
When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will
be stopped in a synchronous manner with no short pulses.
When this bit is set to 1, all STOPPED PCI, PCIF and SRC outputs will
resume in a synchronous manner with no short pulses.
2
1
0
HW
HW
HW
FSC
FSB
FSA
FSC Reflects the value of the FSC pin sampled on power up
0 = FSC was low during VTT_PWRGD# assertion
FSB Reflects the value of the FSB pin sampled on power up
0 = FSB was low during VTT_PWRGD# assertion
FSA Reflects the value of the FSA pin sampled on power up
0 = FSA was low during VTT_PWRGD# assertion
Byte 8 Vendor ID
Bit
7
@Pup
Name
Description
Revision Code Bit 3
Revision Code Bit 2
Revision Code Bit 1
Revision Code Bit 0
Vendor ID Bit 3
0
0
1
1
1
0
0
0
Revision Code Bit 3
Revision Code Bit 2
Revision Code Bit 1
Revision Code Bit 0
Vendor ID Bit 3
6
5
4
3
2
Vendor ID Bit 2
Vendor ID Bit 2
1
Vendor ID Bit 1
Vendor ID Bit 1
0
Vendor ID Bit 0
Vendor ID Bit 0
Byte 9 Control Register 9
Bit
@Pup
Name
Description
RESERVED, Set = 0
RESERVED, Set = 0
RESERVED
7
6
5
4
3
2
0
0
0
0
0
1
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
48M
RESERVED
RESERVED
48-MHz Output Drive Strength
0 = Low, 1 = High
1
0
1
1
RESERVED
PCIF0
RESERVED
PCIF0 Output Drive Strength
0 = Low, 1 = High
Byte 10 Control Register 10
Bit
7
@Pup
Name
Description
0
0
RESERVED
RESERVED
RESERVED
6
RESERVED
.......................Document #: 001-05103 Rev *B Page 8 of 24
CY28547
Byte 10 Control Register 10 (continued)
Bit
5
@Pup
Name
S1
Description
0
0
27M_SS/LCD 96_100M SS Spread Spectrum Selection table:
S[1:0] SS%
‘00’ = –0.5%(Default value)
‘01’ = –1.0%
4
S0
‘10’ = –1.5%
‘11’ = –2.0%
3
2
1
1
RESERVED
27M_SS
RESERVED
27M Spread Output Enable
0 = Disabled, 1 = Enabled
1
1
27M_SS/LCD_100M
Spread Enable
27M_SS/LCD_100M Spread spectrum enable.
0 = Disabled, 1 = Enabled
0
0
RESERVED
RESERVED
Byte 11 Control Register 11
Bit
7
@Pup
Name
Description
RESERVED
0
0
1
RESERVED
RESERVED
SRC[T/C]9
6
RESERVED
5
SRC[T/C]9 Output Enable
0 = Disable (Hi-Z), 1 = Enable
4
1
SRC[T/C]8
SRC[T/C]8 Output Enable
0 = Disable (Hi-Z), 1 = Enable
3
2
1
0
RESERVED
SRC[T/C]10
RESERVED
Allow control of SRC[T/C]10 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
1
0
0
0
SRC[T/C]9
SRC[T/C]8
Allow control of SRC[T/C]9 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]8 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Byte 12 Control Register 12
Bit
7
@Pup
0
Name
RESERVED
Description
RESERVED, Set = 0
RESERVED
6
HW
HW
HW
0
RESERVED
5
RESERVED
RESERVED
4
RESERVED
RESERVED
3
27M_SS/27M_NSS
27-MHz (spread and non-spread) Output Drive Strength
0 = Low, 1 = High
2
1
0
0
1
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED, Set = 1
RESERVED
HW
Byte 13 Control Register 13
Bit
@Pup
Name
Description
7
0
CLKREQ#9
CLKREQ#9 Input Enable
0 = Disabled, 1 = Enabled
6
5
0
0
CLKREQ#8
CLKREQ#7
CLKREQ#8 Input Enable
0 = Disabled, 1 = Enabled
CLKREQ#7 Input Enable
0 = Disabled, 1 = Enabled
.......................Document #: 001-05103 Rev *B Page 9 of 24
CY28547
Byte 13 Control Register 13 (continued)
Bit
@Pup
Name
Description
4
0
CLKREQ#6
CLKREQ#6 Input Enable
0 = Disabled, 1 = Enabled
3
2
1
0
0
0
0
0
CLKREQ#5
CLKREQ#4
CLKREQ#3
CLKREQ#2
CLKREQ#5 Input Enable
0 = Disabled, 1 = Enabled
CLKREQ#4 Input Enable
0 = Disabled, 1 = Enabled
CLKREQ#3 Input Enable
0 = Disabled, 1 = Enabled
CLKREQ#2 Input Enable
0 = Disabled, 1 = Enabled
Byte 14 Control Register 14
Bit
@Pup
Name
Description
7
0
CLKREQ#1
CLKREQ#1 Input Enable
0 = Disabled, 1 = Enabled
6
1
LCD 96_100M Clock
Speed
LCD 96_100M Clock Speed
0 = 96 MHz 1 = 100 MHz
5
4
3
1
1
1
RESERVED
RESERVED
PCI4
RESERVED, Set = 1
RESERVED, Set = 1
PCI4 (Spread and Non-spread) Output Drive Strength
0 = Low, 1 = High
2
1
0
1
1
1
PCI3
PCI2
PCI1
PCI3 (Spread and Non-spread) Output Drive Strength
0 = Low, 1 = High
PCI2 (Spread and Non-spread) Output Drive Strength
0 = Low, 1 = High
PCI1 (Spread and Non-spread) Output Drive Strength
0 = Low, 1 = High
Byte 15 Control Register 15
Bit
@Pup
Name
Description
7
HW
TME_STRAP
Trusted mode enable strap status,
0 = Normal
1 = No overclocking (default)
6
5
4
3
2
1
0
1
1
1
1
0
1
1
RESERVED
RESERVED
RESERVED
RESERVED
IO_VOUT2
IO_VOUT1
IO_VOUT0
RESERVED
RESERVED
RESERVED
RESERVED
IO_VOUT[2,1,0]
000 = 0.63V
001 = 0.71V
010 = 0.77V
011 = 0.82V (Default)
100 = 0.86V
101 = 0.90V
110 = 0.93V
111 = Reserved
Table 6. Crystal Recommendations
Frequency
Drive
(max.)
Shunt Cap Motional
Tolerance
(max.)
Stability
(max.)
Aging
(max.)
(Fund)
Cut
Loading Load Cap
(max.)
(max.)
14.31818 MHz
AT
Parallel 20 pF
0.1 mW
5 pF
0.016 pF
35 ppm
30 ppm
5 ppm
The CY28547 requires a Parallel Resonance Crystal. Substi-
tuting a series resonance crystal will cause the CY28547 to
operate at the wrong frequency and violate the ppm specifi-
cation. For most applications there is a 300-ppm frequency
.....................Document #: 001-05103 Rev *B Page 10 of 24
CY28547
shift between series and parallel crystals due to incorrect
loading.
Use the following formulas to calculate the trim capacitor
values for Ce1 and Ce2.
Load Capacitance (each side)
Crystal Loading
Ce = 2 * CL – (Cs + Ci)
Crystal loading plays a critical role in achieving low ppm perfor-
mance. To realize low ppm performance, the total capacitance
the crystal will see must be considered to calculate the appro-
priate capacitive loading (CL).
Total Capacitance (as seen by the crystal)
1
CLe
=
1
1
(
)
+
Figure 1 shows a typical crystal configuration using the two
trim capacitors. An important clarification for the following
discussion is that the trim capacitors are in series with the
crystal not parallel. It’s a common misconception that load
capacitors are in parallel with the crystal and should be
approximately equal to the load capacitance of the crystal.
This is not true.
Ce2 + Cs2 + Ci2
Ce1 + Cs1 + Ci1
CL....................................................Crystal load capacitance
CLe......................................... Actual loading seen by crystal
using standard value trim capacitors
Ce..................................................... External trim capacitors
Cs..............................................Stray capacitance (terraced)
Ci ...........................................................Internal capacitance
(lead frame, bond wires etc.)
CLK_REQ# Description
The CLKREQ# signals are active LOW inputs used for clean
enabling and disabling selected SRC outputs. The outputs
controlled by CLKREQ# are determined by the settings in
register byte 8. The CLKREQ# signal is a de-bounced signal
in that it’s state must remain unchanged during two consec-
utive rising edges of SRCC to be recognized as a valid
assertion or deassertion. (The assertion and deassertion of
this signal is absolutely asynchronous.)
Figure 1. Crystal Capacitive Clarification
Calculating Load Capacitors
In addition to the standard external trim capacitors, trace
capacitance and pin capacitance must also be considered to
correctly calculate crystal loading. As mentioned previously,
the capacitance on each side of the crystal is in series with the
crystal. This means the total capacitance on each side of the
crystal must be twice the specified crystal load capacitance
(CL). While the capacitance on each side of the crystal is in
series with the crystal, trim capacitors (Ce1,Ce2) should be
calculated to provide equal capacitive loading on both sides.
CLK_REQ[1:9]# Assertion (CLKREQ# -> LOW)
All differential outputs that were stopped are to resume normal
operation in a glitch-free manner. The maximum latency from
the assertion to active outputs is between 2 and 6 SRC clock
periods (2 clocks are shown) with all SRC outputs resuming
simultaneously. All stopped SRC outputs must be driven HIGH
within 10 ns of CLKREQ# deassertion to a voltage greater than
200 mV.
Clock Chip
Ci2
Ci1
Pin
3 to 6p
X2
X1
Cs2
Cs1
Trace
2.8 pF
XTAL
Ce1
Ce2
Trim
33 pF
Figure 2. Crystal Loading Example
.....................Document #: 001-05103 Rev *B Page 11 of 24
CY28547
CLKREQ#X
SRCT(free running)
SRCC(free running)
SRCT(stoppable)
SRCT(stoppable)
Figure 3. CLK_REQ#[1:9] Deassertion/Assertion Waveform
CLK_REQ[1:9]# Deassertion (CLKREQ# -> HIGH)
DOT) clock output of interest is programmed to ‘0’, the clock
outputs are held with “Diff clock” pin driven HIGH, and “Diff
clock#” tri-state. If the control register PD drive mode bit corre-
sponding to the output of interest is programmed to “1”, then
both the “Diff clock” and the “Diff clock#” are tri-state. Note that
Figure 4 shows CPUT = 133 MHz and PD drive mode = ‘1’ for
all differential outputs. This diagram and description is appli-
cable to valid CPU frequencies 100, 133, 166, and 200 MHz.
In the event that PD mode is desired as the initial power-on
state, PD must be asserted HIGH in less than 10 s after
asserting Vtt_PwrGd#. It should be noted that 96_100_SSC
will follow the DOT waveform when selected for 96 MHz and
the SRC waveform when in 100-MHz mode.
The impact of deasserting the CLKREQ# pins is that all SRC
outputs that are set in the control registers to stoppable via
deassertion of CLKREQ# are to be stopped after their next
transition. The final state of all stopped SRC clocks is
Low/Low.
PD (Power-down) Clarification
The VTT_PWRGD#/PD pin is a dual-function pin. During initial
power-up, the pin functions as VTT_PWRGD#. Once
VTT_PWRGD# has been sampled LOW by the clock chip, the
pin assumes PD functionality. The PD pin is an asynchronous
active HIGH input used to shut off all clocks cleanly prior to
shutting off power to the device. This signal is synchronized
internal to the device prior to powering down the clock synthe-
sizer. PD is also an asynchronous input for powering up the
system. When PD is asserted HIGH, all clocks need to be
driven to a LOW value and held prior to turning off the VCOs
and the crystal oscillator.
PD Deassertion
The power-up latency is less than 1.8 ms. This is the time from
the deassertion of the PD pin or the ramping of the power
supply until the time that stable clocks are output from the
clock chip. All differential outputs stopped in a three-state
condition resulting from power down will be driven high in less
than 300 s of PD deassertion to a voltage greater than
200 mV. After the clock chip’s internal PLL is powered up and
locked, all outputs will be enabled within a few clock cycles of
each other. Figure 5 is an example showing the relationship of
clocks coming up. It should be noted that 96_100_SSC will
follow the DOT waveform when selected for 96 MHz and the
SRC waveform when in 100-MHz mode.
PD (Power-down) Assertion
When PD is sampled HIGH by two consecutive rising edges
of CPUC, all single-ended outputs will be held LOW on their
next HIGH-to-LOW transition and differential clocks must be
held HIGH or tri-stated (depending on the state of the control
register drive mode bit) on the next diff clock# HIGH-to-LOW
transition within 4 clock periods. When the SMBus PD drive
mode bit corresponding to the differential (CPU, SRC, and
PD
CPUT, 133MHz
CPUC, 133MHz
SRCT 100MHz
SRCC 100MHz
USB, 48MHz
DOT96T
DOT96C
PCI, 33 MHz
REF
Figure 4. Power-down Assertion Timing Waveform
.....................Document #: 001-05103 Rev *B Page 12 of 24
CY28547
Tstable
<1.8 ms
PD
CPUT, 133MHz
CPUC, 133MHz
SRCT 100MHz
SRCC 100MHz
USB, 48MHz
DOT96T
DOT96C
PCI, 33MHz
REF
Tdrive_PWRDN#
<300 s, >200 mV
Figure 5. Power-down Deassertion Timing Waveform
CPU_STP# Assertion
set with the SMBus configuration to be stoppable via assertion
of CPU_STP# will be stopped within two–six CPU clock
periods after being sampled by two rising edges of the internal
CPUC clock. The final state of all stopped CPU clocks is
High/Low when driven, Low/Low when tri-stated.
The CPU_STP# signal is an active LOW input used for
synchronous stopping and starting the CPU output clocks
while the rest of the clock generator continues to function.
When the CPU_STP# pin is asserted, all CPU outputs that are
CPU_STP#
CPUT
CPUC
Figure 6. CPU_STP# Assertion Waveform
CPU_STP#
CPUT
CPUC
CPUT Internal
CPUC Internal
Tdrive_CPU_STP#,10 ns>200 mV
Figure 7. CPU_STP# Deassertion Waveform
.....................Document #: 001-05103 Rev *B Page 13 of 24
CY28547
PCI_STP# Assertion
driven Low, SRC outputs are High/Low if set to driven and
Low/Low if set to tri-state.
The PCI_STP# signal is an active LOW input used for
synchronous stopping and starting the PCI outputs and SRC
outputs if they are set to be stoppable in SMbus while the rest
of the clock generator continues to function. The set-up time
for capturing PCI_STP# going LOW is 10 ns (tSU). (See
Figure 9.) The PCIF clocks will not be affected by this pin if
their corresponding control bit in the SMBus register is set to
allow them to be free running. All stopped PCI outputs are
PCI_STP# Deassertion
The deassertion of the PCI_STP# signal will cause all PCI and
stoppable PCIF clocks to resume running in a synchronous
manner within two PCI clock periods after PCI_STP# transi-
tions to a HIGH level
1.8mS
CPU_STOP#
PD
CPUT(Free Running)
CPUC(Free Running)
CPUT(Stoppable)
CPUC(Stoppable)
DOT96T
DOT96C
Figure 8. CPU_STP# = Tri-state, CPU_PD = Tri-state, DOT_PD = Tri-state
Tsu
PCI_STP#
PCI_F
PCI
SRC 100MHz
Figure 9. PCI_STP# Assertion Waveform
1.8 ms
CPU_STOP#
PD
CPUT(Free Running
CPUC(Free Running
CPUT(Stoppable)
CPUC(Stoppable)
Figure 10. CPU_STP# = Driven, CPU_PD = Driven, DOT_PD = Driven
.....................Document #: 001-05103 Rev *B Page 14 of 24
CY28547
Tdrive_SRC
Tsu
PCI_STP#
PCI_F
PCI
SRC 100MHz
Figure 11. PCI_STP# Deassertion Waveform
FS_A, FS_B,FS_C
VTT_PWRGD#
PWRGD_VRM
0.2-0.3mS
Delay
Wait for
VTT_PWRGD#
Device is not affected,
VTT_PWRGD# is ignored
Sample Sels
State 2
VDD Clock Gen
Clock State
State 0
Off
State 1
State 3
On
Clock Outputs
Clock VCO
On
Off
Figure 12. VTTPWRGD# Timing DIagram
Figure 13. CY28547 State Diagram
.....................Document #: 001-05103 Rev *B Page 15 of 24
CY28547
C l o c k O f f t o M1
3.3V
Vcc
2.0V
T_delay t
FSC
FSB
FSA
CPU_STOP#
PCI_STOP#
CKPWRGD/PWRDWN
CK505 SMBUS
CK505 State
Off
Latches Open
Off
M1
BSEL[0..2]
Off
CK505 Core Logic
PLL1
Locked
CPU1
PLL2 & PLL3
All Other Clocks
REF Oscillator
T_delay2
T_delay3
Figure 14. BSEL Serial Latching
.....................Document #: 001-05103 Rev *B Page 16 of 24
CY28547
Absolute Maximum Conditions
Parameter
VDD
Description
Core Supply Voltage
Condition
Min.
–0.5
–0.5
–0.5
–65
0
Max.
4.6
Unit
V
4.6
VDD_A
VIN
Analog Supply Voltage
Input Voltage
V
V
+ 0.5
Relative to VSS
Non-functional
Functional
VDC
°C
DD
TS
Temperature, Storage
150
85
150
20
60
–
TA
Temperature, Operating Ambient
Temperature, Junction
°C
TJ
Functional
–
°C
ØJC
Dissipation, Junction to Case
Dissipation, Junction to Ambient
Mil-STD-883E Method 1012.1
JEDEC (JESD 51)
–
°C/W
°C/W
V
ØJA
–
ESDHBM
UL-94
MSL
ESD Protection (Human Body Model) MIL-STD-883, Method 3015
2000
Flammability Rating
At 1/8 in.
V–0
1
Moisture Sensitivity Level
Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
DC Electrical Specifications
Parameter
All VDDs
VILI2C
VIHI2C
VIL_FS
VIH_FS
VILFS_C
VIMFS_C
VIHFS_C
VIL
Description
3.3V Operating Voltage
Input Low Voltage
Condition
Min.
3.135
–
Max. Unit
3.3 ± 5%
3.465
1.0
V
V
SDATA, SCLK
SDATA, SCLK
Input High Voltage
2.2
–
V
V
V
– 0.3
FS_[A,B] Input Low Voltage
FS_[A,B] Input High Voltage
FS_C Input Low Voltage
FS_C Input Middle Voltage
FS_C Input High Voltage
3.3V Input Low Voltage
3.3V Input High Voltage
Input Low Leakage Current
Input High Leakage Current
3.3V Output Low Voltage
3.3V Output High Voltage
High-impedance Output Current
Input Pin Capacitance
Output Pin Capacitance
Pin Inductance
0.35
V
SS
V
+ 0.5
0.7
– 0.3
V
DD
0.35
1.7
+ 0.5
V
SS
0.7
2.0
– 0.3
V
V
V
V
DD
V
0.8
+ 0.3
V
SS
VIH
2.0
–5
–
V
DD
IIL
Except internal pull-up resistors, 0 < VIN < VDD
Except internal pull-down resistors, 0 < VIN < VDD
IOL = 1 mA
5
5
A
A
V
IIH
VOL
–
0.4
–
VOH
IOH = –1 mA
2.4
–10
3
V
IOZ
10
5
A
pF
pF
nH
V
CIN
COUT
LIN
3
6
–
7
VXIH
Xin High Voltage
0.7V
0
VDD
DD
0.3V
VXIL
Xin Low Voltage
V
DD
IDD3.3V
Dynamic Supply Current
In low drive mode per Figure 15 and Figure 17
@133 MHz
–
250
mA
IPD3.3V
IPD3.3V
Power-down Supply Current
Power-down Supply Current
PD asserted, Outputs Driven
PD asserted, Outputs Tri-state
–
–
30
5
mA
mA
.....................Document #: 001-05103 Rev *B Page 17 of 24
CY28547
AC Electrical Specifications
Parameter
Crystal
TDC
Description
Condition
Min.
Max. Unit
XIN Duty Cycle
The device will operate reliably with input duty
cycles up to 30/70 but the REF clock duty cycle
will not be within specification
47.5
52.5
%
TPERIOD
TR/TF
XIN Period
When XIN is driven from an external clock source 69.841
71.0
10.0
500
ns
ns
ps
XIN Rise and Fall Times
XIN Cycle to Cycle Jitter
Measured between 0.3VDD and 0.7VDD
–
–
TCCJ
As an average over 1-s duration
CPU
45
55
TDC
CPUT and CPUC Duty Cycle
Measured at 0V differential at 0.1s
Measured at 0V differential at 0.1s
Measured at 0V differential at 0.1s
Measured at 0V differential at 0.1s
Measured at 0V differential at 0.1s
Measured at 0V differential at 0.1s
Measured at 0V differential at 0.1s
Measured at 0V differential at 0.1s
%
ns
ns
ns
ns
ns
ns
ns
ns
9.99900 10.0100
7.49925 7.50075
5.99940 6.00060
4.99950 5.00050
3.74963 3.75038
2.99970 3.00030
2.49975 2.50025
10.02406 10.02607
TPERIOD
TPERIOD
TPERIOD
TPERIOD
TPERIOD
TPERIOD
TPERIOD
100 MHz CPUT and CPUC Period
133 MHz CPUT and CPUC Period
166 MHz CPUT and CPUC Period
200 MHz CPUT and CPUC Period
266 MHz CPUT and CPUC Period
333 MHz CPUT and CPUC Period
400 MHz CPUT and CPUC Period
TPERIODSS 100 MHz CPUT and CPUC Period, Measured at 0V differential at 0.1s
SSC
7.51804 7.51955
6.01444 6.01564
5.01203 5.01303
3.75902 3.75978
3.00722 3.00782
2.50601 2.50652
9.91400 10.0860
7.41425 7.58575
5.91440 6.08560
4.91450 5.08550
3.66463 3.83538
2.91470 3.08530
2.41475 2.58525
9.91406 10.1362
7.41430 7.62340
TPERIODSS 133 MHz CPUT and CPUC Period, Measured at 0V differential at 0.1s
SSC
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TPERIODSS 166 MHz CPUT and CPUC Period, Measured at 0V differential at 0.1s
SSC
TPERIODSS 200 MHz CPUT and CPUC Period, Measured at 0V differential at 0.1s
SSC
TPERIODSS 266 MHz CPUT and CPUC Period, Measured at 0V differential at 0.1s
SSC
TPERIODSS 333 MHz CPUT and CPUC Period, Measured at 0V differential at 0.1s
SSC
TPERIODSS 400 MHz CPUT and CPUC Period, Measured at 0V differential at 0.1s
SSC
TPERIODAbs 100 MHz CPUT and CPUC Absolute Measured at 0V differential at 1 clock
period
TPERIODAbs 133 MHz CPUT and CPUC Absolute Measured at 0V differential at 1 clock
period
TPERIODAbs 166 MHz CPUT and CPUC Absolute Measured at 0V differential @ 1 clock
period
TPERIODAbs 200 MHz CPUT and CPUC Absolute Measured at 0V differential @ 1 clock
period
TPERIODAbs 266 MHz CPUT and CPUC Absolute Measured at 0V differential @ 1 clock
period
TPERIODAbs 333 MHz CPUT and CPUC Absolute Measured at 0V differential @ 1 clock
period
TPERIODAbs 400 MHz CPUT and CPUC Absolute Measured at 0V differential @ 1 clock
period
TPERI-
ODSSAbs
TPERI-
100 MHz CPUT and CPUC Absolute Measured at 0V differential @ 1 clock
period, SSC
133 MHz CPUT and CPUC Absolute Measured at 0V differential @ 1 clock
period, SSC
ODSSAbs
.....................Document #: 001-05103 Rev *B Page 18 of 24
CY28547
AC Electrical Specifications (continued)
Parameter
Description
Condition
Min.
Max. Unit
5.91444 6.11572
4.91453 5.11060
3.66465 3.85420
2.91472 3.10036
2.41477 2.59780
TPERI-
ODSSAbs
TPERI-
ODSSAbs
TPERI-
ODSSAbs
TPERI-
ODSSAbs
TPERI-
ODSSAbs
TCCJ
166 MHz CPUT and CPUC Absolute Measured at 0V differential @ 1 clock
period, SSC
ns
ns
ns
ns
ns
200 MHz CPUT and CPUC Absolute Measured at 0V differential @ 1 clock
period, SSC
266 MHz CPUT and CPUC Absolute Measured at 0V differential @ 1 clock
period, SSC
333 MHz CPUT and CPUC Absolute Measured at 0V differential @ 1 clock
period, SSC
400 MHz CPUT and CPUC Absolute Measured at 0V differential @ 1 clock
period, SSC
CPU Cycle to Cycle Jitter
CPU2_ITP Cycle to Cycle Jitter
Long-term Accuracy
Measured at 0V differential
–
–
85
125
100
100
150
8
ps
ps
TCCJ2
Measured at 0V differential
LACC
Measured at 0V differential
–
ppm
ps
TSKEW
TSKEW2
TR / TF
TRFM
CPU0 to CPU1 Clock Skew
CPU2_ITP to CPU0 Clock Skew
CPU Rising/Falling Slew rate
Rise/Fall Matching
Measured at 0V differential
–
Measured at 0V differential
–
ps
Measured differentially from ±150 mV
Measured single-endedly from ±75 mV
2.5
–
V/ns
%
20
VHIGH
VLOW
Voltage High
1.15
–
V
Voltage Low
–0.3
300
V
VOX
Crossing Point Voltage at 0.7V Swing
550
mV
SRC at 0.7V
TDC
SRC Duty Cycle
Measured at 0V differential
45
55
%
ns
ns
ns
ns
9.99900 10.0010
10.02406 10.02607
9.87400 10.1260
9.87406 10.1762
TPERIOD
100 MHz SRC Period
Measured at 0V differential @ 0.1s
Measured at 0V differential @ 0.1s
Measured at 0V differential @ 1 clock
TPERIODSS 100 MHz SRC Period, SSC
TPERIODAbs 100 MHz SRC Absolute Period
TPERI-
100 MHz SRC Absolute Period, SSC Measured at 0V differential @ 1 clock
ODSSAbs
TSKEW(windo Any SRC Clock Skew from the
Measured at 0V differential
–
3.0
ns
earliest bank to the latest bank
w)
TCCJ
SRC Cycle to Cycle Jitter
SRC Long Term Accuracy
SRC Rising/Falling Slew Rate
Rise/Fall Matching
Measured at 0V differential
–
–
125
100
8
ps
ppm
V/ns
%
LACC
TR / TF
TRFM
VHIGH
VLOW
VOX
Measured at 0V differential
Measured differentially from ±150 mV
Measured single-endedly from ±75 mV
2.5
–
20
Voltage High
1.15
–
V
Voltage Low
–0.3
300
V
Crossing Point Voltage at 0.7V Swing
550
mV
DOT96 at 0.7V
TDC
DOT96 Duty Cycle
DOT96 Period
Measured at 0V differential
45
55
%
ns
10.4156 10.4177
10.1656 10.6677
TPERIOD
Measured at 0V differential at 0.1s
Measured at 0V differential at 0.1s
Measured at 0V differential at 1 clock
Measured at 0V differential at 1 clock
Measured differentially from ±150 mV
Measured single-endedly from ±75 mV
TPERIODAbs DOT96 Absolute Period
ns
TCCJ
DOT96 Cycle to Cycle Jitter
DOT96 Long Term Accuracy
DOT96 Rising/Falling Slew Rate
Rise/Fall Matching
–
–
250
100
8
ps
LACC
ppm
V/ns
%
TR / TF
TRFM
VHIGH
2.5
–
20
Voltage High
1.15
V
.....................Document #: 001-05103 Rev *B Page 19 of 24
CY28547
AC Electrical Specifications (continued)
Parameter
VLOW
Description
Voltage Low
Crossing Point Voltage at 0.7V Swing
Condition
Min.
–0.3
300
Max. Unit
–
V
VOX
550
mV
LCD_100_SSC at 0.7V
TDC
LCD_100 Duty Cycle
100 MHz LCD_100 Period
Measured at 0V differential
45
55
%
TPERIOD
Measured at 0V differential at 0.1s
Measured at 0V differential at 0.1s
9.99900 10.0010 ns
10.0240 10.0260 ns
TPERIODSS 100 MHz LCD_100 Period, SSC
-0.5%
6
7
TPERIODAbs 100 MHz LCD_100 Absolute Period Measured at 0V differential at 1 clock
9.74900 10.2510 ns
0
TPERI-
ODSSAbs
TCCJ
100 MHz LCD_100 Absolute Period, Measured at 0V differential @ 1 clock
SSC
9.74906 10.3012 ns
LCD_100 Cycle to Cycle Jitter
LCD_100 Long Term Accuracy
Measured at 0V differential
Measured at 0V differential
–
–
250
100
8
ps
ppm
V/ns
%
LACC
TR / TF
TRFM
VHIGH
VLOW
VOX
LCD_100 Rising/Falling Slew Rate Measured differentially from ±150 mV
2.5
–
Rise/Fall Matching
Voltage High
Measured single-endedly from ±75 mV
20
1.15
–
V
Voltage Low
–0.3
300
V
Crossing Point Voltage at 0.7V Swing
550
mV
PCI/PCIF at 3.3V
TDC
PCI Duty Cycle
Spread Disabled PCIF/PCI Period
Measurement at 1.5V
Measurement at 1.5V
Measurement at 1.5V
Measurement at 1.5V
Measurement at 1.5V
45
55
%
ns
ns
ns
ns
29.99700 30.00300
30.08421 30.23459
29.49700 30.50300
29.56617 30.58421
TPERIOD
TPERIODSS Spread Enabled PCIF/PCI Period
TPERIODAbs Spread Disabled PCIF/PCI Period
TPERI-
ODSSAbs
THIGH
Spread Enabled PCIF/PCI Period
Spread Enabled PCIF and PCI high Measurement at 2V
time
12.2709 16.2799 ns
5
5
TLOW
THIGH
TLOW
Spread Enabled PCIF and PCI low Measurement at 0.8V
time
11.8709 16.0799 ns
5
5
Spread Disabled PCIF and PCI high Measurement at 2.V
time
12.2736 16.2766 ns
5
5
Spread Disabled PCIF and PCI low Measurement at 0.8V
time
11.8736 16.0766 ns
5
1.0
–
5
TR / TF
TSKEW
TCCJ
PCIF/PCI Rising/Falling Slew Rate Measured between 0.8V and 2.0V
Any PCI clock to Any PCI clock Skew Measurement at 1.5V
PCIF and PCI Cycle to Cycle Jitter Measurement at 1.5V
4.0
V/ns
ps
1000
500
100
–
ps
LACC
PCIF/PCI Long Term Accuracy
Measurement at 1.5V
–
ppm
48_M at 3.3V
TDC
Duty Cycle
Period
Measurement at 1.5V
Measurement at 1.5V
Measurement at 1.5V
Measurement at 2V
45
55
%
ns
20.83125 20.83542
20.48125 21.18542
8.216563 11.15198
7.816563 10.95198
TPERIOD
TPERIODAbs Absolute Period
ns
THIGH
TLOW
TR / TF
TCCJ
48_M High time
ns
48_M Low time
Measurement at 0.8V
Measured between 0.8V and 2.0V
Measurement at 1.5V
Measurement at 1.5V
ns
Rising and Falling Edge Rate
Cycle to Cycle Jitter
48M Long Term Accuracy
1.0
–
2.0
350
100
V/ns
ps
LACC
–
ppm
.....................Document #: 001-05103 Rev *B Page 20 of 24
CY28547
AC Electrical Specifications (continued)
Parameter
Description
Condition
Measurement at 1.5V
Min.
Max. Unit
27M_NSS/27M_SS at 3.3V
TDC
Duty Cycle
45
55
%
TPERIOD
Spread Disabled 27M Period
Measurement at 1.5V
37.0359 37.0381 ns
4
3
Spread Enabled 27M Period
Measurement at 1.5V
37.0359 37.0381 ns
4
1.0
–
3
TR / TF
TCCJ
Rising and Falling Edge Rate
Cycle to Cycle Jitter
Measured between 0.4V and 2.0V
Measurement at 1.5V
4.0
200
50
V/ns
ps
LACC
27_M Long Term Accuracy
Measured at crossing point VOX
–
ppm
REF
TDC
REF Duty Cycle
REF Period
Measurement at 1.5V
Measurement at 1.5V
Measurement at 1.5V
Measurement at 2V
45
55
%
69.82033 69.86224 ns
68.83429 70.84826 ns
29.97543 38.46654 ns
29.57543 38.26654 ns
TPERIOD
TPERIODAbs REF Absolute Period
THIGH
TLOW
TR / TF
TSKEW
TCCJ
REF High time
Measurement at 0.8V
Measured between 0.8V and 2.0V
Measurement at 1.5V
Measurement at 1.5V
Measurement at 1.5V
REF Low time
REF Rising and Falling Edge Rate
REF Clock to REF Clock
REF Cycle to Cycle Jitter
Long Term Accuracy
1.0
–
4.0
500
V/ns
ps
–
1000
100
ps
LACC
–
ppm
ENABLE/DISABLE and SET-UP
TSTABLE Clock Stabilization from Power-up
TSS Stopclock Set-up Time
–
1.8
–
ms
ns
10.0
Test and Measurement Set-up
For Single-ended Signals and Reference
The following diagram shows test load configurations for the
single-ended PCI, USB, and REF output signals.
Figure 15.Single-ended Load Configuration Low Drive Option
.....................Document #: 001-05103 Rev *B Page 21 of 24
CY28547
Figure 16. Single-ended Load Configuration High Drive Option
The following diagram shows the test load configuration for the
differential CPU and SRC outputs.
Figure 17. 0.8V Differential Load Configuration
3 .3 V s ig n a ls
T D C
-
-
3.3V
2.0V
1.5V
0.8V
0V
T R
T F
Figure 18. Single-ended Output Signals (for AC Parameters Measurement)
Ordering Information
Part Number
Lead-free
CY28547LFXC
Package Type
Product Flow
Commercial, 0 to 85C
72-pin QFN
.....................Document #: 001-05103 Rev *B Page 22 of 24
CY28547
Ordering Information
CY28547LFXCT
72-pin QFN–Tape and Reel
Commercial, 0 to 85C
Package Diagram
72-Lead QFN 10 x 10 mm (Punch Version) LF72A
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.....................Document #: 001-05103 Rev *B Page 23 of 24
CY28547
Document History Page
Document Title: CY28547 Clock Generator for Intel®CK410M/CK505
Document Number: 001-05103
Orig. of
REV.
1.0
Issue Date Change
Description of Change
See ECN
RGL
New data sheet
1.1
See ECN RGL/XLZ Modify the definition of pin 9, 27, 32 and 39
Re-arrange control register map
Update AC Electrical Specifications table
1.2
1.3
See ECN
12/28/06
RGL
JMA
Modify the pin description table
Update the default values in the control register bytes 7, 8, 9, 11, 12, 14, and 15
1. Modified Revision ID Bit from 0010 to 0011
2. Set Byte 12 <7> from DIAG_EN to Reserved
3. Set Byte 12 <6> from CPU_PLL Status to Reserved
4. Set Byte 12 <5> from Video_PLL Status to Reserved
5. Set Byte 12 <4> from Fixed_PLL Status to Reserved
6. Edited Figure 15 and 16 Terminationa Resistor for double load 12-ohm to
22-ohm
7. Edited Figure 15 and 16 Load from 5pF to 4pF.
8. Changed CPU Vox_min from 250ps to 300ps
9. Changed SRC Vox_min from 180ps to 300ps
10. Changed LCD Vox_min from 250ps to 300ps
11. Changed DOTVox_min from 250ps to 300ps
1.4
10/31/07
JMA
Added Mitsui package
.....................Document #: 001-05103 Rev *B Page 24 of 24
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using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific
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reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy
or completeness of the included information. Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply
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