EFM32TG108F16-QFN24T [SILICON]
Microcontroller, 32-Bit, FLASH, CORTEX-M3 CPU, 32MHz, CMOS, PQCC24;
| 型号： | EFM32TG108F16-QFN24T |
| 厂家： | 
SILICON |
| 描述： | Microcontroller, 32-Bit, FLASH, CORTEX-M3 CPU, 32MHz, CMOS, PQCC24 时钟 微控制器 外围集成电路 |
| 文件： | 总48页 (文件大小：1298K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EFM32TG108 DATASHEET
F32/F16/F8/F4
• ARM Cortex-M3 CPU platform
• Communication interfaces
• High Performance 32-bit processor @ up to 32 MHz
• Wake-up Interrupt Controller
• Universal Synchronous/Asynchronous Receiv-
er/Transmitter
• UART/SPI/SmartCard (ISO 7816)/IrDA/I2S
• Triple buffered full/half-duplex operation
• Low Energy UART
• Flexible Energy Management System
• 20 nA @ 3 V Shutoff Mode
• 0.6 µA @ 3 V Stop Mode, including Power-on Reset, Brown-out
Detector, RAM and CPU retention
• 1.0 µA @ 3 V Deep Sleep Mode, including RTC with 32.768 kHz
oscillator, Power-on Reset, Brown-out Detector, RAM and CPU
retention
• 51 µA/MHz @ 3 V Sleep Mode
• 150 µA/MHz @ 3 V Run Mode, with code executed from flash
• 32/16/8/4 KB Flash
• Autonomous operation with DMA in Deep Sleep
Mode
• I2C Interface with SMBus support
• Address recognition in Stop Mode
• Ultra low power precision analog peripherals
• 2× Analog Comparator
• Capacitive sensing with up to 4 inputs
• Supply Voltage Comparator
• 4/4/2/2 KB RAM
• 17 General Purpose I/O pins
• Configurable push-pull, open-drain, pull-up/down, input filter, drive
strength
• Configurable peripheral I/O locations
• 11 asynchronous external interrupts
• Output state retention and wake-up from Shutoff Mode
• 8 Channel DMA Controller
• 8 Channel Peripheral Reflex System (PRS) for autonomous in-
ter-peripheral signaling
• Low Energy Sensor Interface (LESENSE)
• Autonomous sensor monitoring in Deep Sleep Mode
• Ultra efficient Power-on Reset and Brown-Out Detec-
tor
• 2-pin Serial Wire Debug interface
• 1-pin Serial Wire Viewer
• Pre-Programmed UART Bootloader
• Temperature range -40 to 85 ºC
• Single power supply 1.98 to 3.8 V
• QFN24 package
• Timers/Counters
• 2× 16-bit Timer/Counter
• 2×3 Compare/Capture/PWM channels
• 16-bit Low Energy Timer
• 1× 24-bit Real-Time Counter
• 1× 16-bit Pulse Counter
• Watchdog Timer with dedicated RC oscillator @ 50 nA
32-bit ARM Cortex-M0+, Cortex-M3 and Cortex-M4 microcontrollers for:
• Energy, gas, water and smart metering
• Health and fitness applications
• Smart accessories
• Alarm and security systems
• Industrial and home automation
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1 Ordering Information
Table 1.1 (p. 2) shows the available EFM32TG108 devices.
Table 1.1. Ordering Information
Ordering Code
Flash (kB) RAM (kB)
Max
Speed
(MHz)
Supply
Voltage
(V)
Temperature
(ºC)
Package
EFM32TG108F4-QFN24
EFM32TG108F8-QFN24
EFM32TG108F16-QFN24
EFM32TG108F32-QFN24
4
2
2
4
4
32
32
32
32
1.98 - 3.8
1.98 - 3.8
1.98 - 3.8
1.98 - 3.8
-40 - 85
-40 - 85
-40 - 85
-40 - 85
QFN24
QFN24
QFN24
QFN24
8
16
32
Visit www.silabs.com for information on global distributors and representatives.
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2 System Summary
2.1 System Introduction
The EFM32 MCUs are the world’s most energy friendly microcontrollers. With a unique combination of
the powerful 32-bit ARM Cortex-M3, innovative low energy techniques, short wake-up time from ener-
gy saving modes, and a wide selection of peripherals, the EFM32TG microcontroller is well suited for
any battery operated application as well as other systems requiring high performance and low-energy
consumption. This section gives a short introduction to each of the modules in general terms and also
shows a summary of the configuration for the EFM32TG108 devices. For a complete feature set and in-
depth information on the modules, the reader is referred to the EFM32TG Reference Manual.
A block diagram of the EFM32TG108 is shown in Figure 2.1 (p. 3) .
Figure 2.1. Block Diagram
TG108F4/ 8/ 16/ 32
Core andMemory
Clock Management
Energy Management
High Frequency
Crystal
High Frequency
RC
Voltage
Voltage
Oscillator
Oscillator
ARM Cortex- M3 processor
Regulator
Comparator
Low Frequency
RC
Aux High Freq
RC
Oscillator
Oscillator
Flash
Memory
[KB]
RAM
Memory
[KB]
Debug
Interface
DMA
Controller
Power-on
Reset
Brown-out
Detector
Low Frequency
Crystal
Oscillator
Watchdog
Oscillator
4/ 8/ 16/ 32
2/ 2/ 4/ 4
32-bit bus
Peripheral Reflex System
Serial Interfaces
I/O Ports
Timers and Triggers
Analog Interfaces
Security
Timer/
Counter
Low
Energy
Sensor
General
Purpose
I/ O
Analog
Comparator
External
Interrupts
USART
1x
2x
17 pins
Low Energy Real Time
Timer
Counter
Low
Energy
UART™
Pin
Reset
I2C
Pulse
Counter
Watchdog
Timer
2.1.1 ARM Cortex-M3 Core
The ARM Cortex-M3 includes a 32-bit RISC processor which can achieve as much as 1.25 Dhrystone
MIPS/MHz. A Wake-up Interrupt Controller handling interrupts triggered while the CPU is asleep is in-
cluded as well. The EFM32 implementation of the Cortex-M3 is described in detail in EFM32 Cortex-M3
Reference Manual.
2.1.2 Debug Interface (DBG)
This device includes hardware debug support through a 2-pin serial-wire debug interface . In addition
there is also a 1-wire Serial Wire Viewer pin which can be used to output profiling information, data trace
and software-generated messages.
2.1.3 Memory System Controller (MSC)
The Memory System Controller (MSC) is the program memory unit of the EFM32TG microcontroller.
The flash memory is readable and writable from both the Cortex-M3 and DMA. The flash memory is
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divided into two blocks; the main block and the information block. Program code is normally written to
the main block. Additionally, the information block is available for special user data and flash lock bits.
There is also a read-only page in the information block containing system and device calibration data.
Read and write operations are supported in the energy modes EM0 and EM1.
2.1.4 Direct Memory Access Controller (DMA)
The Direct Memory Access (DMA) controller performs memory operations independently of the CPU.
This has the benefit of reducing the energy consumption and the workload of the CPU, and enables
the system to stay in low energy modes when moving for instance data from the USART to RAM or
from the External Bus Interface to a PWM-generating timer. The DMA controller uses the PL230 µDMA
controller licensed from ARM.
2.1.5 Reset Management Unit (RMU)
The RMU is responsible for handling the reset functionality of the EFM32TG.
2.1.6 Energy Management Unit (EMU)
The Energy Management Unit (EMU) manage all the low energy modes (EM) in EFM32TG microcon-
trollers. Each energy mode manages if the CPU and the various peripherals are available. The EMU
can also be used to turn off the power to unused SRAM blocks.
2.1.7 Clock Management Unit (CMU)
The Clock Management Unit (CMU) is responsible for controlling the oscillators and clocks on-board
the EFM32TG. The CMU provides the capability to turn on and off the clock on an individual basis to all
peripheral modules in addition to enable/disable and configure the available oscillators. The high degree
of flexibility enables software to minimize energy consumption in any specific application by not wasting
power on peripherals and oscillators that are inactive.
2.1.8 Watchdog (WDOG)
The purpose of the watchdog timer is to generate a reset in case of a system failure, to increase appli-
cation reliability. The failure may e.g. be caused by an external event, such as an ESD pulse, or by a
software failure.
2.1.9 Peripheral Reflex System (PRS)
The Peripheral Reflex System (PRS) system is a network which lets the different peripheral module
communicate directly with each other without involving the CPU. Peripheral modules which send out
Reflex signals are called producers. The PRS routes these reflex signals to consumer peripherals which
apply actions depending on the data received. The format for the Reflex signals is not given, but edge
triggers and other functionality can be applied by the PRS.
2.1.10 Inter-Integrated Circuit Interface (I2C)
The I2C module provides an interface between the MCU and a serial I2C-bus. It is capable of acting as
both a master and a slave, and supports multi-master buses. Both standard-mode, fast-mode and fast-
mode plus speeds are supported, allowing transmission rates all the way from 10 kbit/s up to 1 Mbit/s.
Slave arbitration and timeouts are also provided to allow implementation of an SMBus compliant system.
The interface provided to software by the I2C module, allows both fine-grained control of the transmission
process and close to automatic transfers. Automatic recognition of slave addresses is provided in all
energy modes.
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2.1.11 Universal Synchronous/Asynchronous Receiver/Transmitter (US-
ART)
The Universal Synchronous Asynchronous serial Receiver and Transmitter (USART) is a very flexible
serial I/O module. It supports full duplex asynchronous UART communication as well as RS-485, SPI,
MicroWire and 3-wire. It can also interface with ISO7816 SmartCards, IrDA and I2S devices.
2.1.12 Pre-Programmed UART Bootloader
The bootloader presented in application note AN0003 is pre-programmed in the device at factory. Auto-
baud and destructive write are supported. The autobaud feature, interface and commands are described
further in the application note.
2.1.13 Low Energy Universal Asynchronous Receiver/Transmitter
(LEUART)
The unique LEUARTTM, the Low Energy UART, is a UART that allows two-way UART communication on
a strict power budget. Only a 32.768 kHz clock is needed to allow UART communication up to 9600 baud/
s. The LEUART includes all necessary hardware support to make asynchronous serial communication
possible with minimum of software intervention and energy consumption.
2.1.14 Timer/Counter (TIMER)
The 16-bit general purpose Timer has 3 compare/capture channels for input capture and compare/Pulse-
Width Modulation (PWM) output.
2.1.15 Real Time Counter (RTC)
The Real Time Counter (RTC) contains a 24-bit counter and is clocked either by a 32.768 kHz crystal
oscillator, or a 32.768 kHz RC oscillator. In addition to energy modes EM0 and EM1, the RTC is also
available in EM2. This makes it ideal for keeping track of time since the RTC is enabled in EM2 where
most of the device is powered down.
2.1.16 Low Energy Timer (LETIMER)
The unique LETIMERTM, the Low Energy Timer, is a 16-bit timer that is available in energy mode EM2
in addition to EM1 and EM0. Because of this, it can be used for timing and output generation when most
of the device is powered down, allowing simple tasks to be performed while the power consumption of
the system is kept at an absolute minimum. The LETIMER can be used to output a variety of waveforms
with minimal software intervention. It is also connected to the Real Time Counter (RTC), and can be
configured to start counting on compare matches from the RTC.
2.1.17 Pulse Counter (PCNT)
The Pulse Counter (PCNT) can be used for counting pulses on a single input or to decode quadrature
encoded inputs. It runs off either the internal LFACLK or the PCNTn_S0IN pin as external clock source.
The module may operate in energy mode EM0 - EM3.
2.1.18 Analog Comparator (ACMP)
The Analog Comparator is used to compare the voltage of two analog inputs, with a digital output indi-
cating which input voltage is higher. Inputs can either be one of the selectable internal references or from
external pins. Response time and thereby also the current consumption can be configured by altering
the current supply to the comparator.
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2.1.19 Voltage Comparator (VCMP)
The Voltage Supply Comparator is used to monitor the supply voltage from software. An interrupt can
be generated when the supply falls below or rises above a programmable threshold. Response time and
thereby also the current consumption can be configured by altering the current supply to the comparator.
2.1.20 Low Energy Sensor Interface (LESENSE)
The Low Energy Sensor Interface (LESENSE), is a highly configurable sensor interface with support for
up to 4 individually configurable sensors. By controlling the analog comparators, LESENSE is capable of
supporting a wide range of sensors and measurement schemes, and can for instance measure resistive
and capacitive sensors. LESENSE also includes a programmable FSM which enables simple processing
of measurement results without CPU intervention. LESENSE is available in energy mode EM2, in addi-
tion to EM0 and EM1, making it ideal for sensor monitoring in applications with a strict energy budget.
2.1.21 General Purpose Input/Output (GPIO)
In the EFM32TG108, there are 17 General Purpose Input/Output (GPIO) pins, which are divided into
ports with up to 16 pins each. These pins can individually be configured as either an output or input. More
advanced configurations like open-drain, filtering and drive strength can also be configured individually
for the pins. The GPIO pins can also be overridden by peripheral pin connections, like Timer PWM
outputs or USART communication, which can be routed to several locations on the device. The GPIO
supports up to 11 asynchronous external pin interrupts, which enables interrupts from any pin on the
device. Also, the input value of a pin can be routed through the Peripheral Reflex System to other
peripherals.
2.2 Configuration Summary
The features of the EFM32TG108 is a subset of the feature set described in the EFM32TG Reference
Manual. Table 2.1 (p. 6) describes device specific implementation of the features.
Table 2.1. Configuration Summary
Module
Cortex-M3
DBG
Configuration
Pin Connections
Full configuration
Full configuration
NA
DBG_SWCLK, DBG_SWDIO,
DBG_SWO
MSC
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration with I2S
Full configuration
Full configuration
Full configuration
Full configuration
NA
DMA
NA
RMU
NA
EMU
NA
CMU
CMU_OUT0, CMU_OUT1
WDOG
PRS
NA
NA
I2C0
I2C0_SDA, I2C0_SCL
US1_TX, US1_RX, US1_CLK, US1_CS
LEU0_TX, LEU0_RX
TIM0_CC[2:0]
USART1
LEUART0
TIMER0
TIMER1
RTC
TIM1_CC[2:0]
NA
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Module
LETIMER0
PCNT0
ACMP0
ACMP1
VCMP
Configuration
Full configuration
Full configuration, 16-bit count register PCNT0_S[1:0]
Pin Connections
LET0_O[1:0]
Full configuration
Full configuration
Full configuration
17 pins
ACMP0_CH[1:0], ACMP0_O
ACMP1_CH[1:0], ACMP1_O
NA
GPIO
Available pins are shown in
Table 4.3 (p. 33)
2.3 Memory Map
The EFM32TG108 memory map is shown in Figure 2.2 (p. 7), with RAM and Flash sizes for the
largest memory configuration.
Figure 2.2. EFM32TG108 Memory Map with largest RAM and Flash sizes
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3 Electrical Characteristics
3.1 Test Conditions
3.1.1 Typical Values
The typical data are based on TAMB=25°C and VDD=3.0 V, as defined in Table 3.2 (p. 8), by simu-
lation and/or technology characterisation unless otherwise specified.
3.1.2 Minimum and Maximum Values
The minimum and maximum values represent the worst conditions of ambient temperature, supply volt-
age and frequencies, as defined in Table 3.2 (p. 8), by simulation and/or technology characterisa-
tion unless otherwise specified.
3.2 Absolute Maximum Ratings
The absolute maximum ratings are stress ratings, and functional operation under such conditions are
not guaranteed. Stress beyond the limits specified in Table 3.1 (p. 8) may affect the device reliability
or cause permanent damage to the device. Functional operating conditions are given in Table 3.2 (p.
8) .
Table 3.1. Absolute Maximum Ratings
Symbol
Parameter
Condition
Min
Typ
Max
Unit
1501 °C
TSTG
Storage tempera-
ture range
-40
TS
Maximum soldering Latest IPC/JEDEC J-STD-020
260 °C
temperature
Standard
VDDMAX
External main sup-
ply voltage
0
3.8
V
V
VIOPIN
Voltage on any I/O
pin
-0.3
VDD+0.3
1Based on programmed devices tested for 10000 hours at 150°C. Storage temperature affects retention of preprogrammed cal-
ibration values stored in flash. Please refer to the Flash section in the Electrical Characteristics for information on flash data re-
tention for different temperatures.
3.3 General Operating Conditions
3.3.1 General Operating Conditions
Table 3.2. General Operating Conditions
Symbol
TAMB
VDDOP
fAPB
Parameter
Min
Typ
Max
Unit
85 °C
3.8
Ambient temperature range
Operating supply voltage
Internal APB clock frequency
Internal AHB clock frequency
-40
1.98
V
32 MHz
32 MHz
fAHB
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3.4 Current Consumption
Table 3.3. Current Consumption
Symbol
Parameter
Condition
Min
Typ
Max
Unit
32 MHz HFXO, all peripheral
clocks disabled, VDD= 3.0 V
157
150
153
155
157
162
200
53
µA/
MHz
28 MHz HFRCO, all peripheral
clocks disabled, VDD= 3.0 V
170 µA/
MHz
21 MHz HFRCO, all peripheral
clocks disabled, VDD= 3.0 V
172 µA/
MHz
EM0 current. No
prescaling. Running
prime number cal-
culation code from
Flash. (Production
test condition = 14
MHz)
14 MHz HFRCO, all peripheral
clocks disabled, VDD= 3.0 V
175 µA/
MHz
IEM0
11 MHz HFRCO, all peripheral
clocks disabled, VDD= 3.0 V
178 µA/
MHz
6.6 MHz HFRCO, all peripheral
clocks disabled, VDD= 3.0 V
183 µA/
MHz
1.2 MHz HFRCO, all peripheral
clocks disabled, VDD= 3.0 V
240 µA/
MHz
32 MHz HFXO, all peripheral
clocks disabled, VDD= 3.0 V
µA/
MHz
28 MHz HFRCO, all peripheral
clocks disabled, VDD= 3.0 V
51
57 µA/
MHz
21 MHz HFRCO, all peripheral
clocks disabled, VDD= 3.0 V
55
59 µA/
MHz
EM1 current (Pro-
duction test condi-
tion = 14 MHz)
14 MHz HFRCO, all peripheral
clocks disabled, VDD= 3.0 V
56
61 µA/
MHz
IEM1
11 MHz HFRCO, all peripheral
clocks disabled, VDD= 3.0 V
58
63 µA/
MHz
6.6 MHz HFRCO, all peripheral
clocks disabled, VDD= 3.0 V
63
68 µA/
MHz
1.2 MHz HFRCO. all peripheral
clocks disabled, VDD= 3.0 V
100
1.0
122 µA/
MHz
EM2 current with RTC
prescaled to 1 Hz, 32.768
kHz LFRCO, VDD= 3.0 V,
TAMB=25°C
1.2 µA
IEM2
EM2 current
EM2 current with RTC
prescaled to 1 Hz, 32.768
kHz LFRCO, VDD= 3.0 V,
TAMB=85°C
2.4
5.0 µA
VDD= 3.0 V, TAMB=25°C
VDD= 3.0 V, TAMB=85°C
VDD= 3.0 V, TAMB=25°C
VDD= 3.0 V, TAMB=85°C
0.59
2.0
1.0 µA
4.5 µA
IEM3
EM3 current
EM4 current
0.02
0.25
0.055 µA
0.70 µA
IEM4
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Figure 3.1. EM2 current consumption. RTC prescaled to 1kHz, 32.768 kHz LFRCO.
Figure 3.2. EM3 current consumption.
Figure 3.3. EM4 current consumption.
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3.5 Transition between Energy Modes
The transition times are measured from the trigger to the first clock edge in the CPU.
Table 3.4. Energy Modes Transitions
Symbol
Parameter
Min
Typ
Max
Unit
tEM10
Transition time from EM1 to EM0
0
HF-
CORE-
CLK
cycles
tEM20
tEM30
tEM40
Transition time from EM2 to EM0
Transition time from EM3 to EM0
Transition time from EM4 to EM0
2
2
µs
µs
µs
163
3.6 Power Management
The EFM32TG requires the AVDD_x, VDD_DREG and IOVDD_x pins to be connected together (with
optional filter) at the PCB level. For practical schematic recommendations, please see the application
note, "AN0002 EFM32 Hardware Design Considerations".
Table 3.5. Power Management
Symbol
Parameter
Condition
Min
Typ
Max
Unit
VBODextthr-
BOD threshold on
falling external sup-
ply voltage
1.74
1.96
1.98
1.98
V
VBODextthr+
BOD threshold on
rising external sup-
ply voltage
1.85
V
V
VPORthr+
Power-on Reset
(POR) threshold on
rising external sup-
ply voltage
tRESET
Delay from reset
is released until
program execution
starts
Applies to Power-on Reset,
Brown-out Reset and pin reset.
163
1
µs
CDECOUPLE
Voltage regulator
decoupling capaci-
tor.
X5R capacitor recommended.
Apply between DECOUPLE pin
and GROUND
µF
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3.7 Flash
Table 3.6. Flash
Symbol
Parameter
Condition
Min
Typ
Max
Unit
ECFLASH
Flash erase cycles
before failure
20000
cycles
TAMB<150°C
10000
10
h
RETFLASH
Flash data retention TAMB<85°C
TAMB<70°C
years
years
µs
20
tW_PROG
Word (32-bit) pro-
gramming time
20
tP_ERASE
tD_ERASE
IERASE
Page erase time
Device erase time
Erase current
20
40
20.4
40.8
20.8 ms
41.6 ms
71 mA
71 mA
IWRITE
Write current
VFLASH
Supply voltage dur-
ing flash erase and
write
1.98
3.8
V
1Measured at 25°C
3.8 General Purpose Input Output
Table 3.7. GPIO
Symbol
VIOIL
Parameter
Condition
Min
Typ
Max
0.30VDD
Unit
V
Input low voltage
Input high voltage
VIOIH
0.70VDD
V
Sourcing 0.1 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= LOWEST
0.80VDD
0.90VDD
0.85VDD
0.90VDD
V
Sourcing 0.1 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= LOWEST
V
V
V
V
V
V
Sourcing 1 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= LOW
Output high volt-
age (Production test
condition = 3.0V,
DRIVEMODE =
STANDARD)
Sourcing 1 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= LOW
VIOOH
Sourcing 6 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= STANDARD
0.75VDD
0.85VDD
0.60VDD
Sourcing 6 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= STANDARD
Sourcing 20 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= HIGH
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Symbol
Parameter
Condition
Min
0.80VDD
Typ
Max
Unit
Sourcing 20 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= HIGH
V
Sinking 0.1 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= LOWEST
0.20VDD
0.10VDD
0.10VDD
0.05VDD
V
V
V
V
V
V
V
V
Sinking 0.1 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= LOWEST
Sinking 1 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= LOW
Sinking 1 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= LOW
Output low voltage
(Production test
condition = 3.0V,
DRIVEMODE =
STANDARD)
VIOOL
Sinking 6 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= STANDARD
0.30VDD
Sinking 6 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= STANDARD
0.20VDD
0.35VDD
0.20VDD
Sinking 20 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= HIGH
Sinking 20 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= HIGH
IIOLEAK
Input leakage cur-
rent
High Impedance IO connected
to GROUND or VDD
±0.1
40
±100 nA
RPU
I/O pin pull-up resis-
tor
kOhm
kOhm
Ohm
RPD
I/O pin pull-down re-
sistor
40
RIOESD
Internal ESD series
resistor
200
tIOGLITCH
Pulse width of puls-
es to be removed
by the glitch sup-
pression filter
10
50 ns
GPIO_Px_CTRL DRIVEMODE
= LOWEST and load capaci-
tance CL=12.5-25pF.
20+0.1CL
20+0.1CL
0.1VDD
250 ns
250 ns
V
tIOOF
Output fall time
GPIO_Px_CTRL DRIVEMODE
= LOW and load capacitance
CL=350-600pF
VIOHYST
I/O pin hysteresis
VDD = 1.98 - 3.8 V
(VIOTHR+ - VIOTHR-
)
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Figure 3.4. Typical Low-Level Output Current, 2V Supply Voltage
0.20
0.15
0.10
0.05
0.00
5
4
3
2
1
- 40°C
25°C
85°C
- 40°C
25°C
85°C
0
0.0
0.5
1.0
1.5
2.0
0.0
0.5
1.0
1.5
2.0
Low- Level Output Voltage [V]
Low- Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = LOWEST
GPIO_Px_CTRL DRIVEMODE = LOW
20
45
40
35
30
25
20
15
10
5
15
10
5
- 40°C
25°C
- 40°C
25°C
85°C
85°C
0
0.0
0
0.5
1.0
1.5
2.0
0.0
0.5
1.0
1.5
2.0
Low- Level Output Voltage [V]
Low- Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = STANDARD
GPIO_Px_CTRL DRIVEMODE = HIGH
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Figure 3.5. Typical High-Level Output Current, 2V Supply Voltage
0.00
–0.05
–0.10
–0.15
–0.20
0.0
–0.5
–1.0
–1.5
–2.0
–2.5
- 40°C
25°C
85°C
- 40°C
25°C
85°C
0.0
0.5
1.0
1.5
2.0
0.0
0.5
1.0
1.5
2.0
High- Level Output Voltage [V]
High- Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = LOWEST
GPIO_Px_CTRL DRIVEMODE = LOW
0
0
- 40°C
- 40°C
25°C
85°C
25°C
85°C
–10
–20
–30
–40
–50
–5
–10
–15
–20
0.0
0.5
1.0
1.5
2.0
0.0
0.5
1.0
1.5
2.0
High- Level Output Voltage [V]
High- Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = STANDARD
GPIO_Px_CTRL DRIVEMODE = HIGH
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Figure 3.6. Typical Low-Level Output Current, 3V Supply Voltage
0.5
0.4
0.3
0.2
0.1
0.0
10
8
6
4
2
- 40°C
25°C
85°C
- 40°C
25°C
85°C
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Low- Level Output Voltage [V]
Low- Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = LOWEST
GPIO_Px_CTRL DRIVEMODE = LOW
40
35
30
25
20
15
10
50
40
30
20
10
0
5
- 40°C
- 40°C
25°C
85°C
25°C
85°C
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Low- Level Output Voltage [V]
Low- Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = STANDARD
GPIO_Px_CTRL DRIVEMODE = HIGH
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Figure 3.7. Typical High-Level Output Current, 3V Supply Voltage
0.0
–0.1
–0.2
–0.3
–0.4
–0.5
0
- 40°C
25°C
85°C
- 40°C
25°C
85°C
–1
–2
–3
–4
–5
–6
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
High- Level Output Voltage [V]
High- Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = LOWEST
GPIO_Px_CTRL DRIVEMODE = LOW
0
0
- 40°C
- 40°C
25°C
85°C
25°C
85°C
–10
–20
–30
–40
–50
–10
–20
–30
–40
–50
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
High- Level Output Voltage [V]
High- Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = STANDARD
GPIO_Px_CTRL DRIVEMODE = HIGH
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Figure 3.8. Typical Low-Level Output Current, 3.8V Supply Voltage
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
14
12
10
8
6
4
2
- 40°C
25°C
85°C
- 40°C
25°C
85°C
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
Low- Level Output Voltage [V]
Low- Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = LOWEST
GPIO_Px_CTRL DRIVEMODE = LOW
50
40
30
20
10
50
40
30
20
10
0
- 40°C
25°C
- 40°C
25°C
85°C
85°C
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
Low- Level Output Voltage [V]
Low- Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = STANDARD
GPIO_Px_CTRL DRIVEMODE = HIGH
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Figure 3.9. Typical High-Level Output Current, 3.8V Supply Voltage
0.0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
0
- 40°C
25°C
85°C
- 40°C
25°C
85°C
–1
–2
–3
–4
–5
–6
–7
–8
–9
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
High- Level Output Voltage [V]
High- Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = LOWEST
GPIO_Px_CTRL DRIVEMODE = LOW
0
0
- 40°C
- 40°C
25°C
85°C
25°C
85°C
–10
–20
–30
–40
–50
–10
–20
–30
–40
–50
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
High- Level Output Voltage [V]
High- Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = STANDARD
GPIO_Px_CTRL DRIVEMODE = HIGH
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3.9 Oscillators
3.9.1 LFXO
Table 3.8. LFXO
Symbol
Parameter
Condition
Min
Typ
Max
Unit
fLFXO
Supported nominal
crystal frequency
32.768
30
kHz
ESRLFXO
Supported crystal
equivalent series re-
sistance (ESR)
120 kOhm
CLFXOL
Supported crystal
external load range
X1
25 pF
nA
ILFXO
Current consump-
tion for core and
buffer after startup.
ESR=30 kOhm, CL=10 pF,
LFXOBOOST in CMU_CTRL is
1
190
400
tLFXO
Start- up time.
ESR=30 kOhm, CL=10 pF,
40% - 60% duty cycle has
been reached, LFXOBOOST in
CMU_CTRL is 1
ms
1See Minimum Load Capacitance (CLFXOL) Requirement For Safe Crystal Startup in energyAware Designer in Simplicity Studio
For safe startup of a given crystal, the energyAware Designer in Simplicity Studio contains a tool to help
users configure both load capacitance and software settings for using the LFXO. For details regarding
the crystal configuration, the reader is referred to application note "AN0016 EFM32 Oscillator Design
Consideration".
3.9.2 HFXO
Table 3.9. HFXO
Symbol
Parameter
Condition
Min
Typ
Max
Unit
fHFXO
Supported nominal
crystal Frequency
4
32 MHz
Supported crystal
equivalent series re-
sistance (ESR)
Crystal frequency 32 MHz
Crystal frequency 4 MHz
30
60 Ohm
ESRHFXO
400
1500 Ohm
gmHFXO
The transconduc-
tance of the HFXO
input transistor at
crystal startup
HFXOBOOST in CMU_CTRL
equals 0b11
20
5
mS
CHFXOL
Supported crystal
external load range
25 pF
µA
4 MHz: ESR=400 Ohm,
CL=20 pF, HFXOBOOST in
CMU_CTRL equals 0b11
85
165
400
Current consump-
tion for HFXO after
startup
IHFXO
32 MHz: ESR=30 Ohm,
CL=10 pF, HFXOBOOST in
CMU_CTRL equals 0b11
µA
µs
tHFXO
Startup time
32 MHz: ESR=30 Ohm,
CL=10 pF, HFXOBOOST in
CMU_CTRL equals 0b11
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3.9.3 LFRCO
Table 3.10. LFRCO
Symbol
Parameter
Condition
Min
Typ
Max
Unit
fLFRCO
Oscillation frequen-
cy , VDD= 3.0 V,
TAMB=25°C
31.29
32.768
150
34.24 kHz
tLFRCO
Startup time not in-
cluding software
calibration
µs
ILFRCO
Current consump-
tion
210
1.5
380 nA
%
TUNESTEPL- Frequency step
for LSB change in
FRCO
TUNING value
Figure 3.10. Calibrated LFRCO Frequency vs Temperature and Supply Voltage
42
40
38
36
34
32
30
42
40
38
36
34
32
30
- 40°C
25°C
85°C
2.0 V
3.0 V
3.8 V
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
3.9.4 HFRCO
Table 3.11. HFRCO
Symbol
Parameter
Condition
Min
Typ
Max
Unit
28 MHz frequency band
21 MHz frequency band
14 MHz frequency band
11 MHz frequency band
7 MHz frequency band
1 MHz frequency band
fHFRCO = 14 MHz
27.16
20.37
13.58
10.67
6.401
1.162
28.0
21.0
14.0
11.0
6.601
1.202
0.6
28.84 MHz
21.63 MHz
14.42 MHz
11.33 MHz
6.801 MHz
1.242 MHz
Oscillation frequen-
cy, VDD= 3.0 V,
TAMB=25°C
fHFRCO
tHFRCO_settling Settling time after
start-up
Cycles
fHFRCO = 28 MHz
fHFRCO = 21 MHz
160
125
190 µA
155 µA
Current consump-
tion (Production test
condition = 14 MHz)
IHFRCO
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Symbol
Parameter
Condition
Min
Typ
Max
Unit
120 µA
fHFRCO = 14 MHz
fHFRCO = 11 MHz
fHFRCO = 6.6 MHz
fHFRCO = 1.2 MHz
104
94
110 µA
90 µA
32 µA
%
63
22
TUNESTEPH- Frequency step
0.33
for LSB change in
FRCO
TUNING value
1For devices with prod. rev. < 19, Typ = 7MHz and Min/Max values not applicable.
2For devices with prod. rev. < 19, Typ = 1MHz and Min/Max values not applicable.
3The TUNING field in the CMU_HFRCOCTRL register may be used to adjust the HFRCO frequency. There is enough adjustment
range to ensure that the frequency bands above 7 MHz will always have some overlap across supply voltage and temperature. By
using a stable frequency reference such as the LFXO or HFXO, a firmware calibration routine can vary the TUNING bits and the
frequency band to maintain the HFRCO frequency at any arbitrary value between 7 MHz and 28 MHz across operating conditions.
Figure 3.11. Calibrated HFRCO 1 MHz Band Frequency vs Supply Voltage and Temperature
1.45
1.40
1.35
1.30
1.25
1.20
1.15
1.10
1.05
1.45
1.40
1.35
1.30
1.25
1.20
1.15
1.10
1.05
- 40°C
25°C
85°C
2.0 V
3.0 V
3.8 V
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
Figure 3.12. Calibrated HFRCO 7 MHz Band Frequency vs Supply Voltage and Temperature
6.70
6.65
6.60
6.55
6.50
6.45
6.40
6.35
6.30
6.70
6.65
6.60
6.55
6.50
6.45
6.40
6.35
6.30
- 40°C
25°C
85°C
2.0 V
3.0 V
3.8 V
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
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Figure 3.13. Calibrated HFRCO 11 MHz Band Frequency vs Supply Voltage and Temperature
11.2
11.1
11.0
10.9
10.8
10.7
10.6
11.2
11.1
11.0
10.9
10.8
10.7
10.6
- 40°C
25°C
85°C
2.0 V
3.0 V
3.8 V
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
Figure 3.14. Calibrated HFRCO 14 MHz Band Frequency vs Supply Voltage and Temperature
14.2
14.1
14.0
13.9
13.8
13.7
13.6
13.5
13.4
14.2
14.1
14.0
13.9
13.8
13.7
13.6
13.5
13.4
- 40°C
25°C
85°C
2.0 V
3.0 V
3.8 V
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
Figure 3.15. Calibrated HFRCO 21 MHz Band Frequency vs Supply Voltage and Temperature
21.2
21.0
20.8
20.6
20.4
20.2
21.2
21.0
20.8
20.6
20.4
20.2
- 40°C
25°C
85°C
2.0 V
3.0 V
3.8 V
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
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Figure 3.16. Calibrated HFRCO 28 MHz Band Frequency vs Supply Voltage and Temperature
28.2
28.0
27.8
27.6
27.4
27.2
27.0
26.8
28.4
28.2
28.0
27.8
27.6
27.4
27.2
27.0
26.8
- 40°C
25°C
85°C
2.0 V
3.0 V
3.8 V
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
3.9.5 AUXHFRCO
Table 3.12. AUXHFRCO
Symbol
Parameter
Condition
Min
Typ
Max
Unit
28 MHz frequency band
21 MHz frequency band
14 MHz frequency band
11 MHz frequency band
7 MHz frequency band
1 MHz frequency band
fAUXHFRCO = 14 MHz
27.16
20.37
13.58
10.67
6.401
1.162
28.0
21.0
14.0
11.0
6.601
1.202
0.6
28.84 MHz
21.63 MHz
14.42 MHz
11.33 MHz
6.801 MHz
1.242 MHz
Oscillation frequen-
cy, VDD= 3.0 V,
TAMB=25°C
fAUXHFRCO
tAUXHFRCO_settlingSettling time after
start-up
Cycles
TUNESTEPAUX-Frequency step
0.33
%
for LSB change in
HFRCO
TUNING value
1For devices with prod. rev. < 19, Typ = 7MHz and Min/Max values not applicable.
2For devices with prod. rev. < 19, Typ = 1MHz and Min/Max values not applicable.
3The TUNING field in the CMU_AUXHFRCOCTRL register may be used to adjust the AUXHFRCO frequency. There is enough
adjustment range to ensure that the frequency bands above 7 MHz will always have some overlap across supply voltage and
temperature. By using a stable frequency reference such as the LFXO or HFXO, a firmware calibration routine can vary the
TUNING bits and the frequency band to maintain the AUXHFRCO frequency at any arbitrary value between 7 MHz and 28 MHz
across operating conditions.
3.9.6 ULFRCO
Table 3.13. ULFRCO
Symbol
Parameter
Condition
Min
Typ
Max
Unit
fULFRCO
Oscillation frequen- 25°C, 3V
cy
0.70
1.75 kHz
TCULFRCO
Temperature coeffi-
cient
0.05
%/°C
%/V
VCULFRCO
Supply voltage co-
efficient
-18.2
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3.10 Analog Comparator (ACMP)
Table 3.14. ACMP
Symbol
VACMPIN
VACMPCM
Parameter
Condition
Min
Typ
Max
Unit
V
Input voltage range
0
0
VDD
VDD
ACMP Common
V
Mode voltage range
BIASPROG=0b0000, FULL-
BIAS=0 and HALFBIAS=1 in
ACMPn_CTRL register
0.1
2.87
195
0.0
0.6 µA
12 µA
BIASPROG=0b1111, FULL-
BIAS=0 and HALFBIAS=0 in
ACMPn_CTRL register
IACMP
Active current
BIASPROG=0b1111, FULL-
BIAS=1 and HALFBIAS=0 in
ACMPn_CTRL register
520 µA
0.5 µA
Internal voltage reference off.
Using external voltage refer-
ence
Current consump-
tion of internal volt-
age reference
IACMPREF
Internal voltage reference
2.15
0
3.00 µA
12 mV
VACMPOFFSET Offset voltage
BIASPROG= 0b1010, FULL-
BIAS=0 and HALFBIAS=0 in
ACMPn_CTRL register
-12
VACMPHYST
ACMP hysteresis
Programmable
17
39
mV
CSRESSEL=0b00 in
ACMPn_INPUTSEL
kOhm
CSRESSEL=0b01 in
ACMPn_INPUTSEL
71
104
136
kOhm
kOhm
kOhm
Capacitive Sense
Internal Resistance
RCSRES
CSRESSEL=0b10 in
ACMPn_INPUTSEL
CSRESSEL=0b11 in
ACMPn_INPUTSEL
tACMPSTART
Startup time
10 µs
The total ACMP current is the sum of the contributions from the ACMP and its internal voltage reference
as given in Equation 3.1 (p. 25) . IACMPREF is zero if an external voltage reference is used.
Total ACMP Active Current
IACMPTOTAL = IACMP + IACMPREF
(3.1)
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Figure 3.17. ACMP Characteristics, Vdd = 3V, Temp = 25°C, FULLBIAS = 0, HALFBIAS = 1
2.5
2.0
1.5
1.0
0.5
0.0
20
15
10
5
HYSTSEL= 0
HYSTSEL= 2
HYSTSEL= 4
HYSTSEL= 6
0
0
4
8
12
0
2
4
6
8
10
12
14
ACMP_CTRL_BIASPROG
ACMP_CTRL_BIASPROG
Current consumption, HYSTSEL = 4
Response time , Vcm
=
1.25V, CP+ to CP- = 100mV
100
80
60
40
20
0
BIASPROG= 0.0
BIASPROG= 4.0
BIASPROG= 8.0
BIASPROG= 12.0
0
1
2
3
4
5
6
7
ACMP_CTRL_HYSTSEL
Hysteresis
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3.11 Voltage Comparator (VCMP)
Table 3.15. VCMP
Symbol
VVCMPIN
VVCMPCM
Parameter
Condition
Min
Typ
Max
Unit
V
Input voltage range
VDD
VDD
VCMP Common
V
Mode voltage range
BIASPROG=0b0000 and
HALFBIAS=1 in VCMPn_CTRL
register
0.3
22
10
0.6 µA
IVCMP
Active current
BIASPROG=0b1111 and
HALFBIAS=0 in VCMPn_CTRL
register. LPREF=0.
30 µA
µs
tVCMPREF
Startup time refer-
ence generator
NORMAL
Single ended
Differential
10
10
17
mV
mV
VVCMPOFFSET Offset voltage
VVCMPHYST
tVCMPSTART
VCMP hysteresis
Startup time
mV
10 µs
The VDD trigger level can be configured by setting the TRIGLEVEL field of the VCMP_CTRL register in
accordance with the following equation:
VCMP Trigger Level as a Function of Level Setting
VDD Trigger Level=1.667V+0.034 ×TRIGLEVEL
(3.2)
3.12 I2C
Table 3.16. I2C Standard-mode (Sm)
Symbol
fSCL
Parameter
Min
Typ
Max
Unit
SCL clock frequency
0
4.7
4.0
250
8
1001 kHz
tLOW
SCL clock low time
µs
tHIGH
SCL clock high time
µs
tSU,DAT
tHD,DAT
tSU,STA
tHD,STA
tSU,STO
tBUF
SDA set-up time
ns
SDA hold time
34502,3 ns
Repeated START condition set-up time
(Repeated) START condition hold time
STOP condition set-up time
Bus free time between a STOP and START condition
4.7
4.0
4.0
4.7
µs
µs
µs
µs
1For the minimum HFPERCLK frequency required in Standard-mode, see the I2C chapter in the EFM32TG Reference Manual.
2The maximum SDA hold time (tHD,DAT) needs to be met only when the device does not stretch the low time of SCL (tLOW).
3When transmitting data, this number is guaranteed only when I2Cn_CLKDIV < ((3450*10-9 [s] * fHFPERCLK [Hz]) - 4).
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Table 3.17. I2C Fast-mode (Fm)
Symbol
fSCL
Parameter
Min
Typ
Max
Unit
SCL clock frequency
0
1.3
0.6
100
8
4001 kHz
tLOW
SCL clock low time
µs
tHIGH
SCL clock high time
µs
tSU,DAT
tHD,DAT
tSU,STA
tHD,STA
tSU,STO
tBUF
SDA set-up time
ns
SDA hold time
9002,3 ns
Repeated START condition set-up time
(Repeated) START condition hold time
STOP condition set-up time
Bus free time between a STOP and START condition
0.6
0.6
0.6
1.3
µs
µs
µs
µs
1For the minimum HFPERCLK frequency required in Fast-mode, see the I2C chapter in the EFM32TG Reference Manual.
2The maximum SDA hold time (tHD,DAT) needs to be met only when the device does not stretch the low time of SCL (tLOW).
3When transmitting data, this number is guaranteed only when I2Cn_CLKDIV < ((900*10-9 [s] * fHFPERCLK [Hz]) - 4).
Table 3.18. I2C Fast-mode Plus (Fm+)
Symbol
fSCL
Parameter
Min
Typ
Max
Unit
SCL clock frequency
0
0.5
10001 kHz
tLOW
SCL clock low time
µs
µs
ns
ns
µs
µs
µs
µs
tHIGH
SCL clock high time
0.26
50
tSU,DAT
tHD,DAT
tSU,STA
tHD,STA
tSU,STO
tBUF
SDA set-up time
SDA hold time
8
Repeated START condition set-up time
(Repeated) START condition hold time
STOP condition set-up time
Bus free time between a STOP and START condition
0.26
0.26
0.26
0.5
1For the minimum HFPERCLK frequency required in Fast-mode Plus, see the I2C chapter in the EFM32TG Reference Manual.
3.13 Digital Peripherals
Table 3.19. Digital Peripherals
Symbol
Parameter
Condition
Min
Typ
Max
Unit
IUSART
USART current
USART idle current, clock en-
abled
7.5
150
6.25
8.75
75
µA/
MHz
ILEUART
LEUART current
I2C current
LEUART idle current, clock en-
abled
nA
II2C
I2C idle current, clock enabled
µA/
MHz
ITIMER
ILETIMER
IPCNT
TIMER current
LETIMER current
PCNT current
TIMER_0 idle current, clock
enabled
µA/
MHz
LETIMER idle current, clock
enabled
nA
PCNT idle current, clock en-
abled
60
nA
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Symbol
IRTC
Parameter
Condition
Min
Typ
Max
Unit
RTC current
GPIO current
RTC idle current, clock enabled
40
nA
IGPIO
GPIO idle current, clock en-
abled
5.31
µA/
MHz
IPRS
PRS current
DMA current
PRS idle current
2.81
8.12
µA/
MHz
IDMA
Clock enable
µA/
MHz
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4 Pinout and Package
Note
Please refer to the application note "AN0002 EFM32 Hardware Design Considerations" for
guidelines on designing Printed Circuit Boards (PCB's) for the EFM32TG108.
4.1 Pinout
The EFM32TG108 pinout is shown in Figure 4.1 (p. 30) and Table 4.1 (p. 30). Alternate locations
are denoted by "#" followed by the location number (Multiple locations on the same pin are split with "/").
Alternate locations can be configured in the LOCATION bitfield in the *_ROUTE register in the module
in question.
Figure 4.1. EFM32TG108 Pinout (top view, not to scale)
Table 4.1. Device Pinout
QFN24 Pin#
and Name
Pin Alternate Functionality / Description
Pin Name
Analog
Timers
Communication
Other
0
1
VSS
PA0
Ground.
LEU0_RX #4
I2C0_SDA #0
PRS_CH0 #0
GPIO_EM4WU0
TIM0_CC0 #0/1/4
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QFN24 Pin#
and Name
Pin Alternate Functionality / Description
Pin Name
Analog
Timers
Communication
Other
2
3
IOVDD_0
PC0
Digital IO power supply 0.
ACMP0_CH0
TIM0_CC1 #4
PCNT0_S0IN #2
US1_TX #0
I2C0_SDA #4
LES_CH0 #0
PRS_CH2 #0
TIM0_CC2 #4
PCNT0_S1IN #2
US1_RX #0
I2C0_SCL #4
LES_CH1 #0
PRS_CH3 #0
4
PC1
ACMP0_CH1
5
6
PB7
PB8
LFXTAL_P
LFXTAL_N
TIM1_CC0 #3
TIM1_CC1 #3
US1_CLK #0
US1_CS #0
Reset input, active low.
7
8
RESETn
PB11
To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up
ensure that reset is released.
TIM1_CC2 #3
LETIM0_OUT0 #1
9
AVDD_2
PB13
Analog power supply 2.
10
11
12
HFXTAL_P
HFXTAL_N
LEU0_TX #1
LEU0_RX #1
PB14
AVDD_0
Analog power supply 0.
TIM1_CC0 #4
LETIM0_OUT0 #0
PCNT0_S0IN #3
US1_RX #2
I2C0_SDA #1
LES_ALTEX0 #0
ACMP0_O #2
13
14
PD6
PD7
TIM1_CC1 #4
LETIM0_OUT1 #0
PCNT0_S1IN #3
CMU_CLK0 #2
LES_ALTEX1 #0
ACMP1_O #2
US1_TX #2
I2C0_SCL #1
15
16
VDD_DREG
DECOUPLE
Power supply for on-chip voltage regulator.
Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this pin.
TIM1_CC1 #0
17
18
PC14
PC15
ACMP1_CH6
LES_CH14 #0
PCNT0_S1IN #0
LES_CH15 #0
DBG_SWO #1
ACMP1_CH7
TIM1_CC2 #0
US1_CLK #2
LEU0_TX #3
I2C0_SDA #5
TIM0_CC0 #5
LETIM0_OUT0 #2
DBG_SWCLK #0/1
BOOT_TX
19
20
21
PF0
PF1
PF2
US1_CS #2
LEU0_RX #3
I2C0_SCL #5
DBG_SWDIO #0/1
GPIO_EM4WU3
BOOT_RX
TIM0_CC1 #5
LETIM0_OUT1 #2
ACMP1_O #0
DBG_SWO #0
GPIO_EM4WU4
TIM0_CC2 #5
TIM1_CC2 #1
LEU0_TX #4
22
23
IOVDD_5
PE12
Digital IO power supply 5.
CMU_CLK1 #2
LES_ALTEX6 #0
I2C0_SDA #6
I2C0_SCL #6
LES_ALTEX7 #0
ACMP0_O #0
24
PE13
GPIO_EM4WU5
4.2 Alternate Functionality Pinout
A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in
Table 4.2 (p. 32). The table shows the name of the alternate functionality in the first column, followed
by columns showing the possible LOCATION bitfield settings.
Note
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Some functionality, such as analog interfaces, do not have alternate settings or a LOCA-
TION bitfield. In these cases, the pinout is shown in the column corresponding to LOCA-
TION 0.
Table 4.2. Alternate functionality overview
Alternate
LOCATION
3
Functionality
ACMP0_CH0
ACMP0_CH1
ACMP0_O
0
1
2
PD6
PD7
4
5
6
Description
Analog comparator ACMP0, channel 0.
Analog comparator ACMP0, channel 1.
Analog comparator ACMP0, digital output.
Analog comparator ACMP1, channel 6.
Analog comparator ACMP1, channel 7.
Analog comparator ACMP1, digital output.
Bootloader RX.
PC0
PC1
PE13
PC14
PC15
PF2
ACMP1_CH6
ACMP1_CH7
ACMP1_O
BOOT_RX
PF1
BOOT_TX
PF0
Bootloader TX.
CMU_CLK0
CMU_CLK1
PD7
Clock Management Unit, clock output number 0.
Clock Management Unit, clock output number 1.
Debug-interface Serial Wire clock input.
PE12
DBG_SWCLK
DBG_SWDIO
DBG_SWO
PF0
PF1
PF2
PF0
Note that this function is enabled to pin out of reset, and has
a built-in pull down.
Debug-interface Serial Wire data input / output.
PF1
Note that this function is enabled to pin out of reset, and has
a built-in pull up.
Debug-interface Serial Wire viewer Output.
PC15
Note that this function is not enabled after reset, and must be
enabled by software to be used.
GPIO_EM4WU0
GPIO_EM4WU3
GPIO_EM4WU4
GPIO_EM4WU5
PA0
PF1
PF2
PE13
Pin can be used to wake the system up from EM4
Pin can be used to wake the system up from EM4
Pin can be used to wake the system up from EM4
Pin can be used to wake the system up from EM4
High Frequency Crystal negative pin. Also used as external
optional clock input pin.
HFXTAL_N
PB14
PB13
HFXTAL_P
I2C0_SCL
High Frequency Crystal positive pin.
I2C0 Serial Clock Line input / output.
I2C0 Serial Data input / output.
LESENSE alternate exite output 0.
LESENSE alternate exite output 1.
LESENSE alternate exite output 6.
LESENSE alternate exite output 7.
LESENSE channel 0.
PD7
PD6
PC1
PC0
PF1
PF0
PE13
PE12
I2C0_SDA
PA0
LES_ALTEX0
LES_ALTEX1
LES_ALTEX6
LES_ALTEX7
LES_CH0
PD6
PD7
PE12
PE13
PC0
PC1
PC14
PC15
PD6
PD7
LES_CH1
LESENSE channel 1.
LES_CH14
LES_CH15
LETIM0_OUT0
LETIM0_OUT1
LEU0_RX
LESENSE channel 14.
LESENSE channel 15.
PB11
PB14
PF0
PF1
Low Energy Timer LETIM0, output channel 0.
Low Energy Timer LETIM0, output channel 1.
LEUART0 Receive input.
PF1
PA0
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Alternate
LOCATION
3
Functionality
0
1
2
4
5
6
Description
LEUART0 Transmit output. Also used as receive input in half
duplex communication.
LEU0_TX
PB13
PF0
PF2
Low Frequency Crystal (typically 32.768 kHz) negative pin.
Also used as an optional external clock input pin.
LFXTAL_N
PB8
LFXTAL_P
PCNT0_S0IN
PCNT0_S1IN
PRS_CH0
PRS_CH2
PRS_CH3
TIM0_CC0
TIM0_CC1
TIM0_CC2
TIM1_CC0
TIM1_CC1
TIM1_CC2
US1_CLK
US1_CS
PB7
Low Frequency Crystal (typically 32.768 kHz) positive pin.
Pulse Counter PCNT0 input number 0.
PC0
PC1
PD6
PD7
PC14
PA0
PC0
PC1
PA0
Pulse Counter PCNT0 input number 1.
Peripheral Reflex System PRS, channel 0.
Peripheral Reflex System PRS, channel 2.
Peripheral Reflex System PRS, channel 3.
Timer 0 Capture Compare input / output channel 0.
Timer 0 Capture Compare input / output channel 1.
Timer 0 Capture Compare input / output channel 2.
Timer 1 Capture Compare input / output channel 0.
Timer 1 Capture Compare input / output channel 1.
Timer 1 Capture Compare input / output channel 2.
USART1 clock input / output.
PA0
PA0
PF0
PF1
PF2
PC0
PC1
PD6
PD7
PB7
PB8
PB11
PC14
PC15
PB7
PE12
PF0
PF1
PB8
USART1 chip select input / output.
USART1 Asynchronous Receive.
US1_RX
US1_TX
PC1
PC0
PD6
PD7
USART1 Synchronous mode Master Input / Slave Output
(MISO).
USART1 Asynchronous Transmit.Also used as receive input
in half duplex communication.
USART1 Synchronous mode Master Output / Slave Input
(MOSI).
4.3 GPIO Pinout Overview
The specific GPIO pins available in EFM32TG108 is shown in Table 4.3 (p. 33). Each GPIO port is
organized as 16-bit ports indicated by letters A through F, and the individual pin on this port is indicated
by a number from 15 down to 0.
Table 4.3. GPIO Pinout
Port
Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin
Pin
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Port A
Port B
Port C
Port D
Port E
Port F
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PA0
PB14 PB13
PB11
-
PB8
PB7
-
-
-
-
-
-
PC1
-
-
PC0
-
PC15 PC14
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PD7
PD6
-
-
-
-
-
PE13 PE12
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PF2
PF1
PF0
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4.4 QFN24 Package
Figure 4.2. QFN24
Note:
1. Dimensioning & tolerancing confirm to ASME Y14.5M-1994.
2. All dimensions are in millimeters. Angles are in degrees.
3. Dimension 'b' applies to metallized terminal and is measured between 0.25 mm and 0.30 mm from
the terminal tip. Dimension L1 represents terminal full back from package edge up to 0.1 mm is
acceptable.
4. Coplanarity applies to the exposed heat slug as well as the terminal.
5. Radius on terminal is optional
Table 4.4. QFN24 (Dimensions in mm)
Symbol
Min
A
A1
A3
b
D
E
D2
E2
e
L
L1
aaa bbb ccc ddd
eee
0.80 0.00
0.25
0.30
0.35
3.50 3.50
3.60 3.60
3.70 3.70
0.35 0.00
0.40
0.203
REF
5.00 5.00
BSC BSC
0.65
BSC
Nom
Max
0.85
-
0.10 0.10 0.10 0.05 0.08
0.90 0.05
0.45 0.10
The QFN24 Package uses Nickel-Palladium-Gold preplated leadframe.
All EFM32 packages are RoHS compliant and free of Bromine (Br) and Antimony (Sb).
For additional Quality and Environmental information, please see:
http://www.silabs.com/support/quality/pages/default.aspx
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5 PCB Layout and Soldering
5.1 Recommended PCB Layout
Figure 5.1. QFN24 PCB Land Pattern
a
p8
p7
p1
p6
b
p9
e
g
c
p2
p5
p3
p4
f
d
Table 5.1. QFN24 PCB Land Pattern Dimensions (Dimensions in mm)
Symbol
Dim. (mm)
0.80
Symbol
P1
Pin number
Symbol
Pin number
a
b
c
d
e
f
1
6
P8
24
25
-
0.30
P2
P9
0.65
P3
7
-
-
-
-
-
5.00
P4
12
13
18
19
-
5.00
P5
-
3.60
P6
-
g
3.60
P7
-
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Figure 5.2. QFN24 PCB Solder Mask
a
b
c
e
g
f
d
Table 5.2. QFN24 PCB Solder Mask Dimensions (Dimensions in mm)
Symbol
Dim. (mm)
0.92
Symbol
Dim. (mm)
a
b
c
d
e
f
5.00
3.72
3.72
-
0.42
0.65
g
-
5.00
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Figure 5.3. QFN24 PCB Stencil Design
a
b
c
x
y
e
z
d
Table 5.3. QFN24 PCB Stencil Design Dimensions (Dimensions in mm)
Symbol
Dim. (mm)
0.60
Symbol
Dim. (mm)
5.00
a
b
c
d
e
x
y
z
0.25
1.00
0.65
1.00
5.00
0.50
1. The drawings are not to scale.
2. All dimensions are in millimeters.
3. All drawings are subject to change without notice.
4. The PCB Land Pattern drawing is in compliance with IPC-7351B.
5. Stencil thickness 0.125 mm.
6. For detailed pin-positioning, see Figure 4.2 (p. 34) .
5.2 Soldering Information
The latest IPC/JEDEC J-STD-020 recommendations for Pb-Free reflow soldering should be followed.
The packages have a Moisture Sensitivity Level rating of 3, please see the latest IPC/JEDEC J-STD-033
standard for MSL description and level 3 bake conditions. Place as many and as small as possible vias
underneath each of the solder patches under the ground pad.
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6 Chip Marking, Revision and Errata
6.1 Chip Marking
In the illustration below package fields and position are shown.
Figure 6.1. Example Chip Marking (top view)
6.2 Revision
The revision of a chip can be determined from the "Revision" field in Figure 6.1 (p. 38) .
6.3 Errata
Please see the errata document for EFM32TG108 for description and resolution of device erratas. This
document is available in Simplicity Studio and online at:
http://www.silabs.com/support/pages/document-library.aspx?p=MCUs--32-bit
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7 Revision History
7.1 Revision 1.40
March 6th, 2015
Updated Block Diagram.
Updated Energy Modes current consumption.
Updated Power Management section.
Updated LFRCO and HFRCO sections.
Added AUXHFRCO to block diagram and Electrical Characteristics.
Corrected unit to kHz on LFRCO plots y-axis.
Updated ACMP section and the response time graph.
Updated VCMP section.
Updated Package dimensions table.
Updated Digital Peripherals section.
7.2 Revision 1.30
July 2nd, 2014
Corrected single power supply voltage minimum value from 1.85V to 1.98V.
Updated current consumption.
Updated transition between energy modes.
Updated power management data.
Updated GPIO data.
Updated LFXO, HFXO, HFRCO and ULFRCO data.
Updated LFRCO and HFRCO plots.
Updated ACMP data.
7.3 Revision 1.21
November 21st, 2013
Updated figures.
Updated errata-link.
Updated chip marking.
Added link to Environmental and Quality information.
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7.4 Revision 1.20
September 30th, 2013
Added I2C characterization data.
Corrected GPIO operating voltage from 1.8 V to 1.85 V.
Document changed status from "Preliminary".
Updated Environmental information.
Updated trademark, disclaimer and contact information.
Other minor corrections.
7.5 Revision 1.10
June 28th, 2013
Updated power requirements in the Power Management section.
Removed minimum load capacitance figure and table. Added reference to application note.
Other minor corrections.
7.6 Revision 1.00
September 11th, 2012
Updated the HFRCO 1 MHz band typical value to 1.2 MHz.
Updated the HFRCO 7 MHz band typical value to 6.6 MHz.
Added GPIO_EM4WU3, GPIO_EM4WU4 and GPIO_EM4WU5 pins and removed GPIO_EM4WU1 in
the Alternate functionality overview table.
Other minor corrections.
7.7 Revision 0.96
May 4th, 2012
Corrected PCB footprint figures and tables.
7.8 Revision 0.95
February 27th, 2012
Corrected operating voltage from 1.8 V to 1.85 V.
Added rising POR level and corrected Thermometer output gradient in Electrical Characteristics section.
Updated Minimum Load Capacitance (CLFXOL) Requirement For Safe Crystal Startup.
Added Gain error drift and Offset error drift to ADC table.
Added reference to errata document.
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7.9 Revision 0.92
July 22nd, 2011
Updated current consumption numbers from latest device characterization data.
7.10 Revision 0.91
February 4th, 2011
Corrected max DAC sampling rate.
Increased max storage temperature.
Added data for <150°C and <70°C on Flash data retention.
Changed latch-up sensitivity test description.
Added IO leakage current.
Added Flash current consumption.
Updated HFRCO data.
Updated LFRCO data.
7.11 Revision 0.90
December 1st, 2010
New peripherals added to pinout, including LESENSE and OpAmps.
7.12 Revision 0.50
May 25th, 2010
Block diagram update.
7.13 Revision 0.40
March 26th, 2010
Initial preliminary release.
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A Disclaimer and Trademarks
A.1 Disclaimer
Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation
of all peripherals and modules available for system and software implementers using or intending to use
the Silicon Laboratories products. Characterization data, available modules and peripherals, memory
sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and
do vary in different applications. Application examples described herein are for illustrative purposes only.
Silicon Laboratories reserves the right to make changes without further notice and limitation to product
information, specifications, and descriptions herein, and does not give warranties as to the accuracy
or completeness of the included information. Silicon Laboratories shall have no liability for the conse-
quences of use of the information supplied herein. This document does not imply or express copyright
licenses granted hereunder to design or fabricate any integrated circuits. The products must not be
used within any Life Support System without the specific written consent of Silicon Laboratories. A "Life
Support System" is any product or system intended to support or sustain life and/or health, which, if it
fails, can be reasonably expected to result in significant personal injury or death. Silicon Laboratories
products are generally not intended for military applications. Silicon Laboratories products shall under no
circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological
or chemical weapons, or missiles capable of delivering such weapons.
A.2 Trademark Information
Silicon Laboratories Inc., Silicon Laboratories, Silicon Labs, SiLabs and the Silicon Labs logo, CMEMS®,
EFM, EFM32, EFR, Energy Micro, Energy Micro logo and combinations thereof, "the world’s most ener-
gy friendly microcontrollers", Ember®, EZLink®, EZMac®, EZRadio®, EZRadioPRO®, DSPLL®, ISO-
modem®, Precision32®, ProSLIC®, SiPHY®, USBXpress® and others are trademarks or registered
trademarks of Silicon Laboratories Inc. ARM, CORTEX, Cortex-M3 and THUMB are trademarks or reg-
istered trademarks of ARM Holdings. Keil is a registered trademark of ARM Limited. All other products
or brand names mentioned herein are trademarks of their respective holders.
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B Contact Information
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Please visit the Silicon Labs Technical Support web page:
http://www.silabs.com/support/pages/contacttechnicalsupport.aspx
and register to submit a technical support request.
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Table of Contents
1. Ordering Information .................................................................................................................................. 2
2. System Summary ...................................................................................................................................... 3
2.1. System Introduction ......................................................................................................................... 3
2.2. Configuration Summary .................................................................................................................... 6
2.3. Memory Map ................................................................................................................................. 7
3. Electrical Characteristics ............................................................................................................................. 8
3.1. Test Conditions .............................................................................................................................. 8
3.2. Absolute Maximum Ratings .............................................................................................................. 8
3.3. General Operating Conditions ........................................................................................................... 8
3.4. Current Consumption ....................................................................................................................... 9
3.5. Transition between Energy Modes .................................................................................................... 11
3.6. Power Management ....................................................................................................................... 11
3.7. Flash .......................................................................................................................................... 12
3.8. General Purpose Input Output ......................................................................................................... 12
3.9. Oscillators .................................................................................................................................... 20
3.10. Analog Comparator (ACMP) .......................................................................................................... 25
3.11. Voltage Comparator (VCMP) ......................................................................................................... 27
3.12. I2C ........................................................................................................................................... 27
3.13. Digital Peripherals ....................................................................................................................... 28
4. Pinout and Package ................................................................................................................................. 30
4.1. Pinout ......................................................................................................................................... 30
4.2. Alternate Functionality Pinout .......................................................................................................... 31
4.3. GPIO Pinout Overview ................................................................................................................... 33
4.4. QFN24 Package ........................................................................................................................... 34
5. PCB Layout and Soldering ........................................................................................................................ 35
5.1. Recommended PCB Layout ............................................................................................................ 35
5.2. Soldering Information ..................................................................................................................... 37
6. Chip Marking, Revision and Errata .............................................................................................................. 38
6.1. Chip Marking ................................................................................................................................ 38
6.2. Revision ...................................................................................................................................... 38
6.3. Errata ......................................................................................................................................... 38
7. Revision History ...................................................................................................................................... 39
7.1. Revision 1.40 ............................................................................................................................... 39
7.2. Revision 1.30 ............................................................................................................................... 39
7.3. Revision 1.21 ............................................................................................................................... 39
7.4. Revision 1.20 ............................................................................................................................... 40
7.5. Revision 1.10 ............................................................................................................................... 40
7.6. Revision 1.00 ............................................................................................................................... 40
7.7. Revision 0.96 ............................................................................................................................... 40
7.8. Revision 0.95 ............................................................................................................................... 40
7.9. Revision 0.92 ............................................................................................................................... 41
7.10. Revision 0.91 .............................................................................................................................. 41
7.11. Revision 0.90 .............................................................................................................................. 41
7.12. Revision 0.50 .............................................................................................................................. 41
7.13. Revision 0.40 .............................................................................................................................. 41
A. Disclaimer and Trademarks ....................................................................................................................... 42
A.1. Disclaimer ................................................................................................................................... 42
A.2. Trademark Information ................................................................................................................... 42
B. Contact Information ................................................................................................................................. 43
B.1. ................................................................................................................................................. 43
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List of Figures
2.1. Block Diagram ....................................................................................................................................... 3
2.2. EFM32TG108 Memory Map with largest RAM and Flash sizes ........................................................................ 7
3.1. EM2 current consumption. RTC prescaled to 1kHz, 32.768 kHz LFRCO. ......................................................... 10
3.2. EM3 current consumption. ..................................................................................................................... 10
3.3. EM4 current consumption. ..................................................................................................................... 10
3.4. Typical Low-Level Output Current, 2V Supply Voltage .................................................................................. 14
3.5. Typical High-Level Output Current, 2V Supply Voltage ................................................................................. 15
3.6. Typical Low-Level Output Current, 3V Supply Voltage .................................................................................. 16
3.7. Typical High-Level Output Current, 3V Supply Voltage ................................................................................. 17
3.8. Typical Low-Level Output Current, 3.8V Supply Voltage ............................................................................... 18
3.9. Typical High-Level Output Current, 3.8V Supply Voltage ............................................................................... 19
3.10. Calibrated LFRCO Frequency vs Temperature and Supply Voltage .............................................................. 21
3.11. Calibrated HFRCO 1 MHz Band Frequency vs Supply Voltage and Temperature ............................................ 22
3.12. Calibrated HFRCO 7 MHz Band Frequency vs Supply Voltage and Temperature ............................................ 22
3.13. Calibrated HFRCO 11 MHz Band Frequency vs Supply Voltage and Temperature ........................................... 23
3.14. Calibrated HFRCO 14 MHz Band Frequency vs Supply Voltage and Temperature ........................................... 23
3.15. Calibrated HFRCO 21 MHz Band Frequency vs Supply Voltage and Temperature ........................................... 23
3.16. Calibrated HFRCO 28 MHz Band Frequency vs Supply Voltage and Temperature ........................................... 24
3.17. ACMP Characteristics, Vdd = 3V, Temp = 25°C, FULLBIAS = 0, HALFBIAS = 1 ............................................. 26
4.1. EFM32TG108 Pinout (top view, not to scale) .............................................................................................. 30
4.2. QFN24 ................................................................................................................................................ 34
5.1. QFN24 PCB Land Pattern ...................................................................................................................... 35
5.2. QFN24 PCB Solder Mask ....................................................................................................................... 36
5.3. QFN24 PCB Stencil Design .................................................................................................................... 37
6.1. Example Chip Marking (top view) ............................................................................................................. 38
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List of Tables
1.1. Ordering Information ................................................................................................................................ 2
2.1. Configuration Summary ............................................................................................................................ 6
3.1. Absolute Maximum Ratings ...................................................................................................................... 8
3.2. General Operating Conditions ................................................................................................................... 8
3.3. Current Consumption ............................................................................................................................... 9
3.4. Energy Modes Transitions ...................................................................................................................... 11
3.5. Power Management ............................................................................................................................... 11
3.6. Flash .................................................................................................................................................. 12
3.7. GPIO .................................................................................................................................................. 12
3.8. LFXO .................................................................................................................................................. 20
3.9. HFXO ................................................................................................................................................. 20
3.10. LFRCO .............................................................................................................................................. 21
3.11. HFRCO ............................................................................................................................................. 21
3.12. AUXHFRCO ....................................................................................................................................... 24
3.13. ULFRCO ............................................................................................................................................ 24
3.14. ACMP ............................................................................................................................................... 25
3.15. VCMP ............................................................................................................................................... 27
3.16. I2C Standard-mode (Sm) ...................................................................................................................... 27
3.17. I2C Fast-mode (Fm) ............................................................................................................................ 28
3.18. I2C Fast-mode Plus (Fm+) .................................................................................................................... 28
3.19. Digital Peripherals ............................................................................................................................... 28
4.1. Device Pinout ....................................................................................................................................... 30
4.2. Alternate functionality overview ................................................................................................................ 32
4.3. GPIO Pinout ........................................................................................................................................ 33
4.4. QFN24 (Dimensions in mm) .................................................................................................................... 34
5.1. QFN24 PCB Land Pattern Dimensions (Dimensions in mm) .......................................................................... 35
5.2. QFN24 PCB Solder Mask Dimensions (Dimensions in mm) ........................................................................... 36
5.3. QFN24 PCB Stencil Design Dimensions (Dimensions in mm) ........................................................................ 37
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List of Equations
3.1. Total ACMP Active Current ..................................................................................................................... 25
3.2. VCMP Trigger Level as a Function of Level Setting ..................................................................................... 27
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