SI2012-KT [SILICON]
Consumer Circuit, PDSO16, TSSOP-16;
| 型号： | SI2012-KT |
| 厂家： | 
SILICON |
| 描述： | Consumer Circuit, PDSO16, TSSOP-16 光电二极管 商用集成电路 |
| 文件： | 总54页 (文件大小：1407K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si3035
3.3 V FCC/JATE DIRECT ACCESS ARRANGEMENT
Features
Complete DAA includes the following:
!
3.3 V to 5 V Digital/Analog
Power Supplies
!
!
!
!
!
!
!
!
!
Support for Caller ID
Low Profile SOIC Packages
Direct Interface to DSPs
!
!
JATE Filter Option
86 dB Dynamic Range TX/RX
Paths
Integrated Modem Codec
Compliant with FCC Part 68
Low-Power Standby Mode
Proprietary ISOcap™ Technology
Pin Compatible with Si3034, Si3032
Optional IIR Digital Filter
!
Daisy-Chaining for Up to Eight
Devices
Ordering Information
See page 50.
!
!
Integrated Ring Detector
3000 V Isolation
Pin Assignments
Si3021 (SOIC)
Applications
! V.90 Modems
! Fax Machines
! Set Top Boxes
1
2
3
4
5
6
7
8
MCLK
FSYNC
SCLK
OFHK
RGDT/FSD
M0
16
15
14
13
12
11
10
9
! Voice Mail Systems
VD
VA
Description
SDO
GND
C1A
The Si3035 is an integrated direct access arrangement (DAA) chipset that
provides a digital, low-cost, solid-state interface to a telephone line.
Available in two 16-pin small outline packages, it eliminates the need for an
analog front end (AFE), an isolation transformer, relays, opto-isolators, and
a 2- to 4-wire hybrid. The Si3035 dramatically reduces the number of
discrete components and cost required to achieve compliance with FCC
Part 68. The Si3035 interfaces directly to standard modem DSPs and
supports all FCC and JATE out-of-band noise requirements. International
support is provided by the pin compatible Si3034.
SDI
FC/RGDT
RESET
M1
AOUT
Si3021 (TSSOP)
1
SDO
SDI
VD
16
2
3
4
5
6
7
8
SCLK
FSYNC
MCLK
OFHK
RGDT/FSD
M0
15
14
13
12
11
10
9
FC/RGDT
RESET
AOUT
M1
Functional Block Diagram
C1A
GND
VA
Si3021
Si3012
Si3012 (SOIC or TSSOP)
MCLK
SCLK
Out
In
TX
TSTA
TSTB
IGND
C1B
TX
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Hybrid
RX
FSYNC
SDI
Digital
Interface
NC
HYBD
RX
SDO
VREG2
VREG
DCT
REXT
DCT
HYBD
VREG2
VREG
FC/RGT
Isolation
Interface
Isolation
Interface
DC
RNG1
RNG2
QB
Termination
REXT
IGND
RGDT/FSD
OFHK
Ring Detect
Off-Hook
RNG1
RNG2
QB
QE
Control
Interface
MODE
RESET
QE
US Patent # 5,870,046
US Patent # 6,061,009
Other Patents Pending
AOUT
Rev. 1.2 12/00
Copyright © 2000 by Silicon Laboratories
Si3035-DS12
Si3035
2
Rev. 1.2
Si3035
TABLE OF CONTENTS
Section
Page
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Analog Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Isolation Barrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Off-Hook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Ring Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Improved JATE Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Digital Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Clock Generation Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Analog Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
On-Hook Line Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Loop Current Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Multiple Device Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Filter Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Revision Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
In-Circuit Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Exception Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Appendix—UL1950 3rd Edition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Pin Descriptions: Si3021 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Pin Descriptions: Si3012 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
SOIC Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
TSSOP Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Rev. 1.2
3
Si3035
Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter1
Symbol
Min2
0
Max2
70
Test Condition
Typ
Unit
Ambient Temperature
Si3021 Supply Voltage, Analog
Si3021 Supply Voltage, Digital3
Notes:
TA
VA
VD
K-Grade
25
5.0
°C
V
4.75
3.0
5.25
5.25
3.3/5.0
V
1. The Si3035 specifications are guaranteed when the typical application circuit (including component
tolerances) and any Si3021 and any Si3012 are used. See Figure 16 on page 15 for typical application
circuit.
2. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated.
3. The digital supply, VD, can operate from either 3.3 V or 5.0 V. The Si3021 supports interface to 3.3 V logic when
operating from 3.3 V. The 3.3 V operation applies to both the serial port and the digital signals
RGDT, OFHK, RESET, M0, and M1.
Table 2. Loop Characteristics
(VA = Charge Pump, VD = +3.3 V ± 0.3 V, TA = 0 to 70°C for K-Grade, Refer to Figure 1)
Parameter
Symbol
VTR
Test Condition
IL = 20 mA
Min
—
Typ
—
Max
7.7
—
Unit
V
DC Termination Voltage
DC Termination Voltage
DC Ring Current (with caller ID)
DC Ring Current (w/o caller ID)
AC Termination Impedance
Operating Loop Current
Loop Current Sense Bits
Ring Voltage Detect
VTR
IL = 105 mA
12
—
—
V
IRDC
IRDC
ZACT
ILP
—
1
mA
µA
Ω
—
—
20
—
—
600
—
20
180
13
15
—
120
—
mA
mA
VRMS
Hz
µA
—
LCS
VRD
FR
LCS = Fh
155
18
26
68
1
Ring Frequency
—
On-Hook Leakage Current
Ringer Equivalence Num. (with caller ID)
Ringer Equivalence Num. (w/o caller ID)
ILK
VBAT = –48 V
—
REN
REN
—
1.0
0.2
1.67
—
—
—
TIP
+
600 Ω
10 µF
IL
VTR
Si3012
–
RING
Figure 1. Test Circuit for Loop Characteristics
4
Rev. 1.2
Si3035
Table 3. DC Characteristics, V = +5 V
D
(VA = +5 V ±5%, VD = +5 V ±5%, TA = 0 to 70°C for K-Grade)
Parameter
Symbol
VIH
Test Condition
Min
3.5
—
Typ
—
Max
Unit
V
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
—
0.8
—
VIL
—
V
VOH
VOL
IL
IO = –2 mA
IO = 2 mA
3.5
—
—
V
—
0.4
10
1
V
–10
—
—
µA
mA
mA
mA
mA
Power Supply Current, Analog
Power Supply Current, Digital1
Total Supply Current, Sleep Mode1
Total Supply Current, Deep Sleep1,2
Notes:
IA
VA pin
0.3
14
ID
VD pin
—
18
2.5
0.5
IA + ID
IA + ID
PDN = 1, PDL = 0
PDN = 1, PDL = 1
—
1.3
0.04
—
1. All inputs at 0.4 or VD – 0.4 (CMOS levels). All inputs held static except clock and all outputs unloaded
(Static IOUT = 0 mA).
2. RGDT is not functional in this state.
Table 4. DC Characteristics, V = +3.3 V
D
(VA = Charge Pump, VD = +3.3 V ± 0.3 V, TA = 0 to 70°C for K-Grade)
Parameter
Symbol
VIH
Test Condition
Min
2.0
—
Typ
—
Max
—
Unit
V
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
VIL
—
0.8
—
V
VOH
VOL
IL
IO = –2 mA
IO = 2 mA
2.4
—
—
V
—
0.35
10
V
–10
—
—
µA
mA
mA
mA
Power Supply Current, Analog1,2
Power Supply Current, Digital3
Total Supply Current, Sleep Mode3
Total Supply Current, Deep Sleep3,4
Power Supply Voltage, Analog1,5
Notes:
IA
VA pin
0.3
9
1
ID
VD pin
—
12
IA + ID
IA + ID
VA
PDN = 1, PDL = 0
PDN = 1, PDL = 1
Charge Pump On
—
1.2
0.04
4.6
2.5
0.5
5.00
—
4.3
V
1. Only a decoupling capacitor should be connected to VA when the charge pump is on.
2. There is no IA current consumption when the internal charge pump is enabled and only a decoupling cap is connected
to the VA pin.
3. All inputs at 0.4 or VD – 0.4 (CMOS levels). All inputs held static except clock and all outputs unloaded
(Static IOUT = 0 mA).
4. RGDT is not functional in this state.
5. The charge pump is recommended to be used only when VD < 4.5 V. When the charge pump is not used, VA should be
applied to the device before VD is applied on power up if driven from separate supplies.
Rev. 1.2
5
Si3035
Table 5. AC Characteristics
(VA = Charge Pump, VD = +3.3 V ± 0.3 V, TA = 0 to 70°C for K-Grade)
Parameter
Symbol
Fs
Test Condition
Min
7.2
36
—
Typ
—
Max
11.025
58
—
Unit
kHz
MHz
Hz
Sample Rate1
Fs = FPLL2/5120
"
PLL1 Output Clock Frequency
Transmit Frequency Response
Receive Frequency Response
Transmit Full Scale Level2 (0 dB gain)
Receive Full Scale Level 2,3 (0 dB gain)
Dynamic Range4
FPLL1
FPLL1 = FMCLK M1/N1
—
Low –3 dB corner
Low –3 dB corner
16
—
16
—
Hz
VTX
VRX
—
0.98
0.98
86
—
VPEAK
VPEAK
dB
—
—
DR
VIN = 1 kHz, –3 dBFS
VIN = 1 kHz, –3 dBFS
VIN = 1 kHz, –3 dBFS
VIN = 1 kHz
80
—
—
Dynamic Range5
DR
84
—
dB
Total Harmonic Distortion6
Dynamic Range (call progress AOUT)
THD (call progress AOUT)
AOUT Full Scale Level
THD
DRAO
THDAO
—
–84
—
—
dB
60
—
—
dB
VIN = 1 kHz
1.0
0.75 VD
10
—
%
—
—
VPP
kΩ
AOUT Output Impedance
Mute Level (call progress AOUT)
Dynamic Range (caller ID mode)
Caller ID Full Scale Level (0 dB gain)2
—
—
–90
—
—
—
dB
DRCID
VCID
VIN = 1 kHz, –13 dBFS
60
—
dB
—
0.8
—
VPEAK
Notes:
1. See Figure 23 on page 22.
2. Parameter measured at TIP and RING of Figure 16 on page 15.
3. Receive Full Scale Level will produce – 0.9 dBFS at SDO.
4. DR = 3 dB + 20 log (RMS signal/RMS noise). Applies to both the transmit and receive paths. Measurement bandwidth
is 300 to 3400 Hz. Sample Rate = 9.6 kHz, Loop Current = 40 mA.
5. DR = 3 dB + 20 log (RMS signal/RMS noise). Applies to both the transmit and receive paths. Measurement bandwidth
is 15 to 3400 Hz. Sample Rate = 9.6 kHz, Loop Current = 40 mA.
6. THD = 20 log (RMS distortion/RMS signal). Applies to both the transmit and receive paths.
Sample Rate = 9.6 kHz, Loop Current = 40 mA.
6
Rev. 1.2
Si3035
Table 6. Absolute Maximum Ratings
Parameter
Symbol
VD, VA
IIN
Value
–0.5 to 6.0
±10
Unit
V
DC Supply Voltage
Input Current, Si3021 Digital Input Pins
Digital Input Voltage
mA
V
VIND
TA
–0.3 to (VD + 0.3)
–40 to 100
–65 to 150
Operating Temperature Range
Storage Temperature Range
°C
°C
TSTG
Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation
should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Table 7. Switching Characteristics—General Inputs
(VA = Charge Pump, VD = 3.0 to 5.25 V, TA = 0 to 70°C for K-Grade, CL = 20 pF)
Parameter1
Symbol
Min
Typ
Max
Unit
Cycle Time, MCLK
MCLK Duty Cycle
Rise Time, MCLK
Fall Time, MCLK
MCLK Before RESET ↑
RESET Pulse Width2
M0, M1 Before RESET↑3
Notes:
tmc
tdty
tr
16.67
40
—
50
—
—
—
—
—
1000
60
5
ns
%
—
ns
tf
—
5
ns
tmr
trl
10
—
—
—
cycles
ns
250
150
tmxr
ns
1. All timing (except Rise and Fall time) is referenced to the 50% level of the waveform. Input test levels are
VIH = VD – 0.4 V, VIL = 0.4 V. Rise and Fall times are referenced to the 20% and 80% levels of the waveform.
2. The minimum RESET pulse width is the greater of 250 ns or 10 MCLK cycle times.
3. M0 and M1 are typically connected to VD or GND and should not be changed during normal operation.
tmc
tr
tf
VIH
VIL
MCLK
tmr
RESET
trl
M0, M1
tmxr
Figure 2. General Inputs Timing Diagram
Rev. 1.2
7
Si3035
Table 8. Switching Characteristics—Serial Interface (DCE = 0)
(VA = Charge Pump, VD = 3.0 to 5.25 V, TA = 0 to 70°C for K-Grade, CL = 20 pF)
Parameter
Symbol
tc
Min
354
—
Typ
Max
—
Unit
ns
%
Cycle time, SCLK
1/256 Fs
SCLK duty cycle
tdty
td1
50
—
—
—
—
—
—
—
—
Delay time, SCLK ↑ to FSYNC ↓
Delay time, SCLK ↑ to SDO valid
Delay time, SCLK ↑ to FSYNC ↑
Setup time, SDI before SCLK ↓
Hold time, SDI after SCLK ↓
Setup time, FC ↑ before SCLK ↑
Hold time, FC ↑ after SCLK ↑
—
10
20
10
—
ns
ns
ns
ns
ns
ns
ns
td2
—
td3
—
tsu
25
20
40
40
th
—
tsfc
thfc
—
—
Note: All timing is referenced to the 50% level of the waveform. Input test levels are VIH = VD – 0.4 V, VIL = 0.4 V
tc
VOH
VOL
SCLK
td1
td3
FSYNC
(mode 0)
td3
FSYNC
(mode 1)
td2
16 Bit
SDO
D15
D15
D14
D14
D1
D1
D0
th
tsu
16 Bit
SDI
D0
tsfc
thfc
FC
Figure 3. Serial Interface Timing Diagram
8
Rev. 1.2
Si3035
Table 9. Switching Characteristics—Serial Interface (DCE = 1, FSD = 0)
(VA = Charge Pump, VD = 3.0 to 5.25 V, TA = 0 to 70°C for K-Grade, CL = 20 pF)
Parameter1,2
Symbol
Min
Typ
Max
Unit
Cycle Time, SCLK
tc
tdty
td1
td2
td3
td4
td5
td6
tsu
th
354
1/256 Fs
50
—
—
10
10
ns
%
SCLK Duty Cycle
—
Delay Time, SCLK ↑ to FSYNC ↑
Delay Time, SCLK ↑ to FSYNC ↓
Delay Time, SCLK ↑ to SDO valid
Delay Time, SCLK ↑ to SDO Hi-Z
Delay Time, SCLK ↑ to RGDT ↓
Delay Time, SCLK ↑ to RGDT ↑
Setup Time, SDO Before SCLK ↓
Hold Time, SDO After SCLK ↓
Setup Time, SDI Before SCLK
Hold Time, SDI After SCLK
Notes:
—
—
ns
ns
—
—
0.25tc – 20
—
0.25tc + 20
ns
ns
ns
ns
ns
ns
ns
ns
—
—
—
25
20
25
20
—
20
20
20
—
—
—
—
—
—
—
—
tsu2
th2
—
—
1. All timing is referenced to the 50% level of the waveform. Input test levels are VIH = VD – 0.4 V, VIL = 0.4 V.
2. Refer to the section "Multiple Device Support" on page 25 for functional details.
32 SCLKs
16 SCLKs
16 SCLKs
tc
SCLK
td1
td2
td2
FSYNC
(mode 1)
td5
td6
td5
FSYNC
(mode 0)
td3
tsu
D15
th
td4
SDO
(master)
D14
D13
D0
td3
SDO
(slave 1)
D15
td5
FSD
(Mode 0)
td2
FSD
(Mode 1)
tsu2
th2
D14
SDI
D15
D13
D0
Figure 4. Serial Interface Timing Diagram (DCE = 1, FSD = 0)
Rev. 1.2
9
Si3035
Table 10. Switching Characteristics—Serial Interface (DCE = 1, FSD = 1)
(VA = Charge Pump, VD = 3.0 to 5.25 V, TA = 0 to 70°C for K-Grade, CL = 20 pF)
Parameter1,2
Symbol
Min
Typ
Max
Unit
Cycle Time, SCLK
tc
tdty
td1
td2
td3
td4
td5
tsu
th
354
1/256 Fs
—
ns
%
SCLK Duty Cycle
—
50
—
—
—
—
—
—
—
—
—
—
Delay Time, SCLK ↑ to FSYNC ↑
Delay Time, SCLK ↑ to FSYNC ↓
Delay Time, SCLK ↑ to SDO valid
Delay Time, SCLK ↑ to SDO Hi-Z
Delay Time, SCLK ↑ to RGDT ↓
Setup Time, SDO Before SCLK ↓
Hold Time, SDO After SCLK ↓
Setup Time, SDI Before SCLK
Hold Time, SDI After SCLK
Notes:
—
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
10
0.25tc – 20
0.25tc + 20
—
—
25
20
25
20
20
20
—
—
—
—
tsu2
th2
1. All timing is referenced to the 50% level of the waveform. Input test levels are VIH = VD – 0.4 V, VIL = 0.4 V.
2. Refer to the section "Multiple Device Support" on page 25 for functional details.
tc
SCLK
td1
td2
FSYNC
(mode 1)
td3
tsu
th
td4
SDO
(master)
D15
D14
D13
D0
td3
D15
td5
SDO
(slave 1)
FSD
SDI
tsu2
th2
D14
D15
D1
D0
Figure 5. Serial Interface Timing Diagram (DCE = 1, FSD = 1)
10
Rev. 1.2
Si3035
Table 11. Digital FIR Filter Characteristics—Transmit and Receive
(V = Charge Pump, V = +5 V ±5%, Sample Rate = 8 kHz, T = 0 to 70°C for K-Grade)
A
D
A
Parameter
Symbol
F(0.1 dB)
F(3 dB)
Min
0
Typ
—
Max
3.3
3.6
0.1
—
Unit
kHz
kHz
dB
Passband (0.1 dB)
Passband (3 dB)
Passband Ripple Peak-to-Peak
Stopband
0
—
–0.1
—
—
4.4
—
kHz
dB
Stopband Attenuation
Group Delay
–74
—
—
tgd
12/Fs
—
sec
Note: Typical FIR filter characteristics for Fs = 8000 Hz are shown in Figures 6, 7, 8, and 9.
Table 12. Digital IIR Filter Characteristics—Transmit and Receive
(V = Charge Pump, V = +5 V ±5%, Sample Rate = 8 kHz, T = 0 to 70°C for K-Grade)
A
D
A
Parameter
Symbol
Min
0
Typ
—
Max
3.6
0.2
—
Unit
kHz
dB
F(3 dB)
Passband (3 dB)
Passband Ripple Peak-to-Peak
Stopband
–0.2
—
—
4.4
kHz
dB
Stopband Attenuation
Group Delay
–40
—
—
—
tgd
1.6/Fs
—
sec
Note: Typical IIR filter characteristics for Fs = 8000 Hz are shown in Figures 10, 11, 12, and 13. Figures 14 and 15 show
group delay versus input frequency.
Rev. 1.2
11
Si3035
Input Frequency—Hz
Input Frequency—Hz
Figure 6. FIR Receive Filter Response
Figure 8. FIR Transmit Filter Response
Input Frequency—Hz
Input Frequency—Hz
Figure 7. FIR Receive Filter Passband Ripple
Figure 9. FIR Transmit Filter Passband Ripple
For Figures 6–9, all filter plots apply to a sample rate of
Fs = 8 kHz. The filters scale with the sample rate as follows:
F(0.1 dB) = 0.4125 Fs
F(– 3 dB) = 0.45 Fs
where Fs is the sample frequency.
12
Rev. 1.2
Si3035
Input Frequency—Hz
Input Frequency—Hz
Figure 10. IIR Receive Filter Response
Figure 12. IIR Transmit Filter Response
Input Frequency—Hz
Input Frequency—Hz
Figure 11. IIR Receive Filter Passband Ripple
Figure 13. IIR Transmit Filter Passband Ripple
For Figures 10–13, all filter plots apply to a sample rate of
Fs = 8 kHz. The filters scale with the sample rate as follows:
F(–3 dB) = 0.45 Fs
where Fs is the sample frequency.
Rev. 1.2
13
Si3035
Input Frequency—Hz
Figure 14. IIR Receive Group Delay
Input Frequency—Hz
Figure 15. IIR Transmit Group Delay
14
Rev. 1.2
Decoupling cap for U1 VD
No Ground Plane In DAA Section
VCC
R3
10
Decoupling cap for U1 VA
C10
R1
D3
Q1
BAV99
C3
Z4
R5
M0
RGDTb
OFHKb
U1
1
2
3
4
5
6
7
8
16
U2
Si3012
MCLK
FSYNCb
SCLK
MCLK
FSYNC
SCLK
VD
SDO
SDI
OFHK
15
R4
R21
RGDT
14
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
M0
13
TSTA
TSTB
IGND
C1B
TX
NC2
RX
REXT
DCT
Q2
VA
12
R27
R28
SDO
SDI
FC
GND
11
C1A
10
C5
R18
FC
RESET
M1
9
RNG1
RESETb
AOUT
RNG2 HYBD
C1
R6
QB
QE
VREG2
VREG
Si3021
SOIC Pinout
C23
+
C12
AOUT
M1
C30
Z1
R2
C20
D4
BAV99
Z5
C6
C16
C2
Q3
C8
R23
FB2
R10
RING
D2
C9
C25
C32
RV1
C11
RV2
D1
C31
C24
R22
C7
R9
TIP
FB1
C4
Note 1: R3 is not required when Vcc=3.3 V and the charge pump is
enabled (CPE = 1).
Note 2: If JATE support is not required, R21, C12 and C23
may be removed (R21 is effectively 0 ohms) and R4 should
be changed to a 604 ohm, 1/4 W, +- 1%.
Note 3: See Appendix for applications requiring UL 1950
3rd Edition compliance.
Figure 16. Typical Application Schematic
Si3035
Bill of Materials
Table 13. Component Values—Typical Application
Component1
Value
Supplier(s)
C1,C4
150 pF, 3 kV, X7R, ±20%
Novacap, Venkel, Johanson, Murata,
Panasonic, SMEC
C2
C3
Not Installed
0.22 µF, 16 V, X7R, ±20%
1 µF, 16 V, Tant/Elec, ±20%
0.1 µF, 16 V, X7R, ±20%
15 nF, 250 V, X7R, ±20%
39 nF, 16 V, X7R, ±20%
2.7 nF, 16 V, X7R, ±20%
C5
C6,C10,C16
C7,C8,C9
C11
Novacap, Johanson, Murata, Panasonic, SMEC
C122
C232
0.1 µF, 16 V, Tant/Elec/X7R, ±20%
1000 pF, 3 kV, X7R, ±10%
Not Installed
C24, C25, C31,C323
C304
Novacap, Venkel, Johanson, Murata, Panasonic, SMEC
Central Semiconductor
D1,D25
D3,D4
FB1,FB2
Q1,Q3
Q2
Dual Diode, 300 V, 225 mA
BAV99 Dual Diode, 70 V, 350 mW
Ferrite Bead
Diodes, Inc., OnSemiconductor, Fairchild
Murata
A42, NPN, 300 V
A92, NPN, 300 V
Sidactor, 275 V, 100 A
MOV, 240 V
OnSemiconductor, Fairchild
OnSemiconductor, Fairchild
Teccor, ST Microelectronics, Microsemi, TI
Panasonic
RV1
RV2
R1
51 Ω, 1/2 W ±5%
15 Ω, 1/4 W ±5%
Not Installed
R2
R36
R42,R18,R212
R5,R6
301 Ω, 1/10 W, ±1%
36 kΩ, 1/10 W ±5%
2 kΩ, 1/10 W ±5%
20 kΩ, 1/10 W ±5%
10 Ω, 1/10 W ±5%
Si3021
R9,R10
R22,R23
R27,R28
U1
Silicon Labs
Silicon Labs
U2
Si3012
Z1
Zener diode, 18 V
Zener diode, 5.6 V, 1/2 W
Vishay, Rohm, OnSemiconductor
Diodes, Inc., OnSemiconductor, Fairchild
Z4,Z5
Notes:
1. The following reference designators were intentionally omitted: C13–C15, C17–C22, C26–C29, R7, R8, R11–R17,
R19, and R20.
2. If JATE support is not required, C12, and C23 may be removed.
3. Alternate population option is C24, C25 (2200 pF, 3 kV, X7R, ±10% and C31, C32 not installed).
4. Install only if needed for improved radiated emissions performance (10 pF, 16 V, NPO, ±10%).
5. Several diode bridge configurations are acceptable (suppliers include General Semi, Diodes Inc.)
6. If the charge pump is not enabled (with the CPE bit in Register 6), VA must be 4.75 to 5.25 V. R3 can be installed with
a 10 Ω, 1/10 W, ±5% if VD is also 4.75 to 5.25 V.
16
Rev. 1.2
Si3035
Analog Output
Figure 17 illustrates an optional application circuit to support the analog output capability of the Si3035 for call
progress monitoring purposes. The ARM bits in Register 6 allow the receive path to be attenuated by 0 dB, –6 dB,
or –12 dB. The ATM bits, which are also in Register 6, allow the transmit path to be attenuated by –20 dB, –26 dB,
or –32 dB. Both the transmit and receive paths can also be independently muted.
+5 V
C2
6
R3
3
2
C4
+
–
5
+
AOUT
C5
4
C1
C6
R1
C3
R2
Speaker
Figure 17. Optional Connection to AOUT for a Call Progress Speaker
Table 14. Component Values—Optional Connection to AOUT
‘
Symbol
Value
C1
C2, C3, C5
C4
2200 pF, 16 V, ±20%
0.1 µF, 16 V, ±20%
100 µF, 16 V, Elec. ±20%
820 pF, 16 V, ±20%
3 kΩ, 1/10 W, ±5%
10 Ω, 1/10 W, ±5%
47 kΩ, 1/10 W, ±5%
LM386
C6
R1
R2
R3
U1
Rev. 1.2
17
Si3035
procedure:
Functional Description
1. Program the PLLs with registers 7 to 9 (N1[7:0], M1[7:0],
N2[3:0] and M2[3:0]) to the appropriate divider ratios for
the supplied MCLK frequency and desired sample rate, as
defined in "Clock Generation Subsystem" on page 20.
The Si3035 is an integrated chipset that provides a
low-cost, isolated, silicon-based interface to the
telephone line. The Si3035 saves cost and board area
by eliminating the need for a modem AFE or serial
codec. It also eliminates the need for an isolation
transformer, relays, opto-isolators, and a 2- to 4-wire
hybrid. The Si3035 solution requires only a few
low-cost, discrete components to achieve full
compliance with FCC Part 68 and JATE out-of-band
noise requirements. See Figure 16 on page 15 for a
typical application circuit. See the pin-compatible
Si3034 or Si3044 data sheets for designs requiring
global support.
2. Wait until the PLLs are locked. This time is between
100 µS and 1 ms.
3. Write an 0x80 into Register 6. This enables the charge
pump for the VA pin, powers up the line-side chip (Si3012),
and enables the AOUT for call progress monitoring.
After this procedure is complete, the Si3035 is ready for
ring detection and off-hook.
Isolation Barrier
The Si3035 achieves an isolation barrier through a
The Si3035 North America/Japan DAA offers a number low-cost, high-voltage capacitor in conjunction with
of new features not supported by the Si3032 device. Silicon Laboratories’ proprietary ISOcap signal
These include operation from a single 3.3 V power processing techniques. These techniques eliminate any
supply, JATE (Japan) filter option, finer resolution for signal degradation due to capacitor mismatches,
both transmit and receive levels on AOUT (call progress common mode interference, or noise coupling. As
output), daisy-chaining for up to eight devices, and an shown in Figure 16 on page 15, the C1, C2, and C4
optional IIR filter. Table 15 summarizes the new Si3035 capacitors isolate the Si3021 (DSP-side) from the
features.
Si3012 (line-side). All transmit, receive, control, and
caller ID data are communicated through this barrier.
Table 15. New Si3035 Features
The ISOcap inter-chip communication is disabled by
default. To enable it, the PDL bit in Register 6 must be
cleared. No communication between the Si3021 and
Si3012 can occur until this bit is cleared. The clock
generator must be programmed to an acceptable
sample rate prior to clearing the PDL bit.
Category
Daisy-Chaining
Si3032
—
Si3035
Up to 8 Devices
Yes
Optional IIR Filter
Receive Gain
—
Off-Hook
0, 6 dB
0, –3 dB
0, 3, 6, 9, 12 dB
The communication system generates an off-hook
command by applying logic 0 to the OFHK pin or writing
a logic 1 to bit 0 of control Register 5. The OFHK pin
must be enabled by setting bit 1 (OHE) of Register 5.
With OFHK at logic 0, the system is in an off-hook state.
This state is used to seize the line for incoming/outgoing
calls and can also be used for pulse dialing. With OFHK
at logic 1, negligible DC current flows through the
hookswitch. When a logic 0 is applied to the OFHK pin,
the hookswitch transistor pair, Q1 and Q2, turn on. The
net effect of the off-hook signal is the application of a
termination impedance across TIP and RING and the
flow of DC loop current. The termination impedance has
both an AC and a DC component.
Transmit Attenuation
0, –3, –6 –9,
–12 dB
VA
VD
5 V
3.3 V* or 5 V
3.3 V or 5 V
3.3 V or 5 V
JATE Support
—
Yes
AOUT Levels (dB)
0, mute
0, –6, –12, mute
*Note: The VA supply is internally generated by an on-chip
charge pump.
Initialization
The AC termination impedance is a 604-Ω resistor,
which is connected to the TX pin. The DC termination is
a 51-Ω resistor, which is connected to the DCT pin.
When the Si3035 is initially powered up, the RESET pin
should be asserted. When the RESET pin is
deasserted, the registers will have default values. This
reset condition guarantees the line-side chip (Si3012) is
powered down with no possibility of loading the line (i.e.,
off-hook). The following is an example initialization
When executing an off-hook sequence, the Si3035
requires 1548/Fs seconds to complete the off-hook and
provide phone line data on the serial link. This includes
the 12/Fs filter group delay. If necessary, for the shortest
18
Rev. 1.2
Si3035
delay, a higher Fs may be established prior to executing
Improved JATE Support
the off-hook, such as an Fs of 10.286 kHz. The delay
allows line transients to settle prior to normal use.
The HYBD pin connects to a node on the internal hybrid
cancellation circuit providing a pin for a balancing
capacitor, C12. C23 adds the necessary transmit
out-of-band filtering required to meet JATE out-of-band
noise specifications. The addition of C23 alters the
transmit path frequency response which must be
balanced with capacitor C12 to obtain maximum hybrid
cancellation.
Ring Detect
The ring signal enters the Si3035 through low value
capacitors connected to TIP and RING. RGDT is a
clipped, half-wave rectified version of the ringing
waveform. See Figure 18 for a timing diagram of the
RGDT pin.
Products using the Si3035 which have been submitted
for JATE approval should document a waiver for the
JATE DC Termination specification. This specification is
met in the Si3034 global DAA device.
The integrated ring detect of the Si3035 allows the
device to present the ring signal to the DSP, through the
serial port, with no additional signaling required. The
signal sent to the DSP is a clipped version of the original
ring signal. In addition, the Si3035 passes through the
caller ID data unaltered.
Digital Interface
The Si3035 has two serial interface modes that support
The system can also detect an occurring ring by the most standard modem DSPs. The M0 and M1 mode
status of the RDT bit of Register 5. This bit is a pins select the interface mode. The key difference
read-only bit that is set when the line-side device between these two serial modes is the operation of the
detects a ring signal at RNG1 and RNG2. The RDT bit FSYNC signal. Table 16 summarizes the serial mode
clears when the system either goes off-hook or 4.5 to 9 definitions.
seconds after the last ring is detected.
Table 16. Serial Modes
If caller ID is supported in the system, the designer can
enable the Si3035 to pass this information to the SDO
Mode M1 M0
Description
output. Following the completion of the first ring, the
system should set the ONHM bit (Register 5, bit 3). This
bit must be cleared at the conclusion of the receipt of
the caller ID data and prior to the next ring burst.
0
1
2
3
0 0 FSYNC frames data
0 1 FSYNC pulse starts data frame
1 0 Slave mode
The Si3021 can support a wake-up-on-ring function
using the RGDT signal. Refer to "Power Management"
on page 24 for more details
1 1 Reserved
.
First Ring
0.2–3.0 seconds
> 0.2 Sec.
0.5–1.5 Sec.
RNG1/
RNG2
DATA
RGDT
SDO
DIGITIZED LINE SIGNAL
Figure 18. Ring Detect Timing
Rev. 1.2
19
Si3035
The digital interface consists of a single, synchronous Figure 21 and Figure 22 illustrate the secondary frame
serial link which communicates both telephony and read cycle and write cycle, respectively. During a read
control data.
cycle, the R/W bit is high and the 5-bit address field
contains the address of the register to be read. The
contents of the 8-bit control register are placed on the
SDO signal. During a write cycle, the R/W bit is low and
the 5-bit address field contains the address of the
register to be written. The 8-bit data to be written
immediately follows the address on SDI. Only one
register can be read or written during each secondary
frame. See "Control Registers" on page 34 for the
register addresses and functions.
In Serial mode 0 or 1, the Si3021 operates as a master,
where the master clock (MCLK) is an input, the serial
data clock (SCLK) is an output, and the frame sync
signal (FSYNC) is an output. The MCLK frequency and
the value of the sample rate control registers 7, 8, 9,
and 10 determine the sample rate (Fs). The serial port
clock, SCLK, runs at 256 bits per frame, where the
frame rate is equivalent to the sample rate. Refer to
"Clock Generation Subsystem" on page 20 for more
details on programming sample rates.
In serial mode 2, the Si3021 operates as a slave device,
where the MCLK is an input, the SCLK is a no connect
(except for the master device for which it is an output),
and the FSYNC is an input. In addition, the RGDT/FSD
pin operates as a delayed frame sync (FSD) and the
FC/RGDT pin operates as ring detect (RGDT). In this
mode, FC operation is not supported. For further details
on operating the Si3021 as a slave device, refer to
"Multiple Device Support" on page 25.
The Si3035 transfers 16-bit or 15-bit telephony data in
the primary timeslot and 16-bit control data in the
secondary timeslot. Figure 19 and Figure 20 show the
relative timing of the serial frames. Primary frames
occur at the frame rate and are always present. To
minimize overhead in the external DSP, secondary
frames are present only when requested.
Two methods exist for transferring control information in
the secondary frame. The default power-up mode uses
the LSB of the 16-bit transmit (TX) data word as a flag
to request a secondary transfer. In this mode, only
15-bit TX data is transferred, resulting in a loss of SNR
but allowing software control of the secondary frames.
As an alternative method, the FC pin can serve as a
hardware flag for requesting a secondary frame. The
external DSP can turn on the 16-bit TX mode by setting
the SB bit of Register 1. In the 16-bit TX mode, the
hardware FC pin must be used to request secondary
transfers.
Clock Generation Subsystem
The Si3035 contains an on-chip clock generator. Using
a single MCLK input frequency, the Si3035 can
generate all the desired standard modem sample rates,
as well as the common 11.025 kHz rate for audio
playback.
The clock generator consists of two PLLs (PLL1 and
PLL2) that achieve the desired sample frequencies.
Figure 23 on page 22 illustrates the clock generator.
Communications Frame 1 (CF1)
(CF2)
Secondary
Prim ary
Prim ary
FSYNC
FC
0
D15 – D1 D0 = 1 (Software FC Bit)
D15 – D1 D0 = 0 (Software FC Bit)
XMT Data
Secondary
XMT Data
SDI
Data
Secondary
Data
RCV Data
RCV Data
SDO
16 SCLKS
128 SCLKS
256 SCLKS
Figure 19. Software FC Secondary Request
20
Rev. 1.2
Si3035
Communications Frame 1 (CF1)
(CF2)
Primary
Secondary
Primary
FSYNC
FC
0
D15–D0
Secondary
Data
XMT Data
XMT Data
RCV Data
SDI
Secondary
Data
RCV Data
SDO
16 SCLKS
128 SCLKS
256 SCLKS
Figure 20. Hardware FC Secondary Request
FSYNC
(mode 0)
FSYNC
(mode 1)
D15 D14 D13 D12 D11 D10 D9 D8 D7
D0
0
0
1
A
A
A
A
A
SDI
R/W
D7 D6 D5
D4 D3 D2 D1 D0
D
D
D
D
D
D
D
D
SDO
Figure 21. Secondary Communication Data Format—Read Cycle
Rev. 1.2
21
Si3035
FSYNC
(mode 0)
FSYNC
(mode 1)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5
D4 D3 D2 D1 D0
0
0
0
A
A
A
A
A
D
D
D
D
D
D
D
D
SDI
R/W
SDO
Figure 22. Secondary Communication Data Format—Write Cycle
FUP1
FPLL1
FUP2
FPLL2
DIV
25
1
0
DIV N1
8 bits
DIV N2
4 bits
MCLK
DIV
5
PLL1
PLL2
1024·Fs
0
1
DIV M1
8 bits
DIV M2
4 bits
DIV
16
CGM
Bit
Figure 23. Clock Generation Subsystem
The architecture of the dual PLL scheme allows for fast Programming the Clock Generator
lock time on initial start-up, fast lock time when
As noted in Figure 23, the clock generator must output a
changing modem sample rates, high noise immunity,
and the ability to change modem sample rates with a
single register write. A large number of MCLK
frequencies between 1 MHz and 60 MHz are supported.
MCLK should be from a clean source, preferably
directly from a crystal with a constant frequency and no
dropped pulses.
"
clock equal to 1024 Fs, where Fs is the desired
"
sample rate. The 1024 Fs clock is determined through
programming of the following registers:
Register 7—N1 divider, 8 bits.
Register 8—M1 divider, 8 bits.
Register 9—N2/M2 dividers, 4 bits/4 bits.
Register 10—CGM, 1 bit.
In serial mode 2, the Si3021 operates as a slave device.
The clock generator is configured (by default) to set the
SCLK output equal to the MCLK input. The net effect is
the clock generator multiplies the MCLK input by 20. For
further details of slave mode operation, refer to "Multiple
Device Support" on page 25.
When using the Si3035 for modem applications, the
clock generator can be programmed to allow for a single
register write to change the modem sampling rate.
These standard sample rates are shown in Table 17.
The programming method is described below.
22
Rev. 1.2
Si3035
Table 17. N2, M2 Values (CGM = 0, 1)
Table 18. MCLK Examples
Fs (Hz)
7200
8000
8229
8400
9000
9600
10286
N2
2
M2
2
MCLK (MHz)
1.8432
N1
1
M1
20
72
9
CGM
0
9
10
8
4.0000
5
1
7
4.0960
1
0
6
7
5.0688
11
5
80
48
6
0
4
5
6.0000
1
3
4
6.1440
1
0
7
10
8.1920
32
1
225
4
1
9.2160
0
The main design consideration is the generation of a
base frequency, defined as the following:
10.0000
10.3680
11.0592
12.288
25
9
144
32
10
3
1
0
F
M1
MCLK
= ---------------------------------- = 3 6. 8 64 M H z , C G M = 0
3
0
F
Base
N1
M1 16
1
0
F
MCLK
= --------------------------------------------- = 36.864MHz, CGM = 1
F
14.7456
16.0000
18.4320
24.5760
25.8048
33.8688
44.2368
46.0800
47.9232
48.0000
56.0000
60.0000
2
5
0
Base
N1 25
5
18
2
1
N1 (Register 7) and M1 (Register 8) are 8-bit unsigned
values. FMCLK is the clock provided to the MCLK pin.
Table 18 lists several standard crystal oscillator rates
that could be supplied to MCLK. This list simply
represents a sample of MCLK frequency choices. Many
more are possible.
1
0
32
7
75
10
160
125
4
1
0
147
96
5
0
After the first PLL has been setup, the second PLL can
be programmed easily. The values for N2 and M2
(Register 9) are shown in Table 17. N2 and M2 are 4-bit
unsigned values.
1
0
13
125
35
25
10
96
36
24
0
When programming the registers of the clock generator,
the order of register writes is important. For PLL1
updates, N1 (Register 7) must always be written first,
immediately followed by a write to M1 (Register 8). For
PLL2, the CGM bit must be set as desired prior to
writing N2/M2 (Register 9). Changes to the CGM bit
only take effect when N2/M2 are written.
0
1
1
PLL Lock Times
The Si3035 changes sample rates very quickly.
However, lock time will vary based on the programming
of the clock generator. The major factor contributing to
PLL lock time is the CGM bit. When the CGM bit is used
(set to 1), PLL2 will lock slower than when CGM is 0.
The following relationships describe the boundaries on
PLL locking time:
Note: The values shown in Table 17 and Table 18 satisfy the
equations above. However, when programming the
registers for N1, M1, N2, and M2, the value placed in
these registers must be one less than the value calcu-
lated from the equations. For example, for CGM = 0
with a MCLK of 48.0 MHz, the values placed in the N1
and M1 registers would be 0x7C and 0x5F, respec-
tively. If CGM = 1, a non-zero value must be pro-
grammed to Register 9 in order for the 16/25 ratio to
take effect.
PLL1 lock time < 1 ms (CGM = 0,1)
PLL2 lock time: 100 us to 1 ms (CGM = 0)
PLL2 lock time <1 ms (CGM = 1)
For modem designs, it is recommended that PLL1 be
programmed
during
initialization.
No
further
programming of PLL1 is necessary. The CGM bit and
PLL2 can be programmed for the desired initial sample
Rev. 1.2
23
Si3035
rate, typically 7200 Hz. All further sample rate changes PDN bit is cleared. The Si3021 is fully operational,
are then made by simply writing to Register 9 to update except for the ISOcap link. No communication between
PLL2.
the Si3021 and Si3012 can occur during reset
operation. Any bits associated with the Si3012 are not
valid in this mode.
The final design consideration for the clock generator is
the update rate of PLL1. The following criteria must be
satisfied in order for the PLLs to remain stable:
The most common mode of operation is the normal
operation. In this mode, the PDL and PDN bits are
cleared. The Si3021 is fully operational and the ISOcap
link is passing information between the Si3021 and the
Si3012. The clock generator must be programmed to a
valid sample rate prior to entering this mode.
F
MCLK
N1
F
= --------------------- ≥ 144 kHz
UP1
Where FUP1 is shown in Figure 23 on page 22.
Setting Generic Sample Rates
The Si3035 supports a low-power sleep mode. This
mode supports the popular wake-up-on-ring feature of
many modems. The clock generator registers 7, 8, and
9 must be programmed with valid non-zero values prior
to enabling sleep mode. Then, the PDN bit must be set
and the PDL bit cleared. When the Si3035 is in sleep
mode, the MCLK signal may be stopped or remain
active, but it must be active before waking up the
Si3035. The Si3021 is non-functional except for the
ISOcap and RGDT signal. To take the Si3035 out of
sleep mode, pulse the reset pin (RESET) low.
The above clock generation description focuses on the
common modem sample rates. An application may
require a sample rate not listed in Table 17, such as the
common audio rate of 11.025 kHz. The restrictions and
equations above still apply; however, a more generic
relationship between MCLK and Fs (the desired sample
rate) is needed. The following equation describes this
relationship:
5 1024 Fs
--------------------------------
M1 M2
N1 N2
--------------------- = r a t i o
MCLK
where Fs is the sample frequency, ratio is 1 for
CGM = 0 and 25/16 for CGM = 1, and all other symbols
are shown in Figure 23 on page 22.
In summary, the power down/up sequence for sleep
mode is as follows:
1. Registers 7, 8, and 9 must have valid non-zero values.
By knowing the MCLK frequency and desired sample
rate, the values for the M1, N1, M2, N2 registers can be
determined. When determining these values, remember
to consider the range for each register as well as the
minimum update rate for the first PLL.
2. Set the PDN bit (Register 6, bit 3) and clear the PDL bit
(Register 6, bit 4).
3. MCLK may stay active or stop.
4. Restore MCLK before initiating the power-up sequence.
5. Reset the Si3035 using RESET pin (after MCLK is
present).
The values determined for M1, N1, M2, and N2 must be
adjusted by minus one when determining the value
written to the respective registers. This is due to internal
logic, which adds one to the value stored in the register.
This addition allows the user to write a zero value in any
of the registers and the effective divide by is one. A
special case occurs when both M1 and N1 and/or M2
and N2 are programmed with a zero value. When Mx
and Nx are both zero, the corresponding PLLx is
bypassed. Note that if M2 and N2 are set to zero, the
ratio of 25/16 is eliminated and cannot be used in the
above equation. In this condition the CGM bit has no
effect.
6. Program registers to desired settings.
The Si3035 also supports an additional power-down
mode. When both the PDN (Register 6, bit 3) and PDL
(Register 6, bit 4) are set, the chipset enters a complete
power-down mode and draws negligible current (deep
sleep mode). PLL2 should be turned off prior to entering
deep sleep mode (i.e., set Register 9 to 0 and then
Register 6 to 0x18). In this mode, the RGDT pin does
not function. Normal operation may be restored using
the same process for taking the chipset out of sleep
mode.
Analog Output
Power Management
The Si3035 supports an analog output (AOUT) for
driving the call progress speaker found with most of
today’s modems. AOUT is an analog signal that is
comprised of a mix of the transmit and receive signals.
The receive portion of this mixed signal has a 0 dB gain,
while the transmit signal has a gain of –20 dB.
The Si3035 supports four basic power management
operation modes: normal operation, reset operation,
sleep, and full power down. The power management
modes are controlled by the PDN and PDL bits of
Register 6.
On power up, or following a reset, the Si3035 is in reset
operation. In this mode, the PDL bit is set, while the
The AOUT level can be adjusted via the ATM and ARM
bits in control Register 6. The transmit portion of the
24
Rev. 1.2
Si3035
AOUT signal can be set to –20 dB, –26 dB, –32 dB, or An LCS value of zero means the loop current is less
mute. The receive portion of the AOUT signal can be than required for normal operation and the system
set to 0 dB, –6 dB, –12 dB, or mute. Figure 17 on page should be on-hook. Typically, an LCS value of 15 means
17 illustrates a recommended application circuit. In the the loop current is greater than 155 mA.
configuration shown, the LM386 provides a gain of
26 dB. Additional gain adjustments may be made by
current. This allows for a stable LCS value when the
varying the voltage divider created by R1 and R3 of
The LCS detector has a built-in hysteresis of 2 mA of
loop current is near a transition level. The LCS value is
a rough approximation of the loop current, and the
Figure 17.
designer is advised to use this value in a relative means
rather than an absolute value.
On-Hook Line Monitor
The Si3035 allows the user to detect line activity when
This feature enables the host processor to detect if an
the device is in an on-hook state. When the system is
additional line has “picked up” while the modem is
on-hook, the line data can be passed to the DSP across
transferring information. In the case of a second phone
the serial port while drawing a small amount of DC
going off-hook, the loop current falls approximately 50%
current from the line. This feature is similar to the
and is reflected in the value of the LCS bits.
passing of line information (such as caller ID), while
on-hook, following a ring signal detection. To activate
this feature, set the ONHM bit in Register 5.
Multiple Device Support
The Si3035 supports the operation of up to seven
The on-hook line monitor can also be used to detect
whether a phone line is physically connected to the
Si3012 and associated circuitry. When the on-hook line
monitor is activated (if no line is connected), the output
of SDO will move towards a negative full scale value
(–32768). The value is guaranteed to be at least 89% of
negative full scale.
additional devices on a single serial interface. Figure 25
on page 27 shows the typical connection of the Si3035
and one additional serial voice codec (Si3000).
The Si3035 must be the master in this configuration. The
secondary codec should be configured as a slave device
with SCLK and FSYNC as inputs. On power up, the
Si3035 master will be unaware of the additional codec
on the serial bus. The FC/RGDT pin is an input,
operating as the hardware control for secondary frames.
The RGDT/FSD pin is an output, operating as the active
low ring detection signal. It is recommended that the
master device be programmed for master/slave mode
prior to enabling the ISOcap, because a ring signal
would cause a false transition to the slave device’s
FSYNC.
If a line is present while in on-hook line monitor mode,
SDO will have a near zero value. The designer must
allow for the group delay of the receive filter (12/Fs)
before making a decision.
Loop Current Monitor
When the system is in an off-hook state, the LCS bits of
Register 12 indicate the approximate amount of DC
loop current that is flowing in the loop. The LCS is a
4-bit value ranging from zero to fifteen. Each unit
represents approximately 6 mA of loop current from
LCS codes 1–14. The typical LCS transfer function is
shown in Figure 24.
Register 14 provides the necessary control bits to
configure the Si3035 for master/slave operation. Bit 0
(DCE) sets the Si3035 in master/slave mode, also
referred to as daisy-chain mode. When the DCE bit is
set, the FC/RGDT pin becomes the ring detect output
and the RGDT/FSD pin becomes the frame sync delay
output.
Bits 7:5 (NSLV2:NSLV0) set the number of slaves to be
supported on the serial bus. For each slave, the Si3035
will generate a FSYNC to the DSP. In daisy-chain mode,
the polarity of the ring signal can be controlled by bit 1
(RPOL). When RPOL = 1, the ring detect signal (now
output on the FC/RGDT pin) is active high.
15
10
LCS
BIT
5
0
The Si3035 supports a variety of codecs (e.g., Si3000)
as well as additional Si3035s. The type of slave codec(s)
used is set by bits 4:3 (SSEL1:SSEL0). These bits
determine the type of signalling used in the LSB of SDO.
This assists the DSP in isolating which data stream is
the master and which is the slave. If the LSB is used for
0
6
12 18 24 30 36 42 48 54 60 66 72 78 84 90 96
Loop Current (mA)
155
Figure 24. Typical LCS Transfer Function
Rev. 1.2
25
Si3035
signalling, the master device will have a unique setting Register 13 must be 0.
relative to the slave devices. The DSP can use this
The receive path can support gains of 0, 3, 6, 9, and
information to determine which FSYNC marks the
beginning of a sequence of data transfers.
12 dB. The gain is selected by bits 2:0 (ARX2:ARX0).
The receive path can also be muted by setting bit 3
(RXM). The transmit path can support attenuations of 0,
3, 6, 9, and 12 dB. The attenuation is selected by bits
6:4 (ATX2:ATX0). The transmit path can also be muted
by setting bit 7 (TXM).
The delayed frame sync (FSD) of each device is
supplied as the FSYNC of each subsequent slave
device in the daisy chain. The master Si3035 will
generate an FSYNC signal for each device every 16 or
32 SCLK periods. The delay period is set by Register 14,
bit 2 (FSD). Figures 26–29 show the relative timing for
daisy chaining operation. Primary communication
frames occur in sequence, followed by secondary
Filter Selection
The Si3035 supports additional filter selections for the
receive and transmit signals. When set, the IIRE bit of
Register 16 enables the IIR filters defined in Table 12 on
page 11. This filter provides a much lower, however
non-linear, group delay than the default FIR filters.
communication
frames,
if
requested.
When
writing/reading the master device via a secondary frame,
all secondary frames of the slave devices must be
written as well. When writing/reading a slave device via
a secondary frame, the secondary frames of the master
and all other slaves must be written as well. "No
operation" writes/reads to secondary frames are
accomplished by writing/reading a zero value to address
zero.
If FSD is set for 16 SCLK periods between FSYNCs,
only serial mode 1 can be used. In addition, the slave
devices must delay the tri-state to active transition of
their SDO sufficiently from the rising edge of SCLK to
avoid bus contention.
The Si3035 supports the operation of up to eight Si3035
devices on a single serial bus. The master Si3035 must
be configured in serial mode 1. The slave(s) Si3035 is
configured in serial mode 2. Figure 30 shows a typical
master/slave connection using three Si3035 devices.
When in serial mode 2, FSYNC becomes an input,
RGDT/FSD becomes the delay frame sync output, and
FC/RGDT becomes the ring detection output. In
addition, the internal PLLs are fixed to a multiply by 20.
This provides the desired sample rate when the master’s
SCLK is provided to the slave’s MCLK. The SCLK of the
slave is a no connect in this configuration. The delay
between FSYNC input and delayed frame sync output
(RGDT/FSD) will be 16 SCLK periods. The RGDT/FSD
output has a waveform identical to the FSYNC signal in
serial mode 0. In addition, the LSB of SDO is set to zero
by default for all devices in serial mode 2.
Gain Control
The Si3035 supports multiple gain and attenuation
settings for the receive and transmit paths, respectively,
via Register 13. When the ARX bit is set, 6 dB of gain is
applied to the receive path. When the ATX bit is set,
–3 dB of gain is applied to the transmit path.
Register 15 can be used to provide additional gain
control. For Register 15 to have an effect on the receive
and transmit paths, the ATX and ARX bits of
26
Rev. 1.2
Si3035
MCLK
DSP
Si3021
MCLK
SCLK
SCLK
SDI
SDO
SDI
SDO
FSYNC
FSYNC
INT0
FC/RGDT
VCC
RGDT/FSD
M0
M1
+5 V
47 kΩ
47 kΩ
47 kΩ
Si3000
SCLK
MCLK
FSYNC
SDI
SDO
Voice
Codec
Figure 25. Typical Connection for Master/Slave Operation (e.g., Data/Fax/Voice Modem)
Rev. 1.2
27
Si3035
Master
Slave 1
Serial Mode 1
Reg 14: NSLV = 1, SSEL = 2, FSD = 0, DCE = 1
Serial Mode 2
Reg 14 Reset values: NSLV = 1, SSEL = 3, FSD = 1, DCE = 1
Primary Frame (Data)
Secondary Frame (Control)
128 SCLKs
128 SCLKs
Master FSYNC
32 SCLKs
32 SCLKs
Master FSD/
Slave1 FSYNC
SDI [0]
SDI [15..1]
1
1
Master
Master
Slave1
Slave1
Master
Slave1
SDO [0]
SDO[15..1]
1
0
Master
Master
Slave1
Slave1
Master
Slave1
Comments
Primary frames with secondary frame requested via SDI[0] = 1
Figure 26. Daisy Chaining of a Single Slave (Pulse FSD)
Master
Slave 1
Serial Mode 1
Reg 14: NSLV = 1, SSEL = 2, FSD = 1, DCE = 1
Serial Mode 2
Reg 14 Reset values: NSLV = 1, SSEL = 3, FSD = 1, DCE = 1
Primary Frame (Data)
Secondary Frame (Control)
128 SCLKs
128 SCLKs
Master FSYNC
Master FSD/
Slave1 FSYNC
16 SCLKs
16 SCLKs
16 SCLKs
16 SCLKs
SDI [0]
SDI [15..1]
1
1
Master
Master
Slave1
Slave1
Master
Slave1
SDO [0]
SDO[15..1]
1
0
Master
Master
Slave1
Slave1
Master
Slave1
Comments
Primary frames with secondary frame requested via SDI[0] = 1
Figure 27. Daisy Chaining of a Single Slave (Frame FSD)
28
Rev. 1.2
Master
Slave 1
Serial Mode 1
Reg 14: NSLV = 7, SSEL = 2, FSD = 1, DCE = 1
Serial Mode 2
Reg 14 Reset values: NSLV = 1, SSEL = 3, FSD = 1, DCE = 1
Primary Frame (Data)
Secondary Frame (Control)
128 SCLKs
128 SCLKs
Master
FSYNC
16 SCLKs
Master FSD/
Slave1 FSYNC
Slave1 FSD/
Slave2 FSYNC
Slave2 FSD/
Slave3 FSYNC
Slave3 FSD/
Slave4 FSYNC
Slave4 FSD/
Slave5 FSYNC
Slave5 FSD/
Slave6 FSYNC
Slave6 FSD/
Slave7 FSYNC
SDI [0]
SDI [15..1]
1
1
1
1
1
1
1
1
Master
Master
Slave1
Slave1
Slave2
Slave2
Slave3
Slave3
Slave4
Slave4
Slave5
Slave5
Slave6
Slave6
Slave7
Slave7
Master
Slave1
Slave2
Slave3
Slave4
Slave5
Slave6
Slave7
SDO [0]
SDO[15..1]
1
0
0
0
0
0
0
0
Master
Master
Slave1
Slave1
Slave2
Slave2
Slave3
Slave3
Slave4
Slave4
Slave5
Slave5
Slave6
Slave6
Slave7
Slave7
Master
Slave1
Slave2
Slave3
Slave4
Slave5
Slave6
Slave7
Comments
Primary frames with secondary frame requested via SDI[0] = 1
Figure 28. Daisy Chaining of Eight DAAs
Si3035
Master
Slave 1
Serial Mode 0
Reg 14: NSLV = 1, SSEL = 2, FSD = 0, DCE = 1
Serial Mode 2
Reg 14 Reset values: NSLV = 1, SSEL = 3, FSD = 1, DCE = 1
Primary Frame (Data)
Secondary Frame (Control)
128 SCLKs
128 SCLKs
16 SCLKs
Master FSYNC
Master FSD/
Slave1 FSYNC
SDI [0]
SDI [15..1]
1
1
Master
Master
Slave1
Slave1
Master
Slave1
1
0
Master
Master
Slave1
Slave1
SDO [0]
SDO [15..1]
Master
Slave1
Comments
Primary frames with secondary frame requested via SDI[0] = 1
Figure 29. Daisy Chaining with Framed FSYNC and Framed FSD
30
Rev. 1.2
Si3035
MCLK
DSP
Si3021–Master
MCLK
SCLK
SDI
SCLK
SDO
SDI
SDO
FSYNC
FSYNC
INT0
FC/RGDT
RGDT/FSD
VCC
M1
M0
47 kΩ
47 kΩ
Si3021–Slave 1
MCLK
SCLK
FSYNC
SDI
SDO
RGDT/FSD
VCC
M1
M0
Si3021–Slave 2
MCLK
SCLK
FSYNC
SDI
SDO
RGDT/FSD
VCC
M1
M0
Figure 30. Typical Connection for Multiple Si3035s
Rev. 1.2
31
Si3035
can be used, the test circuit in Figure 1 on page 4 is
adequate. In addition, an off-hook sequence must be
performed to connect the power source to the line-side
chip.
Revision Identification
The Si3035 provides the system designer the ability to
determine the revision of the Si3021 and/or the Si3012.
Register 11 identifies the revision of the Si3021 with 4
bits named REVA. Register 13 identifies the revision of
the Si3012 with 4 bits named REVB. Table 19 shows
the values for the various revisions.
For the start-up test mode, no line-side power is
necessary and no off-hook sequence is required. The
start-up test mode is enabled by default. When the PDL
bit (Register 6, bit 4) is set (the default case), the line
side is in a power-down mode and the DSP-side is in a
digital loop-back mode. In this mode, data received on
SDI is passed through the internal filters and
transmitted on SDO. This path will introduce
approximately 0.9 dB of attenuation on the SDI signal
received. The group delay of both transmit and receive
filters will exist between SDI and SDO. Clearing the
PDL bit disables this mode and the SDO data is
switched to the receive data from the line side. When
the PDL bit is cleared the FDT bit (Register 12, bit 6) will
Table 19. Revision Values
Revision
Si3021
1000
1001
1010
—
Si3012
—
A
B
C
D
E
G
—
—
0100
0101
0111
become
active,
indicating
the
successful
—
communication between the line-side and DSP-side.
This can be used to verify that the ISOcap link is
operational.
—
The remaining test modes require an off-hook sequence
to operate. The following sequence defines the off-hook
Calibration
The Si3035 initiates an auto-calibration by default requirement:
whenever the device goes off-hook or experiences a
loss in line power. Calibration is used to remove any
offsets that may be present in the on-chip A/D converter
which could affect the A/D dynamic range.
Auto-calibration is typically initiated after the DAA DC
termination stabilizes and takes 512/Fs seconds to
complete. Due to the large variation in line conditions
and line card behavior that may be presented to the
DAA, it can be beneficial to use manual calibration in
lieu of auto-calibration. Manual calibration should be
executed as close as possible to 512/Fs seconds before
valid transmit/receive data is expected.
1. Power up or reset.
2. Program clock generator to desired sample rate.
3. Enable line-side by clearing PDL bit.
4. Issue off-hook
5. Delay 1548/Fs to allow calibration to occur.
6. Set desired test mode.
The ISOcap digital loopback mode allows the data
pump to provide a digital input test pattern on SDI and
receive that digital test pattern back on SDO. To enable
this mode, set the DL bit of Register 1. In this mode, the
isolation barrier is actually being tested. The digital
The following steps should be taken to implement stream is delivered across the isolation capacitor, C1 of
manual calibration:
Figure 16 on page 15, to the line-side device and
returned across the same barrier. In this mode, the
0.9 dB attenuation and filter group delays also exist.
1. The CALD (auto-calibration disable—Register 17) bit must
be set to 1.
The analog loopback mode allows an external device to
drive the RX pin of the line-side chip and receive the
signal from the TX pin. This mode allows testing of
external components connecting the RJ-11 jack (TIP
and RING) to the line side of the Si3035. To enable this
mode, set the AL bit of Register 2.
2. The MCAL (manual calibration) bit must be toggled to 1
and then 0 to begin and complete the calibration.
3. The calibration will be completed in 512/Fs seconds.
In-Circuit Testing
The Si3035’s advanced design provides the modem
manufacturer with an increased ability to determine
system functionality during production line tests, as well
as support for end-user diagnostics. Four loopback
modes exist allowing increased coverage of system
components. For three of the test modes, a line-side
power source is needed. While a standard phone line
The final testing mode, internal analog loopback, allows
the system to test the basic operation of the
transmit/receive path of the line side and the external
components R4, R18, R21, and C5 of Figure 16 on
page 15. In this test mode, the data pump provides a
32
Rev. 1.2
Si3035
digital test waveform on SDI. This data is passed across chip must be reset. This is accomplished by setting the
the isolation barrier, looped from the TX to the RX pin, PDL bit for at least 1 ms.
passed back across the isolation barrier, and presented
to the data pump on SDO. To enable this mode, clear
bit (Register 12, bit 7). The CLE bit indicates a time-out
the HBE bit of Register 2.
Another useful bit is the communication link error (CLE)
error for the ISOcap link following a change to either
Clearing the HBE bit will cause a DC offset which PLL1 or PLL2. For more information, see “Clock
affects the signal swing of the transmit signal. In this test Generation Subsystem” on page 20. When the CLE bit
mode, it is recommended that the transmit signal be is set, the DSP-side chip has failed to receive
12 dB lower than normal transmit levels. This lower verification from the line side that the clock change has
level will eliminate clipping caused by the DC offset been accepted in an expected period of time (less than
which results from disabling the hybrid. It is assumed in 10 ms). This condition indicates a severe error in
this test that the line AC impedance is nominally 600 Ω. programming the clock generator or possibly a defective
line-side chip.
Note: All test modes are mutually exclusive. If more than one
test mode is enabled concurrently, the results are
unpredictable.
Exception Handling
The Si3035 provides several mechanisms to determine
if an error occurs during operation. Through the
secondary frames of the serial link, the controlling DSP
can read several status bits. The bit of highest
importance is the frame detect bit (FDT, Register 12,
bit 6). This bit indicates that the DSP-side (Si3021) and
line-side (Si3012) devices are communicating. During
normal operation, the FDT bit can be checked before
reading any bits that indicate information about the line
side. If FDT is not set, the following bits related to the
line-side are invalid: RDT, LCS, CBID, and REVB. The
RGDT operation will also be non-functional.
Following power-up and reset, the FDT bit is not set
because the PDL bit (Register 6, bit 4) defaults to 1. In
this state, the ISOcap link is not operating and no
information about the line-side can be determined. The
user must program the clock generator to a valid
configuration for the system and clear the PDL bit to
activate the ISOcap link. While the Si3021 and Si3012
are establishing communication, the Si3035 will not
generate FSYNC signals. Establishing communication
will take less than 10 ms. Therefore, if the controlling
DSP serial interface is interrupt driven, based on the
FSYNC signal, the controlling DSP does not require a
special delay loop to wait for this event to complete.
The FDT bit can also indicate if the line-side executes
an off-hook request successfully. If the line-side is not
connected to a phone line (i.e., the user fails to connect
a phone line to the modem), the FDT bit remains
cleared. The controlling DSP must allow sufficient time
for the line-side to execute the off-hook request. The
maximum time for FDT to be valid following an off-hook
request is 10 ms. At this time, the LCS bits indicate the
amount of loop current flowing. For more information,
see “Loop Current Monitor” on page 25. If the FDT bit
fails to be set following an off-hook request, the line-side
Rev. 1.2
33
Si3035
Control Registers
Any register not listed here is reserved and should not be written.
Table 20. Register Summary
Register Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
DL
Bit 0
SB
1
2
3
4
5
6
7
8
Control 1
SR
Control 2
AL
HBE
RXE
Control 3
Control 4
DAA Control 1
DAA Control 2
PLL1 Divide N1
OPOL
PDL
ONHM
PDN
RDT
OHE
OH
CPE
ATM1
ARM1
ATM0
ARM0
N1[7:0]
PLL1 Multiply
M1
M1[7:0]
9
PLL2 Div./Mult.
N2/M2
N2[3:0]
M2[3:0]
10
11
12
13
PLL Control
CGM
Chip Revision
Line Side Status
REVA[3:0]
LCS[3:0]
CLE
FDT
Transmit and
Receive Gain
CBID
REVB[3:0]
ARX
ATX
DCE
ARX0
0
14
15
Daisy-Chain
Control
NSLV2
TXM
NSLV1
ATX2
NSLV0
ATX1
SSEL1
SSEL0
RXM
1
FSD
ARX2
0
RPOL
ARX1
0
TX/RX Gain
Control
ATX0
IIRE
16
17
IIR Filter Control
Calibration
0
0
0
0
MCAL
CALD
34
Rev. 1.2
Si3035
Register 1. Control 1
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name SR
Type R/W
DL
SB
R/W R/W
Reset settings = 0000_0000
Bit
Name
Function
7
SR
Software Reset.
0 = Enables chip for normal operation.
1 = Sets all registers to their reset value.
6:2
1
Reserved Read returns zero.
DL
Isolation Digital Loopback.
0 = Disables digital loopback mode across the isolation barrier.
1 = Enables digital loopback mode across the isolation barrier.
0
SB
Serial Digital Interface Mode.
0 = Operation is in 15-bit mode and the LSB of the data field indicates whether a secondary
frame is required.
1 = The serial port is operating in 16-bit mode and requires use of the secondary frame sync
signal, FC/RGDT, to initiate control data reads/writes.
Register 2. Control 2
Bit
D7
D6
D5
D4
D3
AL
D2
D1
D0
Name
Type
HBE RXE
R/W R/W
R/W
Reset settings = 0000_0011
Bit
7:4
3
Name
Reserved Read returns zero.
AL Analog Loopback.
Function
0 = Disables analog loopback mode.
1 = Enables analog loopback mode.
2
1
Reserved Read returns zero.
HBE
Hybrid Enable.
0 = Disconnects hybrid in transmit path.
1 = Connects hybrid in transmit path.
0
RXE
Receive Enable.
0 = Disables receive path.
1 = Enables receive path.
Rev. 1.2
35
Si3035
Register 3. Control 3
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
Reset settings = 0000_0000
Bit
Name
Reserved Read returns zero.
Function
7:0
Register 4. Control 4
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
Reset settings = 0000_0000
Bit
Name
Reserved Read returns zero.
Function
7:0
36
Rev. 1.2
Si3035
Register 5. DAA Control 1
Bit
D7
D6
D5
D4
OPOL ONHM RDT
R/W R/W
D3
D2
D1
D0
OH
Name
Type
OHE
R/W
R
R/W
Reset settings = 0000_0000
Bit
7:5
4
Name
Reserved Read returns zero.
Function
OPOL
Off-Hook Polarity.
0 = Off-hook pin is active low.
1 = Off-hook pin is active high.
3
2
ONHM
On-Hook Line Monitor.
0 = Normal on-hook mode.
1 = Enables low-power monitoring mode allowing the DSP to receive line activity without
going off-hook. This mode is used for caller ID detection.
RDT
Ring Detect.
0 = No ring is occurring. Reset either 4.5–9 seconds after last positive ring is detected or
when the system executes an off-hook.
1 = Indicates a ring is occurring.
1
0
OHE
OH
Off-Hook Pin Enable.
0 = Off-hook pin is ignored.
1 = Enables the operation of the off-hook pin.
Off-Hook.
0 = Line side chip is on-hook.
1 = Causes the line side chip to go off-hook. This bit operates independently of OHE and is a
logic OR with the off-hook pin when OHE = 1.
Rev. 1.2
37
Si3035
Register 6. DAA Control 2
Bit
Name CPE ATM1 ARM1 PDL PDN
Type R/W R/W R/W R/W R/W
Reset settings = 0111_0000
D7
D6
D5
D4
D3
D2
D1
ATM0 ARM0
R/W R/W
D0
Bit
Name
Function
7
CPE
Charge Pump Enable.
0 = Charge pump is disabled.
1 = Charge pump is enabled. (The VA pin should not be connected to a supply.
VD = 3.3 V ± 10%.)
6,1 ATM[1:0] AOUT Transmit Path Level Control.
00 = –20 dB transmit path attenuation for call progress AOUT pin only.
01 = –32 dB transmit path attenuation for call progress AOUT pin only.
10 = Mutes transmit path for call progress AOUT pin only.
11 = –26 dB transmit path attenuation for call progress AOUT pin only.
5,0 ARM[1:0] AOUT Receive Path Level Control.
00 = 0 dB receive path attenuation for call progress AOUT pin only.
01 = –12 dB receive path attenuation for call progress AOUT pin only.
10 = Mutes receive path for call progress AOUT pin only.
11 = –6 dB receive path attenuation for call progress AOUT pin only.
4
3
2
PDL
PDN
Power Down Line-Side Chip.
0 = Normal operation. Program the clock generator before clearing this bit.
1 = Places the Si3012 in power down or reset state.
Power Down.
0 = Normal operation.
1 = Powers down the Si3021. A pulse on RESET is required to restore normal operation.
Reserved Read returns zero.
Register 7. PLL1 Divide N1
Bit
D7
D6
D5
D4
N1[7:0]
R/W
D3
D2
D1
D0
Name
Type
Reset settings = 0000_0000 (serial mode 0, 1, 2)
Bit
Name
Function
7:0
N1[7:0]
N1 Divider.
Contains the (value – 1) for determining the output frequency on PLL1.
38
Rev. 1.2
Si3035
Register 8. PLL1 Multiply M1
Bit
D7
D6
D5
D4
M1[7:0]
R/W
D3
D2
D1
D0
Name
Type
Reset settings = 0000_0000 (serial mode 0, 1)
Reset settings = 0001_0011 (serial mode 2)
Bit
Name
Function
7:0
M1[7:0]
M1 Multiplier.
Contains the (value – 1) for determining the output frequency on PLL1
Register 9. PLL2 Divide/Multiply N2/M2
Bit
D7
D6
N2[3:0]
R/W
D5
D4
D3
D2
M2[3:0]
R/W
D1
D0
Name
Type
Reset settings = 0000_0000 (serial mode 0, 1, 2)
Bit
Name
Function
7:4
N2[3:0]
N2 Divider.
Contains the (value – 1) for determining the output frequency on PLL2.
3:0
M2[3:0]
M2 Multiplier.
Contains the (value – 1) for determining the output frequency on PLL2.
Register 10. PLL Control Register
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
CGM
R/W
Reset settings = 0000_0000
Bit
7:1
0
Name
Reserved Read returns zero.
CGM Clock Generation Mode.
0 = No additional ratio is applied to the PLL and faster lock times are possible.
Function
1 = A 25/16 ratio is applied to the PLL allowing for a more flexible choice of MCLK frequencies
while slowing down the PLL lock time.
Rev. 1.2
39
Si3035
Register 11. Chip Revision
Bit
D7
D6
D5
D4
D3
D2
REVA
R[3:0]
D1
D0
Name
Type
Reset settings = N/A
Bit
7:4
3:0
Name
Reserved
REVA[3:0]
Function
Read returns zero.
Chip Revision.
Four-bit value indicating the revision of the Si3021 (DSP-side) chip.
Register 12. Line Side Status
Bit
Name CLE FDT
Type R/W
Reset settings = N/A
D7
D6
D5
D4
D3
D2
D1
D0
LCS[3:0]
R
R
Bit
Name
Function
7
CLE
Communications (ISOcap Link) Error.
0 = ISOcap communication link between the Si3021 and the Si3012 is operating correctly.
1 = Indicates a communication problem between the Si3021 and the Si3012. A write of 0 or a
reset is required to clear this bit.
6
FDT
Frame Detect.
0 = Indicates ISOcap link has not established frame lock.
1 = Indicates ISOcap link frame lock has been established.
5:4
3:0
Reserved Read returns zero.
LCS[3:0] Loop Current Sense.
Four-bit value returning the loop current in 6 mA increments.
0 = Loop current < 0.4 mA typical.
1111 = Loop current > 155 mA typical.
See “Loop Current Monitor” on page 25.
40
Rev. 1.2
Si3035
Register 13. Transmit and Receive Gain
Bit
D7
D6
CBID
R
D5
D4
D3
D2
D1
D0
Name
Type
REVB[3:0]
R
ARX ATX
R/W R/W
Reset settings = 0000_0000
Bit
7
Name
Reserved Read returns zero.
CBID Chip B ID.
Function
6
0 = Indicates the line side is domestic only.
1 = Indicates the line side has international support.
5:2 REVB[3:0] Chip Revision.
Four-bit value indicating the revision of the Si3012 (line-side) chip.
Receive Gain.
1
ARX
0 = 0 dB gain is applied to the receive path.
1 = 6 dB gain is applied to the receive path.
Note: This bit should be zero if using Register 15 to control gain.
0
ATX
Transmit Gain.
0 = 0 dB gain is applied to the receive path.
1 = –3 dB gain (attenuation) is applied to the transmit path.
Note: This bit should be 0 if using Register 15 to control gain.
Rev. 1.2
41
Si3035
Register 14. Daisy-Chain Control
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name NSLV2 NSLV1 NSLV0 SSEL1 SSEL0 FSD RPOL DCE
Type
R/W
R/W
R/W
R/W
R/W
R/W R/W R/W
Reset settings = 0000_0010 (serial mode 0, 1)
Reset settings = 0011_1111 (serial mode 2)
Bit
Name
Function
7:5 NSLV[2:0] Number of Slave Devices.
000 = 0 slaves. Simply redefines the FC/RGDT and RGDT/FSD pins.
001 = 1 slave device.
010 = 2 slave devices.
011 = 3 slave devices.
100 = 4 slave devices. (For four or more slave devices, the FSD bit MUST be set.)
101 = 5 slave devices.
110 = 6 slave devices.
111 = 7 slave devices.
4:3 SSEL[1:0] Slave Device Select.
00 = 16-bit SDO receive data.
01 = Reserved.
10 = 15-bit SDO receive data. LSB = 1 for the Si3035 device.
11 = 15-bit SDO receive data. LSB = 0 for the Si3035 device.
2
FSD
Delayed Frame Sync Control.
0 = Sets the number of SCLK periods between frame syncs to 32.
1 = Sets the number of SCLK periods between frame syncs to 16. This bit MUST be set when
Si3035 devices are slaves. For the master Si3035, only serial mode 1 is allowed in this case.
1
0
RPOL
DCE
Ring Detect Polarity.
0 = The FC/RGDT pin (operating as ring detect) is active low.
1 = The FC/RGDT pin (operating as ring detect) is active high.
Daisy-Chain Enable.
0 = Daisy chaining disabled.
1 = Enables the Si3035 to operate with slave devices on the same serial bus. The FC/RGDT
signal (pin 7) becomes the ring detect output and the RDGT/FSD signal (pin 15) becomes the
delayed frame sync signal. Note that ALL other bits in this register are ignored if DCE = 0.
42
Rev. 1.2
Si3035
Register 15.TX/RX Gain Control
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
TXM
R/W
ATX2
R/W
ATX1
R/W
ATX0
R/W
RXM
R/W
ARX2 ARX1 ARX0
R/W
R/W
R/W
Reset settings = 0000_0000
Bit
Name
Function
7
TXM
Transmit Mute.
0 = Transmit signal is not muted.
1 = Mutes the transmit signal.
6:4
ATX[2:0] Analog Transmit Attenuation.
000 = 0 dB attenuation.
001 = 3 dB attenuation.
010 = 6 dB attenuation.
011 = 9 dB attenuation.
1xx = 12 dB attenuation.
Note: Register 13 ATX bit must be 0 if these bits are used.
3
RXM
Receive Mute.
0 = Receive signal is not muted.
1 = Mutes the receive signal.
2:0
ARX[2:0] Analog Receive Gain.
000 = 0 dB gain.
001 = 3 dB gain.
010 = 6 dB gain.
011 = 9 dB gain
1xx = 12 dB gain.
Note: Register 13 ARX bit must be 0 if these bits are used.
Rev. 1.2
43
Si3035
Register 16. IIR Filter Control
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
0
0
0
IIRE
1
0
0
0
R/W R/W R/W R/W R/W R/W R/W R/W
Reset settings = 0000_1000
Bit
7:5
4
Name
Function
Reserved Read returns zero (must always be written with zeroes).
IIRE
IIR Filter Enable.
0 = FIR filter enabled.
1 = Transmit and receive filters are realized with an IIR filter characteristic. To enable IIR filter
write 0x18; to disable IIR filter write 0x08. See Table 12 on page 11 for more details on IIR fil-
ter performance.
3:0
Reserved Read returns 0x8 (must always be written with 0x8).
Register 17. International Control
Bit
D7
D6
MCAL CALD
R/W R/W
D5
D4
D3
D2
D1
D0
Name
Type
0
Reset settings = 0000_0000
Bit
7
Name
Function
Reserved Must be zero.
6
MCAL
CALD
Manual Calibration.
0 = No calibration.
1 = Initiate calibration.
5
Auto-Calibration.
0 = Auto-calibration enabled.
1 = Auto-calibration disabled.
4:0
Reserved Read returns zero.
44
Rev. 1.2
Si3035
APPENDIX—UL1950 3RD EDITION
Although designs using the Si3035 comply with UL1950 The bottom schematic of Figure 31 shows the
3rd Edition and pass all overcurrent and overvoltage configuration in which the ferrite beads (FB1, FB2) are
tests, there are still several issues to consider.
on the protected side of the sidactor (RV1). For this
design, the ferrite beads can be rated at 200 mA.
Figure 31 shows two designs that can pass the UL1950
overvoltage tests, as well as electromagnetic In a cost optimized design, it is important to remember
emissions. The top schematic of Figure 31 shows the that compliance to UL1950 does not always require
configuration in which the ferrite beads (FB1, FB2) are overvoltage tests. It is best to plan ahead and know
on the unprotected side of the sidactor (RV1). For this which overvoltage tests will apply to your system.
configuration, the current rating of the ferrite beads System-level elements in the construction, such as fire
needs to be 6 A. However, the higher current ferrite enclosure and spacing requirements, need to be
beads are less effective in reducing electromagnetic considered during the design stages. Consult with your
emissions.
professional testing agency during the design of the
product to determine which tests apply to your system.
C24
75 Ω @ 100 MHz, 6 A
1.25 A
FB1
TIP
RV1
75 Ω @ 100 MHz, 6 A
FB2
RING
C25
C24
600 Ω @ 100 MHz, 200 mA
FB1
1.25 A
TIP
RV1
FB2
RING
600 Ω @ 100 MHz, 200 mA
C25
Figure 31. Circuits that Pass all UL1950 Overvoltage Tests
Rev. 1.2
45
Si3035
Pin Descriptions: Si3021
Si3021 (SOIC)
Si3021 (TSSOP)
MCLK
FSYNC
SCLK
OFHK
RGDT/FSD
M0
1
1
2
3
4
5
6
7
8
SDO
SDI
VD
16
16
15
14
13
12
11
10
9
2
SCLK
FSYNC
MCLK
OFHK
RGDT/FSD
M0
15
FC/RGDT
RESET
AOUT
M1
3
4
5
6
7
8
14
13
12
11
10
9
VD
VA
SDO
GND
C1A
SDI
FC/RGDT
RESET
M1
C1A
AOUT
GND
VA
Table 21. Si3021 Pin Descriptions
Description
SOIC TSSOP
Pin Name
Pin #
Pin #
1
13
MCLK
Master Clock Input.
High speed master clock input. Generally supplied by the system crystal
clock or modem/DSP.
2
14
FSYNC
Frame Sync Output.
Data framing signal that is used to indicate the start and stop of a
communication/data frame.
3
4
15
16
SCLK
VD
Serial Port Bit Clock Output.
Controls the serial data on SDO and latches the data on SDI.
Digital Supply Voltage.
Provides the digital supply voltage to the Si3021, nominally either 5 V or
3.3 V.
5
6
1
2
SDO
SDI
Serial Port Data Output.
Serial communication data that is provided by the Si3021 to the modem/DSP.
Serial Port Data Input.
Serial communication and control data that is generated by the modem/DSP
and presented as an input to the Si3021.
7
3
FC/RGDT
Secondary Transfer Request Input/Ring Detect Output.
An optional signal to instruct the Si3021 that control data is being requested
in a secondary frame. When daisy chain is enabled, this pin becomes the
ring detect output. Produces an active low rectified version of the ring signal.
8
9
4
5
RESET
AOUT
Reset Input.
An active low input that is used to reset all control registers to a defined, ini-
tialized state. Also used to bring the Si3034 out of sleep mode.
Analog Speaker Output.
Provides an analog output signal for driving a call progress speaker.
46
Rev. 1.2
Si3035
Table 21. Si3021 Pin Descriptions (Continued)
Pin Name Description
SOIC TSSOP
Pin #
Pin #
10
6
M1
Mode Select 1 Input.
The second of two mode select pins that is used to select the operation of the
serial port/DSP interface.
11
7
C1A
Isolation Capacitor 1A.
Connects to one side of the isolation capacitor C1. Used to communicated
with the line-side device.
12
13
8
9
GND
VA
Ground.
Connects to the system digital ground.
Analog Supply Voltage.
Provides the analog supply voltage for the Si3021, nominally 5 V. This supply
is typically generated internally with an on-chip charge pump set through a
control register.
14
15
10
11
M0
Mode Select 0 Input.
The first of two mode select pins that is used to select the operation of the
serial port/DSP interface.
RGDT/FSD
Ring Detect/Delayed Frame Sync Output.
Output signal that indicates the status of a ring signal. Produces an active
low rectified version of the ring signal. When daisy chain is enabled, this sig-
nal becomes a delayed frame sync to drive a slave device.
16
12
OFHK
Off-Hook Input.
An active low input control signal that provides a termination across TIP and
RING for line seizing and pulse dialing.
Rev. 1.2
47
Si3035
Pin Descriptions: Si3012
Si3012 (SOIC or TSSOP)
TSTA
TSTB
IGND
C1B
TX
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
NC
RX
REXT
DCT
HYBD
VREG2
VREG
RNG1
RNG2
QB
QE
Table 22. Si3012 Pin Descriptions
Description
(SOIC or
TSSOP)
Pin #
Pin Name
Test Input A.
1
TSTA
Allows access to test modes which are reserved for factory use. This pin has an
internal pull-up and should be left as a no connect for normal operation.
Test Input B.
2
TSTB
Allows access to test modes which are reserved for factory use. This pin has an
internal pull-up and should be left as a no connect for normal operation.
Isolated Ground.
3
4
5
IGND
C1B
Connects to ground on the line-side interface.
Isolation Capacitor 1B.
Connects to one side of isolation capacitor C1.
Ring 1 Input.
RNG1
Connects through a capacitor to the TIP lead of the telephone line. Provides the ring
and caller ID signals to the Si3035.
Ring 2 Input.
6
RNG2
Connects through a capacitor to the RING lead of the telephone line. Provides the
ring and caller ID signals to the Si3035.
Transistor Base.
7
8
9
QB
QE
Connects to the base of the hookswitch transistor, Q3.
Transistor Emitter.
Connects to the emitter of the hookswitch transistor, Q3.
Voltage Regulator.
VREG
Connects to an external capacitor to provide bypassing for an internal voltage
regulator.
Voltage Regulator 2.
10
VREG2
Connects to an external capacitor to provide bypassing for an internal voltage
regulator.
48
Rev. 1.2
Si3035
Table 22. Si3012 Pin Descriptions (Continued)
(SOIC or
TSSOP)
Pin #
Pin Name
HYBD
DCT
Description
Hybrid Node Output.
11
12
13
14
Balancing capacitor connection used for JATE out-of-band noise support.
DC Termination.
Provides DC termination to the telephone network.
External Resistor.
REXT
RX
Connects to an external resistor.
Receive Input.
Serves as the receive-side input from the telephone network.
No Connect.
15
16
NC
TX
Transmit Output.
Provides the output through an AC termination impedance to the telephone network.
Rev. 1.2
49
Si3035
Ordering Guide
Table 23. Ordering Guide
Digital
(SOIC)
Line
(SOIC)
Digital
(TSSOP)
Line
(TSSOP)
Chipset
Region
Interface
Temperature
Si3034
Si3035
Si3036
Si3038
Si3044
Global
FCC/Japan
FCC/Japan
Global
DSP Serial I/F Si3021-KS Si3014-KS Si3021-KT Si3014-KT 0°C to 70°C
DSP Serial I/F Si3021-KS Si3012-KS Si3021-KT Si3012-KT 0°C to 70°C
AC Link
AC Link
Si3024-KS Si3012-KS Si3024-KT Si3012-KT 0°C to 70°C
Si3024-KS Si3014-KS Si3024-KT Si3014-KT 0°C to 70°C
Enhanced
Global
DSP Serial I/F Si3021-KS Si3015-KS
0°C to 70°C
Si3044
Enhanced
Global
DSP Serial I/F Si3021-BS Si3015-BS
–40°C to 85°C
Si3046
Si3048
FCC/JATE
Global
AC Link
AC Link
Si3025-KS Si3012-KS
Si3025-KS Si3014-KS
0°C to 70°C
0°C to 70°C
50
Rev. 1.2
Si3035
SOIC Outline
Figure 32 illustrates the package details for the Si3021 and Si3012. Table 24 lists the values for the dimensions
shown in the illustration.
Figure 32. 16-pin Small Outline Plastic Package (SOIC)
Table 24. Package Diagram Dimensions
Controlling Dimension: mm
Symbol
Inches
Millimeters
Min
Max
0.069
0.010
0.059
0.020
0.010
0.394
0.157
—
Min
1.35
Max
A
A1
A2
b
0.053
0.004
0.051
0.013
0.007
0.386
0.150
1.75
0.25
1.50
0.51
0.25
10.01
4.00
—
0.10
1.30
0.330
0.19
c
D
E
9.80
3.80
e
0.050 BSC
0.228
1.27 BSC
5.80
H
L
0.244
0.050
—
6.20
1.27
—
0.016
0.40
L1
γ
0.042 BSC
—
1.07 BSC
—
0.004
8°
0.10
8°
θ
0°
0°
Rev. 1.2
51
Si3035
TSSOP Outline
Figure 33 illustrates the package details for the Si3021 and Si3014. Table 25 lists the values for the dimensions
shown in the illustration.
θ 2
E1
E
S
R1
R
θ 1
L
e
L1
θ 3
D
c
A2
A
b
A1
Figure 33. 16-pin Thin Small Shrink Outline Package (TSSOP)
Table 25. Package Diagram Dimensions
Symbol
Millimeters
Nom
1.10
Min
—
Max
1.20
0.15
1.05
0.30
0.20
5.15
A
A1
A2
b
c
D
0.05
0.80
0.19
0.09
4.85
—
1.00
—
—
5.00
e
E
E1
L
0.65 BSC
6.40 BSC
4.40
4.30
0.45
4.50
0.75
0.60
L1
R
R1
S
θ1
θ2
θ3
1.00 REF
—
0.09
0.09
0.20
0
—
—
—
8
—
—
—
12 REF
12 REF
52
Rev. 1.2
Si3035
Data Sheet Changes from Version 1.0
to Version 1.1
! Typical Application Circuit was updated.
! C24, C25 value changed from 470 pF to 1000 pF
and C31, C32 were added in Table 13. The
tolerance was also changed from 20% to 10%.
! Power Supply Voltage, Analog maximum changed
from 4.75 V to 5.00 V in Table 4.
! Last paragraph updated in “Power Management”
text section.
Data Sheet Changes from Version 1.1
to Version 1.2
! TSSOP information added.
! Total supply currents updated in Table 3 and Table 4.
! Cycle time updated in Table 7.
! Delay times updated in Table 8, Table 9, and
Table 10.
! Figure 4 updated.
! Revision G values added in Table 19.
! Figure 16, “Typical Application Schematic,” on page
15 updated.
! Table 13, “Component Values—Typical Application,”
on page 16 (BOM) updated.
Rev. 1.2
53
Si3035
Contact Information
Silicon Laboratories Inc.
4635 Boston Lane
Austin, TX 78735
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Email: productinfo@silabs.com
Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep-
resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-
quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per-
sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap-
plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
Silicon Laboratories, Silicon Labs, and ISOcap are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
54
Rev. 1.2
相关型号：
©2020 ICPDF网 联系我们和版权申明