SI3011-KS_技术文档

Si3052

Si3017/11/18

GLOBAL PCI DAA CHIPSET

Features

! Si3052 PCI DAA and Si3018

! Watchdog timer

global, Si3011 TBR21, or Si3017 ! External EPROM interface

FCC line-side DAA

! 32-bit, 33 MHz, PCI 2.3 compliant

interface

! Compliant with FCC, TBR21,

JATE, and other PTTs

! 80 dB dynamic range TX/RX Path

! PPMI 1.1 and wake support with ! 2- to 4-wire Hybrid

PME and Vaux

! Patented ISOcap™ technology

! Bus master and target operation, ! >5000 V isolation

DMA controller

! Wake-on-ring and ring validation

Ordering Information

! 16 x 8 FIFO on DMA paths

! Interrupt controller

! Lowest cost external bill-of-

material (BOM)

! 3.3 V digital power supply

! 64-Pin TQFP, 0 to 70 °C

See page 97.

Pin Assignments

Applications

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

! V.92 soft data/fax modems

1

2

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

3

Description

4

5

6

The Si3052 is a system-side silicon direct access arrangement (DAA)

device that integrates a 32-bit, 33 MHz PCI bus interface. The Si3052 is

paired with the Si3018 global line-side device, Si3011 FCC/TBR21 line-

side device, or Si3017 FCC line-side device. The PCI DAA chipset is

compliant with global standards and includes a V.92 quality codec (80 dB

SNR, –75 dB THD), dc termination (50 Ω, current limiting), ac termination

(600 Ω, complex impedance), and an integrated hybrid.

Si3052

64-Lead TQFP

(epad)

7

8

9

10

11

12

13

14

15

16

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Functional Block Diagram

Si3017/11/18

Call Progress

Speaker

16

15

1

2

DCT2

QE

AOUT

IGND

DCT3

DCT

RX

TIP

Si3018

3

4

5

6

14

DAA Control

DAA

RING

IB

13

12

11

QB

QE2

SC

PCI

Addr/Data

C1B

C2B

VREG

RNG1

PCI

Interface

with

DMA Control

Interrupt Control

ID/ROM Interface

PCI

Control

VREG2

RNG2

7

8

10

9

FIFOs

EPROM

US Patent # 5,870,046

US Patent # 6,061,009

Patents pending

VD

Vaux

GND

Rev. 1.0 7/03

Si3052-DS10

Si3052/17/11/18

2

Rev. 1.0

Si3052/17/11/18

TABLE OF CONTENTS

Section

Page

Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

AOUT PWM Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

PCI Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

DMA Bus Master Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

DAA Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

FIFO Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Telephone Line Interface Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Isolation Barrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Parallel Handset Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Loop Current Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Off-Hook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

DC Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

AC Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Transhybrid Balance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Ring Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Ring Validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Ringer Impedance and Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

DTMF Dialing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Pulse Dialing and Spark Quenching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Billing Tone Detection and Receive Overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Billing Tone Filter (Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

On-Hook Line Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Caller ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Overload Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Sample Rate Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Filter Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

In-Circuit Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Revision Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

PCI and DAA Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Pin Descriptions: Si3052 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Pin Descriptions: Si3017/11/18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Package Outline: 64-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Package Outline: 16-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Rev. 1.0

3

Si3052/17/11/18

Electrical Specifications

Table 1. Recommended Operating Conditions

1

2

Symbol

Test Condition

Unit

°C

V

Parameter

Min

Typ

25

Max

70

Ambient Temperature

Si3052 Supply Voltage, Core

Si3052 IO Supply Voltage

Note:

T

K-Grade

0

A

VD

3.0

3.3

5.0

3.6

V

3.3 V Signaling

5 V Signaling

V

IO

4.75

5.25

V

1. The Si3052 specifications are guaranteed when the typical application circuit (including component tolerance) and

Si3052 and Si3017/11/18 are used. Refer to Figure 13 on page 16 for the typical application schematic.

2. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.

Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated.

4

Rev. 1.0

Si3052/17/11/18

1

Table 2. PCI Interface DC Characteristics for 5 V_IO

(V_IO= 4.75 to 5.25 V, T_A= 0 to 70 °C)

Parameter

Symbol

Test Condition

Min

—

Typ

20

12

1

Max

21

28

15

—

Unit

mA

V

2

Power Supply Current, Core

I

D0 uninitialized

D,VD

3

D0 initialized

—

4

D3 wake-on-ring

—

5

D3 deep sleep

—

2

Power Supply Current, IO

I

D0 uninitialized

—

0.35

—

52

47

—

D,VIO

3

D0 initialized

—

4,5

D3

—

High Level Input Voltage

Low Level Input Voltage

Input/Hi-Z Leakage Current

High Level Output Voltage

Low Level Output Voltage

Input Pin Capacitance

CLK Pin Capacitance

IDSEL Pin Capacitance

Pin Inductance

V

2.0

–0.5

—

V +0.5

IH

IO

V

I

—

0.8

±10

—

V

IL

0 < V < V

IO

—

µA

V

IL

IN

V

I = –2 mA

2.4

—

OH

O

6

V

I = 3 mA,6 mA

—

0.55

10

12

8

V

OL

O

C

—

pF

nH

µA

in

C

5

—

CLK

C

—

IDSEL

L

—

4

20

1

PME input leakage

I

0 < Vo ≤ 5.25 V,

—

OFF

7

V

off or floating

IO

Notes:

1. Applies to pins AD[31:0], CBE[3:0], FRAME, IRDY, TRDY, DEVSEL, STOP, PERR, SERR, PAR, INTA, PME, GNT,

REQ, CLK, RESET, and IDSEL.

2. The D0 uninitialized condition is defined as active PCI interface and idle line-side device. Max power numbers assume

constant PCI reads of worst case data using no output stepping. Typical power numbers assume no further PCI bus

reads (control bits PDN = 0, PDL = 1).

3. The D0 initialized condition is defined as conducting audio through the line-side device. Max power numbers assume

constant PCI reads of worst case data using no output stepping. Typical power numbers assume servicing DMA for

8 kHz audio sampling rate and two-stage output stepping (control bits PDN = 0, PDL = 0).

4. D3 condition is defined as inactive PCI bus. Wake-on-ring configuration assumes inactive PCI interface and active line-

side device (control bits PDN = 1, PDL = 0).

5. D3 condition is defined as inactive PCI bus. Deep Sleep configuration assumes inactive PCI interface and line-side

device (control bits PDN = 1, PDL = 1).

6. Signals without pullups have 3 mA low output current. Signals requiring pullups have 6 mA; the latter include FRAME,

RDY, TRDY, DEVSEL, STOP, SERR, PERR, INTA.

7. This input leakage is the maximum leakage into the PME open drain driver when power is removed from V , assuming

IO

that no event has occurred to cause the device to assert PME.

Rev. 1.0

5

Si3052/17/11/18

1

Table 3. PCI Interface DC Characteristics for 3.3 V_IO

(V_IO= 3.0 to 3.6 V, T_A= 0 to 70 °C)

Parameter

Symbol

Test Condition

Min

—

Typ

20

12

1

Max

21

28

15

—

Unit

mA

V

2

Power Supply Current, Core

I

D0 unitialized

D,VD

3

D0 initialized

4

D3 wake-on-ring

5

D3 deep sleep

2

Power Supply Current, IO

I

D0 unitialized

0.35

—

36

35

—

D,VIO

3

D0 initialized

4,5

D3

High Level Input Voltage

Low Level Input Voltage

Input Leakage Current

High Level Output Voltage

Low Level Output Voltage

Input Pin Capacitance

CLK Pin Capacitance

IDSEL Pin Capacitance

Pin Inductance

V

0.5 V

V +0.5

IO

IH

IO

V

I

–0.5

—

0.3 V

V

IL

IO

0 < V < V

IO

—

±10

—

µA

V

IL

IN

V

I = –0.5 mA

0.9 V

—

OH

O

IO

V

I = 1.5 mA

—

0.1 V

10

12

8

V

OL

O

IO

C

—

pF

nH

µA

in

C

5

—

CLK

C

—

IDSEL

L

—

4

20

1

PME input leakage

I

0 < Vo ≤ 3.6,

—

OFF

6

V

off or floating

IO

Notes:

1. Applies to pins AD[31:0], CBE[3:0], FRAME, TRDY, DEVSEL, STOP, PERR, SERR, PAR, INTA, PME, GNT, REQ, CLK,

RESET, and IDSEL.

2. The D0 uninitialized condition is defined as active PCI interface and idle line-side device. Max power numbers assume

constant PCI reads of worst case data using no output stepping. Typical power numbers assume no further PCI bus

reads (control bits PDN = 0, PDL = 1).

3. The D0 initialized condition is defined as conducting audio through the lines-side device. Max power numbers assume

constant PCI reads of worst case data using no output stepping. Typical power numbers assume servicing DMA for

8 kHz audio sampling rate and 2-stage output stepping (control bits PDN = 0, PDL = 0).

4. D3 condition is defined as inactive PCI bus. Wake-on-ring configuration assumes inactive PCI interface and active line-

side device (control bits PDN = 1, PDL = 0).

5. D3 condition is defined as inactive PCI bus. Deep sleep configuration assumes inactive PCI interface and line-side

device (control bits PDN = 1, PDL = 1).

6. This input leakage is the maximum leakage into the PME open drain driver when power is removed from V_IO, assuming

that no event has occurred to cause the device to assert PME.

6

Rev. 1.0

Si3052/17/11/18

Table 4. DC Characteristics for Non-PCI pins¹

(VD = 3.0 to 3.6 V, T_A= 0 to 70 °C)

Parameter

Symbol

Test Condition

Min

2.0

—

Max

—

Unit

V

2

High Level Input Voltage

V

IH

2

Low Level Input Voltage

V

0.8

±10

—

V

IL

2

Input Leakage Current

I

0 < V < V

IO

—

µA

V

IL,1

IL,2

IN

3

Input Leakage Current

I

0 < V < V

—

IN

D

2

High Level Output Voltage

V

IO = –2 mA

IO = –7.5 mA

IO = 2 mA

2.4

2.0

—

OH

—

V

2

Low Level Output Voltage

V

0.35

0.8

10

V

OL

IO = 8 mA

—

V

Input Pin Capacitance

C

—

pF

in

Notes:

1. Applies to PIN_37, PIN_38, VAUX_SENSE, XIN, XOUT, C1A, C2A.

2. Applies to 5 V-tolerant 3.3 V pins PIN_37, PIN_38, and VAUX_SENSE.

3. Applies to 3.3 V pins XIN, XOUT, C1A, C2A.

Rev. 1.0

7

Si3052/17/11/18

1

Table 5. PCI Interface AC Characteristics for 5V_IO

(V_IO= 4.75 to 5.25 V, T_A= 0 to 70 °C)

Parameter

Symbol

Test Condition

Min

Max

—

Unit

mA

3

Switching Current,

I_OH(AC)

0 < V

< 1.4

–44

OUT

2

High

3

1.4 < V

3.1 < V

< 2.4

–44 + (V

– 1.4)/0.024

OUT

—

OUT

3

< V

—

11.9 x (V

-5.25) x

IO

OUT

(V

+2.45)

OUT

V

= 3.1

—

–142

mA

OUT

(Test Point)

3

Switching Current,

Low

I_OH(AC)

V

≥ 2.2

95

32

—

mA

OUT

V

= 1.375

OUT

3

2.2 > V

> 0.55

V

/0.023

OUT

3

0.71>V

>0

—

78.5 x V

x

OUT

(4.4 – V

)

OUT

V

= 0.71

—

206

mA

OUT

(Test Point)

Low Clamp Current

High Clamp Current

I_CL

-5<V <-1

–25 + (V +1)/0.015

—

mA

IN

I

V

+ 1 < V < V + 4

–25 + (V – V – 1)/

CH

IO

IN

IO

IN

IO

0.015

4

Output Rise Slew

Rate

slew

0.4 to 2.4 V

2.4 to 0.4 V

1

5

V/ns

R

4

Output Fall Slew

Rate

slew

F

1

Notes:

1. Applies to pins AD[31:0], CBE[3:0], FRAME, IRDY, TRDY, DEVSEL, STOP, PERR, SERR, PAR, INTA, PME, GNT, REQ,

and IDSEL.

2. Switching current High parameters do not apply to open-drain signals SERR, PME, and INTA.

3. Outputs are characterized to meet switching current templates. I_OHis tested at 1.4 V and 2.4 V only. I_OLis tested at 0.53 V

and 1.375 V only.

4. Cumulative edge rate across the specified range with load of 1 kΩ to V_IO, 1 kΩ to ground and 10 pF to ground.

8

Rev. 1.0

Si3052/17/11/18

1

Table 6. PCI Interface AC Characteristics for 3.3V_IO

(V_IO= 3.0 to 3.6 V, T_A= 0 to 70 °C)

Symbo

Parameter

Test Condition

Min

Max

Unit

l

3

Switching Current,

High²

I_OH(AC)

0 < V

< 0.3 V_IO

–12 V_IO

–17.1(V_IO– V

—

mA

—

OUT

3

0.3 V_IO< V

< 0.9 V_IO

)

OUT

3

0.7 V_IO< V

< V_IO

(98/V_IO) x (V

– V_I

OUT

_O) x (V

– 0.4 V_IO)

OUT

V

= 0.7 V_IO

–32 V_IO

mA

—

OUT

(Test Point)

3

Switching Current,

Low

I_OH(AC)

V_IO> V

0.6 > V

≥ 0.6V_IO

16 V_IO

mA

—

OUT

3

> 0.1V_IO

>0³

26.7 V_OUT

—

0.18 V_IO>V

(256/V_IO) x V

x

OUT

(V_IO– V

)

OUT

V

= 0.71

38xV_IO

mA

—

OUT

(Test Point)

Low Clamp Current

High Clamp Current

I_CL

I_CH

–3 < V ≤ 1

–25 + (V + 1)/0.015

mA

—

IN

V_IO+ 1 ≤ V_IN< V_IO+ 4

–25+(V – V_IO– 1)/

IN

0.015

4

Output Rise Slew

Rate

slew_R

slew_F

0.2 V_IOto 0.6 V_IO

1

4

V/ns

4

Output Fall Slew

Rate

0.6 V_IOto 0.2 V_IO

1

Notes:

1. Applies to pins AD[31:0], CBE[3:0], FRAME, IRDY, TRDY, DEVSEL, STOP, PERR, SERR, PAR, INTA, PME, GNT,

REQ, and IDSEL.

2. Switching current high parameters do not apply to open-drain signals SERR, PME, and INTA.

3. Outputs are characterized to meet switching current templates. Production testing is done at the designated Test Point

voltages only.

4. Cumulative edge rate across the specified range with load of 1 kΩ to V_IO, 1 kΩ to ground and 10 pF to ground.

Rev. 1.0

9

Si3052/17/11/18

Table 7. PCI Interface Timing Characteristics

(V_D= 3.0 to 3.6 V, V_IO= 3.0 to 5.25 V, T_A= 0 to 70 °C, see Figure 1)

Parameter

Symbol

Test Condition

Min

30

11

2

Typ

—

Max

—

Unit

ns

PCICLK Cycle Time

PCICLK High Time

PCICLK Low Time

PCICLK to Signal Valid Delay—

t

cyc

t

—

ns

high

t

—

ns

low

t

—

11

ns

val

1

Bused Signals

PCICLK to Signal Valid Delay—

t

2

—

12

ns

val(ptp)

1,3

Point to Point

2

Float to Active Delay

t

2

—

7

—

28

—

ns

on

2

Active to Float Delay

off

Input Setup Time to PCICLK—

Bused Signals

t

su

Input Setup Time to PCICLK—

Point to Point

t

10

—

ns

su(ptp)

3

Input Hold Time for PCICLK

Reset Active to Output Float Delay

Notes:

t

0

—

ns

h

2

t

—

30

rst-off

1. For 5 V signaling, T_valis evaluated with 50 pF load to ground. For 3.3 V signaling, T_valis evaluated with 25 Ω in parallel

with 10 pF to ground (rising) or 25 Ω to V_IOwith 10 pF to ground (falling).

2. For purposes of identifying float timing measurements, the Hi-Z or off state is defined to be when the total current is less

than or equal to the leakage current specification.

3. The point-to-point signals are REQ and GNT.

t_high

PCICLK

t_low

t_cyc

RESET

t_off

t_rst-off

t_on

OUTPUTS

Hi-Z

t_val

OUTPUTS

Valid

t_su

t_h

Valid

Input

INPUTS

Figure 1. PCI Timing

10

Rev. 1.0

Si3052/17/11/18

Table 8. DAA Loop Characteristics¹

(V_D= 3.0 to 3.6 V, T_A= 0 to 70 °C, see Figure 2)

Parameter

Symbol

Test Condition

I_L= 20 mA, ILIM = 0

Min

Typ

Max

Unit

DC Termination Voltage

V

—

6.0

V

TR

DCV = 00, MINI = 11, DCR = 0

I_L= 120 mA, ILIM = 0

DCV = 00, MINI = 11, DCR = 0

I_L= 20 mA, ILIM = 0

DCV = 11, MINI = 00, DCR = 0

I_L= 120 mA, ILIM = 0

DCV = 11, MINI = 00, DCR = 0

I_L= 20 mA, ILIM = 1

DCV = 11, MINI = 00, DCR = 0

I_L= 60 mA, ILIM = 1

DCV = 11, MINI = 00, DCR = 0

I_L= 50 mA, ILIM = 1

DCV = 11, MINI = 00, DCR = 0

I_L= 20 mA, ILIM = 0

DCV = 11, MINI = 00, DCR = 1

I_L= 60 mA, ILIM = 0

DC Termination Voltage

V

9

—

7.5

—

V

2

—

9

—

40

—

40

7.5

—

40

16

—

DCV = 11, MINI = 00, DCR = 1

V_TR= –48 V

2

On-Hook Leakage Current

I

—

10

—

5

120

60

3

µA

mA

µA

LK

LP

2

Operating Loop Current

MINI = 00, ILIM = 0

Operating Loop Current

MINI = 00, ILIM = 1

—

2

DC Ring Current

dc current flowing through ring

detection circuitry

1.5

2,3

Ring Detect Voltage

V

RT = 0

RT = 1

12

18

13

—

15

21

—

18

25

68

0.2

V

RD

rms

3

Ring Detect Voltage

rms

2

Ring Frequency

F

Hz

R

2

Ringer Equivalence Number

REN

Notes:

1. All parameters apply to Si3018 Global and Si3011 TBR21 line-side devices.

2. Parameter applies to Si3017 FCC line-side device.

3. The ring signal is guaranteed to not be detected below the minimum. The ring signal is guaranteed to be detected

above the maximum.

TIP

+

600 Ω

I_L

V

Si3017/11/18

TR

10 µF

–

RING

Figure 2. Test Circuit for Loop Characteristics

Rev. 1.0

11

Si3052/17/11/18

Table 9. DAA AC Characteristics¹

(V_D= 3.0 to 3.6 V, T_A= 0 to 70 °C, Fs = 8 kHz)

Parameter

2

Symbol

Fs

Test Condition

Min Typ Max

Unit

kHz

Hz

Sample Rate

7.2

—

5

16

—

2

Receive Frequency Response

Low –3 dBFS Corner

0 dBm

2,3

Transmit Full Scale Level

V

1.1

78

V

FS

PEAK

2,3,4

Receive Full Scale Level

V

0 dBm

VPEAK

2,5,6,7

Dynamic Range

DR

ILIM = 0, DCV = 11, MINI = 00

DCR = 0, IL = 100 mA

dB

5,6,8

Dynamic Range

DR

ILIM = 0, DCV = 00, MINI = 11

DCR = 0, IL = 20 mA

—

79

—

5,6,9

Dynamic Range

DR

ILIM = 1, DCV = 11, MINI = 00

DCR = 0, IL = 50 mA

78

7,8

Transmit Total Harmonic Distortion

THD

ILIM = 0, DCV = 11, MINI = 00

DCR = 0, IL = 100 mA

–72

–78

Transmit Total Harmonic

ILIM = 0, DCV = 00, MINI = 11

DCR = 0, IL = 20 mA

2,7,8

Distortion

7,8

Receive Total Harmonic Distortion

ILIM = 0, DCV = 00, MINI = 11

DCR = 0, IL = 20 mA

Receive Total Harmonic Distortion

ILIM = 1,DCV = 11, MINI = 00

DCR = 0, IL = 50 mA

2,7

Dynamic Range (caller ID mode)

DR

V

= 1 kHz, –13 dBm

IN

—

50

6

—

CID

2

Caller ID Full Scale Level

V

CID

V

PP

Notes:

1. All parameters apply to Si3018 Global and Si3011 TBR21 line-side devices.

2. Parameter applies to Si3017 FCC line-side device.

3. Measured at TIP and RING with 600 Ω. termination at 1 kHz, as shown in Figure 2.

4. Receive full scale level produces –0.9 dBFS.

5. DR = 20 x log (rms V_FS/rms V )+ 20 x log (rms V /rms noise). V_FSis the 0 dBm full-scale level.

IN

6. Measurement is 300 to 3400 Hz. Applies to both transmit and receive paths.

7. V_IN= 1 kHz, –3 dBFS

8. THD = 20 x log (rms distortion / rms signal).

9. DR_CID= 20 x log (rms V_CID/rms V_IN)+ 20 x log (rms V_IN/rms noise). V_CIDis the 6 V full-scale level.

12

Rev. 1.0

Si3052/17/11/18

Table 10. Digital FIR Filter Characteristics—Transmit and Receive

(V_D= 3.0 to 3.6 V, Sample Rate = 8 kHz, T_A= 0 to 70 °C)

Parameter

Symbol

Min

0

Typ

—

Max

3.3

3.6

0.1

—

Unit

kHz

dB

Passband (0.1 dB)

Passband (3 dB)

Passband Ripple Peak-to-Peak

Stopband

F

(0.1 dB)

F

0

—

(3 dB)

–0.1

—

4.4

—

kHz

dB

Stopband Attenuation

Group Delay

–74

—

t

12/Fs

—

s

gd

Note: Typical FIR filter characteristics for Fs = 8000 Hz are shown in Figures 3, 4, 5, and 6.

Table 11. Digital IIR Filter Characteristics—Transmit and Receive

(V_D= 3.0 to 3.6 V, Sample Rate = 8 kHz, T_A= 0 to 70 °C)

Parameter

Symbol

Min

0

Typ

—

Max

3.6

0.2

—

Unit

kHz

dB

Passband (3 dB)

Passband Ripple Peak-to-Peak

Stopband

F

(3 dB)

–0.2

—

4.4

kHz

dB

Stopband Attenuation

Group Delay

–40

—

t

1.6/Fs

—

s

gd

Note: Typical IIR filter characteristics for Fs = 8000 Hz are shown in Figures 7, 8, 9, and 10. Figures 11 and 12 show group

delay versus input frequency.

Rev. 1.0

13

Si3052/17/11/18

Input Frequency—Hz

Figure 3. FIR Receive Filter Response

Figure 5. FIR Transmit Filter Response

Input Frequency—Hz

Figure 4. FIR Receive Filter Passband Ripple

Figure 6. FIR Transmit Filter Passband Ripple

For Figures 3–6, all filter plots apply to a sample rate of

Fs = 8 kHz. The filters scale with the sample rate as follows:

F_{(0.1 dB)}= 0.4125 Fs

F_{(–3 dB)}= 0.45 Fs

where Fs is the sample frequency.

For Figures 7–10, all filter plots apply to a sample rate of

Fs = 8 kHz. The filters scale with the sample rate as follows:

F_{(–3 dB)}= 0.45 Fs

where Fs is the sample frequency.

14

Rev. 1.0

Si3052/17/11/18

Input Frequency—Hz

Figure 7. IIR Receive Filter Response

Figure 10. IIR Transmit Filter Passband Ripple

Input Frequency—Hz

Figure 11. IIR Receive Group Delay

Figure 8. IIR Receive Filter Passband Ripple

Input Frequency—Hz

Figure 12. IIR Transmit Group Delay

Figure 9. IIR Transmit Filter Response

Rev. 1.0

15

Si3052/17/11/18

Typical Application Schematic

16

Rev. 1.0

Si3052/17/11/18

Rev. 1.0

17

Si3052/17/11/18

Bill of Materials

Component(s)

Value

Supplier(s)

Panasonic, Murata, Vishay

Venkel, SMEC

C1, C2

C3

33pF, Y2, X7R, ±20%

10 nF, 250 V, X7R, ±20%

1.0 µF, 35 V, Elec/Tant, ±20%

0.1 µF, 16 V, X7R, ±20%

2.7 nF, 50 V, X7R, 20%

680 pF, Y2, X7R, ±10%

0.01 µF, 16 V, X7R, ±20%

C4

Panasonic

1

C5, C6, C50, C117

Venkel, SMEC

C7

Venkel, SMEC

C8, C9

Panasonic, Murata, Vishay

Venkel, SMEC

C10, C52-C53, C56–C57, C60,

C81, C84–C87, C103–C115,

1

C123–C125

C40–41

22 pF, 50 V, COG, ±5%

1.0 µF, 16 V, X7R, ±20%

1.0uF, 16V, X7R, ±20%

10 µF, 16 V, Elec, ±20%

0.047 µF, 16 V, X7R, ±20%

Venkel, SMEC

Panasonic

1

C51,C54,C55,C58,C59

1

C81-C82, C85-C86, C88

1

C80, C82, C88, C116

1

C83, C118, C119, C120, C121

Venkel, SMEC

Central Semiconductor

2

D1, D2

Dual Diode, 225 mA, 300 V,

CMPD2004S

FB1, FB2

Ferrite Bead, BLM21AJ601S

NPN, 300 V, MMBTA42

PNP, 300 V, MMBTA92

NPN, 80 V, 330 mW, MMBTA06

Sidactor, 275 V, 100 A

1.07 kΩ, 1/2 W, 1%

Murata

Q1, Q3

Fairchild, OnSemi, Central Semi

Teccor, Protek, ST Micro

Q2

Q4, Q5

RV1

R1

Venkel, SMEC, Panasonic

R2

150 Ω, 1/16 W, 5%

R3

3.65 kΩ, 1/2 W, 1%

R4

2.49 kΩ, 1/2 W, 1%

R5, R6

100 kΩ, 1/16 W, 5%

20 MΩ, 1/16 W, 5%

R7, R8

R9

1 MΩ, 1/16 W, 1%

R10

536 Ω, 1/4 W, 1%

Notes:

1. Decoupling capacitors based on PCI Specification Rev 2.2.

2. Several diode bridge configurations are acceptable; parts, such as a single DF-04S or four 1N4004 diodes, may be

used (suppliers include General Semiconductor, Diodes Inc., etc.).

3. A 56 Ω, 1%, 1/16 W resistor may be used if needed for R12–R13 (0 Ω) to decrease emissions.

4. Murata BLM21AJ601S may be used if needed for R15–R16 (0 Ω) to decrease emissions.

5. R40 should be populated with a 0 Ω resistor if 3.3 V aux is present; otherwise, R41 should be populated with a 0 Ω

resistor.

6. Required for compatibility with future line-side devices.

18

Rev. 1.0

Si3052/17/11/18

Component(s)

Value

73.2 Ω, 1/2 W, 1%

0 Ω, 1/16 W

Supplier(s)

Venkel, SMEC, Panasonic

Silicon Labs

R11

3

R12, R13

5

R15, R16

0 Ω, 1/16 W

5

R40

0 Ω, 1/16 W

5

6

R41 , R60–R64

NI

R51, R52

20 MΩ, 1/16 W, 5%

Si3052

U1

U2

Y1

Z1

Si3017/11/18

32.768 kHz, 50 ppm

Zener Diode, 43 V, 1/2 W

Silicon Labs

ECS, Epson, CTS

General Semiconductor, Diodes Inc.

Notes:

1. Decoupling capacitors based on PCI Specification Rev 2.2.

2. Several diode bridge configurations are acceptable; parts, such as a single DF-04S or four 1N4004 diodes, may be

used (suppliers include General Semiconductor, Diodes Inc., etc.).

3. A 56 Ω, 1%, 1/16 W resistor may be used if needed for R12–R13 (0 Ω) to decrease emissions.

4. Murata BLM21AJ601S may be used if needed for R15–R16 (0 Ω) to decrease emissions.

5. R40 should be populated with a 0 Ω resistor if 3.3 V aux is present; otherwise, R41 should be populated with a 0 Ω

resistor.

6. Required for compatibility with future line-side devices.

Rev. 1.0

19

Si3052/17/11/18

AOUT PWM Output

Figure 15 illustrates an optional circuit to support the ARM[1:0] and ATM[1:0] (Offset 0x36) control receive

pulse-width modulation (PWM) output capability of the and transmit gains in 6 dB steps and receive and

Si3052 for call progress monitoring. This mode is transmit muting. Alternatively, ARM[7:0] and ATM[7:0]

enabled by setting the PWME bit (Offset 0x31).

(Offset 0x44 and 0x45) control gains and muting with

finer resolution. These registers allow the receive and

transmit paths to be independently controlled and

attenuated linearly. Setting these 8-bit registers to all 0s

mutes the receive and transmit paths. These registers

affect the call progress output only and do not affect

transmit and receive operations on the telephone line.

The AOUT signal is a standard digital output from

PIN_39, which represents the sum of independently-

scalable receive and transmit call progress contents in

pulse-width modulation (PWM) form. The sampling rate

of the audio path signals is 32 kHz. The format of the

PWM is configurable by the PWMM bits (Offset 0x31).

12 V

5 VCC

3.3 VCCbus

R61

R62

R63

Only install one

LS1

SPEAKER

Q10

R60

1

PIN_39

C101

Figure 15. AOUT PWM Circuit for Call Progress

Table 12. Component Values—AOUT PWM

Component

C101

Value

Supplier(s)

Venkel, SMEC

Intervox

1 nF, 16 V, X7R, ±20%

BRT1209PF-06

LS1

Q10

MOSFET N GSD, FDV301N

Fairchild

R60

15 kΩ, 1/10 W, 5%

0 Ω, 1/10 W, 5%

NI

Venkel, SMEC, Panasonic

R61

R62, R63

20

Rev. 1.0

Si3052/17/11/18

programming the DMA interrupt address register (Offset

0x10 read and 0x20 write). The current DMA address

PCI Functional Description

The Si3052 provides the interface between a PCI 2.3- register (read or write) contains the physical memory

compliant bus and the Si3018 using the Silicon address of the DMA operation in progress. If the DMA

Laboratories’ proprietary ISOcap™ technology. The Interrupt Address register (read or write) is

Si3052 has several major functional blocks including programmed, an interrupt is generated and the interrupt

DMA, bus mastering, DAA control/status, power status register flag (Offset 0x04) is set when the DMA

management, PNP configuration, EPROM interface, transfer reaches the interrupt address. When the flag is

interrupt control/status, FIFO buffering, and a watchdog set, it is cleared by setting the interrupt status register

timer. Table 13 on page 23 indicates which PCI flag.

commands are supported and the method of

implementation. The PCI timing for write, read, and

the status of the current DMA operation. Each bit

arbitration operations is shown in Figures 15 through

The DMA Status register (Offset 0x04, bits 3:0) contains

generates an interrupt if the corresponding mask bit is

set. If the PCI bus master logic detects an abort

17.

condition, the DMA Status register (Offset 0x04, bits

DMA Bus Master Operation

5:4) is set based on the abort condition. The DMA

The Si3052 supports DMA bus master for write and

Status register is cleared by reading the register value.

read operations to memory. A DMA write is a data

To recover the PCI bus master state machine, clear the

transfer from memory to the Si3052 FIFO buffers. A

DMA reset bit in the DMA Control register (Offset 0x00,

DMA read is a data transfer from the Si3052 FIFO

bit 1) and enable DMA operation by setting the DMA

buffers to memory. Separate registers are defined and

enable bit in the DMA Control register (Offset 0x00,

configured for independent operation of DMA read and

bit 8).

DMA write.

DMA Master Control

DMA Master Transfer Setup

The DMA interrupt mode bit (Offset 0x00, bit 6)

A DMA transfer is set up by programming the DMA start

configures the interrupt mode. For level trigger mode,

address register (read or write) and DMA end address

the interrupt occurs when the event happens and the

register (read or write) to physical memory locations.

status bit remains set as long as the conditions that

The size of the data transfer is calculated as the

created the interrupt remain active. In level trigger

difference between the DMA start and end memory

mode, the status bit is non-sticky. For edge trigger

address locations. The DMA start and end memory

mode, the interrupt occurs when the event happens and

addresses must be on a double-word (4-byte) boundary.

the status bit remains set until cleared by setting the

A programming sequence for a DMA write is as follows: DMA Status register. In edge trigger mode, the status bit

is sticky.

1. Allocate DMA memory buffer (non-cacheable, continuous).

The DMA master mode bit (Offset 0x00, bit 7)

configures the DMA operation mode. In multiple mode,

the DMA address wraps around to the starting address

when the ending address is reached. In single mode,

the DMA stops when it reaches the end address. The

advantage of multiple DMA mode over single DMA

mode is that the Si3052 continuously transfers data

without processor intervention. The single DMA mode

has a control flow similar to the PC core logic DMA

controller.

2. Set DMA write start address register to physical memory

address.

3. Set DMA write end address register to physical memory

address.

4. Fill DMA write FIFO buffer.

5. Set DMA control register start bit.

To start the DMA operation, set the DMA enable bit

(Offset 0x00, bit 8). To stop the DMA operation, clear

this bit. DMA restart bit (Offset 0x00, bit 9) restarts the

DMA operation in single mode but is ignored in multiple

mode.

DAA Control

When the DMA is setup, the processor can use a polling

routine to monitor the current DMA status and process

the FIFO read and FIFO write buffers. Base the polling

interval on the size of the allocated DMA memory buffer.

The DAA registers are accessed by either direct or

indirect methods. The access mode is selected by the

data mode bits (Offset 0x00, bits 11, 12).

Direct DAA Register Access

DMA Master Status

The DAA registers are accessed directly through either

memory or I/O cycles. For memory accesses, the base

address is set in PCI configuration register 10h. For I/O

DMA status is monitored by reading the current DMA

address (Offset 0x14 read and 0x24 write) or by

Rev. 1.0

21

Si3052/17/11/18

accesses, the base address is set in PCI configuration secondary timeslot for control data. If data mode (Offset

register 14h. Memory and I/O cycles are used 0x00, bits 12:11) is set to indirect, the LSB of the 16-bit

interchangeably to access internal registers.

transmit word is used as a flag to indicate control

address/data in the DMA write buffer. If the LSB is 1, the

transmit word is interpreted as control address/data and

written to the corresponding control register. Only 15-bit

data is transmitted resulting in a loss of SNR but

allowing efficient access to DAA control registers.

Indirect DAA Register Access

The DAA registers can be indirectly accessed through

the DMA master write buffer. The DMA write buffer can

contain DAA control and data. This is equivalent to

having a primary timeslot for modem data and a

DMA WRITE Buffer

DMA READ Buffer

Signaling Bits

0

1

DATA

CONTROL (write command)

DATA

CONTROL (all 0s)

DATA

1

Interleaved data

and control

words

CONTROL (read command)

CONTROL (register data)

Core Logic

(PCI Target)

PCI Bus

Si3052

(PCI Master)

DAA Registers

Figure 16. Indirect DAA Register Access

22

Rev. 1.0

Si3052/17/11/18

Table 13. PCI Command Summary

C/BE[3:0]

0000

0001

0010

0011

0100

0101

0110

0111

Command Type

Implementation

Not Supported

Interrupt Acknowledge

Special Cycle

Not Supported

Supported

I/O Read

I/O Write

Supported

Reserved

Memory Read

Support only linear addressing mode

Memory Write

1000

1001

1010

1011

1100

1101

1110

Reserved

Configuration Read

Configuration Write

Memory Read Multiple

Dual Address Cycle

Memory Ready Line

Memory Write and Invalidate

Supported

Aliases to Memory Read

Not Supported

Aliases to Memory Read

Aliases to Memory Write

1111

PCICLK

3

4

5

6

7

8

9

1

2

FRAME

AD

ADDRESS

BUS CMD

DATA-1

BE-1

DATA-2

BE-2

DATA-3

BE-3

C/BE

IRDY

TRDY

DEVSEL

ADDRESS

PHASE

DATA

PHASE

DATA

PHASE

DATA

PHASE

BUS TRANSACTION

Figure 17. PCI Write Operation

Rev. 1.0

23

Si3052/17/11/18

PCICLK

3

4

5

6

7

8

9

1

2

FRAME

AD

ADDRESS

BUS CMD

DATA-1

DATA-2

DATA-3

BE

C/BE

IRDY

TRDY

ADDRESS

PHASE

DATA

PHASE

DATA

PHASE

BUS TRANSACTION

DATA

PHASE

DEVSEL

Figure 18. PCI Read Operation

PCICLK

REQ-a

4

5

6

7

3

1

2

REQ-b

GNT-a

GNT-b

FRAME

AD

ADDRESS

DATA

ADDRESS

DATA

access - A

access - B

Figure 19. PCI Arbitration

24

Rev. 1.0

Si3052/17/11/18

B3 State

Power Management

B3 is the powerdown condition. The 3.3 V PCI power

bus is removed so there is no power to any PCI I/O

pads and non-Vaux PCI core logic. No PCI bus activity

is allowed. All PCI BUS signals are guaranteed to be

held static, with the exception of PME. Vaux is available

for all PME-related logic and I/O. Exit from B3 requires

application of supply and is always accompanied by an

active RESET. Software must guarantee that the DAA

PCI Function enters D3 before placing the PCI Bus in

B3.

The Si3052 conforms to the PCI Bus Power

Management Specification, Revision 1.1. The PCI

functions operate between the D0 and D3 power states.

The PCI Bus controller operates between the B0 and B3

bus power states.

D0 Uninitialized State

D0 Uninitialized is the default condition after either a

warm or a cold reset. 3.3 V is available from the PCI

power bus to power all PCI I/O pads and non-Vaux PCI

core logic. 3.3 V Vaux is available for all Vaux-power I/O

and logic. Powerdown (Offset 0x36, bit 3) defaults low

(inactive) and Powerdown Link (Offset 0x36, bit 4)

defaults high (active), meaning that the system-side

device is fully operational except for the ISOcap, and

the line-side device has no communication or power.

PME-related logic is not cleared by reset.

EPROM Interface

During Si3052 initialization, the EE_SD and EE_SC

pins are examined to determine if an external EPROM

is present. A pullup resistor on EE_SC and a logic high

on EE_SD indicate this condition. The EPROM load

sequence reads six data bytes immediately after a cold

reset. The first data byte is a header of 95h. the next

four data bytes are the PCI subsystem Vendor ID

(SVID) and the subsystem ID (SSID) values. The final

data byte is a cyclic redundancy check (CRC) code. The

EPROM map is shown in Figure 20.

D0 Active State

D0 active is the fully-active condition arrived at from D0

Uninitialized after software configuration. 3.3 V is

available from the PCI power bus to power all PCI I/O

pads and non-Vaux PCI core logic. 3.3 V Vaux is

available for all Vaux-power I/O and logic.

.

Bits

7

6

5

4

3

2

1

0

D3 Hot State

0x05

CRC

D3 (hot) is the powered-up idle condition. 3.3 V is

available from the PCI power bus to power all PCI I/O

pads and non-Vaux PCI core logic; however, PCICLK

can be stopped for minimal power consumption. PCI

BUS signals are guaranteed to be held low during D3

(hot). 3.3 V Vaux is available for all Vaux-power I/O and

logic at a max current draw of 20 mA per card if wake-

on-ring is not enabled or 375 mA per card if wake-on-

ring is enabled.

SSID(15:8)

0x04

0x03

Bytes

SSID(7:0)

0x02

0x01

SVID(15:8)

SVID(7:0)

D3 Cold State

0x00

EPROM ID(0x95)

D3 (cold) is the powered-down idle condition. The 3.3 V

PCI power bus is removed so there is no power to all

PCI I/O pads and non-Vaux PCI core logic. PCI BUS

signals are guaranteed to be held low during D3 (cold).

Vaux is available for all Vaux-power I/O and logic at a

max current draw of 20 mA per card if wake-on-ring is

not enabled, or 375 mA per card if wake-on-ring is

enabled.

Figure 20. EPROM Map

The 8-bit CRC code indicates error detection in a faulty

EPROM. The CRC is calculated using the following

generator polynomial:

G(X) = X⁸+ X²+ X¹+ 1

B0 State

B0 is the fully-active bus power condition. 3.3 V is

available from the PCI power bus to power to all PCI I/O

pads and non-Vaux PCI core logic. 3.3 V Vaux is

available for all Vaux-power I/O and logic. The PCICLK

is active, and all bus transactions are available.

The CRC byte is calculated by appending an all-zero

byte to the end of the data bytes and dividing the string

by the generator polynomial in modulo-2 fashion. The

remainder of the division is the CRC byte value.

An example calculation follows.

Rev. 1.0

25

Si3052/17/11/18

Data Bytes:

EPROM Bytes:

0x95

0x43

0x15

0x52

Header byte

SVID[7:0]

SVID[15:8]

SSID[7:0]

SSID[15:8]

CRC byte

0x95

0x43

0x15

0x52

0x30

0x00

Header byte

SVID[7:0]

SVID[15:8]

SSID[7:0]

SSID[15:8]

All zero byte

0x30

0x3D

3.3 VCC bus

VA

R62

U3

1

2

3

4

8

NC Vcc

A1 NC

A2 SCL

Vss SDA

7

6

5

PIN_39

PIN_38

C100

Option PIN_38

PIN_39

PIN_38 Function

CLKRUN

PNPID

PIN_39 Function

AOUT

0

1

2

3

4

5

6

7

8

X

A

1

0

A

1

0

A

1

0

A

1

PNPID

AOUT

PNPID

AOUT

SCL/AOUT

PNPID

SDA

---

SDA

SCL/AOUT

Note: X = No Install

1 = 4.7 kW pullup to 3.3 V

0 = 4.7 kW pulldown to GND

A = Voltage divider between V_Aand GND

Figure 21. EPROM Circuit

26

Rev. 1.0

Si3052/17/11/18

Interrupt Sources

INTA is a level triggered interrupt pin for Si3052

interrupt sources. The sources for the INTA interrupt are

as follows:

! Ring Detect

! PCI Target Abort

! PCI Master Abort

! DMA Read End of Buffer

! DMA Read Interrupt Address

! DMA Write End of Buffer

! DMA Write Interrupt Address

! Interrupt Counter

! ISOcap Frame Detect

! Receive Overload

! Billing tone Detect

! Drop Out Detect

! Overload Detect

PME is a level triggered interrupt pin for PCI Power

Management events. The source for the PME interrupt

is ring detect with or without ring validation.

FIFO Buffers

The FIFO buffers are fixed as 16 bits wide by 8 samples

deep for DMA master read and write. The sample data

is contained in the lowest 16 bits of a 32-bit word. The

FIFO buffers do not support DMA target operations. The

FIFO buffers are not memory mapped and cannot be

accessed directly.

Rev. 1.0

27

Si3052/17/11/18

and other circuitry.

Telephone Line Interface Functional

Description

The Si3018 can be fully programmed to meet

international requirements and is compliant with FCC,

TBR21, JATE, and other country-specific PTT

specifications as shown in Table 14. Also, the Si3018

meets the most stringent global requirements for out-of-

band energy, emissions, immunity, lightning surges, and

safety. The Si3011 meets all TBR21 and FCC

requirements. The Si3017 meets all FCC requirements.

Together, the Si3052 and Si3017/11/18 comprise an

integrated direct access arrangement (DAA) that

provides a programmable line interface to meet global

telephone line interface requirements. The device

implements Silicon Laboratories’ proprietary ISOcap™

technology, which offers the highest level of integration

by replacing an analog front end (AFE), an isolation

transformer, relays, opto-isolators, a 2- to 4-wire hybrid,

Table 14. Country Specific Register Settings

Offset 0x40

ACT2,ACT DCT[1:0]

Line-Side

Country

Argentina

OHS

0

RZ

0

RT

0

3018

!

3011

3017

00

10

00

10

00

10

00

10

00

10

01

11

01

11

10

11

10

01

10

11

10

11

!

Australia

1

Austria

0

!

Bahrain

0

1

Belgium

Brazil

0

Bulgaria

Canada

Chile

0

!

0

!

0

China

0

Colombia

Croatia

0

Cyprus

0

Czech Republic

0

1

Denmark

0

Ecuador

Egypt

0

!

0

El Salvador

0

!

1

Finland

0

1

France

0

1

Germany

0

1

0

Greece

Guam

0

!

Hong Kong

Hungary

0

1

Iceland

0

Notes:

1. TBR21 includes the following countries: Austria, Belgium, Denmark, Finland, France, Germany, Greece, Iceland,

Ireland, Italy, Luxembourg, Netherlands, Norway, Portugal, Spain, Sweden, Switzerland, and the United Kingdom.

2. Supported for loop currents ≥ 20 mA.

3. Products using the Si3011/17 which have been submitted for JATE approval should document a waiver for the JATE

dc termination specification. This specification is met in the Si3018 global line-side device.

28

Rev. 1.0

Si3052/17/11/18

Table 14. Country Specific Register Settings (Continued)

Offset 0x40

Line-Side

Country

OHS

0

1

0

ACT2,ACT DCT[1:0]

RZ

0

1

0

1

RT

0

1

0

3018

!

3011

!

3017

!

India

00

10

00

10

00

10

00

10

11

10

00

10

00

10

00

10

11

01

10

11

10

01

11

10

11

10

11

01

10

01

10

11

10

01

10

11

10

Indonesia

!

1

Ireland

!

Israel

!

1

Italy

!

3

Japan

!

Jordan

Kazakhstan

Kuwait

!

Latvia

Lebanon

Luxembourg

Macao

1

!

2

Malaysia

Malta

!

Mexico

Morocco

1

Netherlands

New Zealand

Nigeria

!

1

Norway

Oman

Pakistan

Peru

!

Philippines

Poland

1

Portugal

!

Romania

Russia

Saudi Arabia

Singapore

Slovakia

!

Slovenia

South Africa

South Korea

Notes:

1. TBR21 includes the following countries: Austria, Belgium, Denmark, Finland, France, Germany, Greece, Iceland,

Ireland, Italy, Luxembourg, Netherlands, Norway, Portugal, Spain, Sweden, Switzerland, and the United Kingdom.

2. Supported for loop currents ≥ 20 mA.

3. Products using the Si3011/17 which have been submitted for JATE approval should document a waiver for the JATE

dc termination specification. This specification is met in the Si3018 global line-side device.

Rev. 1.0

29

Si3052/17/11/18

Table 14. Country Specific Register Settings (Continued)

Offset 0x40

Line-Side

Country

OHS

ACT2,ACT DCT[1:0]

RZ

0

RT

0

3018

!

3011

!

3017

1

Spain

Sweden

0

10

00

10

00

11

01

10

01

10

11

10

1

0

!

1

Switzerland

Syria

0

!

0

!

Taiwan

0

!

Thailand

UAE

0

!

0

!

1

United Kingdom

USA

0

!

0

!

Yemen

0

!

Notes:

1. TBR21 includes the following countries: Austria, Belgium, Denmark, Finland, France, Germany, Greece, Iceland,

Ireland, Italy, Luxembourg, Netherlands, Norway, Portugal, Spain, Sweden, Switzerland, and the United Kingdom.

2. Supported for loop currents ≥ 20 mA.

3. Products using the Si3011/17 which have been submitted for JATE approval should document a waiver for the JATE

dc termination specification. This specification is met in the Si3018 global line-side device.

Initialization

Isolation Barrier

When the Si3052 is initially powered up, the RESET pin The Si3052 achieves an isolation barrier through low-

must be asserted. When the RESET pin is de-asserted, cost, high-voltage capacitors in conjunction with Silicon

the registers have their default values. The DAA Laboratories’ proprietary ISOcap™ signal processing

registers cannot be accessed during the crystal warm- techniques. These techniques eliminate signal

up period. The following is an example initialization degradation from capacitor mismatches, common mode

procedure:

interference, or noise coupling. The C1, C2, C8, and C9

capacitors isolate the Si3052 system-side device from

the Si3017/11/18 line-side device. All transmit, receive,

control, ring detect, and caller ID data are

communicated through this barrier. Y2 class capacitors

can be used to achieve surge performance of 5 kV or

greater.

1. Select the crystal frequency using the XTAL bit

(Offset 0x28, bit 24).

2. Poll the DAA status bit (Offset 0x4, bit 23) until it indicates

the DAA is ready.

3. Select the desired sample rate using the SRC bits

(Offset 0x37, bits 3:0).

The ISOcap communications link is disabled by default.

To enable it, the PDL bit (Offset 0x36, bit 4) must be

cleared. No communication between the Si3052 and

Si3017/11/18 can occur until this bit is cleared and the

FDT bit (Offset 0x3C, bit 6) is high.

4. Power up the line side by clearing the PDL bit

(Offset 0x36, bit 4).

5. Enable AOUT by setting ARM[1:0] (Offset 0x36, bits 5:0)

and ATM[1:0] (Offset 36, bits 6:1) to the desired level.

6. Set the required line interface parameters (i.e., DCT[1:0],

ACT, OHS, and RT) as defined in Table 14.

Parallel Handset Detection

7. Prior to receiving or transmitting data, ensure FDT (Offset

3C, bit 6) is set indicating the Si3018 is ready for normal

operation.

The Si3052 can detect a parallel handset going off-

hook. When the Si3052 is off-hook, the loop current can

be monitored via the LCS bits (Offset 0x3C, bits 4:0). A

significant drop in loop current can signal a parallel

handset going off-hook. If a parallel handset causes the

LCS bits to read 0s, the DropOut Detect Interrupt bit

(Offset 0x34, bit 3) can be checked to verify that a valid

line still exists.

After the procedure is complete, the DAA is ready for

off-hook, on-hook line monitoring, and ring detection.

30

Rev. 1.0

Si3052/17/11/18

For the Si3052 to operate in parallel with another Loop Current Measurement

handset, the parallel handset must have a sufficiently

high dc termination to support two DAAs off-hook on the

same line. Improved parallel handset operation can be

achieved by changing the dc impedance from 50 to

800 Ω by setting the DCR bit (Offset 0x4A, bit 0) and

setting DCV[1:0] (Offset 0x4A, bits 7:6) to 00b. MAP = 1

is necessary to access the DCR and DCV bits.

When the Si3052 is off-hook, the LCS bits measure loop

current in 3.3 mA/bit resolution. These bits detect

another phone going off-hook by monitoring the dc loop

current. The line current sense transfer function is

shown in Figure 22 and is detailed in Table 15. The LCS

bits display loop current down to the minimum operation

loop current for the DAA, which is set by the MINI[1:0]

bits.

Loop Current Sensing

When the LCS bits have reached their maximum value,

the Loop Current Sense Overload Interrupt bit fires;

however, LCSI firing does not necessarily guarantee

that an overload situation has occurred. An overload

situation in the DAA is determined by the status of the

OPD bit. After the LCSI interrupt fires, the OPD bit

should be checked to determine if an overload situation

exists. The OPD bit indicates an overload situation

when loop current exceeds either 160 mA (ILIM = 0) or

60 mA (ILIM = 1).

The Si3052 measures loop current. The LCS[4:0] bits

(Offset 0x3C, bits 4:0) report loop current

measurements when off-hook. The following can be

determined with the LCS bits:

! When off-hook, detect if a parallel phone goes on- or

off-hook.

! Determine if sufficient loop current is available to

operate.

! Detect if there is an overload condition (see

"Overload Detection" on page 37).

Overload

30

25

20

LCS

BITS

15

10

5

0

3.3 6.6 9.9 13.2 16.5 19.8 23.1 26.4 29.7 33 36.3 39.6 42.9 46.2 49.5 52.8 56.1 59.7 62.7 66 69.3 72.6 75.9 79.2 82.5 85.8 89.1 92.4 95.7 99 102.3

127

Loop Current

(mA)

Figure 22. Typical LCS Transfer Function (ILIM = 0)

Table 15. Loop Current Transfer Function

Condition

LCS[4:0]

00000

Insufficient line current for normal operation. Use the DODI bit (Offset 0x34, bit 3) to

determine if a line is still connected.

00100

11111

Minimum line current for normal operation. (MINI[1:0] = 01)

Loop current may be excessive. For FCC, low voltage, and JATE termination, cur-

rent may be >120 mA. For TBR21, current may be >60 mA. Use the OPD bit (Offset

0x43, bit 1) to determine if an overload condition exists.

Rev. 1.0

31

Si3052/17/11/18

Off-Hook

FCC DCT Mode

The software generates an off-hook command by

setting the OH bit (Offset 0x35, bit 0). This state seizes

the line for incoming/outgoing calls and can also be

used for pulse dialing. When on-hook, negligible dc

current flows through the hookswitch. When off-hook,

the hookswitch transistor pair, Q1 and Q2, turn on. A

termination impedance is applied across TIP and RING

and causes dc loop current to flow. The termination

impedance has an ac and dc component.

12

11

10

9

8

Several events occur internally to the DAA when the OH

bit is set. There is a 250 µs latency for the off-hook

command to communicate to the line-side device. When

the line-side device goes off-hook, an off-hook counter

forces a delay before transmission or reception can

occur. This off-hook counter time is controlled by the

FOH[1:0] bits (Offset 0x4F, bits 6:5). The default setting

for the off-hook counter time is 128 ms, but can be

adjusted up to 512 ms or down to either 64 or 8 ms.

After the off-hook counter expires, a resistor calibration

is performed for 17 ms. The resistor calibration can be

disabled by setting the RCALD bit (Offset 0x49, bit 5).

After the resistor calibration is performed, an ADC

calibration is performed for 256 ms. The ADC

calibration can be disabled by setting the CALD bit

(Offset 0x41, bit 5). Refer to "Calibration" on page 37 for

information on automatic and manual calibration.

Disabling the resistor and the ADC calibrations should

only be done when a fast response is needed after

going off-hook, such as when responding to a Type II

caller-ID signal. See "Caller ID" on page 36. To

calculate the total time required to go off-hook and start

transmission or reception, the digital filter delay

(typically 1.5 ms with the FIR filter) should be included

in the calculation.

7

6

.01 .02 .03 .04 .05 .06 .07 .08 .09 .1 .11

Loop C urrent (A)

Figure 23. FCC Mode I/V Characteristics

TBR21 mode (DCT[1:0] = 11 ), shown in Figure 24,

b

provides current limiting while maintaining a transmit

full-scale level of –0.5 dBm at TIP and RING. The dc

termination current limits before reaching 60 mA.

CTR21 DCT Mode

45

40

35

30

25

15

10

5

0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6

Loop Current (A)

DC Termination

Figure 24. TBR21 Mode I/V Characteristics

The Si3052 has four programmable dc termination

modes that are selected with the DCT[1:0] bits (Offset

0x40, bits 3:2).

Japan mode (DCT[1:0] = 01 ), shown in Figure 25, is a

b

lower voltage mode and supports a transmit full-scale

level of –0.5 dBm. The low voltage requirement is

dictated by countries, such as Japan and Malaysia.

FCC mode (DCT[1:0] = 10 ), shown in Figure 23, is the

b

default dc termination mode and supports a transmit full

scale level of –0.5 dBm at TIP and RING. This mode

meets FCC requirements and the requirements of many

other countries.

32

Rev. 1.0

Si3052/17/11/18

Table 16. AC Termination Settings

Japan DCT Mode

10.5

10

ACT2 ACT

AC Termination

9.5

0

Real, nominal 600 Ω termination that

satisfies the impedance requirements of

FCC part 68, JATE, and other countries.

9

8.5

8

7.5

7

0

1

0

Complex impedance that satisfies global

complex impedance requirements.

6.5

6

Complex impedance that satisfies global

complex impedance requirements

EXCEPT New Zealand. Achieves higher

return loss for some complex ac termi-

nation.

5.5

.01 .02 .03 .04 .05 .06 .07 .08 .09 .1 .11

Loop Current (A)

Figure 25. Japan Mode I/V Characteristics

1

Complex impedance for use in New

Zealand.

Low-voltage mode (DCT[1:0] = 00 ), shown in

b

Figure 26, is the lowest line voltage mode supported on

the Si3052, with a transmit full-scale level of –0.5 dBm.

This low-voltage mode is offered for situations that

require low line voltage operation.

Transhybrid Balance

The Si3052 contains an on-chip analog hybrid that

performs the 2- to 4-wire conversion and near-end echo

cancellation. This hybrid circuit is adjusted for each ac

termination setting selected. The Si3052 also offers a

digital hybrid for additional near-end echo cancellation.

For each ac termination setting selected, the eight

programmable hybrid registers (Offsets 0x5D–0x64)

can be programmed with coefficients to increase

cancellation of real-world line characteristics. The digital

filter can produce 10 dB or greater of near-end echo

cancellation in addition to the echo cancellation

provided by the analog hybrid circuitry.

Low Voltage Mode

10.5

10

9.5

9

8.5

8

7.5

7

6.5

6

Ring Detection

5.5

The ring signal is connected from TIP and RING to the

RNG1 and RNG2 pins. The Si3052 supports either full-

or half-wave ring detection. Full-wave ring detection

detects a polarity reversal and the ring signal. See

“Caller ID” on page 36. The ring detection threshold is

programmable with the RT bit (Offset 0x40, bit 0).

.01 .02 .03 .04 .05 .06 .07 .08 .09 .1 .11

Loop Current (A)

Figure 26. Low-Voltage Mode I/V

Characteristics

AC Termination

The ring detector output can be monitored with the

register bits RDTP, RDTN, and RDT (Offset 0x35, bits 6,

5, and 2). Software must detect the frequency of the ring

signal to distinguish a ring from pulse dialing by

The Si3052 has four ac termination impedance settings.

The ACT and ACT2 bits select the ac impedance. The

available ac termination settings are listed in Table 16.

telephone

equipment

connected

in

parallel.

Alternatively, hardware ring validation can be used. See

"Ring Validation" on page 34.

The ring detector mode is controlled by the RFWE bit

(Offset 0x42, bit 1). When the RFWE bit is 0 (default

mode), the ring detector operates in half-wave rectifier

mode. Only positive ring signals are detected. A positive

ring signal is defined as a voltage greater than the ring

threshold across RNG1-RNG2. Conversely, a negative

Rev. 1.0

33

Si3052/17/11/18

ring signal is defined as a voltage less than the negative Ring validation requires five parameters:

ring threshold across RNG1-RNG2.

! Timeout parameter to place a lower limit on the

When the RFWE bit is 1, the ring detector operates in

full-wave rectifier mode. Positive and negative ring

signals are detected.

frequency of the ring signal on the RAS[5:0] bits

(Offset 0x48, bits 5:0). The frequency is measured

by calculating the time between crossings of positive

and negative ring thresholds.

The RDTP and RDTN behavior is based on the RNG1-

RNG2 voltage. When the signal on RNG1-RNG2 is

above the positive ring threshold, the RDTP bit is set.

When the signal on RNG1-RNG2 is below the negative

ring threshold, the RDTN bit is set. When the signal on

RNG1-RNG2 is between these thresholds, neither bit is

set.

! Minimum count to place an upper limit on the

frequency on the RMX[5:0] bits (Offset 0x46, bits

5:0).

! Time interval over which the ring signal must be the

correct frequency on the RCC[2:0] bits (Offset 0x47,

bits 2:0).

The RDT behavior is also based on the RNG1-RNG2 ! Timeout period that defines when the ring pulse has

voltage. When the RFWE bit is 0, a positive ring signal

sets the RDT bit for a period of time. When the RFWE

bit is 1, either a positive or negative ring signal sets the

RDT bit.

ended with the most recent ring threshold crossing

on the RTO [3:0] bits (Offset 0x47, bits 6:3).

! Delay period between when the ring signal is

validated and when a valid ring signal is indicated to

help accommodate distinctive ring on the RDLY [2:0]

bits (Offset 0x47, bit 7; Offset 0x46, bits 7:6)

The RDT bit acts like a one shot. When a new ring

signal is detected, the one shot is reset. If no new ring

signals are detected before the one shot counter

reaches 0, the RDT bit returns to 0. The length of this

count (in seconds) is 65536 divided by the sample rate.

The RDT bit is also reset to 0 by an off-hook event.

The ring validation enable bit, RNGV (Offset 0x48,bit 7),

enables or disables the ring validation feature in normal

operating mode and low-power sleep mode.

Ringer Impedance and Threshold

Ring Validation

The ring detector in many DAAs is ac coupled to the line

with a large 1 µF, 250 V decoupling capacitor. The ring

detector on the Si3052 is resistively coupled to the line.

The network produces a high ringer impedance to the

line of approximately 20 MΩ to meet the majority of

country PTT specifications including FCC and TBR21.

This feature prevents false triggering of a ring detection

by validating the ring parameters. Invalid signals, such

as line-voltage changes when a parallel handset goes

off-hook, pulse dialing, and high-voltage line tests, are

ignored. Ring validation can be enabled during normal

operation and in low-power sleep mode.

Several countries including Poland, South Africa, and

Slovenia require a maximum ringer impedance that can

be met with an internally-synthesized impedance by

setting the RZ bit (Offset 0x40, bit 1).

The ring validation circuit operates by calculating the

time between alternating crossings of positive and

negative ring thresholds to validate that the ring

frequency is within tolerance. High- and low-frequency

tolerances are programmable in the RAS[5:0] and

RMX[5:0] fields. The RCC[2:0] bits define the length of

time the ring signal must be within tolerance.

Countries also specify ringer thresholds differently. The

RT bit (Offset 0x40, bit 0) selects between two different

ringer thresholds: 15 V ±10% and 21.5 V ±10%. These

two settings satisfy ringer threshold requirements

worldwide. The thresholds are set so that a ring signal is

guaranteed to not be detected below the minimum, and

a ring signal is guaranteed to be detected above the

maximum.

Once the duration of the ring frequency is validated by

the RCC bits, the circuitry stops checking for frequency

tolerance and begins checking for the end of the ring

signal, which is defined by a lack of additional threshold

crossings for a period of time configured by the

RTO[3:0] bits. When the ring frequency is first validated,

a timer defined by the RDLY[2:0] bits is started. If the

RDLY[2:0] timer expires before the ring timeout, the ring

is validated, and a valid ring is indicated. If the ring

timeout expires before the RDLY[2:0] timer, a valid ring

is not indicated.

DTMF Dialing

The Si3018 meets all the country requirements for

DTMF dialing listed in Table 14 on page 28. If desired,

higher DTMF levels can be achieved by setting the

DIAL bit (Offset 0x42, bit 6) at low loop currents

(<15 mA). Higher DTMF levels can also be achieved if

the amplitude is increased and the peaks of the DTMF

signal are clipped at digital full scale, avoiding wrapping

the waveform.

34

Rev. 1.0

Si3052/17/11/18

Clipping the signal produces distortion and the line are filtered out by the low-pass digital filter on

intermodulation of the signal. Generally, increased the Si3052. The ROV bit (Offset 0x41, bit 1) is set when

distortion between 10–20% is acceptable during DTMF a line signal is greater than 1.1 V , indicating a receive

PK

signaling. Several dB higher DTMF levels can be overload condition. The BTD bit (Offset 0x41, bit 0) is

achieved with this technique, compared with a digital set when a line signal (billing tone) is large enough to

full-scale peak signal.

excessively reduce the line-derived power supply of the

Si3018 line-side device. When the BTD bit is set, the dc

termination is changed to an 800 Ω dc impedance to

Pulse Dialing and Spark Quenching

Going off- and on-hook to generate make and break ensure minimum line voltage levels even in the

pulses accomplishes pulse dialing. The nominal rate is presence of billing tones.

10 pulses per second. Some countries have tight

The OVL bit (Offset 0x43, bit 2) can be pulled following

specifications for pulse fidelity including make and

a billing tone detection. When the OVL bit returns to 0,

break times, make resistance, and rise and fall times. In

indicating that the billing tone has passed, the ROV bit

a traditional solid-state dc holding circuit, there are

considerations for meeting these requirements.

remains sticky and must be written to 0 to be reset. After

the billing tone passes, the DAA initiates an auto-

The Si3052 dc holding circuit has active control of the calibration sequence that must complete before data

on-hook and off-hook transients to maintain pulse can be transmitted.

dialing fidelity.

Certain line events, such as an off-hook event on a

Spark quenching requirements in countries, such as parallel phone or a polarity reversal, can trigger the

Italy, the Netherlands, South Africa, and Australia, ROV or the BTD bits, after which the ROV bit must be

address the on-hook transition during pulse dialing. reset. Look for multiple events before qualifying if billing

These tests provide an inductive dc feed resulting in a tones are actually present.

large voltage spike. A spike is caused by the line

Although the DAA remains off-hook during a billing tone

inductance and the sudden decrease in current through

event, the received data from the line is corrupted when

the loop when going on-hook. The traditional way of

a large billing tone occurs. To receive data through a

addressing this problem is to put a parallel RC shunt

billing tone, an external LC filter must be added. A

across the hookswitch relay. The capacitor is large

modem manufacturer can provide this filter in the form

(~1 µF, 250 V) and relatively expensive. In the Si3052,

the OHS bit (Offset 0x40, bit 6), OHS2 bit (Offset 0x4F,

bit 3), and SQ[1:0] bits (Offset 0x6B, bits 6,4) can ramp

down the loop current to pass these tests without

requiring additional components. A slow ramp-down of

the loop current introduces a delay between the time the

OH bit is cleared and the time the DAA actually goes

on-hook.

of a dongle that connects on the phone line before the

DAA. The manufacturer does not have to include a

costly LC filter internal to the modem when it is only

necessary to support a few countries.

Alternatively, when a billing tone is detected, the system

software can notify the user that a billing tone has

occurred. The user can contact the telephone company

to disable the billing tones or to purchase an external

LC filter.

To ensure proper operation of the DAA during pulse

dialing, disable the automatic resistor calibration that is

performed each time the DAA enters the off-hook state

by setting the RCALD bit.

Billing Tone Filter (Optional)

To operate without degradation during billing tones in

Germany, Switzerland, and South Africa, an external LC

notch filter is required. The Si3052 can remain off-hook

during a billing tone event, but modem data is lost in the

presence of large billing tone signals. The notch filter

design requires two notches, one at 12 kHz and one at

16 kHz. Because these components are fairly

expensive and few countries supply billing tone support,

this filter is placed in an external dongle or added as a

population option for these countries. Figure 27 shows

an example billing tone filter.

Billing Tone Detection and Receive

Overload

“Billing tones” or “metering pulses” generated by the

central office can produce modem connection

difficulties. The billing tone is a 12 or 16 kHz signal and

is occasionally used in Germany, Switzerland, and

South Africa. Depending on line conditions, the billing

tone might be large enough to cause major errors

related to the modem data. The Si3052 chipset can

provide feedback indicating the beginning and end of a

billing tone.

L1 must carry the entire loop current. The series

resistance of the inductors is important to achieve a

narrow and deep notch. This design has more than

25 dB of attenuation at 12 and 16 kHz.

Billing tone detection is enabled by setting the BTE bit

(Offset 0x41, bit 2). Billing tones less than 1.1 V on

PK

Rev. 1.0

35

Si3052/17/11/18

Caller ID

Table 17. Component Values—Optional Billing

Tone Filters

The Si3052 can pass caller ID data from the phone line

to a software caller ID decoder.

Symbol

C1,C2

C3

Value

Type I Caller ID

Type I Caller ID sends the CID data while the phone is

on-hook. In systems where the caller ID data is passed

on the phone line between the first and second rings,

utilize the following method to capture the caller ID data:

0.027 µF, 50 V, ±10%

0.01 µF, 250 V, ±10%

L1

3.3 mH, >120 mA, <10 Ω, ±10%

10 mH, >40 mA, <10 Ω, ±10%

1. After identifying a ring signal using one of the methods

described in "Ring Detection" on page 33, determine when

the first ring has completed.

L2

2. Assert the ONHM bit (Offset 0x35, bit 3) to enable current

caller ID.

C1

3. The low-current ADC, which is powered from the system-

side device, digitizes the caller ID data passed across the

RNG 1/2 pins.

C2

L1

4. Clear the ONHM bit after the caller ID data is received.

In systems where the caller ID data is preceded by a

line polarity (battery) reversal, use the following method

to capture the caller ID data:

TIP

From Line

RING

1. Enable full-wave rectified ring detection (Offset 0x42, bit

1).

L2

To

DAA

C3

2. Monitor the RDTP and RDTN register bits to identify

whether a polarity reversal or ring signal has occurred. A

polarity reversal trips either the RDTP or RDTN ring

detection bits, and, thus, the full-wave ring detector must

be used to distinguish a polarity reversal from a ring. The

lowest specified ring frequency is 15 Hz; therefore, if a

battery reversal occurs, the DSP software should wait a

minimum of 40 ms to verify that the event observed is a

battery reversal and not a ring signal. This time is greater

than half the period of the longest ring signal. If another

edge is detected during this 40 ms pause, this event is

characterized as a ring signal and not a battery reversal.

Figure 27. Billing Tone Filter

The billing tone filter affects the DAA’s ac termination

and return loss. The current complex ac termination

passes worldwide return loss specifications with and

without the billing tone filter by at least 3 dB. The ac

termination is optimized for frequency response and

hybrid cancellation while having greater than 4 dB of

margin with or without the dongles for South Africa,

Australia, TBR21, Germany, and Switzerland country-

specific specifications.

3. Assert the ONHM bit (Offset 0x35, bit 3) to enable the low-

current caller ID ADC. The low-current ADC, which is

powered from the system-side device, digitizes the caller

ID data passed across the RNG 1/2 pins.

4. Clear the ONHM bit after the caller ID data is received.

Type II Caller ID

On-Hook Line Monitor

Type II Caller ID sends the CID data while the phone is

off-hook and is often referred to as caller ID/call waiting

(CID/CW). To receive the CID data while off-hook, use

the following procedure:

The Si3052 receives line activity when in an on-hook

state through the RNG1/2 pins. This mode detects caller

ID data and no line current is drawn. See “Caller ID” on

page 36. This mode is enabled by setting the ONHM bit

(Offset 0x35, bit 3). ARX [2:0] (Offset 0x3F, bits 2:0)

provides gain to the normal receive path of the DAA and

functions as a gain bit for the on-hook line monitor.

1. The Caller Alert Signal (CAS) tone is sent from the Central

Office (CO) and is digitized along with the line data. The

software must detect the presence of this tone.

2. Since the Si3052 is the only device on the line and is Type

II CID-compliant, the software must mute its upstream data

output to avoid propagation of its reply tone and the

subsequent CID data. After muting its upstream data

output, the software must then return an

acknowledgement (ACK) tone to the CO to request the

36

Rev. 1.0

Si3052/17/11/18

transmission of the CID data.

lower, but non-linear, group delay than the default FIR

filter.

3. The CO then responds with the CID data, and the software

unmutes the upstream data output and continues with

normal operation.

Power Management

The Si3052 supports four basic power management

operation modes: normal operation, reset operation,

sleep mode, and full powerdown mode. The power

management modes are controlled by the PDL and

PDN bits (Offset 0x36, bits 4,3).

4. The muting of the upstream data path by the software

mutes the handset in a telephone application so the user

cannot hear the acknowledgement tone and CID data

being sent.

The CID data presented to the software could have up

to a 10% dc offset. The software caller ID decoder must

either use a high-pass or a band-pass filter to accurately

retrieve the caller ID data.

On powerup or following a reset, the Si3052 is in reset

operation. The PDL bit is set, and the PDN bit is

cleared. The Si3052 is fully-operational except for the

ISOcap™ link. No communication between the Si3052

and Si3017/11/18 can occur during reset operation. Bits

associated with the Si3017/11/18 are not valid in this

mode.

Overload Detection

The Si3052 can be programmed to detect an overload

condition that exceeds the normal operating power

range of the DAA circuit. To use the overload detection

feature, the following steps should be performed:

1. Set the OH bit (Offset 0x35, bit 0) to go off-hook, and wait

25 ms to allow line transients to settle.

The most common mode of operation is normal

operation. The PDL and PDN bits are cleared. The

Si3052 is fully-operational, and the ISOcap link is

passing information between the Si3052 and the

Si3017/11/18. A valid sample rate must be programmed

before entering this mode.

2. Enable overload detection by setting the OPE bit

(Offset 0x41, bit 3).

If the DAA senses an overload situation, it automatically

presents an 800 Ω impedance to the line to reduce the

hookswitch current. At this time, the DAA also sets the

OPD bit (Offset 0x43, bit 0) to indicate that an overload

condition exists. The line current detector within the

DAA has a threshold that is dependant upon the ILIM bit

(Offset 0x4A, bit 1). When ILIM = 0, the overload

detection threshold equals 160 mA. When ILIM = 1, the

overload detection threshold equals 60 mA. The OPE

bit should always be cleared before going off-hook.

The Si3052 supports a low-power sleep mode for the

wake-up-on-ring feature of many modems. The sample

rate must be programmed with a valid non-zero value

before enabling sleep mode. The PDN bit must then be

set and the PDL bit cleared. The Si3052 is non-

functional except for the ISOcap link signal. To take the

Si3052 out of sleep mode, pulse (RESET) low.

In summary, the powerdown/up sequence for sleep

mode is as follows:

1. SRC[3:0] must have a valid non-zero value.

Gain Control

2. Set the PDN bit (Offset 0x36, bit 3) and clear the PDL bit

(Offset 0x36, bit 4).

The Si3052 supports multiple receive gain and transmit

attenuation settings (Offset 0x3F). The receive path

supports gains of 0, 3, 6, 9, and 12 dB, as selected with

the ARX[2:0] bits. The receive path can be muted with

the RXM bit. The transmit path supports attenuations of

0, 3, 6, 9, and 12 dB, as selected with the ATX[2:0] bits.

The transmit path can be muted with the TXM bit.

3. Reset the Si3052 by pulsing the RESET pin.

4. Program registers to required settings.

The Si3052 also supports an additional powerdown

mode. When the PDN and PDL bits are set, the chipset

enters a complete powerdown mode and draws

negligible current (deep sleep mode). Normal operation

is restored using the same process for taking the

Si3052 out of sleep mode.

Sample Rate Converter

The SCR [3:0] bits (Offset 0x37, bits 3:0) are used to

select the sample rate. The following sample rates are

supported: 7200, 8000, 8229, 8400, 9000, 9600, 10286,

12000, 13714, and 16000 Hz.

Calibration

The Si3017/11/18 initiates an auto-calibration by default

when the device goes off-hook or experiences a loss in

line power. Calibration removes offsets that are present

in the on-chip ADC and which could affect the ADC

dynamic range. Auto-calibration is initiated after the

DAA dc termination stabilizes and takes 256 ms to

complete. Because of the large variation in line

conditions and line card behavior that is presented to

Filter Selection

The Si3052 supports two filter selections for the receive

and transmit signals as defined in Table 10 and Table 11

on page 13. The IIRE (Offset 0x40, bit 4) selects

between the IIR and FIR filters. The IIR filter provides a

Rev. 1.0

37

Si3052/17/11/18

the DAA, it might be beneficial to use manual calibration components connecting the RJ-11 jack (TIP and RING)

instead of auto-calibration.

to the Si3017/11/18. To enable this mode, set the AL bit

(Offset 0x32, bit 3).

Execute manual calibration as close to 256 ms as

possible before valid transmit/receive data is expected. The final testing mode, internal analog loopback, allows

the system to test the basic operation of the transmit

The following steps implement manual calibration:

and receive paths on the line-side device and the

1. The CALD (Offset 0x41, bit 5) bit must be set to 1.

external components. In this test mode, the data pump

2. The MCAL bit (Offset 0x41, bit 6) must be toggled to one

provides a digital test waveform. Data is passed across

the isolation barrier, transmitted to and received from

the line, passed back across the isolation barrier, and

and then 0 to begin and complete the calibration.

3. The calibration is completed in 256 ms.

presented to the data pump. To enable this mode, clear

In-Circuit Testing

the HBE bit (Offset 0x32, bit 1). The test circuit in

Four loopback modes exist allowing increased

Figure 2 on page 11 is an adequate line feed for this

coverage of system components. For three of the test

test.

modes, an off-hook sequence must be performed.

Note: All test modes are mutually-exclusive. If more than one

For the start-up test mode, no line-side power is

necessary, and no off-hook sequence is required. The

start-up test mode is enabled by default. When the PDL

bit (Offset 0x36, bit 4) is set (the default case), the line-

side is in a powerdown mode, and the PCI side is in a

digital loop-back mode. Data received is passed through

the internal filters and transmitted. This path introduces

approximately 0.9 dB of attenuation. There is a group

delay of transmit and receive filters. Clearing the PDL

bit disables this mode, and the data is switched to the

receive data from the line-side. When the PDL bit is

cleared, the FDT bit (Offset 0x3C, bit 6) becomes active

indicating the successful communication between the

Si3017/11/18 and the Si3052. This verifies that the

ISOcap™ link is operational.

test mode is enabled concurrently, the results are

unpredictable.

Revision Identification

The revision of the system side (Si3052) and line side

(Si3017/11/18) can be determined using the SREV[3:0]

bits (Offset 0x3B, bits 3:0) and LREV[3:0] bits

(Offset 0x3D, bits 5:2), respectively. Table 18 lists the

revision values.

Table 18. Revision Values

Revision

Si3052

0011

Si3017/11/18

0011

C

D

0100

The remaining test modes require an off-hook sequence

to operate. The following sequence defines the off-hook

requirements:

Register Map

1. Powerup or reset.

The Si3052 is designed to provide backwards

compatibility to previous designs based on the Si3035

and Si3034 DAAs. When the MAP bit (Offset 0x31,

bit 6) is cleared (default value), the Si3052 operates in

this backwards-compatible mode. When the MAP bit is

set, several bits in the register map become available

and several other bits are no longer accessible. The

Si3052 is designed to operate in either MAP = 1 or

MAP = 0. Following powerup or reset, the desired MAP

mode should be selected prior to setting other bits, and

the MAP mode should remain in the same state until the

next power up or reset. Table 19 shows the bits affected

by the state of the MAP bit.

2. Program the required sample rate.

3. Enable line-side device by clearing PDL bit.

4. Issue off-hook

5. Allow calibration to occur.

6. Set required test mode.

The ISOcap™ digital loopback mode allows the data

pump to provide a digital input test pattern and receive

that digital test pattern back. To enable this mode, set

the DL bit (Offset 0x31, bit 1). The isolation barrier is

actually being tested. The digital stream is delivered

across the isolation capacitors (C1 and C2) to the line-

side device and returned across the same barrier. While

an off-hook sequence is necessary, a valid line feed is

not needed for this test.

The analog loopback mode allows an external device to

drive

a signal on the telephone line into the

Si3017/11/18 line-side device and have it driven back

out onto the line. This mode is for testing external

38

Rev. 1.0

Si3052/17/11/18

Table 19. Bits selected by MAP bit

MAP = 0

ATM[1:0], TXM

ARM[1:0], RXM

DCT[1:0]

MAP = 1

ATM[7:0]

ARM[7:0]

DCV[1:0]

MINI[1:0]

ILIM

DIAL

FJM

VOL [1:0]

DCR

HYBx[7:0]

When MAP = 1, the ATM[7:0] bits replace the ATM[1:0] and TXM bits. The ARM[7:0] replaces the ARM[1:0] and

RXM bits. The DCV[1:0], MINI[1:0], and ILIM bits replace the DCT[1:0] bits. Table 20 lists the equivalent settings for

dc termination.

Table 20. DC Termination Equivalents

DCV[1:0]

MINI[1:0]

ILIM

DCT[1:0] = 00

(low voltage)

00

11

0

DCT[1:0] = 01

(JATE)

01

10

11

00

0

1

DCT[1:0] = 10

(FCC)

DCT[1:0] = 11

(TBR21)

Table 20 should be used to translate the DCT[1:0] bits in Table 14, “Country Specific Register Settings,” on

page 28. The DIAL, FJM, and VOL[1:0] bits do not have a MAP = 1 equivalent and are unused.

The DCR bit switches the dc termination into 800 Ω mode. This is the same mode used by the billing tone detector

and overload detector. The HYBx registers are described in the section, "Transhybrid Balance" on page 33.

Rev. 1.0

39

Si3052/17/11/18

PCI Configuration Registers

Note: Registers not listed here are reserved and must not be written.

Table 21. PCI Register Summary

Register

Name

Bits

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16

00h

PCI Device ID

and Vendor ID

DID[15:0]

D15 D14 D13 D12 D11 D10 D9

D8

VID[15:0]

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16

D7

D6 D5 D4 D3 D2 D1 D0

04h

08h

PCI Status

and Command

DPE

SSE RMAS RTAS STAS

DST[1:0]

DPD FBBC

C66

CPM INTS

D15 D14 D13 D12 D11 D10 D9

D8

D7

D6 D5 D4 D3 D2 D1 D0

INTD FBBM SEE STEP PEN

MWI

BME MAE IOAE

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16

Device

Revision

Identification

CC[23:8]

D15 D14 D13 D12 D11 D10 D9

D8

D7

D6 D5 D4 D3 D2 D1 D0

CC[7:0]

REV[7:0]

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16

0Ch

10h

14h

2Ch

Cache Line

Size, Master

Latency Timer

HT[7:0]

D15 D14 D13 D12 D11 D10 D9

D8

D7

D6 D5 D4 D3 D2 D1 D0

MLTC[5:0]

CLS[7:0]

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16

Memory Base

Address

MBA[31:16]

D15 D14 D13 D12 D11 D10 D9

D8

D7

D6 D5 D4 D3 D2 D1 D0

MBA[15:0]

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16

I/O Base

Address

IOBA[31:16]

D15 D14 D13 D12 D11 D10 D9

D8

D7

D6 D5 D4 D3 D2 D1 D0

IOBA[15:0]

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16

Subsystem ID,

Subsystem

Vendor ID

SSID[15:0]

D15 D14 D13 D12 D11 D10 D9

D8

D7

D6 D5 D4 D3 D2 D1 D0

SVID[15:0]

40

Rev. 1.0

Si3052/17/11/18

Table 21. PCI Register Summary (Continued)

Register

Name

Bits

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16

34h

Capabilities

Pointer

D15 D14 D13 D12 D11 D10 D9

D8

D7

D6 D5 D4 D3 D2 D1 D0

CPTR[7:0]

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16

3Ch

40h

80h

84h

MAX_LAT,

MIN_GNT,

Interrupt Pin,

Interrupt Line

MLAT[7:0]

D15 D14 D13 D12 D11 D10 D9

INTP[7:0]

MGNT[7:0]

D6 D5 D4 D3 D2 D1 D0

INTL[7:0]

D8

D7

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16

Retry Time-

out, TRDY

Timeout

D15 D14 D13 D12 D11 D10 D9

D8

D7

D6 D5 D4 D3 D2 D1 D0

RT[7:0]

TYT[7:0]

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16

Power

Management

Capabilities

P3C P3H PD2 PD1 PD0 D2S D1S

D15 D14 D13 D12 D11 D10 D9

NXT[7:0]

AUXC[2:0]

D8 D7

DVS

PCL

VER[2:0]

D6 D5 D4 D3 D2 D1 D0

CID[7:0]

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16

Power

Management

Control and

Status (Vaux

powered)

D15 D14 D13 D12 D11 D10 D9

PMS DSC[1:0] DSE[3:0]

D8

D7

D6 D5 D4 D3 D2 D1 D0

PME

PST[1:0]

Rev. 1.0

41

Si3052/17/11/18

PCI Register 00h. PCI Device ID and Vendor ID

Bit

Name

Type

Bit

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16

DID[15:0]

R

D15 D14 D13 D12 D11 D10 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

VID[15:0]

R

Reset setting = 0x30521543

Bit

Name

Function

31:16

DID[15:0]

Device Identification.

PCI Device ID is 3052 for the Si3052 device.

15:0

VID[15:0]

Vendor Identification.

PCI Vendor ID is 1543 for Silicon Laboratories.

42

Rev. 1.0

Si3052/17/11/18

PCI Register 04h. PCI Status and Command

Bit

Name

Type

Bit

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16

DPE SSE RMAS RTAS STAS

DST[1:0]

R

DPD FBBC

C66 CPM INTS

R

D15 D14 D13 D12 D11 D10 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

INTD FBBM SEE STEP PEN

R/W R/W R/W R/W

MWI

R/W

BME MAE IOAE

R/W R/W R/W

Name

Type

R

Reset setting = 0x02900080

Bit

31

30

29

Name

DPE

Function

Detect Parity Error.

SSE

Signaled System Error.

RMAS

Received Master Abort Status.

Set when PCI master terminates a host-to-PCI transaction with a master abort.

28

RTAS

Received Target Abort Status.

Set when the Si3052 initiates a PCI transaction and it is terminated by the target.

27

STAS

Signaled Target Abort Status.

26:25

DST[1:0]

Device Select Timing.

Indicates timing of DEVSEL when the Si3052 responds to a PCI transaction as a target.

24

23

22

21

20

DPD

FBBC

Reserved

C66

Data Parity Detected.

Fast Back-to-Back Capable Status Flag.

Read returns zero.

66 MHz Capable Status Flag.

CPM

Capabilities List.

PME supported.

19

INTS

Reserved

INTD

Interrupt Status.

18:11

Read returns zero.

10

9

8

7

6

5

4

3

2

1

0

Interrupt Disable.

FBBM

SEE

Fast Back-to-Back Master Enable.

System Error Enable

Data Stepping Enable.

Parity Error Enable.

Read returns zero.

STEP

PEN

Reserved

MWI

Memory Write and Invalidate Enable.

Read returns zero.

Reserved

BME

Bus Master Enable.

MAE

Memory Access Enable.

I/O Access Enable.

IOAE

Rev. 1.0

43

Si3052/17/11/18

PCI Register 08h. Device Revision Identification

Bit

Name

Type

Bit

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16

CC[23:8]

R

D15 D14 D13 D12 D11 D10 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

REV[7:0]

R

Name

Type

CC[7:0]

R

Reset setting = 0x07030003

Bit

31:8

7:0

Name

Function

CC[23:0]

REV[7:0]

Class Code.

Revision Identification Number.

PCI Register 0Ch. Cache Line Size, Master Latency Timer

Bit

Name

Type

Bit

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16

HT[7:0]

R

D15 D14 D13 D12 D11 D10 D9

D8

D7

D6

D5

D4

CLS[7:0]

R/W

D3

D2

D1

D0

Name

Type

MLTC[5:0]

R/W

Reset setting = 0x00000000

Bit

Name

Reserved

HT[7:0]

Function

31:24

23:16

Read returns zero.

Header Type.

A single function, non-bridge type header format.

15:10

MLTC[5:0]

Master Latency Timer Count.

Sets the minimum number of PCI clock cycles that the Si3052 is guaranteed access to

the PCI bus. After the count has expired, the Si3052 surrenders the PCI bus when other

PCI master devices are granted the bus by the arbiter. Programmable in increments of

1 ms.

9:8

7:0

Reserved

CLS[7:0]

Read returns zero.

Cache Line Size.

All cache type transactions are aliases to normal reads and writes.

44

Rev. 1.0

Si3052/17/11/18

PCI Register 10h. Memory Base Address

Bit

Name

Type

Bit

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16

MBA[31:16]

R/W

D15 D14 D13 D12 D11 D10 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

MBA[15:0]

R/W

Reset setting = 0x00000000

Bit

Name

Function

31:0

MBA[31:0]

Memory Base Address.

Memory space is in 4096 byte increments.

PCI Register 14h. I/O Base Address

Bit

Name

Type

Bit

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16

IOBA[31:16]

R/W

D15 D14 D13 D12 D11 D10 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

IOBA[15:0]

R/W

Reset setting = 0x00000001

Bit

Name

Function

31:0

IOBA[31:0] I/O Base Address.

I/O space is 256 bytes.

Rev. 1.0

45

Si3052/17/11/18

PCI Register 2Ch. Subsystem ID, Subsystem Vendor ID

Bit

Name

Type

Bit

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16

SSID[15:0]

R

D15 D14 D13 D12 D11 D10 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

SVID[15:0]

R

Reset setting = N/A

Bit

Name

Function

31:16

SSID[15:0] PCI Subsystem ID.

EPROM or resistor ID configurable.

15:0

SVID[15:0] PCI Subsystem Vendor ID.

EPROM or resistor ID configurable.

PCI Register 34h. Capabilities Pointer

Bit

Name

Type

Bit

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16

D15 D14 D13 D12 D11 D10 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

CPTR[7:0]

R

Name

Type

Reset setting = 0x00000080

Bit

31:8

7:0

Name

Function

Reserved

CPTR[7:0]

Read returns zero.

Capabilities Pointer.

Location of PME information.

46

Rev. 1.0

Si3052/17/11/18

PCI Register 3Ch. MAX_LAT, MIN_GNT, Interrupt Pin, Interrupt Line

Bit

Name

Type

Bit

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16

MGNT[7:0]

R

MLAT[7:0]

R

D15 D14 D13 D12 D11 D10 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

INTL[7:0]

R/W

Name

Type

INTP[7:0]

R

Reset setting = 0x3E010100

Bit

Name

Function

31:24

MLAT[7:0]

MAX_LAT.

Sets the value of MAX_LAT. See PCI 2.2 specification, section 6.2.4 (250 ns units). The

maximum latency between bus grants is limited to 62–250 ns.

23:16

MGNT[7:0] MIN_GNT.

Identifies the length of the burst period, assuming a 33 MHz clock (250 ns units). A mini-

mum grant of 250 ns is required for burst transactions.

15:8

7:0

INTP[7:0]

INTL[7:0]

Interrupt Pin.

Identifies which interrupt pin the Si3052 uses. Default interrupt pin is INTA.

Interrupt Line.

Identifies the interrupt line register to which the Si3052 is connected.

PCI Register 40h. Retry Timeout, TRDY Timeout

Bit

Name

Type

Bit

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16

D15 D14 D13 D12 D11 D10 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

TYT[7:0]

R

Name

Type

RT[7:0]

R

Reset setting = 0x00000000

Bit

Name

Reserved

RT[7:0]

Function

31:16

15:8

Read returns zero.

Retry Timeout.

Sets number of retries that the Si3052 as master performs.

7:0

TYT[7:0]

TRDY Timeout.

Sets number of PCI clocks that the Si3052 as master waits for TRDY.

Rev. 1.0

47

Si3052/17/11/18

PCI Register 80h. Power Management Capabilities

Bit

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16

P3H PD2 PD1 PD0 D2S D1S

AUXC[2:0]

DVS

R

PCL

R

VER[2:0]

Name P3C

R

Type

Bit

D15 D14 D13 D12 D11 D10 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

CID[7:0]

R

Name

Type

NXT[7:0]

R

Reset setting = 0xC8420001

Bit

Name

Function

31

P3C

PME Support D3 Cold.

ANDed with 3.3 Vaux pin.

30

29

P3H

PD2

PME Support D3 Hot.

PME Support D2.

Not supported.

28

PD1

PME Support D1.

Not supported.

27

26

PD0

D2S

PME Support D0.

D2 Support.

Not supported.

25

D1S

D1 Support.

Not supported.

24:22

AUXC[2:0]

Aux_Current.

Less than 55 mA in D3 cold.

21

20

DVS

Reserved

PCL

Device Specific.

Read returns zero.

PME Clock.

19

18:16

VER[2:0]

Version.

Complies with PPM 1.1.

15:8

7:0

NXT[7:0]

CID[7:0]

Next Item.

Capability ID.

48

Rev. 1.0

Si3052/17/11/18

PCI Register 84h. Power Management Control and Status (Vaux powered register)

Bit

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16

Name

Type

Bit

D15 D14 D13 D12 D11 D10 D9

D8

PME

R/W

D7

D6

D5

D4

D3

D2

D1

PST[1:0]

R/W

D0

DSC[1:0]

R

DSE[3:0]

R

Name PMS

R/W

Type

Reset setting = 0x00000000

Bit

31:16

15

Name

Reserved

PMS

Function

Read returns zero.

PME Status (sticky).

Write 1 to clear.

14:13

12:9

DSC[1:0]

DSE[3:0]

Data Scale.

No data register implemented.

Data Select.

No data register implemented.

8

PME

PME Enable (sticky).

7:2

1:0

Reserved

PST[1:0]

Read returns zero.

Power State.

00 = D0

01 = D1 (Not supported)

10 = D2 (Not supported)

11 = D3 Hot

Rev. 1.0

49

Si3052/17/11/18

PCI and DAA Control Registers

Note: Registers not listed here are reserved and must not be written.

Table 22. PCI Register Summary (32-Bit)

Offset

Name

Bits

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16

0x00 DMA and

Interrupt

MTIE

DIE

WIE TAIE MAIE RBIE RAIE WAIE WBIE

Control

D15 D14 D13 D12 D11 D10

D9

D8

D7

D6 D5 D4 D3 D2 D1 D0

DM[1:0]

DMAR DMAE DMAM DMAI

DRST PRST

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16

0x04 DMA and

Interrupt

DAA

EER WFU WFF WFE RFO RFF

RFE

Status

D15 D14 D13 D12 D11 D10

D9

D8

D7

D6 D5 D4 D3 D2 D1 D0

MTO DIS WIS PTA PMA DRB DRA DWA DWB

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16

0x08 DMA Read

Address Start

DRAS[31:16]

D15 D14 D13 D12 D11 D10

D9

D8

D7

D6 D5 D4 D3 D2 D1 D0

DRAS[15:0]

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16

0x0C DMA Read

Address Stop

DRAP[31:16]

D15 D14 D13 D12 D11 D10

D9

D8

D7

D6 D5 D4 D3 D2 D1 D0

DRAP[15:0]

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16

0x10 DMA Read

Address

DRAI[31:16]

Interrupt

D15 D14 D13 D12 D11 D10

D9

D8

D7

D6 D5 D4 D3 D2 D1 D0

DRAI[15:0]

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16

0x14 Current DMA

Read Address

CDRA[31:16]

D15 D14 D13 D12 D11 D10

D9

D8

D7

D6 D5 D4 D3 D2 D1 D0

CDRA[15:0]

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16

0x18 DMA Write

Address Start

DWAS[31:16]

D15 D14 D13 D12 D11 D10

D9

D8

D7

D6 D5 D4 D3 D2 D1 D0

DWAS[15:0]

50

Rev. 1.0

Si3052/17/11/18

Table 22. PCI Register Summary (32-Bit) (Continued)

Offset

Name

Bits

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16

DWAP[31:16]

0x1C DMA Write

Address Stop

D15 D14 D13 D12 D11 D10

D9

D8

D7

D6 D5 D4 D3 D2 D1 D0

DWAP[15:0]

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16

0x20 DMA Write

Address

DWAI[31:16]

Interrupt

D15 D14 D13 D12 D11 D10

D9

D8

D7

D6 D5 D4 D3 D2 D1 D0

DWAI[15:0]

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16

0x24 Current DMA

Write Address

CDWA[31:16]

D15 D14 D13 D12 D11 D10

D9

D8

CDWA[15:0]

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16

D7

D6 D5 D4 D3 D2 D1 D0

0x28 Watchdog

Timer

STPM STPE XTAL

D15 D14 D13 D12 D11 D10 D9 D8

WDT[15:0]

WTS WTC

D7

D6 D5 D4 D3 D2 D1 D0

Rev. 1.0

51

Si3052/17/11/18

Table 23. DAA Register Summary (8-Bit)

Offset Name

Control 1

Bit 7

Bit 6

Bit 5

PWMM[1:0]

WDTE

Bit 4

Bit 3

PWME

AL

Bit 2

Bit 1

DL

Bit 0

0x31

0x32

0x33

0x34

0x35

0x36

0x37

0x38

0x39

0x3A

0x3B

0x3C

0x3D

0x3E

0x3F

0x40

0x41

0x42

0x43

0x44

0x45

0x46

0x47

0x48

0x49

0x4A

0x4B

0x4C

0x4D

SR

MAP

Control 2

RDM

HBE

RXE

Interrupt Mask

RDTM ROVM FDTM

BTDM DODM LCSM

Interrupt Source

RDTI

ROVI

FDTI

BTDI

DODI

ONHM

PDN

LCSI

RDT

DAA Control 1

RDTN

RDTP

OH

1

DAA Control 2

ATM[1] ARM[1]

PDL

ATM[0] ARM[0]

SRC[3:0]

Sample Rate Control

Reserved

DAA Control 3

DDL

System-side Revision

Line-Side Status

Line-Side Revision

Reserved

LSID[3:0]

FDT

SREV[3:0]

LCS[4:0]

LREV[3:0]

1

TX/RX Gain Control

International Control 1

International Control 2

International Control 3

International Control 4

AOUT RX Attenuation

AOUT TX Attenuation

Ring Validation Control 1

Ring Validation Control 2

TXM

ATX[2:0]

ACT

RXM

DCT[1:0]

OPE

ARX[2:0]

RZ

1

ACT2

CALZ

OHS

IIRE

RT

MCAL

CALD

BTE

ROV

BTD

1

DIAL

FJM

VOL[1:0]

RFWE

OVL

OPD

2

ARM[7:0]

2

ATM[7:0]

RDLY[1:0]

RDLY[2]

RMX[5:0]

RTO[3:0]

RCC[2:0]

Ring Validation Control 3 RNGV

Resistor Calibration

RAS[5:0]

RCALD

MINI[1:0]

2

DC Termination Control

Reserved

DCV[1:0]

ILIM

DCR

Reserved

Note: All register bits are available when MAP = 0 and MAP = 1 except

1. Only available when MAP = 0

2. Only available when MAP = 1

52

Rev. 1.0

Si3052/17/11/18

Table 23. DAA Register Summary (8-Bit) (Continued)

Offset Name

Reserved

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x4E

0x4F

0x5D

0x5E

0x5F

0x60

0x61

0x62

0x63

0x64

0x65

0x66

0x67

0x68

0x69

0x6A

0x6B

DAA Control 4

Hybrid 1

FOH[1:0]

OHS2

2

HYB1[7:0]

2

Hybrid 2

HYB2[7:0]

Hybrid 3

HYB3[7:0]

HYB4[7:0]

HYB5[7:0]

HYB6[7:0]

HYB7[7:0]

HYB8[7:0]

Hybrid 4

Hybrid 5

Hybrid 6

Hybrid 7

Hybrid 8

Reserved

Spark Quenching Control

SQ1

SQ0

Note: All register bits are available when MAP = 0 and MAP = 1 except

1. Only available when MAP = 0

2. Only available when MAP = 1

Rev. 1.0

53

Si3052/17/11/18

PCI Register Offset 0x00 DMA and Interrupt Control

Bit

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16

MTIE

DIE

WIE

TAIE

MAIE

RBIE

RAIE

WAIE

WBIE

Name

R/W

Type

Bit

D15 D14 D13 D12 D11 D10 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

DM[1:0]

DMAR DMAE DMAM DMAI

DRST

PRST

Name

R/W

R/W R/W R/W R/W

R/W

Type

Reset setting = 0x00000000

Bit

31:25

24

Name

Reserved

MTIE

Function

Read returns zero.

DMA Master Timeout Interrupt Enable.

0 = Interrupt disable.

1 = Interrupt enable.

23

22

21

20

19

18

17

16

DIE

WIE

DAA Interrupt Enable.

0 = Interrupt disable.

1 = Interrupt enable.

Watchdog Timer Interrupt Enable.

0 = Interrupt disable.

1 = Interrupt enable.

TAIE

MAIE

RBIE

RAIE

WAIE

WBIE

PCI Target Abort Interrupt Enable.

0 = Interrupt disable.

1 = Interrupt enable.

PCI Master Abort Interrupt Enable.

0 = Interrupt disable.

1 = Interrupt enable.

DMA Read End of Buffer Interrupt Enable.

0 = Interrupt disable.

1 = Interrupt enable.

DMA Read Address Interrupt Enable.

0 = Interrupt disable.

1 = Interrupt enable.

DMA Write Address Interrupt Enable.

0 = Interrupt disable.

1 = Interrupt enable.

DMA Write End of Buffer Interrupt Enable.

0 = Interrupt disable.

1 = Interrupt enable.

54

Rev. 1.0

Si3052/17/11/18

Bit

Name

Reserved

DM[1:0]

Function

15:13

12:11

Read returns zero.

Data Mode.

00 = Direct.

01 = Indirect, Parallel.

10 = Indirect, Serial, LSB first.

11 = Indirect, Serial, MSB first.

10

9

Reserved

DMAR

Read returns zero.

DMA Restart.

0 = DMA continue.

1 = DMA restart.

8

7

6

DMAE

DMAM

DMAI

DMA Enable.

0 = DMA disable.

1 = DMA enable.

DMA Master Mode.

0 = Multiple mode.

1 = Single mode.

DMA Interrupt Mode.

0 = Interrupt status bit is sticky.

1 = Interrupt status bit is non-sticky.

Applies to address and end-of-buffer interrupts.

5:2

1

Reserved

DRST

Read returns zero.

DMA Reset.

0 = DMA continue.

1 = DMA reset.

0

PRST

PCI DAA Soft Reset.

0 = Normal operation.

1 = DAA reset. The PCI registers are not affected. All DAA registers are reset to default

values. Write zero to clear.

Rev. 1.0

55

Si3052/17/11/18

PCI Register Offset 0x04 DMA and Interrupt Status

Bit

Name

Type

Bit

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16

DAA EER WFU WFF WFE RFO RFF RFE

R

R/W R/W R/W R/W R/W R/W

D5 D4 D3 D2 D1 D0

D15 D14 D13 D12 D11 D10 D9

D8

D7

D6

Name

Type

MTO DIS WIS PTA PMA DRB DRA DWA DWB

R/W R/W R/W R/W R/W R/W R/W R/W R/W

Reset setting = 0x00000000

Bit

31:24

23

Name

Reserved

DAA

Function

Read returns zero.

DAA Status.

0 = DAA ready.

1 = DAA not ready.

22

EER

EPROM Read Status.

0 = No status.

1 = EPROM read failure.

21

20

19

18

17

16

15:9

8

WFU

WFF

DMA Write FIFO Underrun.

DMA Write FIFO Full.

DMA Write FIFO Empty.

DMA Read FIFO Overrun.

DMA Read FIFO Full.

DMA Read FIFO Empty.

Read returns zero.

WFE

RFO

RFF

RFE

Reserved

MTO

DMA Master Timeout Status.

0 = Normal operation.

1 = Master timeout from TRDY timer or retry timer. Write 1 to clear.

7

6

5

DIS

WIS

PTA

DAA Interrupt Status.

0 = Normal operation.

1 = DAA interrupt has occurred. Write 1 to clear.

Watchdog Timer Interrupt Status.

0 = Normal operation.

1 = Watchdog timer has expired. Write 1 to clear.

PCI Target Abort Interrupt Status.

0 = Normal operation.

1 = PCI Target Abort has occurred. Write 1 to clear.

56

Rev. 1.0

Si3052/17/11/18

Bit

Name

Function

4

PMA

PCI Master Abort Interrupt Status.

0 = Normal operation.

1 = PCI Master Abort has occurred. Write 1 to clear.

3

2

1

0

DRB

DRA

DWA

DWB

DMA Read End of Buffer Interrupt Status.

0 = Normal operation.

1 = DMA Read has reached end of buffer. Write 1 to clear.

DMA Read Address Interrupt Status.

0 = Normal operation.

1 = DMA Read has reached interrupt address. Write 1 to clear.

DMA Write Address Interrupt Status.

0 = Normal operation.

1 = DMA Write has reached interrupt address. Write 1 to clear.

DMA Write End of Buffer Interrupt Status.

0 = Normal operation.

1 = DMA Write has reached end of buffer. Write 1 to clear.

Rev. 1.0

57

Si3052/17/11/18

PCI Register Offset 0x08 DMA Read Address Start

Bit

Name

Type

Bit

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16

DRAS[31:16]

R/W

D15 D14 D13 D12 D11 D10 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

DRAS[15:0]

R/W

Reset setting = 0x00000000

Bit

Name

Function

31:0

DRAS[31:0] DMA Read Address Start.

PCI Register Offset 0x0C DMA Read Address Stop

Bit

Name

Type

Bit

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16

DRAP[31:16]

R/W

D15 D14 D13 D12 D11 D10 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

DRAP[15:0]

R/W

Reset setting = 0x00000000

Bit

Name

Function

31:0

DRAP[31:0] DMA Read Address Stop.

58

Rev. 1.0

Si3052/17/11/18

PCI Register Offset 0x10 DMA Read Address Interrupt

Bit

Name

Type

Bit

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16

DRAI[31:16]

R/W

D15 D14 D13 D12 D11 D10 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

DRAI[15:0]

R/W

Reset setting = 0x00000000

Bit

Name

Function

31:0

DRAI[31:0] DMA Read Address Interrupt.

PCI Register Offset 0x14 Current DMA Read Address

Bit

Name

Type

Bit

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16

CDRA[31:16]

R

D15 D14 D13 D12 D11 D10 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

CDRA[15:0]

R

Reset setting = 0x00000000

Bit

Name

Function

31:0

CDRA[31:0] Current DMA Read Address.

Rev. 1.0

59

Si3052/17/11/18

PCI Register Offset 0x18 DMA Write Address Start

Bit

Name

Type

Bit

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16

DWAS[31:16]

R/W

D15 D14 D13 D12 D11 D10 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

DWAS[15:0]

R/W

Reset setting = 0x00000000

Bit

Name

Function

31:0

DWAS[31:0] DMA Write Address Start.

PCI Register Offset 0x1C DMA Write Address Stop

Bit

Name

Type

Bit

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16

DWAP[31:16]

R/W

D15 D14 D13 D12 D11 D10 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

DWAP[15:0]

R/W

Reset setting = 0x00000000

Bit

Name

Function

31:0

DWAP[31:0] DMA Write Address Stop.

60

Rev. 1.0

Si3052/17/11/18

PCI Register Offset 0x20 DMA Write Address Interrupt

Bit

Name

Type

Bit

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16

DWAI[31:16]

R/W

D15 D14 D13 D12 D11 D10 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

DWAI[15:0]

R/W

Reset setting = 0x00000000

Bit

Name

Function

31:0

DWAI[31:0] DMA Write Address Interrupt.

PCI Register Offset 0x24 Current DMA Write Address

Bit

Name

Type

Bit

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16

CDWA[31:16]

R

D15 D14 D13 D12 D11 D10 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

CDWA[15:0]

R

Reset setting = 0x00000000

Bit

Name

Function

31:0 CDWA[31:0] Current DMA Write Address.

Rev. 1.0

61

Si3052/17/11/18

PCI Register Offset 0x28 Watchdog Timer

Bit

Name

Type

Bit

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16

STPM STPE XTAL

WTS WTC

R/W R/W

R/W

D15 D14 D13 D12 D11 D10

D9

D8

D7 D6 D5 D4 D3

D2

D1

D0

Name

Type

WDT[15:0]

R/W

Reset settings = 0x02000000

Bit

31:27

26

Name

Reserved

STPM

Function

Read returns zero.

Address/Data Stepping Mode.

0 = 4 steps.

1 = 2 steps.

STPE

XTAL

25

24

Address/Data Stepping Enable.

0 = Disabled.

1 = Enabled.

External Crystal Frequency Select.

0 = 16.384 MHz

1 = 32.768 kHz

25:18

17

Reserved

WTS

Read returns zero.

PCI Watchdog Timer Status.

0 = Watchdog timer idle/counting.

1 = Watchdog timer expired.

WTC

16

PCI Watchdog Timer Control.

0 = Watchdog timer disabled.

1 = Watchdog timer enabled. When set this bit is cleared by a hardware reset.

15:0

WDT[15:0]

PCI Watchdog Timer.

Timer is free running and clocked by the PCI system clock. For 33 MHz PCI, the timer

increments every (256/33 MHz) = 7.76 µs. The timer overflows in 508 ms without register

accesses, generating an interrupt and stopping DMA operations.

62

Rev. 1.0

Si3052/17/11/18

DAA Register Offset 0x31 Control 1

Bit

D7

SR

D6

D5

PWMM[1:0]

R/W

D4

D3

D2

D1

DL

D0

Name

Type

MAP

R/W

PWME

R/W

Reset settings = 0000_0000

Bit

Name

Function

7

SR

Software Reset.

0 = Enables Si3052 for normal operation.

1 = Sets all registers to their reset value.

Note: Bit clears automatically after being set.

6

MAP

Register Map.

0 = Basic register set (Si3014 compatible) selected.

1 = Enhanced register set selected.

Note: This bit should be set during initialization only.

5:4

PWMM[1:0] Pulse-Width Modulation Mode.

Selects the type of signal on the call progress AOUT pin.

00 = PWM output clocked at 16.384 MHz. A local density of 1s and 0s tracks the com-

bined transmit and receive signal.

01 = Balanced conventional PWM output signal has high and low portions of the modu-

lated pulse centered on the 32 kHz sample clock.

10 = Conventionally PWM output signal returns to 0 at 32 kHz intervals and rises at a

time in the 32 kHz period proportional to the instantaneous amplitude.

11 = Reserved

3

PWME

Pulse-Width Modulation Enable.

0 = Call progress PWM AOUT disabled.

1 = Call progress PWM AOUT enabled.

2

1

Reserved

DL

Read returns zero.

Isolation Digital Loopback.

0 = Digital loopback across isolation barrier disabled.

1 = Enables digital loopback mode across isolation barrier. The line-side device must be

enabled and off-hook before setting this mode. This data path includes RX and TX filters.

A valid phone line is not necessary for this mode.

0

Reserved

Read returns zero.

Rev. 1.0

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Si3052/17/11/18

DAA Register Offset 0x32 Control 2

Bit

D7

D6

D5

D4

D3

AL

D2

D1

D0

WDTE

R/W

Name

Type

RDM

R/W

HBE

R/W

RXE

R/W

Reset settings = 0000_0011

Bit

7:5

4

Name

Reserved

WDTE

Function

Read returns zero.

DAA Watchdog Timer Enable.

0 = Watchdog timer disabled.

1 = Watchdog timer enabled. When set, this bit is cleared only by a hardware reset. The

watchdog timer monitors DAA register writes. If a register write does not occur within a

4.096 second window, the DAA is put into an on-hook state. Only a write of a DAA regis-

ter restarts the timer.

3

2

1

0

AL

Analog Loopback.

0 = Analog loopback mode disabled.

1 = Enables external analog loopback mode.

RDM

HBE

RXE

Ring Detect Mode.

0 = Ring detect on positive threshold.

1 = Ring detect on positive and negative threshold.

Hybrid Enable.

0 = Disconnects hybrid in transmit path.

1 = Connects hybrid in transmit path.

Receive Enable.

0 = Receive path disabled.

1 = Enables receive path.

64

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DAA Register Offset 0x33 Interrupt Mask

Bit

D7

D6

D5

D4

D3

DODM

R/W

D2

D1

D0

Name

Type

RDTM

R/W

ROVM

R/W

FDTM

R/W

BTDM

R/W

LCSM

R/W

Reset settings = 0000_0000

Bit

Name

Function

7

RDTM

Ring Detect Interrupt Mask.

0 = A ring signal does not cause an interrupt.

1 = A ring signal causes an interrupt.

6

5

ROVM

FDTM

Receive Overload Interrupt Mask.

0 = A receive overload does not cause an interrupt.

1 = A receive overload causes an interrupt.

Frame Detect Interrupt Mask.

0 = ISOcap frame lock does not cause an interrupt.

1 = ISOcap frame lock causes an interrupt.

4

BTDM

Billing Tone Detect Interrupt Mask.

0 = A billing tone does not cause an interrupt.

1 = A billing tone causes an interrupt.

3

DODM

LCSM

Drop Out Detect Interrupt Mask.

0 = A line supply dropout does not cause an interrupt.

1 = A line supply dropout causes an interrupt.

2

Loop Current Sense Overload Interrupt Mask.

0 = Loop current sense overload does not cause an interrupt.

1 = Loop current sense overload causes an interrupt.

1:0

Reserved

Read returns zero.

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DAA Register Offset 0x34 Interrupt Status

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

RDTI

R/W

ROVI

R/W

FDTI

R/W

BTDI

R/W

DODI

R/W

LCSI

R/W

Reset settings = 0000_0000

Bit

Name

Function

7

RDTI

Ring Detect Interrupt Status.

0 = No ring.

1 = Ring detected. Write 0 to clear.

6

5

4

3

2

ROVI

FDTI

BTDI

DODI

LCSI

Receive Overload Interrupt Status.

0 = No receive overload.

1 = Receive overload detected. Write 0 to clear.

Frame Detect Interrupt Status.

0 = Frame detect established.

1 = Frame detect lost. Write 0 to clear.

Billing Tone Detect Interrupt Status.

0 = No billing tone.

1 = Billing tone detected. Write 0 to clear.

Drop Out Detect Interrupt Status.

0 = Line-side power available.

1 = Line-side power unavailable. Reads 1 when off hook.

Loop Current Sense Overload Interrupt.

0 = The LCS bits have not reached max (all ones).

1 = The LCS bits have reached max value. If the LCSM bit is set, a hardware interrupt

occurs. This bit must be written to 0 to clear it.

LCSI does not necessarily imply that an overload situation has occurred. An overload sit-

uation in the DAA is determined by the status of the OPD bit. After the LCSI interrupt fires,

the OPD bit should be checked to determine if an overload situation exists.

1:0

Reserved

Read returns zero.

66

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DAA Register Offset 0x35 DAA Control 1

Bit

D7

D6

RDTN

R

D5

RDTP

R

D4

D3

D2

RDT

R

D1

D0

OH

Name

Type

ONHM

R/W

Reset settings = 0000_0000

Bit

7

Name

Reserved

RDTN

Function

Read returns zero.

6

Ring Detect Signal Negative.

0 = No ring signal is occurring.

1 = A negative ring signal is occurring.

5

RDTP

Ring Detect Signal Positive.

0 = No ring signal is occurring.

1 = A positive ring signal is occurring.

4

3

Reserved

ONHM

Read returns zero.

On-Hook Line Monitor.

0 = Normal on-hook mode.

1 = Enables low-power monitoring mode allowing the DSP to receive line activity without

going off-hook. This mode is used for caller-ID detection.

2

RDT

Ring Detect.

0 = Reset either 4.5–9 seconds after last positive ring is detected or when the system

executes an off-hook.

1 = Indicates a ring is occurring.

1

0

Reserved

OH

Read returns zero.

Off-Hook.

0 = Line-side device on-hook.

1 = Causes the line-side device to go off-hook.

Rev. 1.0

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DAA Register Offset 0x36 DAA Control 2

Bit

D7

D6

ATM[1]

R/W

D5

ARM[1]

R/W

D4

D3

D2

D1

ATM[0]

R/W

D0

ARM[0]

R/W

Name

Type

PDL

R/W

PDN

R/W

Reset settings = 0111_0000

Bit

7

Name

Function

Reserved

ATM[1:0]

Read returns zero.

6,1

AOUT Transmit Path Level Control (MAP = 0 only).

00 = –20 dB transmit path attenuation for call progress AOUT pin only.

01 = –32 dB transmit path attenuation for call progress AOUT pin only.

10 = Mutes transmit path for call progress AOUT pin only.

11 = –26 dB transmit path attenuation for call progress AOUT pin only.

5,0

ARM[1:0]

AOUT Receive Path Level Control (MAP = 0 only).

00 = 0 dB receive path attenuation for call progress AOUT pin only.

01 = –12 dB receive path attenuation for call progress AOUT pin only.

10 = Mutes receive path for call progress AOUT pin only.

11 = –6 dB receive path attenuation for call progress AOUT pin only.

4

3

PDL

PDN

Powerdown Line-Side Chip.

0 = Normal operation. Program the clock generator before clearing this bit.

1 = Powers down the Si3017/11/18.

Powerdown PCI DAA.

0 = Normal operation.

1 = Powers down the DAA logic. A DAA soft reset is required to restore normal operation.

The PCI interface is not affected.

2

Reserved

Read returns zero.

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DAA Register Offset 0x37 Sample Rate Control

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

SRC[3:0]

R/W

Reset settings = 0000_0001

Bit

7:4

3:0

Name

Function

Reserved

SRC[3:0]

Read returns zero.

Sample Rate Control.

Sets the sampling rate.

0000 = 7200 Hz

0001 = 8000 Hz

0010 = 8229 Hz

0011 = 8400 Hz

0100 = 9000 Hz

0101 = 9600 Hz

0110 = 10286 Hz

0111 = 12000 Hz

1000 = 13714 Hz

1001 = 16000 Hz

1010–1111 = Reserved

DAA Register Offset 0x38 Reserved

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

Reset settings = 0000_0000

Bit

Name

Function

7:0

Reserved

Read returns zero.

DAA Register Offset 0x39 Reserved

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

Reset settings = 0000_0000

Bit

Name

Function

7:0

Reserved

Read returns zero.

Rev. 1.0

69

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DAA Register Offset 0x3A DAA Control 3

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

DDL

R/W

Reset settings = 0000_0000

Bit

7:1

0

Name

Reserved

DDL

Function

Read returns zero.

Digital Data Loopback.

0 = Normal Operation.

1 = Loopback transmit to receive before the filters. Output data is identical to input data.

DAA Register Offset 0x3B System-side Revision

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

LSID[3:0]

R

SREV[3:0]

R

Reset settings = xxxx_xxxx

Bit

Name

Function

7:4

LSID[3:0]

Line-Side ID.

0000 = Si3017 FCC

0001 = Si3018 Global

0100 = Si3011 TBR21

Other = Reserved

3:0

SREV[3:0]

System-Side Revision.

Four bit value indicating the revision of the Si3052 device.

0011 = Rev C

0100 = Rev D

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DAA Register Offset 0x3C Line-side Status

Bit

D7

D6

FDT

R

D5

D4

D3

D2

LCS[4:0]

R

D1

D0

Name

Type

Reset settings = N/A

Bit

7

Name

Reserved

FDT

Function

Read returns zero.

6

Frame Detect.

0 = Indicates ISOcap link has not established frame lock.

1 = Indicates ISOcap link frame lock is established.

5

Reserved

LCS[4:0]

Read returns zero.

4:0

Loop Current Sense.

Five-bit value returning the loop current in 3.3 mA/bit resolution when the DAA is in an off-

hook state.

00000 = Indicates the loop current is less than required for normal operation.

00100 = Indicates minimum loop current for normal operation.

11111 = Indicates a loop current is > 127 mA.

DAA Register Offset 0x3D Line-Side Revision

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

LREV[3:0]

R

Reset settings = 00xx_xx00

Bit

7:6

5:2

Name

Function

Reserved

LREV[3:0]

Read returns zero.

Line-Side Revision.

Four-bit value indicating the revision of the Si3017/11/18 device.

0011 = Rev C

0100 = Rev D

1:0

Reserved

Read returns zero.

Rev. 1.0

71

Si3052/17/11/18

DAA Register Offset 0x3E Reserved

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

Reset settings = 0000_0000

Bit

Name

Function

7:0

Reserved

Read returns zero.

DAA Register Offset 0x3F TX/RX Gain Control

Bit

D7

D6

D5

ATX[2:0]

R/W

D4

D3

D2

D1

ARX[2:0]

R/W

D0

Name

Type

TXM

R/W

RXM

R/W

Reset settings = 0000_0000

Bit

Name

Function

7

TXM

Transmit Mute (MAP = 0 only).

0 = Transmit signal is not muted.

1 = Mutes the transmit signal.

Analog Transmit Attenuation.

000 = 0 dB attenuation

001 = 3 dB attenuation

010 = 6 dB attenuation

011 = 9 dB attenuation

1xx = 12 dB attenuation

Receive Mute (MAP = 0 only).

0 = Receive signal is not muted.

1 = Mutes the receive signal.

Analog Receive Gain.

000 = 0 dB gain

6:4

ATX[2:0]

3

RXM

2:0

ARX[2:0]

001 = 3 dB gain

010 = 6 dB gain

011 = 9 dB gain

1xx = 12 dB gain

72

Rev. 1.0

Si3052/17/11/18

DAA Register Offset 0x40 International Control 1

Bit

D7

D6

D5

D4

D3

D2

D1

RZ

D0

RT

Name

Type

ACT2

R/W

OHS

R/W

ACT

R/W

IIRE

R/W

DCT[1:0]

R/W

Reset settings = 0000_1000

Bit Name

Function

7

ACT2 AC Termination Select 2.

Works with the ACT bit to select one of four ac terminations.

Si3018 settings:

ACT2

ACT

AC Termination

0

1

0

1

0

1

Real, 600 Ω

Global complex impedance

TBR21 complex impedance

New Zealand complex impedance

The global complex impedance satisfies minimum return loss requirements in a country requiring

a complex ac termination. The other complex impedances can be used for improved return loss

performance.

Si3011 Settings:

ACT2

ACT

AC Termination

0

1

0

1

0

1

Real, 600 Ω

TBR21 complex impedance

Real, 600 Ω

Si3017 Settings:

ACT2

ACT

AC Termination

X

Real, 600 Ω

6

OHS

On-Hook Speed.

This bit, in combination with the OHS2 bit and the SQ[1:0] bits, sets the amount of time for the

line-side device to go on-hook. The on-hook speeds specified are measured from the time the OH

bit is cleared until loop current equals zero.

Si3018 settings:

OHS

OHS2

SQ[1:0]

00

Mean On-Hook Speed

Less than 0.5 ms

3 ms ±10% (meets ETSI standard)

26 ms ±10% (meets Australia spark quenching spec)

0

1

0

1

X

00

11

Si3011 and Si3017 settings:

OHS

OHS2

SQ[1:0]

Mean On-Hook Speed

X

XX

Less than 0.5 ms

5

4

ACT

IIRE

AC Termination Select.

When the ACT2 bit is cleared, the ACT bit selects the following:

0 = Selects the real impedance (600 W).

1 = Selects the complex impedance.

IIR Filter Select.

0 = FIR Filter selected.

1 = IIR Filter selected.

Rev. 1.0

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Si3052/17/11/18

Bit Name

Function

3:2 DCT[1:0] DC Termination Select (MAP = 0 only).

Si3018 settings:

00 = Low voltage mode.

01 = Japan, Lower voltage mode.

10 = FCC, Standard voltage mode.

11 = TBR21, Current limiting mode.

Si3011 settings:

00,10 = FCC, standard voltage mode.

01,11 = TBR21, current limiting mode.

Si3017 settings:

XX = FCC, standard voltage mode.

1

0

RZ

RT

Ringer Impedance.

Si3018 settings:

0 = Maximum (high) ringer impedance.

1 = Synthesize ringer impedance. See “Ringer Impedance and Threshold” on page 34..

Si3011 and Si3017 settings:

X = Maximum (high) ringer impedance.

Ringer Threshold Select.

Satisfies country requirements on ring detection. Signals below the lower level do not generate a

ring detection; signals above the upper level are guaranteed to generate a ring detection.

Si3018 settings:

0 = 11 to 22 Vrms

1 = 17 to 33 V

rms

Si3011 and Si3017 settings:

X = 11 to 22 V

rms

74

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DAA Register Offset 0x41 International Control 2

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

CALZ

R/W

MCAL

R/W

CALD

R/W

OPE

R/W

BTE

R/W

ROV

R/W

BTD

R/W

Reset Settings = 0000_0000

Bit

Name

Function

7

CALZ

Clear Calibration.

0 = Normal operation.

1 = Clear calibration data. This bit must be written back to 0 after being set.

6

5

MCAL

CALD

Manual Calibration.

0 = No calibration.

1 = Initiate calibration.

Auto-Calibration Disable.

0 = Enable auto-calibration.

1 = Disable auto-calibration.

4

3

Reserved

OPE

Read returns zero.

Overload Protect Enable.

0 = Disabled.

1 = Enabled.

When the OPE bit is set, the OPD indicates when an overload condition is occurring. The

OPD bit should always be cleared before going off-hook, and set 25 ms following off-hook

in order to prevent false overload detections.

2

BTE

Billing Tone Protect Enable.

When set, the DAA can detect a billing tone signal on the line and maintain an off-hook

state through the billing tone. If a billing tone is detected, the BTD bit is set to indicate the

event.

0 = Billing tone detection disabled. The BTD bit is not functional.

1 = Billing tone detection enabled. The BTD is functional.

1

0

ROV

BTD

Receive Overload.

Set when the receive input has an excessive input level (i.e., receive pin goes below

ground). Cleared by writing a zero to this location (sticky).

0 = Normal receive input level.

1 = Excessive receive input level.

Billing Tone Detected.

Set if a billing tone is detected. Automatically cleared (non-sticky).

0 = No billing tone detected.

1 = Billing tone detected.

Rev. 1.0

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DAA Register Offset 0x42 International Control 3

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

DIAL

R/W

FJM

R/W

VOL[1:0]

R/W

RFWE

R/W

Reset Settings = 0000_0000

Bit

7

Name

Reserved Read returns zero.

Function

6

DIAL

DTMF Dialing Mode (MAP = 0 only).

Si3018 settings:

0 = Normal operation.

1 = Increase headroom for DTMF dialing.

Si3011 and Si3017 settings:

X = Normal operation.

5

FJM

Force Japan DC Termination Mode (MAP = 0 only).

Si3018 settings:

0 = Normal operation.

1 = When DCT[1:0], is set to 10 (FCC mode), setting this bit forces the Japan dc termination

b

mode.

Si3011 and Si3017 settings:

X = Normal operation.

4:3

VOL[1:0] Line Voltage Adjust (MAP = 0 only).

When set, this bit adjusts the TIP-RING line voltage. Lowering this voltage improves margin

in low voltage countries.

Si3018 settings:

00 = Normal operation.

01 = –0.125 V below Japan mode.

10 = equivalent to DCT[1:0] = 01 (Japan mode).

11 = equivalent to DCT[1:0] = 01 (Japan mode).

Si3011 and Si3017 settings:

XX = Normal operation.

2

1

Reserved Read returns zero.

RFWE

Ring Detector Full-Wave Rectifier Enable.

When RNGV is disabled, this bit controls the ring detector mode. When RNGV is enabled,

this bit configures the RDT bit to either follow the ringing signal detected by the ring valida-

tion circuit, or to follow an unqualified ring detect one-shot signal initiated by a ring-threshold

crossing and terminated by a fixed counter timeout of approximately five seconds.

RNGV

RFWE

RDT bit

0

1

0

1

0

1

Half-Wave

Full-Wave

Validated Ring Envelope

Ring Threshold Crossing One-Shot

0

Reserved Read returns zero.

76

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DAA Register Offset 0x43 International Control 4

Bit

D7

D6

D5

D4

D3

D2

OVL

R

D1

D0

OPD

R

Name

Type

Reset Settings = 0000_0000

Bit Name

7:3 Reserved Read returns zero.

Function

2

OVL

Overload Detected.

Has the same function as ROV but clears itself after the overload is removed. See “Billing Tone

Detection and Receive Overload” on page 35. Masked by the off-hook counter only and is not

affected by the BTE bit.

0 = Normal receive input level.

1 = Excessive receive input level.

1

0

Reserved Read returns zero.

OPD Overload Protect Detect.

This bit is used to indicate that the DAA has detected a line feed overload. The detector firing

threshold depends on the setting of the ILIM bit.

OPD

ILIM

Overload Threshold

160 mA

Overload Status

No overload condition exists

An overload condition has been detected

0

1

0

1

0

1

60 mA

160 mA

60 mA

This bit must be enabled by setting the OPE bit. OPD is a sticky bit and is cleared by writing

OPE to zero.

Rev. 1.0

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DAA Register Offset 0x44 Call Progress Receive Attenuation (MAP = 1)

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

ARM[7:0]

R/W

Reset settings = 0000_0000

Bit

Name

ARM[7:0] AOUT Receive Path Attenuation.

Function

7:0

When decremented from the default setting, these bits linearly attenuate the AOUT receive

path signal used for call progress monitoring. Setting the bits to 0s mutes the AOUT receive

path.

0111_1111 = +6 dB (gain)

0100_0000 = 0 dB

0010_0000 = –6 dB (attenuation)

0001_0000 = –12 dB

...

0000_0000 = Mute

Note: Function available when DAA Register offset 0x31 bit 6 is set to 1 (MAP = 1).

78

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DAA Register Offset 0x45 Call Progress Transmit Attenuation (MAP = 1)

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

ATM[7:0]

R/W

Reset settings = 0000_0000

Bit

Name

Function

7:0

ATM[7:0]

AOUT Receive Path Attenuation.

When decremented from the default setting, these bits linearly attenuate the AOUT

transmit path signal used for call progress monitoring. Setting the bits to 0s mutes the

AOUT transmit path.

0111_1111 = +6 dB (gain)

0100_0000 = 0 dB

0010_0000 = –6 dB (attenuation)

0001_0000 = –12 dB

...

0000_0000 = Mute

Note: Function available when DAA Register offset 0x31 bit 6 is set to 1 (MAP = 1).

Rev. 1.0

79

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DAA Register Offset 0x46 Ring Validation Control 1

Bit

D7

RDLY[1:0]

R/W

D6

D5

D4

D3

D2

D1

D0

Name

Type

RMX[5:0]

R/W

Reset settings = 1001_0110

Bit

Name

Function

7:6

RDLY[1:0]

Ring Delay.

These bits, in combination with the RDLY[2] bit, set the amount of time between when a

ring signal is validated and when a valid ring signal is indicated.

RDLY[2]

RDLY[1:0]

Delay

0

...

1

00

01

10

0 ms

256 ms

512 ms

11

1792 ms

Ring Assertion Maximum Count.

5:0

RMX[5:0]

These bits set the maximum ring frequency for a valid ring signal within a 10% margin of

error. During ring qualification, a timer is loaded with the RAS[5:0] field upon a TIP/RING

event and decrements at a regular rate. When a subsequent TIP/RING event occurs,

the timer value is compared to the RMX[5:0] field, and, if it exceeds the value in

RMX[5:0], the frequency of the ring is too high and the ring is invalidated. The difference

between RAS[5:0] and RMX[5:0] identifies the minimum duration between TIP/RING

events to qualify as a ring, in binary-coded increments of 2.0 ms (nominal). A TIP/RING

event typically occurs twice per ring tone period. At 20 Hz, TIP/RING events would occur

every 1/(2 x 20 Hz) = 25 ms. To calculate the correct RMX[5:0] value for a frequency

range [f_min, f_max], the following equation should be used:

1

--------------------------------------------

RMX[5:0] ≥ RAS[5:0] –

, RMX ≤ RAS

2 × f_max × 2 ms

To compensate for error margin and ensure a sufficient ring detection window, it is rec-

ommended that the calculated value of RMX[5:0] be incremented by 1.

80

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DAA Register Offset 0x47 Ring Validation Control 2

Bit

D7

RDLY[2]

R/W

D6

D5

D4

D3

D2

D1

RCC[2:0]

R/W

D0

Name

Type

RTO[3:0]

R/W

Reset settings = 0010_1101

Bit

Name

Function

7

RDLY[2]

Ring Delay Bit 2.

This bit, in combination with the RDLY[1:0] bits, sets the amount of time between when a

ring signal is validated and when a valid ring signal is indicated.

RDLY[2]

RDLY[1:0]

Delay

0

...

1

00

01

10

0 ms

256 ms

512 ms

11

1792 ms

6:3

RTO[3:0]

Ring Timeout.

Determine when ringing is finished after the most recent ring threshold crossing.

0000 = Invalid

0001 = 128 x 1 = 128 ms

0010 = 128 x 2 = 256 ms

...

1111 = 128 x 15 = 1920 ms

2:0

RCC[2:0]

Ring Confirmation Count.

Determine the time interval over which the ring signal must meet tolerances defined by

RAS[5:0] and RMX[5:0] to be classified as a valid ring signal.

000 = 100 ms

001 = 150 ms

010 = 200 ms

011 = 256 ms

100 = 384 ms

101 = 512 ms

110 = 640 ms

111 = 1024 ms

Rev. 1.0

81

Si3052/17/11/18

DAA Register Offset 0x48 Ring Validation Control 3

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

RNGV

R/W

RAS[5:0]

R/W

Reset settings = 0001_1001

Bit

Name

Function

7

RNGV

Ring Validation Enable.

0 = Ring validation feature is disabled.

1 = Ring validation feature is enabled in normal operating mode and low-power mode.

6

Reserved Read returns zero.

5:0

RAS[5:0] Ring Assertion Time.

These bits set the minimum ring frequency for a valid ring signal. During ring qualifica-

tion, a timer is loaded with the RAS[5:0] field upon a TIP/RING event and decrements at

a regular rate. If a second or subsequent TIP/RING event occurs after the timer has

timed out then the frequency of the ring is too low and the ring is invalidated. The differ-

ence between RAS[5:0] and RMX[5:0] identifies the minimum duration between

TIP/RING events to qualify as a ring, in binary-coded increments of 2.0 ms (nominal). A

TIP/RING event typically occurs twice per ring tone period. At 20 Hz, TIP/RING events

would occur every

1/(2 x 20 Hz) = 25 ms. To calculate the correct RAS[5:0] value for a frequency range

[f_min, f_max], the following equation should be used:

1

-------------------------------------------

RAS[5:0] ≥

2 × f_min × 2 ms

DAA Register Offset 0x49 Resistor Calibration

Bit

D7

D6

D5

RCALD

R/W

D4

D3

D2

D1

D0

Name

Type

Reset settings = 000x_xxxx

Bit

7:6

5

Name

Reserved

RCALD

Function

Read returns zero.

Resistor calibration disable.

0 = Internal resistor calibration enabled.

1 = Internal resistor calibration disabled.

4:0

Reserved

Read returns zero or one.

82

Rev. 1.0

Si3052/17/11/18

DAA Register Offset 0x4A DC Termination Control (MAP = 1)

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

DCV[1:0]

R/W

MINI[1:0]

R/W

ILIM

R/W

DCR

R/W

Reset settings = 0000_0000

Bit

Name

Function

7:6

DCV[1:0]

TIP/RING Voltage Adjust.

Adjust the voltage on the DCT pin of the line-side device, which affects the TIP/RING

voltage on the line. Low voltage countries should use a lower TIP/RING voltage. Raising

the TIP/RING voltage improves signal headroom.

Si3018 settings:

DCV[1:0] DCT Pin Voltage

00

01

10

11

3.1 V

3.2 V

3.35 V

3.5 V

Si3011 and Si3017 settings:

DCV[1:0] DCT Pin Voltage

XX

3.35 V

5:4

MINI[1:0]

Minimum Operational Loop Current.

Adjusts the minimum loop current so the DAA can operate. Increasing the minimum

operational loop current improves signal headroom at a lower TIP/RING voltage.

Si3018 settings:

MINI[1:0] Min Loop Current

00

01

10

11

10 mA

12 mA

14 mA

16 mA

Si3011 and Si3017 settings:

MINI[1:0] Min Loop Current

XX

10 mA

3:2

1

Reserved

ILIM

Read returns zero.

Current Limiting Enable.

Si3018 and Si3011 settings:

0 = Current limiting mode disabled.

1 = Current limiting mode enabled. Limits loop current to a maximum of 60 mA per the

TBR21 standard.

Si3017 settings:

X = Current limiting mode disabled.

0

DCR

DC Impedance Selection.

0 = 50 W dc termination is selected. Use this mode for all standard applications.

1 = 800 Ω dc termination is selected.

Note: Function available when DAA Registers offset 0x31 bit 6 is set to 1 (MAP = 1).

Rev. 1.0

83

Si3052/17/11/18

DAA Register Offset 0x4B Reserved

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

Reset settings = 0000_xxxx

Bit

Name

Function

7:0

Reserved

Read returns zero or one.

DAA Register Offset 0x4C Reserved

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

Reset settings = 0000_0000

Bit

Name

Function

7:0

Reserved

Read returns zero.

DAA Register Offset 0x4D Reserved

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

Reset settings = 0000_0000

Bit

7:0

Name

Function

Reserved

Read returns zero.

84

Rev. 1.0

Si3052/17/11/18

DAA Register Offset 0x4E Reserved

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

Reset settings = 0000_0000

Bit

Name

Function

7:0

Reserved

Read returns zero.

DAA Register Offset 0x4F DAA Control 4

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

FOH[1:0]

R/W

OHS2

R/W

Reset settings = 0010_0000

Bit

Name

Reserved Read returns zero.

Function

7

6:5 FOH[1:0] Fast Off-Hook Selection.

Determines the length of the off-hook counter.

00 = 512 ms

01 = 128 ms (default)

10 = 64 ms

11 = 8 ms

4

3

Reserved Read returns zero.

OHS2

On-Hook Speed 2.

Si3018 settings:

This bit, in combination with the OHS bit and the SQ[1:0] bits on-hook speeds specified are

measured from the time the OH bit is cleared until loop current equals zero.

OHS

OHS2

SQ[1:0] Mean On-Hook Speed

0

1

0

1

X

00

11

Less than 0.5 ms

3 ms ±10% (meets ETSI standard)

26 ms ±10% (meets Australia spark quenching spec)

Si3011 and Si3017 settings:

OHS

X

OHS2

X

SQ[1:0] Mean On-Hook Speed

XX Less than 0.5 ms

2:0 Reserved Read returns zero.

Rev. 1.0

85

Si3052/17/11/18

DAA Register Offset 0x5D Programmable Hybrid Register 1 (MAP = 1)

Bit

D7

D6

D5

D4

HYB1[7:0]

R/W

D3

D2

D1

D0

Name

Type

Reset settings = 0000_0000

Bit

Name

Function

7:0

HYB1[7:0]

Hybrid 1.

Programmed with a coefficient value to adjust the hybrid response to reduce near-end

echo. This register represents the first tap in the four-tap filter. When this register is set

to 0s, this filter stage does not effect on the hybrid response. Refer to “AN84: Digital

Hybrid with the Si305x DAAs” for more information on selecting coefficients for the pro-

grammable hybrid.

Note: Function available when DAA Registers offset 0x31 bit 6 is set to 1 (MAP = 1).

DAA Register Offset 0x5E Programmable Hybrid Register 2 (MAP = 1)

Bit

D7

D6

D5

D4

HYB2[7:0]

R/W

D3

D2

D1

D0

Name

Type

Reset settings = 0000_0000

Bit

Name

Function

7:0

HYB2[7:0]

Hybrid 2.

Programmed with a coefficient value to adjust the hybrid response to reduce near-end

echo. This register represents the first tap in the four-tap filter. When this register is set

to 0s, this filter stage does not effect on the hybrid response. Refer to “AN84: Digital

Hybrid with the Si305x DAAs” for more information on selecting coefficients for the pro-

grammable hybrid.

Note: Function available when DAA Registers offset 0x31 bit 6 is set to 1 (MAP = 1).

86

Rev. 1.0

Si3052/17/11/18

DAA Register Offset 0x5F Programmable Hybrid Register 3 (MAP = 1)

Bit

D7

D6

D5

D4

HYB3[7:0]

R/W

D3

D2

D1

D0

Name

Type

Reset settings = 0000_0000

Bit

Name

Function

7:0

HYB3[7:0]

Hybrid 3.

Programmed with a coefficient value to adjust the hybrid response to reduce near-end

echo. This register represents the first tap in the four-tap filter. When this register is set

to 0s, this filter stage does not effect on the hybrid response. Refer to “AN84: Digital

Hybrid with the Si305x DAAs” for more information on selecting coefficients for the pro-

grammable hybrid.

Note: Function available when DAA Registers offset 0x31 bit 6 is set to 1 (MAP = 1).

DAA Register Offset 0x60 Programmable Hybrid Register 4 (MAP = 1)

Bit

D7

D6

D5

D4

HYB4[7:0]

R/W

D3

D2

D1

D0

Name

Type

Reset settings = 0000_0000

Bit

Name

Function

7:0

HYB4[7:0]

Hybrid 4.

Programmed with a coefficient value to adjust the hybrid response to reduce near-end

echo. This register represents the first tap in the four-tap filter. When this register is set

to 0s, this filter stage has no effect on the hybrid response. Refer to “AN84: Digital

Hybrid with the Si305x DAAs” for more information on selecting coefficients for the pro-

grammable hybrid.

Note: Function available when DAA Registers offset 0x31 bit 6 is set to 1 (MAP = 1).

Rev. 1.0

87

Si3052/17/11/18

DAA Register Offset 0x61 Programmable Hybrid Register 5 (MAP = 1)

Bit

D7

D6

D5

D4

HYB5[7:0]

R/W

D3

D2

D1

D0

Name

Type

Reset settings = 0000_0000

Bit

Name

Function

7:0

HYB5[7:0]

Hybrid 5.

Programmed with a coefficient value to adjust the hybrid response to reduce near-end

echo. This register represents the first tap in the four-tap filter. When this register is set

to 0s, this filter stage does not effect on the hybrid response. Refer to “AN84: Digital

Hybrid with the Si305x DAAs” for more information on selecting coefficients for the pro-

grammable hybrid.

Note: Function available when DAA Registers offset 0x31 bit 6 is set to 1 (MAP = 1).

DAA Register Offset 0x62 Programmable Hybrid Register 6 (MAP = 1)

Bit

D7

D6

D5

D4

HYB6[7:0]

R/W

D3

D2

D1

D0

Name

Type

Reset settings = 0000_0000

Bit

Name

Function

7:0

HYB6[7:0]

Hybrid 6.

Programmed with a coefficient value to adjust the hybrid response to reduce near-end

echo. This register represents the first tap in the four-tap filter. When this register is set

to all 0s, this filter stage does not effect on the hybrid response. Refer to “AN84: Digital

Hybrid with the Si305x DAAs” for more information on selecting coefficients for the pro-

grammable hybrid.

Note: Function available when DAA Registers offset 0x31 bit 6 is set to 1 (MAP = 1).

88

Rev. 1.0

Si3052/17/11/18

DAA Register Offset 0x63 Programmable Hybrid Register 7 (MAP = 1)

Bit

D7

D6

D5

D4

HYB7[7:0]

R/W

D3

D2

D1

D0

Name

Type

Reset settings = 0000_0000

Bit

Name

Function

7:0

HYB7[7:0]

Hybrid 7.

Programmed with a coefficient value to adjust the hybrid response to reduce near-end

echo. This register represents the first tap in the four-tap filter. When this register is set

to all 0s, this filter stage does not effect on the hybrid response. Refer to “AN84: Digital

Hybrid with the Si305x DAAs” for more information on selecting coefficients for the pro-

grammable hybrid.

Note: Function available when DAA Registers offset 0x31 bit 6 is set to 1 (MAP = 1).

DAA Register Offset 0x64 Programmable Hybrid Register 8 (MAP = 1)

Bit

D7

D6

D5

D4

HYB8[7:0]

R/W

D3

D2

D1

D0

Name

Type

Reset settings = 0000_0000

Bit

Name

Function

Hybrid 8.

7:0

HYB8[7:0]

Programmed with a coefficient value to adjust the hybrid response to reduce near-end

echo. This register represents the first tap in the four-tap filter. When this register is set

to all 0s, this filter stage does not effect on the hybrid response. Refer to “AN84: Digital

Hybrid with the Si305x DAAs” for more information on selecting coefficients for the pro-

grammable hybrid.

Note: Function available when DAA Registers offset 0x31 bit 6 is set to 1 (MAP = 1).

Rev. 1.0

89

Si3052/17/11/18

DAA Register Offset 0x6B Spark Quenching Control

Bit

Name

Type

D7

D6

D5

D4

D3

D2

D1

D0

0

SQ1

R/W

0

SQ0

R/W

0

Reset settings = 0000_0000

Bit

7

Name

Reserved Always write this bit to zero.

Spark Quenching.

Function

6, 4

SQ[1:0]

These bits, in combination with the OHS bit and the OHS2 bit, set the amount of time for the

line-side device to go on-hook. The on-hook speeds specified are measured from the time

the OH bit is cleared until loop current equals zero.

Si3018 settings:

OHS

OHS2

SQ[1:0]

00

Mean On-Hook Speed

Less than 0.5 ms

3 ms ±10% (meets ETSI standard)

26 ms ±10% (meets Australia spark quenching spec)

0

1

0

1

X

11

Si3011 and Si3017 settings:

OHS

OHS2

SQ[1:0]

Mean On-Hook Speed

X

XX

Less than 0.5 ms

5

Reserved Always write this bit to zero.

Reserved Always write these bits to zero.

3:0

90

Rev. 1.0

Si3052/17/11/18

Pin Descriptions: Si3052

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

1

2

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

3

4

5

6

Si3052

64-Lead TQFP

(epad)

7

8

9

10

11

12

13

14

15

16

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Table 24. Pin Descriptions

Pin #

Pin Name Description

3.3/5 V IO Digital Supply Input.

1

2

V

IO

AD[17]

AD[16]

C/BE[2]

Address/Data Bit Input/Output.

Multiplexed address/data bit for the PCI interface.

3

4

Address/Data Bit Input/Output.

Multiplexed address/data bit for the PCI interface.

Command/Byte Enable Bit Input/Output.

Multiplexed command/byte enables for the PCI interface. The pin is an output during

master operation and an input during slave operation. The pin indicates cycle type dur-

ing the address phase and byte enable during the data phase of a transaction.

5

6

FRAME

IRDY

Cycle Frame Indicator Input/Output.

PCI bus master output indicating the beginning and duration of a bus transfer.

Initiator Ready Input/Output.

PCI bus master output indicating that the initiator device is ready to transmit or receive

data.

7

8

TRDY

DEVSEL

STOP

Target Ready Input/Output.

PCI bus target output indicating that the target device is ready to transmit or receive

data.

Device Select Input/Output.

PCI bus target output indicating the device has decoded the address of the current

transaction that matches the target device’s select range.

9

Stop Transaction Input/Output.

PCI bus target output indicating a request to the bus master to stop the current transac-

tion.

10

PERR

Parity Error Input/Output.

Reports PCI bus data parity errors.

Rev. 1.0

91

Si3052/17/11/18

Table 24. Pin Descriptions (Continued)

Pin #

Pin Name Description

11

SERR

System Error Input/Output.

Reports PCI bus system errors.

12

13

PAR

Address/Data Parity Bit Input/Output.

Even parity across AD[31:0] and C/BE[3:0] for address and data bus phases. The par-

ity is delayed one PCI clock cycle from the corresponding address or data bus phase.

C/BE[1]

Command/Byte Enable Bit Input/Output.

Multiplexed command/byte enables for the PCI interface. The pin is an output during

master operation and an input during slave operation. The pin indicates cycle type dur-

ing the address phase and byte enable during the data phase of a transaction.

14

15

AD[15]

AD[14]

Address/Data Bit Input/Output.

Multiplexed address/data bit for the PCI interface.

Address/Data Bit Input/Output.

Multiplexed address/data bit for the PCI interface.

16

17

V

3.3/5 V Digital Supply Input.

IO

AD[13]

AD[12]

AD[11]

AD[10]

AD[09]

AD[08]

C/BE[0]

Address/Data Bit Input/Output.

Multiplexed address/data bit for the PCI interface.

18

19

20

21

22

23

Address/Data Bit Input/Output.

Multiplexed address/data bit for the PCI interface.

Address/Data Bit Input/Output.

Multiplexed address/data bit for the PCI interface.

Address/Data Bit Input/Output.

Multiplexed address/data bit for the PCI interface.

Address/Data Bit Input/Output.

Multiplexed address/data bit for the PCI interface.

Address/Data Bit Input/Output.

Multiplexed address/data bit for the PCI interface.

Command/Byte Enable Bit Input/Output.

Multiplexed command/byte enables for the PCI interface. The pin is an output during

master operation and an input during slave operation. The pin indicates cycle type dur-

ing the address phase and byte enable during the data phase of a transaction.

24

AD[07]

Address/Data Bit Input/Output.

Multiplexed address/data bit for the PCI interface.

25

26

V

3.3/5 V IO Digital Supply Input.

IO

AD[06]

Address/Data Bit Input/Output.

Multiplexed address/data bit for the PCI interface.

92

Rev. 1.0

Si3052/17/11/18

Table 24. Pin Descriptions (Continued)

Pin #

Pin Name Description

27

AD[05]

AD[04]

AD[03]

AD[02]

AD[01]

AD[00]

INTA

Address/Data Bit Input/Output.

Multiplexed address/data bit for the PCI interface.

28

29

30

31

32

33

Address/Data Bit Input/Output.

Multiplexed address/data bit for the PCI interface.

Address/Data Bit Input/Output.

Multiplexed address/data bit for the PCI interface.

Address/Data Bit Input/Output.

Multiplexed address/data bit for the PCI interface.

Address/Data Bit Input/Output.

Multiplexed address/data bit for the PCI interface.

Address/Data Bit Input/Output.

Multiplexed address/data bit for the PCI interface.

PCI Interrupt Output (Open Drain).

Level triggered interrupt pin for internal device interrupt sources.

34

35

3.3VAUX

XOUT

3.3 Vaux Sense Input.

Crystal Output.

Connection to 16.384 MHz crystal.

36

37

38

XIN

Crystal Input.

Connection to 16.384 MHz crystal.

RST

PCI Device Reset Input.

PCI bus master reset signal.

CLKRUN/ System Clock Control Input/Output (Open Drain).

PNPID/

EE_SD

An optional PCI signal defined for mobile applications. As an input, high indicates that

PCICLK is active. The signal is driven low when the bus controller wants to stop PCI-

CLK. As an output, low indicates a request to activate PCICLK. If unused, this pin

requires a weak pulldown.

PCI PnP ID select Input.

Resistor selection for PCI Plug-n-Play (PnP) identification.

EPROM Serial Data Input/Output.

Serial data input/output to external PnP EPROM.

39

AOUT/

PNPID/

EE_SC

Call Progress Monitor Output.

Pulse-Width Modulation (PWM) signal for driving a call progress speaker.

PCI PnP ID Select Input.

Resistor selection for PCI Plug-n-Play (PnP) Identification.

EPROM Serial Clock Output.

Serial clock output to external PnP EPROM.

Rev. 1.0

93

Si3052/17/11/18

Table 24. Pin Descriptions (Continued)

Pin #

Pin Name Description

40

PME

Power Management Event Output (Open Drain).

Indicates a PCI power management event. This pin powers up in the high impedance

state.

41

42

C2A

C1A

Isolation Capacitor 2 A Input/Output.

Differential isolation for communication with the DAA line-side device.

Isolation Capacitor 1 A Input/Output.

Differential isolation for communication with the DAA line-side device.

43

44

45

VA

VD

Voltage Regulator Bypass Output.

3.3 V Digital Supply Input.

PCI Bus Clock Input.

PCICLK

PCI bus clock for all bus transaction timing. All synchronous signals are driven and

sampled on the rising edge of this clock.

46

47

GNT

REQ

Master Grant Input.

Indicates that the system arbiter has granted PCI bus access.

Master Request Output (Tri-State).

Indicates a request to the system arbiter for access to the PCI bus. When RST is low,

this pin is high-impedance.

48

49

50

51

52

53

54

AD[31]

AD[30]

AD[29]

AD[28]

AD[27]

AD[26]

AD[25]

Address/Data Bit Input/Output.

Multiplexed address/data bit for the PCI interface.

Address/Data Bit Input/Output.

Multiplexed address/data bit for the PCI interface.

Address/Data Bit Input/Output.

Multiplexed address/data bit for the PCI interface.

Address/Data Bit Input/Output.

Multiplexed address/data bit for the PCI interface.

Address/Data Bit Input/Output.

Multiplexed address/data bit for the PCI interface.

Address/Data Bit Input/Output.

Multiplexed address/data bit for the PCI interface.

Address/Data Bit Input/Output.

Multiplexed address/data bit for the PCI interface.

55

56

V

3.3/5 V ID Digital Supply Input.

IO

AD[24]

Address/Data Bit Input/Output.

Multiplexed address/data bit for the PCI interface.

94

Rev. 1.0

Si3052/17/11/18

Table 24. Pin Descriptions (Continued)

Pin #

Pin Name Description

57

C/BE[3]

Command/Byte Enable Bit Input/Output.

Multiplexed command/byte enables for the PCI interface. The pin is an output during

master operation and an input during slave operation. The pin indicates cycle type dur-

ing the address phase and byte enable during the data phase of a transaction.

58

59

IDSEL

AD[23]

AD[22]

AD[21]

AD[20]

AD[19]

AD[18]

GND

Initialize Device Select Input.

Chip select during PCI configuration register read/write cycles.

Address/Data Bit Input/Output.

Multiplexed address/data bit for the PCI interface.

60

Address/Data Bit Input/Output.

Multiplexed address/data bit for the PCI interface.

61

Address/Data Bit Input/Output.

Multiplexed address/data bit for the PCI interface.

62

Address/Data Bit Input/Output.

Multiplexed address/data bit for the PCI interface.

63

Address/Data Bit Input/Output.

Multiplexed address/data bit for the PCI interface.

64

Address/Data Bit Input/Output.

Multiplexed address/data bit for the PCI interface.

epad

Exposed Die Paddle Ground.

Rev. 1.0

95

Si3052/17/11/18

Pin Descriptions: Si3017/11/18

16

15

1

2

DCT2

IGND

QE

DCT

RX

DCT3

3

4

5

6

14

IB

13

12

11

QB

QE2

SC

C1B

C2B

VREG

RNG1

VREG2

RNG2

7

8

10

9

Table 25. Si3017/11/18 Pin Descriptions

Description

Pin #

Pin Name

1

QE

Transistor Emitter.

Connects to the emitter of Q3.

2

3

4

5

6

7

8

DCT

RX

DC Termination.

Provides dc termination to the telephone network.

Receive Input.

Serves as the receive side input from the telephone network.

Internal Bias 1.

IB

Provides internal bias.

Isolation Capacitor 1B.

C1B

Connects to one side of isolation capacitor C1 and communicates with the Si3052.

Isolation Capacitor 2B.

C2B

Connects to one side of isolation capacitor C2 and communicate with the Si3052.

Voltage Regulator.

Connects to an external capacitor to provide bypassing for an internal power supply.

Ring 1.

VREG

RNG1

Connects through a capacitor to the RING lead of the telephone line. Provides the ring

and caller ID signals to the Si3052.

9

RNG2

Ring 2.

Connects through a capacitor to the TIP lead of the telephone line. Provides the ring

and caller ID signals to the Si3052.

10

11

12

13

14

15

16

VREG2

SC

Voltage Regulator 2.

Connects to an external capacitor to provide bypassing for an internal power supply.

Circuit Enable.

Enables transistor network.

Transistor Emitter 2.

QE2

Connects to the emitter of Q4.

Transistor Base.

QB

Connects to the base of transistor Q3. Used to go on- and off-hook.

DC Termination 3.

DCT3

IGND

DCT2

Provides the dc termination to the telephone network.

Isolated Ground.

Connects to ground on the line-side interface.

DC Termination 2.

Provides dc termination to the telephone network.

96

Rev. 1.0

Si3052/17/11/18

Ordering Guide

System-Side

Line-Side

Region

Interface

Temperature

Part #

Package

TQFP

Part #

Package

SOIC

FCC

PCI

Si3052-KQ

Si3054-KS

Si3054-KT

Si3017-KS

Si3011-KS

Si3018-KS

Si3018-KT

Si3018-KS

Si3018-KT

0 to 70 °C

TBR21

Global

TQFP

SOIC

PCI

TQFP

SOIC

PCI

TQFP

TSSOP

SOIC

AC-Link

SOIC

TSSOP

Rev. 1.0

97

Si3052/17/11/18

Package Outline: 64-Pin TQFP

Figure 28 illustrates the package details for the Si3052. Table 26 lists the values for the dimensions shown in the

illustration.

0° Min.

64

49

0.08/0.20 R

1

48

A2

A1

GAUGE PLANE

0-7°

E1

E

0.08

R. Min.

L

0.20 Min.

e

16

33

1.00 REF

Detail A

17

32

D1

D

Exposed Pad

4.5 x 4.5 mm

b

with lead finish

See Detail A

A

0.09/0.20

0.09/0.16

base metal

b1

See Detail B

Detail B

Figure 28. 64-Pin Thin Quad Flat Package (TQFP)

Table 26. 64-Pin Package Diagram Dimensions

Symbol

Millimeters

Nom

Min

—

Max

1.20

0.15

1.05

A

A1

A2

D

—

0.05

0.95

—

1.00

12.00 BSC

10.00 BSC

12.00 BSC

10.00 BSC

0.60

D1

E

E1

L

0.45

0.75

e

0.50 BSC

0.22

b

0.17

0.27

0.23

b1

0.20

98

Rev. 1.0

Si3052/17/11/18

Package Outline: 16-Pin SOIC

Figure 29 illustrates the package details for the Si3017/11/18. Table 27 lists the values for the dimensions shown in

the illustration.

16

9

8

h

E

H

0.010

GAUGE PLANE

θ

1

L

B

Detail F

D

C

A2

A1

A

e

See Detail F

γ

Seating Plane

Figure 29. 16-pin Small Outline Integrated Circuit (SOIC) Package

Table 27. Package Diagram Dimensions

Millimeters

Symbol

Typical*

Min

Max

A

A1

A2

B

C

D

E

e

1.35

1.75

!

.10

1.30

.33

.25

1.50

.51

.19

.25

!

9.80

3.80

1.27 BSC

5.80

.25

10.01

4.00

—

H

h

6.20

.50

L

.40

1.27

0.10

8º

γ

—

θ

0º

!

*Note: Typical parameters are for information

purposes only.

Rev. 1.0

99

Si3052/17/11/18

Document Change List

Revision 0.86 to Revision 1.0

! Si3017 descriptions added.

! Si3011 descriptions added.

! Table 2 on page 5 TBD values defined.

! Table 3 on page 6 TBD values defined.

! Figure 13 on page 16 updated.

! Figure 14 on page 17 updated.

! "Bill of Materials" on page 18 updated.

! Figure 14 on page 17 updated.

! Table 14 on page 28 updated.

! "Initialization" on page 30 updated.

! "Parallel Handset Detection" on page 30 updated.

! Table 15 on page 31 updated.

! "DC Termination" on page 32 updated.

! "Ring Detection" on page 33 updated.

! "DTMF Dialing" on page 34 updated.

! "Billing Tone Detection and Receive Overload" on

page 35 updated.

! "On-Hook Line Monitor" on page 36 updated.

! "Overload Detection" on page 37 updated.

! "In-Circuit Testing" on page 38 updated.

! "Revision Identification" on page 38 updated.

! "Register Map" on page 38 updated.

! Table 19 and Table 20 added.

! Register descriptions updated.

100

Rev. 1.0

Si3052/17/11/18

Notes:

Rev. 1.0

101

Si3052/17/11/18

Contact Information

Silicon Laboratories Inc.

4635 Boston Lane

Austin, TX 78735

Tel: 1+(512) 416-8500

Fax: 1+(512) 416-9669

Toll Free: 1+(877) 444-3032

Email: productinfo@silabs.com

Internet: www.silabs.com

The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.

Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from

the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features

or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep-

resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-

quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to

support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per-

sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap-

plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.

Silicon Laboratories, Silicon Labs, ISOmodem, and ISOcap are trademarks of Silicon Laboratories Inc.

Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.

102

Rev. 1.0


型号：	SI3011-KS
厂家：	SILICON
描述：	Consumer Circuit, PDSO16, SOIC-16 光电二极管商用集成电路
文件：	总102页 (文件大小：1759K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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