SI32192-A-FM1 [SILICON]
Digital SLIC,;
| 型号： | SI32192-A-FM1 |
| 厂家： | 
SILICON |
| 描述： | Digital SLIC, 电信 电信集成电路 |
| 文件： | 总32页 (文件大小：685K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
Si3219x: ProSLIC Single FXS Solution
®
ProSLIC Single-Channel FXS Solutions
KEY FEATURES
The Si3219x Single FXS ProSLIC® devices implement a complete foreign exchange sta-
• Complete FXS solution in a single 4 x 6
mm package
tion (FXS) telephony interface solution in a single package that conforms to all relevant
global specifications. The Si3219x ProSLIC ICs operate from a 3.3 V supply and have a
3-wire ISI digital interface with 1.8 to 3.3 V I/O. The Si3219x devices are designed to
operate with a capacitive boost tracking battery supply for lower power, cost, and foot-
print than other tracking supplies in the industry. Self-testing and metallic loop testing
(MLT) are facilitated by the built-in DSP, monitor ADC, and test load. The devices are
available with wideband audio for better-than-PSTN voice quality and DTMF detection.
The Si3219x devices are available in a 4 x 6 mm, 38-pin QFN package.
• Performs all BORSCHT functions
• Ideal for short- or medium-loop
applications
• Ultra-low power consumption
• Patented low-power ringing
• Adaptive ringing
• Dynamic overhead control
• Ringing current limiting
Applications:
• Simplified configuration and diagnostics
• Supported by ProSLIC API
• VoIP Gateways and Routers
• xDSL IADs
• Audio diagnostics with loopback
• Integrated test load
• Optical Network Terminals/Units (ONT/U)
• Analog Terminal Adapters (ATA)
• Cable eMTA
• Global programmability
• Wideband voice support
• On-hook transmission
• Wireless Fixed Terminals (WFT)
• Wireless Local Loop (WLL)
• WiMAX CPE
• Loop or ground start operation
• Smooth polarity reversal
• A-Law/µ-Law companding, linear PCM
• Flexible integrated tracking dc-dc controller
supporting patent-pending low-cost
capacitive boost configuration
SLIC
Linefeed
Control
CODEC
ADC
DTMF and
TIP
Tone Gen
• Software-programmable parameters:
• Ringing frequency, amplitude, cadence,
and waveshape
FXS
Caller ID
RING
Linefeed
Monitor
DAC
Host Interface
3-wire ISI
• Two-wire ac impedance
• Transhybrid balance
Ringing
Generator
DSP
• DC current loop feed (10–45 mA)
• Loop closure and ring trip thresholds
• Ground key detect threshold
• Pulse metering
Line Diagnostics
DC-DC Controller
PLL
• DTMF generation
Si3219x
• DTMF detection (Si32193)
• 3.3 V operation
• Support for 1.8 V I/O
• Maximum battery up to –100 V
• Pb-free/RoHS-compliant packaging
• 3-wire Integrated Serial Interface (ISI)
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Table of Contents
1. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Product Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2. Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4. FXS Features
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1 DC Feed Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . .18
4.2 Linefeed Operation States . . . . . . . . . . . . . . . . . . . . . . . . . .18
4.3 Line Voltage and Current Monitoring. . . . . . . . . . . . . . . . . . . . . . .18
4.4 Power Monitoring and Power Fault Detection. . . . . . . . . . . . . . . . . . . .18
4.5 Thermal Overload Shutdown . . . . . . . . . . . . . . . . . . . . . . . . .19
4.6 Loop Closure Detection . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.7 Ground Key Detection . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.8 Ringing Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.9 Polarity Reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.10 Two-wire Impedance Synthesis . . . . . . . . . . . . . . . . . . . . . . . .20
4.11 Transhybrid Balance Figure . . . . . . . . . . . . . . . . . . . . . . . . .20
4.12 Tone Generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.13 DTMF Detection (Si32193 Only). . . . . . . . . . . . . . . . . . . . . . . .20
4.14 Pulse Metering . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.15 DC-DC Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.16 Wideband Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.17 Test Facilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
5. System Interfaces
. . . . . . . . . . . . . . . . . . . . . . . . . . . .22
5.1 Integrated Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . .22
5.2 Input/Output Voltage Selection . . . . . . . . . . . . . . . . . . . . . . . .22
6. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.1 Pin Descriptions: 38 Pin QFN (Si32192/3) . . . . . . . . . . . . . . . . . . . . .23
7. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.1 Package Outline: 38-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . .26
8. Land Pattern
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
8.1 Land Pattern: 38-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . .28
9. Top Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9.1 Top Marking 38-pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . .30
10. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
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Si3219x: ProSLIC Single FXS Solution
Ordering Guide
1. Ordering Guide
Table 1.1. Si3219x Ordering Guide
Package Type2
Max VBAT
P/N
Description
Temperature
Wideband FXS, ISI interface,
parametric MLT
Si32192-A-FM1
QFN38
–100 V
–100 V
–100 V
0 to 70 °C
Wideband FXS, ISI interface,
parametric MLT
Si32192-A-GM1
Si32193-A-FM1
QFN38
QFN38
–40 to 85 °C
0 to 70 °C
Wideband FXS, ISI interface,
parametric MLT, DTMF detection
Wideband FXS, ISI interface,
parametric MLT, DTMF detection
Si32193-A-GM1
Si32192-A-ZM1
QFN38
QFN38
–100 V
–100 V
–40 to 85 °C
0 to 70 °C
Wideband FXS, ISI interface,
parametric MLT, customer-specific
Si32192-A-ZM2
Si32193-A-ZM1
Wideband FXS, ISI interface,
parametric MLT, customer-specific
QFN38
QFN38
–100 V
–100 V
0 to 70 °C
0 to 70 °C
Wideband FXS, ISI interface,
parametric MLT, DTMF detection, custom-
er-specific
Si32193-A-ZM2
Wideband FXS, ISI interface,
parametric MLT, DTMF detection, custom-
er-specific
QFN38
–100 V
0 to 70 °C
Note:
1. Adding the suffix "R" to the part number (e.g. Si3219x-A-FMR) denotes tape and reel.
2. QFN - Quad-Flat No-leads.
Table 1.2. Ordering GuideSi3219x Evaluation Kits
VBAT Max1
Part Number
Description
Si32193ACB10SL0EVB
ISI Wideband FXS with DTMF detection and low-cost capacitive boost dc-dc convert-
er EVB
–100 V
Note:
1. EVB VBAT max may be limited by BOM option.
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Si3219x: ProSLIC Single FXS Solution
Ordering Guide
1.1 Product Identification
The product identification number is a finished goods part number or is specified by a finished goods part number, such as a special
customer part number.
Example:
Si32193-A-FM1R
Product Designator
Shipping Option
Blank = Trays
R = Tape and Reel
Revision
Package Type
M1 or M2 = QFN
Part Type / Lead Finish
F = Commercial / RoHS-Compliant
G = Industrial / RoHS-Compliant
Z = Commercial / RoHS-Compliant, Customer-Specific
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Si3219x: ProSLIC Single FXS Solution
Functional Description
2. Functional Description
SLIC
Linefeed
Control
CODEC
ADC
DTMF and
TIP
Tone Gen
FXS
RING
Caller ID
Linefeed
Monitor
DAC
Host Interface
3-wire ISI
Ringing
Generator
DSP
Line Diagnostics
DC-DC Controller
PLL
Si3219x
Figure 2.1. Si3219x Functional Block Diagram
The Si3219x series provides all SLIC, codec, DTMF detection, and signal generation functions needed for one complete analog tele-
phone interface. The Si3219x performs all battery, over-voltage, ringing, supervision, codec, hybrid, and test (BORSCHT) functions; it
also supports extensive metallic loop and self-test capabilities.
The Si3219x supports wideband audio (150 Hz–6.8 kHz) compliant with PKT-SP-HDV-104-120823, and is configurable to support the
full ITU-T-G.722-201209 bandwidth (50 Hz–7 kHz). The wideband mode provides an expanded audio band with a 16 kHz sample rate
for enhanced audio quality.
The Si3219x series supports a 3-wire ISI digital interface.
The Si3219x incorporates a programmable dc-dc converter controller that reacts to line conditions to provide the optimal battery voltage
required for each line-state. Si3219x ICs are available with voltage ratings of –100 V.
Programmable on-hook voltage, programmable off-hook loop current, reverse polarity operation, loop or ground start operation, and on-
hook transmission are supported. Loop current and voltage are continuously monitored by an integrated monitoring ADC.
The Si3219x single ProSLIC devices support ringing with or without a programmable dc offset and can operate in low-power ringing
and adaptive-ringing modes. The available voltage offset, frequency, waveshape, and cadence options are designed to ring the widest
variety of terminal devices and to reduce external controller requirements.
A complete audio transmit and receive path is integrated, including ac impedance and hybrid gain. These features are software-pro-
grammable, allowing a single hardware design to meet global requirements.
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Si3219x: ProSLIC Single FXS Solution
Electrical Specifications
3. Electrical Specifications
Table 3.1. Recommended Operating Conditions
Parameter
Symbol
Test Condition
Min
0
Typ
25
Max
70
Unit
°C
F-grade,
Z-grade
TA
Ambient Temperature
G-grade
–40
—
25
85
°C
Internally
Limited
TJHV
Silicon Junction Temperature, High Voltage Die
Continuous
Continuous
—
°C
TJLV
VDDD, VDDA
VBAT
Silicon Junction Temperature, Low Voltage Die
Supply Voltages
—
—
3.3
—
125
3.47
–15
°C
V
3.13
–100
1.71
Battery Voltage2
IO Supply Voltage
Note:
V
VDDIO
—
3.47
V
1. All minimum and maximum specifications apply across the recommended operating conditions. Typical values apply at nominal
supply voltages and an operating temperature of 25 °C unless otherwise stated.
2. Minimum and maximum battery voltage limits are dependent upon loop conditions and dc-dc converter configuration.
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Si3219x: ProSLIC Single FXS Solution
Electrical Specifications
Table 3.2. Power Supply Characteristics
Parameter
Supply Currents:
Symbol
IDD
Test Condition
Min
—
—
—
—
—
—
—
—
—
Typ
5.13
—
Max
—
—
—
—
—
—
—
—
—
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
VT and VR = Hi-Z , RSTB = 0
Reset
IVBAT
IDD
IVBAT
IDD
IVBAT
IDD
IVBAT
IDD
11.15
0.6
Supply Currents:
VT and VR = Hi-Z
High Impedance, Open
VTR = –48 V,
Automatic Power Save Mode Enabled
VTR = –48 V,
11.6
0.6
Supply Currents:
Forward/Reverse, On-hook
30.44
2.1
Supply Currents:
Forward/Reverse, On-hook
Automatic Power Save Mode Disabled
VT or VR = –48 V
11.5
Supply Currents:
VR or VT = Hi-Z,
Tip/Ring Open, On-hook
IVBAT
—
—
—
0.4
30.6
1.3
—
—
—
mA
mA
mA
Automatic Power Save Mode Enabled
VT or VR = –48 V
IDD
Supply Currents:
VR or VT = Hi-Z,
Tip/Ring Open, On-hook
IVBAT
Automatic Power Save Mode Disabled
IDD
IVBAT
IDD
—
—
—
44.7
2.9
—
—
—
mA
mA
mA
Supply Currents:
VTR = 48 V
Forward/Reverse OHT, On-hook
Supply Currents:
44.4
ILOOP = 20 mA, RLOAD = 200 Ω
Forward/Reverse Active, Off-
hook
IVBAT
IDD
—
—
21.65
33.8
—
—
mA
mA
VTR = 55 VRMS + 0 VDC
,
Supply Currents:
Ringing
low power ringing, sinusoidal,
IVBAT
—
24.4
—
mA
f = 20 Hz, RLOAD = 3 REN = 2333 Ω
Note:
1. All specifications are for a tracking low-cost capacitive boost dc-dc converter at 25 °C. VDDD, VDDA = 3.3 V; VDC = 12 V.
2. IDD includes IDDIO + IDDD + IDDA
.
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Si3219x: ProSLIC Single FXS Solution
Electrical Specifications
Table 3.3. AC Characteristics
Parameter
TX/RX Performance
Test Condition
Min
Typ
Max
Unit
See Figure
3.4 Overload
Compres-
sion Per-
Overload Compression
2-Wire - PCM
—
—
formance on
page 14.
200 Hz to 3.4 kHz (µ-law/A-law)
200 Hz to 3.4 kHz (16-bit linear)
—
—
—
—
–40
–63
dB
dB
Single Frequency Distortion
Signal-to-(Noise + Distortion) Ratio1
See Figure
3.3 Transmit
and Receive
Path SNDR
on page
200 Hz to 3.4 kHz
transmit or receive path
—
—
Active off-hook, and OHT, any ZT
13.
Audio Tone Generator Signal-to-
Distortion Ratio1
0 dBm0, Active off-hook, and OHT,
any ZT
46
—
—
—
—
dB
dB
Intermodulation Distortion
Gain Accuracy1
–41
2-Wire to PCM or PCM to 2-Wire
1014 Hz, Any gain setting
–0.2
—
0.2
dB
See Figure 3.5 Receive Path Frequency Response on
page 14 and Figure 3.6 Transmit Path Frequency Re-
sponse on page 15.
0 dBm 0 5
Attenuation Distortion vs. Frequency
Group Delay vs. Frequency
See Figure 3.7 Transmit Group Delay Distortion on page
15 and Figure 3.8 Receive Group Delay Distortion on
page 16.
1014 Hz sine wave,
reference level –10 dBm,
Signal level:
—
—
—
—
Gain Tracking2
3 dB to –37 dB
—
—
—
—
26
—
—
0.25
0.5
1.0
500
—
dB
dB
dB
μs
–37 dB to –50 dB
–50 dB to –60 dB
—
Round-Trip Group Delay
2-Wire Return Loss3
1014 Hz, Within same time-slot
200 Hz to 3.4 kHz
450
30
dB
Transhybrid Balance3
300 Hz to 3.4 kHz
26
30
—
dB
Noise Performance
C-Message weighted
—
—
8
14
dBrnC
dBmP
Idle Channel Noise4
Psophometric weighted
–82
–76
PSRR from VDDD, VDDIO @ 3.3 V
RX and TX, 200 Hz to 3.4 kHz
—
55
—
dB
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Si3219x: ProSLIC Single FXS Solution
Electrical Specifications
Parameter
Test Condition
Min
Typ
Max
Unit
Longitudinal Performance
200 Hz to 1 kHz
1 kHz to 3.4 kHz
—
—
60
58
—
—
dB
dB
Longitudinal to Metallic/PCM Bal-
ance (forward or reverse)
Metallic/PCM to Longitudinal Bal-
ance
200 Hz to 3.4 kHz
—
—
—
—
—
dB
Ω
Longitudinal Impedance
Longitudinal Current Capability
Note:
200 Hz to 3.4 kHz at TIP or RING
Active off-hook 60 Hz
Reg 73 = 0x0B
50
—
25
—
mA
1. Analog signal measured as VTIP – VRING. Assumes ideal line impedance matching.
2. The quantization errors inherent in the μ/A-law companding process can generate slightly worse gain tracking performance in the
signal range of 3 to –37 dB for signal frequencies that are integer divisors of the 8 kHz PCM sampling rate.
3. VDD = 3.3 V, VBAT = –52 V, no fuse resistors; RL = 600 Ω, ZS = 600 Ω synthesized using RS register coefficients.
4. The level of any unwanted tones within the bandwidth of 0 to 4 kHz does not exceed –55 dBm.
5. 0 dBm 0 is equal to 0 dBm into 600 Ω.
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Si3219x: ProSLIC Single FXS Solution
Electrical Specifications
Table 3.4. Linefeed Characteristics
Parameter
Symbol
Test Condition
Differential
Min
—
Typ
—
Max
45
Unit
mA
mA
mA
%
DC Feed Current
Common Mode
—
—
30
Differential + Common Mode
ILIM = 18 mA
—
—
45
DC Loop Current Accuracy
—
—
10
Active Mode; VOC = 48 V,
VTIP – VRING
DC Open Circuit Voltage Accu-
racy
—
—
—
4
V
DC Differential Output Resist-
ance
RDO
ILOOP < ILIM
160
640
Ω
IRING < ILIM; VRING wrt ground,
VRING = –51 V
DC On-Hook Voltage Accuracy-
Ground Start (TIP Open)
VOHTO
—
—
4
V
DC Output Resistance-Ground
Start (TIP Open)
RROTO
IRING < ILIM; RING to ground
TIP to ground
160
400
—
—
—
—
—
—
640
—
10
10
4
Ω
kΩ
%
DC Output Resistance-Ground
Start (TIP Open)
RTOTO
Loop Closure Detect Threshold
Accuracy
ITHR = 13 mA
Ground Key Detect Threshold
Accuracy
ITHR = 13 mA
—
%
AC detection, VRING = 70 Vpk,
no offset, ITH = 80 mA
—
mA
Ring Trip Threshold Accuracy
DC detection, 20 V dc offset, ITH
= 13 mA
—
–100
—
—
—
1
1
mA
VPK
%
VRINGING
RTHD
Open circuit, VBAT = –100 V
50 VRMS, 0 VOFFSET, 0–5 REN
Ringing Amplitude
—
—
Sinusoidal Ringing Total Har-
monic Distortion
Ringing Frequency Accuracy
Ringing Cadence Accuracy
Loop Voltage Sense Accuracy
Loop Current Sense Accuracy
f = 16 Hz to 60 Hz
Accuracy of ON/OFF times
VTIP – VRING = 48 V
ILOOP = 18 mA
—
—
—
—
—
—
2
1
50
4
%
ms
%
7
10
%
Table 3.5. Digital I/O Characteristics
Parameter
Symbol
VIH
Test Condition
Min
Typ
—
Max
VDDIO
Unit
V
0.7 x VDDIO
High-Level Input Voltage
Low-Level Input Voltage
High-Level Output Voltage
Low-Level Output Voltage
Input Leakage Current
PSCLK, RSTB, ISI_MOSI
PSCLK, RSTB, ISI_MOSI
ISI_MISO, IO = –4 mA
ISI_MISO, IO = 4 mA
VIL
0.3 x VDDIO
—
—
V
VOH
VOL
IL
VDDIO – 0.6
—
—
0.4
10
V
—
—
—
V
—
μA
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Si3219x: ProSLIC Single FXS Solution
Electrical Specifications
Table 3.6. Charge Pump Characteristics
Parameter
Output Voltage (DCDRV, DCFF)
Output Current
Symbol
VCP
Test Condition
Min
Typ
—
Max
Unit
V
2 x VDDD – 1
2 x VDDD
31
ICP
—
—
mA
Note:
1. Peak drive current capability is >60 mA.
Table 3.7. Switching Characteristics (General Inputs)
Parameter
Symbol
Min
Typ
Max
Unit
tRST
RSTB Pulse Width
200
—
—
—
μs
RSTB High to First Register/RAM
Access
tRCS
5
—
ms
Note:
1. All timing is referenced to the 50% level of the waveform. Input test levels are VIH = VDDIO – 0.4 V, VIL = 0.4 V. Rise and Fall
times are referenced to the 20% and 80% levels of the waveform.
2. MSIF_LOCK signal on SoC must be active before valid SPI communication.
ISI Interface
tRST
PSCLK
RSTB
tRCS
Register Access
Figure 3.1. Si3219x Reset Timing Diagram
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Si3219x: ProSLIC Single FXS Solution
Electrical Specifications
Table 3.8. Switching Characteristics (ISI)
Parameter
Symbol
Min
7.5
5
Typ
—
Max
—
Unit
ns
tsu
th
Setup Time, ISI_MOSI to PSCLK Fall
Hold Time, ISI_MOSI to PSCLK Fall
Delay Time, PSCLK Rise to ISI_MISO
PSCLK Period
—
—
ns
td
—
—
16
—
ns
tp
—
40.69
50
ns
PSCLK Duty Cycle
40
60
%
Note:
1. Timing should be guaranteed by ISI-enabled host SoC.
tp
PSCLK
tsu
th
ISI_MOSI
td
ISI_MISO
Figure 3.2. ISI Timing Diagram
Table 3.9. Thermal Conditions
Parameter
Storage Temperature Range
Symbol
TSTG
θJA
Test Condition
Value
Unit
°C
–55 to 150
35
°C/W
°C/W
°C
Thermal Resistance, Typical QFN-381
θJC
15
Internally Limited
125
Maximum Junction Temperature, (High Voltage Die)3
TJHV
Continuous
Maximum Junction Temperature (Low Voltage Die)2
TJLV
°C
Note:
1. The thermal resistance of an exposed pad package is assured when the recommended printed circuit board layout guidelines are
followed correctly. The specified performance requires that the exposed pad be soldered to an exposed copper surface of at least
equal size and that multiple vias are added to enable heat transfer between the top-side copper surface and a large internal/
bottom copper plane. Thermal resistance values are empirical measurements taken from Silicon Labs 2-Layer EVBs.
2. Operation of the Si3219x above 125 °C junction temperature may degrade device reliability.
3. Si3219x linefeed is equipped with on-chip thermal limiting circuitry that shuts down the circuit when the junction temperature ex-
ceeds the thermal shutdown threshold. The thermal shutdown threshold is normally set to 145 °C; when in the ringing state the
thermal shutdown is set to 200 °C.
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Si3219x: ProSLIC Single FXS Solution
Electrical Specifications
Table 3.10. Absolute Maximum Ratings
Parameter
Supply Voltage
Symbol
VDD, VDDIO
VIND
Value
–0.5 to 4.0
Unit
V
Digital Input Voltage
Battery Supply Voltage
Tip or Ring Voltage
TIP, RING Current
Note:
–0.3 to VDDIO + 0.5
+0.4 to 102
VBAT – 0.4
V
VBAT
V
VTIP, VRING
ITIP, IRING
V
±100
mA
1. Permanent device damage may occur or the reliability of the device may be affected if the device is operated at or above the
absolute maximum ratings.
Operating Region
Figure 3.3. Transmit and Receive Path SNDR
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Electrical Specifications
Figure 3.4. Overload Compression Performance
Figure 3.5. Receive Path Frequency Response
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Electrical Specifications
Typical Response
Typical Response
Figure 3.6. Transmit Path Frequency Response
Typical Response
Figure 3.7. Transmit Group Delay Distortion
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Electrical Specifications
Typical Response
Figure 3.8. Receive Group Delay Distortion
Typical Response
Figure 3.9. Receive Wideband Frequency Response
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Si3219x: ProSLIC Single FXS Solution
Electrical Specifications
Typical Response
Figure 3.10. Transmit Wideband Frequency Response
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Si3219x: ProSLIC Single FXS Solution
FXS Features
4. FXS Features
4.1 DC Feed Characteristics
ProSLIC internal linefeed circuitry provides completely programmable dc feed characteristics.
When in the active state, the ProSLIC operates in one of three dc linefeed operating regions: a constant-voltage region, a constant-
current region, or a resistive region, as shown in the figure below. The constant-voltage region has a low resistance, typically 160 Ω.
The constant-current region approximates infinite resistance.
VTR(V)
Constant-V
Region
VOC
Resistive
Region
VRES
VILIM
Constant-I
Region
ILOOP(mA)
0
ISC
IRES
Figure 4.1. Dual ProSLIC DC Feed Characteristics
4.2 Linefeed Operation States
The linefeed interface includes eight different register-programmable operating states as listed in Table 4.1 Linefeed Operating States
on page 19. The Open state is the default condition in the absence of any preloaded register settings. The device may also automati-
cally enter the open state in the event of a linefeed fault condition.
4.3 Line Voltage and Current Monitoring
The ProSLIC continuously monitors the TIP, RING, and battery voltages and currents via an on-chip Monitor ADC and stores the result-
ing values in individual RAM locations. Additionally, VTIP, VRING, loop current, and longitudinal current values are calculated based on
the differential and common mode voltage measurements. The ADC updates all registers at a rate of 2 kHz or greater.
4.4 Power Monitoring and Power Fault Detection
The Si3219x line monitoring functions are used to continuously protect against excessive power conditions.
If the Si3219x detects an overpower condition, it automatically sets that device to the open state and generates a "power alarm" inter-
rupt.
The interrupt can be masked, but masking the automatic transition to open is not recommended since it is used to protect the Si3219x
HVIC under excessive power conditions.
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FXS Features
4.5 Thermal Overload Shutdown
If the die temperature exceeds the maximum junction temperature threshold, TJmax, of 145 °C or 200 °C (depending on the operating
state), the device has the ability to shut itself down to a low-power state without user intervention. A thermal alarm interrupt is generated
to notify host that the device has been switched to open state.
Table 4.1. Linefeed Operating States
Linefeed State
Description
Open
Output is high-impedance and audio is not transmitted. This is the default state after powerup or following
a hardware reset. This state can also be used in the presence of line fault conditions and to generate
open switch intervals (OSIs). This state is used in line diagnostics mode as a high impedance state dur-
ing linefeed testing. A power fault condition may also force the device into the open state.
Forward Active
Reverse Active
Forward OHT
Reverse OHT
Linefeed circuitry and audio are active. In Forward Active state, the TIP lead is more positive than the
RING lead; in Reverse Active state, the RING lead is more positive than the TIP lead.
Provides data transmission during an on-hook loop condition (e.g., transmitting caller ID data between
ringing bursts). Linefeed circuitry and audio are active. In Forward OHT state, the TIP lead is more posi-
tive than the RING lead; in Reverse OHT state, the RING lead is more positive than the TIP lead.
TIP Open
RING Open
Ringing
Provides an active linefeed on the RING lead and sets the TIP lead to high impedance (≥400 kΩ) for
ground start operation in forward polarity. Loop closure and ground key detect circuitry are active.
Provides an active linefeed on the TIP lead and sets the RING lead to high impedance (≥400 kΩ) for
ground start operation in reverse polarity. Loop closure and ground key detect circuitry are active.
Drives programmable ringing signal onto TIP and RING leads with or without dc offset.
4.6 Loop Closure Detection
The Si3219x provides a completely programmable loop closure detection mechanism. The loop closure detection scheme provides two
unique thresholds to allow hysteresis, and also includes a programmable debounce filter to eliminate false detection. A loop closure
detect status bit provides continuous status, and a maskable interrupt bit is also provided.
4.7 Ground Key Detection
The Si3219x provides a ground key detect mechanism using a programmable architecture similar to the loop closure scheme. The
ground key detect scheme provides two unique thresholds to allow hysteresis and also includes a programmable debounce filter to
eliminate false detection. A ground key detect status bit provides continuous status, and a maskable interrupt bit is also provided.
4.8 Ringing Generation
The Si3219x supports the patented Low-Power Ringing (LPR) method exclusively, which when used with a tracking battery scheme,
maximizes the ringing power transfered to the load and reduces overall power consumption. Ringing is fully programmable including
frequency, amplitude, dc offset, wave shape and crest factor. The Si3219x also supports automatic ring cadencing and ringtrip detec-
tion (AC and DC).
Balanced
Unbalanced
LPR
GND
GND
TIP
GND
TIP
RING
VBAT
TIP
RING
VBAT
RING
VBAT
Figure 4.2. Ringing Mode
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FXS Features
4.9 Polarity Reversal
The Si3219x supports polarity reversal for message waiting and various other signaling modes. The ramp rate can be programmed for
a smooth or abrupt transition to accommodate different application requirements.
4.10 Two-wire Impedance Synthesis
The ac two-wire impedance synthesis is generated on-chip using a DSP-based scheme to optimally match the output impedance of the
Si3219x to the reference impedance. Most real or complex two-wire impedances can be generated with appropriate register coeffi-
cients.
4.11 Transhybrid Balance Figure
The trans-hybrid balance function is implemented on-chip using a DSP-based scheme to effectively cancel the reflected receive path
signal from the transmit path.
4.12 Tone Generators
The Si3219x includes two digital tone generators that allow a wide variety of single- or dual-tone frequency and amplitude combina-
tions. Each tone generator has its own set of registers that hold the desired frequency, amplitude, and cadence to allow generation of
DTMF and call progress tones for different requirements. The tones can be directed to either receive or transmit paths.
4.13 DTMF Detection (Si32193 Only)
In DTMF, two tones generate a DTMF digit. One tone is chosen from four possible row tones, and one tone is chosen from four possi-
ble column tones. The sum of these tones constitutes one of 16 possible DTMF digits.
4.14 Pulse Metering
The pulse metering system for the Si3219x is designed to inject a 12 or 16 kHz billing tone into the audio path with maximum amplitude
of 0.85 VRMS at TIP and RING into a 200 Ω ac load impedance. The tone is generated in the DSP via a table lookup that guarantees
spectral purity by not allowing drift. The tone will ramp up until it reaches a host-programmed threshold, at which point it will maintain
that level until instructed to ramp down, thuscreating a trapezoidal envelope.
The amplitude is controlled by an automatic gain control circuit (AGC). While the tone is ramping up, the AGC takes the feedback audio
and applies it to a band pass filter, which is programmed for the 12 or 16 kHz frequency of interest. When the peak is detected, the
ramp is stopped.
4.15 DC-DC Controller
The Si3219x-C devices integrate a dc-dc controller to control an external tracking dc-dc converter which generates the high voltage
supply (VBAT) to the SLIC. The tracking VBAT voltage generated from a single positive dc input is optimized to minimize power con-
sumption by closely tracking the SLIC state, even tracking the ringing waveforms.
The dc-dc controller output DCDRV is driven by an internal charge pump which allows it to connect directly to the gate of the MOSFET
switch of the dc-dc converter. This eliminates the need for the MOSFET predrive circuit that is typically required when other SLICs are
used with a MOSFET with VTH greater than VDDD. See Table 3.6 Charge Pump Characteristics on page 11.
4.16 Wideband Audio
The Si3219x supports wideband audio (150 Hz–6.8 kHz) compliant with PKT-SP-HDV-104-120823, and is configurable to support the
full ITU-T-G.722-201209 bandwidth (50 Hz–7 kHz). The wideband provides an expanded audio band at a 16-bit, 16 kHz sample rate for
enhanced audio quality while maintaining standard telephony audio compatibility. Wideband audio samples are transmitted and re-
ceived at an effective 16 kHz rate by using multiple timeslots in a single 8 kHz frame.
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Si3219x: ProSLIC Single FXS Solution
FXS Features
4.17 Test Facilities
The Si3219x supports a rich set of metallic loop tests to diagnose external faults, as well as a set of inward self-tests to support diag-
nostics of the Si3219x-based voice port. Implementation of metallic loop tests required the ProSLIC® MLT API, while the inward self-
tests are included in the standard ProSLIC® API.
Table 4.2. Supported Tests
Test
Metallic Loop Tests
Description
Voltages
Measures ac and dc voltages from T-R, T-G, and R-G.
Discriminates between resistive fault and off-hook terminating device.
Measures Ringer Equivalence Number (REN).
Measures T-R capacitance of on-hook load.
Receiver Off-hook
REN
REN Capacitance
Capacitance
Resistance
Measures 3-Terminal Capacitance.
Measures resistance from T-R, T-G, or R-G.
Inward Self-Tests
PCM Loopback
DC Feed
Configures Si3219x for 8- or 16-bit PCM loopback.
Verify dc Feed I/V and loop closure using integrated test load.
Ringing and Ringtrip
Verify ringing voltage (ac and dc). Optional ringtrip check to support system level signal-
ing verification.
Battery
Verify VBAT.
Audio Gain
Measure gain of RX (host to line) and TX (line to host) paths without using an external
load, test equipment, or requiring the host to provide audio samples.
In addition to these specific test suites, the user is free to use the general test facilities listed in the following table:
Table 4.3. General Test Facilities
Test
Description
Monitor ADC
Provides TIP/RING voltages (inside and outside overcurrent protection), TIP/RING cur-
rents and VBAT voltage.
Audio Diagnostic Filters
Loopback Modes
Three cascaded second-order Biquad filters with peak hold and averaging capabilities.
Digital and analog loopback modes to isolate portions of the audio path.
Tone Generators
The dual-tone generators may be used as general-purpose test signal generators.
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System Interfaces
5. System Interfaces
5.1 Integrated Serial Interface
The ISI interface supported on select Si3219x devices is a three-wire proprietary interface which serializes SPI and PCM communica-
tions and interrupts, reducing the SoC interface from nine wires to three (PSCLK, ISI_MISO, ISI_MOSI). SPI communications and PCM
data transfers are embedded in the serial data. The host side of the ISI is integrated onto selected SoCs from several vendors.
ISI is a point to point interface; therefore, it is not possible to daisy-chain more than one ISI ProSLIC device.
Both µ-255 Law (μ-Law) and A-law companding formats are supported in addition to 16-bit linear data mode with no companding.
5.2 Input/Output Voltage Selection
The digital host interface I/O (ISI) on the Si3219x may directly interface to 1.8 V to 3.3 V devices. The I/O voltage selection is made by
supplying the VDDIO pin with the appropriate I/O supply voltage.
To avoid power supply sequencing issues, VDDIO should be connected to the same supply as VDD in 3.3 V interface designs. Other
voltages between 1.8 V and 3.3 V can also be used for VDDIO (for example 2.5 V), but steps must be taken to ensure that the VDDIO
supply comes up after the VDD supply if VDDIO is not connected to VDD.
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Si3219x: ProSLIC Single FXS Solution
Pin Descriptions
6. Pin Descriptions
6.1 Pin Descriptions: 38 Pin QFN (Si32192/3)
38
37
36
35
EPAD
16
34
33
32
NC
NC
STIPC
1
2
31
30
SRINGC
NC
3
29 SRINGDC
VDDIO
GND
28
27
26
25
24
23
22
4
SRINGAC
STIPAC
5
PSCLK
GND
STIPDC
VDDA
GND
6
7
ISI_MISO
ISI_MOSI
8
9
IREF
NC
DCFF
NC
CAPM
10
11
12
21 CAPP
20
GND
13
14
15
17
18
19
Table 6.1. Si3219x Pin Descriptions
Pin #
Pin Name
Description
No connection.
1
NC
This pin should be left unconnected.
No connection.
2
3
4
5
6
7
NC
NC
This pin should be left unconnected.
No connection.
This pin should be left unconnected.
Digital IO Supply Voltage.
VDDIO
GND
3.3 V or 1.8 V digital power supply for internal circuitry.
Ground.
Connect to ground.
ISI Bus Clock Input.
Clock input for ISI bus timing.
Ground.
PSCLK
GND
Connect to ground.
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Pin Descriptions
Pin #
Pin Name
Description
Transmit ISI Output.
8
ISI_MISO
ISI Master Input, Slave Output. Output data to ISI bus.
Transmit ISI Input.
9
ISI_MOSI
ISI Master Output, Slave input. Input data from ISI bus.
No connection.
10
11
12
NC
DCFF
NC
This pin should be left unconnected.
DC-DC Charge Pump Output.
No connection.
This pin should be left unconnected.
DC Drive.
13
14
15
DCDRV
SDCL
DC-DC converter control signal output which drives external transistor.
DC Monitor.
DC-DC converter monitor input used to detect overcurrent situations in the converter.
DC Monitor.
SDCH
DC-DC converter monitor input used to detect overcurrent situations in the converter.
IC Voltage Supply.
16
17
18
VDDD
VDDREG
RSTB
3.3 V digital power supply for internal circuitry.
Regulated Core Power Supply.
Reset Input.
Active low input. Hardware reset used to place all control registers in the default state.
VBAT Sense.
19
20
21
22
23
24
25
26
SVBAT
GND
Input used to sense voltage on DC-DC converter output voltage lead.
Ground.
Connect to ground.
SLIC Stabilization Capacitor.
CAPP
CAPM
IREF
Capacitor used in dc feed low-pass filter.
SLIC Stabilization Capacitor.
Capacitor used in dc feed low-pass filter.
Current Reference Input.
Connects to an external resistor used to provide a high accuracy reference current.
Ground.
GND
Connect to ground.
Analog Supply Voltage.
VDDA
STIPDC
Analog 3.3 V power supply for internal analog circuitry.
TIP DC Sense.
Analog DC input used to sense voltage on TIP lead.
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Si3219x: ProSLIC Single FXS Solution
Pin Descriptions
Pin #
Pin Name
Description
TIP AC Sense.
27
STIPAC
Analog AC input used to sense voltage on TIP lead.
RING AC Sense.
28
29
30
31
32
33
34
35
36
37
38
—
SRINGAC
SRINGDC
SRINGC
STIPC
VDDHV
NC
Analog AC input used to sense voltage on RING lead.
RING DC Sense.
Analog DC input used to sense voltage on RING lead.
RING Coarse Sense Input.
Voltage sensing outside protection circuit.
TIP Coarse Sense Input.
Voltage sensing outside protection circuit.
Analog Supply Voltage.
Analog 3.3 V power supply for internal analog circuitry.
No connection.
This pin should be left unconnected.
Battery Voltage Supply.
VBAT
NC
Connect to battery supply from DC-DC converter.
No connection.
This pin should be left unconnected.
RING Terminal.
RING
Connect to the RING lead of the subscriber loop.
No connection.
NC
This pin should be left unconnected.
TIP Terminal.
TIP
Connect to the TIP lead of the subscriber loop.
Exposed paddle.
EPAD
Connect to ground.
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Si3219x: ProSLIC Single FXS Solution
Package Outline
7. Package Outline
7.1 Package Outline: 38-Pin QFN
The figure below illustrates the package details for the Si3219x in a 38-pin QFN package. The table below lists the values for the di-
mensions shown in the illustration.
Figure 7.1. 38-Pin QFN Package
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Si3219x: ProSLIC Single FXS Solution
Package Outline
Table 7.1. Package Dimensions
Dimension
Min
Nom
0.85
0.02
0.20REF
0.20
4.00
2.60
0.40 BSC.
6.00
4.60
0.40
—
Max
0.90
0.05
A
A1
A3
b
0.80
0.00
0.18
3.90
2.50
0.25
4.10
2.70
D
D2
e
E
5.90
4.50
0.30
—
6.10
4.70
0.50
0.10
0.07
0.10
0.05
0.08
0.10
E2
L
aaa
bbb
ccc
ddd
eee
fff
—
—
—
—
—
—
—
—
—
—
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1982.
3. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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Si3219x: ProSLIC Single FXS Solution
Land Pattern
8. Land Pattern
8.1 Land Pattern: 38-Pin QFN
The figure below shows the recommended land pattern details for the 38-Pin QFN package. The table below lists the values for the
dimensions shown in the illustration.
Figure 8.1. 38-Pin QFN Land Pattern
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Si3219x: ProSLIC Single FXS Solution
Land Pattern
Table 8.1. PCB Land Pattern
Dimension
mm
4.00
6.00
0.40
0.20
0.80
2.70
4.70
C1
C2
e
X1
Y1
X2
Y2
Note:
General
1. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabri-
cation Allowance of 0.05mm.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
Solder Mask Design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm
minimum, all the way around the pad.
Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
2. The stencil thickness should be 0.125mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins.
4. A 4x3 array of 0.85 mm square openings on 1.2 mm pitch should be used for the center ground pad to achieve a target solder
coverage of ~50%.
Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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Si3219x: ProSLIC Single FXS Solution
Top Marking
9. Top Marking
9.1 Top Marking 38-pin QFN
Figure 9.1. 38-Pin QFN Top Marking
Table 9.1. Top Marking Explanation
Mark Method:
Pin 1 Mark:
Laser
Circle = 0.50 mm Diameter (Bottom-
Left-Justified)
Font Size
0.60 mm Right-Justified
Device Part Number
YY = Year
Line 1 Mark Format:
Line 2 Mark Format:
Si32192FM1
Manufacturing Code from the Assembly Purchase Order
form.
WW = Work Week
TTTTTT = Mfg Code
Assigned by the Assembly House. Corresponds to the
year and work week of the assembly release.
Line 3 Mark Format:
Circle = 1.0 mm Diameter
Center-Justified
"e3" Pb-Free Symbol
TH, TW, or CN
CC = Country of Origin ISO Code
Abbreviation
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Si3219x: ProSLIC Single FXS Solution
Revision History
10. Revision History
Revision 1.0
June, 2018
• Updated Table 3.2 Power Supply Characteristics on page 7.
• Updated Table 3.3 AC Characteristics on page 8.
• Updated Idle Channel Noise specification.
• Numerous clarifications throughout.
Revision 0.9
April, 2017
• Initial revision.
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intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical"
parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes without
further notice to the product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. Without prior
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