SI4022-ICCC16 [SILICON]
RF and Baseband Circuit, PDSO16, TSSOP-16;
| 型号： | SI4022-ICCC16 |
| 厂家： | 
SILICON |
| 描述： | RF and Baseband Circuit, PDSO16, TSSOP-16 电信 光电二极管 电信集成电路 |
| 文件： | 总22页 (文件大小：645K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si4022 Universal ISM Band
Si4022
FSK Transmitter
DESCRIPTION
PIN ASSIGNMENT
SDI
SCK
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
FSK
Silicon Labs’ Si4022 is a single chip, low power, multi-channel FSK
transmitter designed for use in applications requiring FCC or ETSI
conformance for unlicensed use in the bands at 868 and 915 MHz. Used in
conjunction with Integration’s FSK receivers, it is a flexible, low cost, and
highly integrated solution that does not require production alignments. All
required RF functions are integrated. Only an external crystal and bypass
filtering is needed for operation.
VDD
VSS_B
RF02
RF01
VSS_A
nSEL
SDO
nIRQ
CLK
VREFO
VSS_D
nRES
XTL / REF
The transmitter has a completely integrated PLL for easy RF design, and its
rapid settling time allows for fast frequency-hopping, bypassing multipath
fading and interference to achieve robust wireless links. The PLL’s high
resolution allows the usage of multiple channels in any of the bands. In
addition, highly stable and accurate FSK modulation is accomplished by
direct closed-loop modulation with bit rates up to 115.2 kbps.
This document refers to Si4022-IC Rev A0.
See www.silabs.com/integration for any applicable
errata. See back page for ordering information.
FEATURES
The integrated power amplifier of the transmitter has an open-collector
differential output and can directly drive a loop antenna with programmable
output level, no additional matching network is required. An automatic
antenna tuning circuit is built in to avoid both costly trimming procedures
and de-tuning due to the “hand effect”.
•
•
•
•
•
Fully integrated (low BOM, easy design-in)
No alignment required in production
Fast settling, programmable, high-resolution PLL
Fast frequency hopping capability
Stable and accurate FSK modulation with
programmable deviation
For battery-operated applications the device supports various power saving
modes with wake-up interrupt generation options based on a low battery
voltage detector and a sleep timer. Several additional features ease system
design. Power-on reset and clock signals are provided to the microcontroller.
An on-chip baud rate generator and a data FIFO are available. The transmitter
is programmed and controlled via an SPI compatible interface.
•
•
•
•
•
•
•
•
•
•
•
Programmable PLL loop bandwidth
Direct loop antenna drive
Automatic antenna tuning circuit
Programmable output power level
SPI bus for interfacing with microcontroller
Clock and reset signals for microcontroller
64 bit TX data FIFO
Integrated programmable crystal load capacitor
Standard 10 MHz crystal reference
Power-saving modes
FUNCTIONALBLOCKDIAGRAM
Multiple event handling options for wake-up
activation
•
•
•
•
•
Wake-up timer
Low battery detection
2.2 to 3.8 V supply voltage
Low power consumption
13 RF02
REFERENCE
CRYSTAL
OSCILLATOR
9
SYNTHESIZER
XTL
12 RF01
CLOCK
FREQUENCY
Low standby current (typ. 0.3 μA)
LEVEL
LOAD CAP
TYPICALAPPLICATIONS
6
CLK
nIRQ
SDO
SDI
5
4
1
LOW BAT
•
•
•
•
•
•
•
•
•
Remote control
LOW
BATTERY
DETECT
TRESHOLD
Home security and alarm
Wireless keyboard/mouse and other PC peripherals
Toy control
Remote keyless entry
Tire pressure monitoring
Telemetry
VDD 15
CONTROLLER
11
VSS_A
2
3
SCK
TIMEOUT
PERIOD
VDD_B 14
nSEL
WAKE-UP
TIMER
8
VSS_D
16
FSK
7
VREFO
Personal/patient data logging
Remote automatic meter reading
10
nRES
1IA4
222-DS rev 1.1r 030
i
Si4022
DETAILED FEATURE-LEVEL DESCRIPTION
The Si4022 FSK transmitter is designed to cover the unlicensed
frequency bands at 868, and 915 MHz. The device facilitates
compliance with FCC and ETSI requirements.
LowBattery VoltageDetector
The low battery detector circuit monitors periodically (typ. 8 ms)
the supply voltage and generates an interrupt if it falls below a
programmablethresholdlevel.
PLL
The programmable PLL synthesizer determines the operating
frequency, while preserving accuracy based on the on-chip
crystal-controlled reference oscillator. The PLL’s high resolution
allows the usage of multiple channels in any of the bands. The
FSK deviation is selectable (from 20 to 160 kHz with 20 kHz
increments) to accommodate various bandwidth, data rate and
crystal tolerance requirements, and it is also highly accurate
due to the direct closed-loop modulation of the PLL. The
transmitted digital data can be sent asynchronously through
the FSK pin or over the control interface using the appropriate
command.
Wake-UpTimer
The wake-up timer has very low current consumption (4 μA max)
and can be programmed from 1 ms to several hours.
It calibrates itself to the crystal oscillator at every startup and
then at every 40 seconds with an accuracy of ±0.5%. When the
crystal oscillator is switched off, the calibration circuit switches
it back on only long enough for a quick calibration (a few
milliseconds) to facilitate accurate wake-up timing. The periodic
autocalibration feature can be turned off.
Event Handling
The RF VCO in the PLL performs automatic calibration, which
requires only a few microseconds. To ensure proper operation
in the programmed frequency band, the RF VCO is automatically
calibrated upon activation of the synthesizer.
In order to minimize current consumption, the transmitter
supports the sleep mode. Switching between the various modes
is controlled by the appropriate bits in the Power Management
Command (page 11).
Si4022 generates an interrupt signal on several events (wake-
up timer timeout, low supply voltage detection, on-chip FIFO
almost empty). This signal can be used to wake up the
microcontroller, effectively reducing the period the
microcontroller has to be active. The cause of the interrupt can
be read out from the receiver by the microcontroller through the
SDO pin.
RF PowerAmplifier(PA)
The power amplifier has an open-collector differential output
and can directly drive a loop antenna with a programmable output
power level. An automatic antenna tuning circuit is built in to
avoid costly trimming procedures and the so-called “hand
effect.”
CrystalOscillatorandMicrocontrollerClockOutput
InterfaceandController
The chip has a single-pin crystal oscillator circuit, which provides
a 10 MHz reference signal for the PLL. To reduce external parts
and simplify design, the crystal load capacitor is internal and
programmable. Guidelines for selecting the appropriate crystal
can be found later in this datasheet. The transmitter can supply
the clock signal for the microcontroller, so accurate timing is
possible without the need for a second crystal. In normal
operation it is divided from the reference 10 MHz. During sleep
mode a low frequency (typical 32 kHz) output clock signal can
be switched on.
An SPI compatible serial interface lets the user select the
frequency band, center frequency of the synthesizer, and the
output power. Division ratio for the microcontroller clock, wake-
up timer period, and low supply voltage detector threshold are
also programmable. Any of these auxiliary functions can be
disabled when not needed. All parameters are set to default after
power-on; the programmed values are retained during sleep mode.
The interface supports the read-out of a status register, providing
detailed information about the status of the transmitter.
When the microcontroller turns the crystal oscillator off by
clearing the appropriate bit using the Power Management
Command, the chip provides a certain number (default is 128)
of further clock pulses (“clock tail”) for the microcontroller to
let it go to idle or sleep mode.
Si4022
PIN DEFINITION
Pin type key: D=digital, A=analog, S=supply, I=input, O=output, IO=input/output
SDI
SCK
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
FSK
VDD
nSEL
SDO
VSS_B
RF02
IA4222
nIRQ
RF01
CLK
VSS_A
nRES
XTL / REF
VREFO
VSS_D
Pin
Name
Function
Type
Description
1
2
3
4
5
6
7
8
SDI
SCK
SDI
SCK
DI
DI
Serial control / data input
Serial interface clock input
nSEL
SDO
nSEL
SDO
DI
Chip (interface) select input (active low)
Serial status data output
DO
DO
DO
AO
S
nIRQ
CLK
nIRQ
CLK
Interrupt request output (active low)
Clock output for the microcontroller
Voltage reference output
VREFO
VSS_D
VREFO
VSS_D
XTL
Negative supply voltage (digital)
Crystal connection (other terminal of crystal to VSS)
External reference input
AIO
DI
9
XTL / REF
REF
10
11
12
13
14
15
16
nRES
VSS_A
RFO1
RFO2
VSS_B
VDD
nRES
VSS_A
RFO1
RFO2
VSS_B
VDD
DO
S
Reset output (active low)
Negative supply voltage (analog)
RF differential signal output (open collector)
RF differential signal output (open collector)
Negative supply voltage (bulk)
AO
AO
S
S
Positive supply voltage
FSK
FSK
DI
Data input for asynchronous modulation
Si4022
GENERAL DEVICE SPECIFICATION
All voltages are referenced to V , the potential on the ground reference pin VSS.
ss
Absolute Maximum Ratings (non-operating)
Symbol
Vdd
Parameter
Min
-0.5
-0.5
-25
Max
6.0
Units
Positive supply voltage
V
V
Vin
Voltage on any pin
Vdd+0.5
25
Iin
Input current into any pin except VDD and VSS
Electrostatic discharge with human body model
Storage temperature
mA
ESD
Tst
1000
125
V
oC
oC
-55
Tld
Lead temperature (soldering, max 10 s)
260
Recommended Operating Range
Symbol
Vdd
Parameter
Min
2.2
Max
3.8
Units
V
oC
Positive supply voltage
Ambient operating temperature
Top
-40
+85
ELECTRICAL SPECIFICATION
(Min/max values are valid over the whole recommended operating range, typ conditions: T
= 27 oC; V
= 2.7 V)
dd = Voc
op
DC Characteristics
Symbol
Parameter
Conditions/Notes
Min
Typ
Max
Units
868 MHz band, Pout = 0dBm
915 MHz band, Pout = 0dBm
14
15
Idd,TX0
Supply current
mA
868 MHz band, Pout = Pmax
915 MHz band, Pout = Pmax
23
24
Idd,TXmax
Ipd
Supply current
mA
µA
µA
Standby current (Note 1)
all blocks disabled
1
Low battery voltage detector and
wake-up timer current
Ilb
5
Ix
Idle current
crystal oscillator is ON
0.5
mA
V
Vlb
Vlba
Low battery detection threshold
Low battery detection accuracy
programmable in 0.1 V steps
2.0
3.5
± 0.05
1.5
V
Vdd threshold required
to generate a POR
VPOR
V
larger glithches on the Vdd
generate a POR even above
the threshold VPOR
VPOR,hyst
SRVdd
POR hysteresis
Vdd slew rate
0.6
V
for proper POR generation
0.1
V/ms
Note 1: Using a CR2032 battery (225 mAh capacity), the expected battery life is greater than 2 years using a 60-second wake-up period
for sending 100 bytes packets in length at 19.2 kbps with +6 dBm output power in the 915 MHz band.
Si4022
DC Characteristics (continued)
Symbol
Parameter
Conditions/Notes
Min
Typ
Max
Units
Vil
Vih
Iil
Digital input low level
Digital input high level
Digital input current
Digital input current
Digital output low level
Digital output high level
0.3*Vdd
V
V
0.7*Vdd
Vil = 0 V
-1
-1
1
1
µA
µA
V
Iih
Vih = Vdd, Vdd = 3.8 V
Iol = 2 mA
Vol
Voh
0.4
I
oh = -2 mA
Vdd-0.4
V
AC Characteristics
Symbol
Parameter
Conditions/Notes
Min
Typ
Max
Units
868 MHz band, 20 kHz resolution
915 MHz band, 20 kHz resolution
801.92
881.92
878.06
958.06
fLO
Transmitter frequency
MHz
fref
PLL reference frequency
PLL frequency resolution
(Note 1)
9
10
20
11
MHz
kHz
fres
Frequency error < 1kHz
after 1 MHz step
tlock
tsp
PLL lock time
30
μs
μs
pF
Initial calibration after power-up
with running crystal oscillator
PLL startup time
500
16
Crystal load capacitance,
see crystal selection guide
Programmable in 0.5 pF steps,
tolerance +/- 10%
Cxl
8.5
Internal POR pulse width
(Note 2)
After Vdd has reached 90% of
final value
tPOR
tsx
50
2
100
5
ms
ms
ms
ms
Crystal oscillator startup time
Wake-up timer clock period
Programmable wake-up time
CrystalESR<100
Calibrated every 40 seconds
(Note 3)
tPBt
0.995
1
1
1.005
8.4*106
twake-up
Note 1: Using anything but a 10 MHz crystal is allowed but not recommended because all crystal-referred timing and frequency
parameters will change accordingly.
Note 2: No command are accepted by the chip during this period.
Note 3: Autocalibration can be turned off.
Si4022
AC Characteristics (continued)
Symbol
BR
Parameter
Conditions/Notes
(Note 4)
Min
Typ
Max
115.2
6
Units
FSK bit rate
kbps
mA
Iout
Open collector output current
Adjustable in 8 steps
0.5
With optimal antenna impedance
(Note 5)
Pmax
Pout
Psp
Available output power
Typical output power
Spurious emission
6
dBm
dBm
dBm
pF
Adjustable in 8 steps
(3 dB/step)
Pmax - 21
Pmax
-52
2.8
22
Out of band, EIRP (Note 6)
Set by the automatic antenna
tuning circuit
Cout
Qout
Lout
Output capacitance
1.6
16
2.2
18
Quality factor of the output
capacitance
100 kHz from carrier
1 MHz from carrier (Note 4)
-85
-105
Output phase noise
dBc/Hz
Cin, D
Digital input capacitance
Digital output rise/fall time
Clock output rise/fall time
Slow clock frequency
2
pF
ns
tr, f
15 pF pure capacitive load
10 pF pure capacitive load
Tolerance +/- 1 kHz
10
15
tr, f ,ckout
fckout, slow
ns
32
kHz
Setting
(bw1, bw0)
Max. datarate
[kbps]
Phase noise at
1 MHz offset [dBc/Hz]
PLL bandwidth
00
01
10
11
19.2
38.4
64
-112
-110
-107
-102
15 kHz
30 kHz
60 kHz (POR default)
120 kHz
115.2
Y antenna [S]
1.35E-3 – j1.2E-2
1.45E-3 – j1.3E-2
Z antenna [Ω]
9 + j82
L antenna [nH]
Band
868 MHz
915 MHz
15.2
13.6
8.7 + j77
Note 4: The maximum FSK bitrate and the output phase noise are dependent on the PLL settings (with the Extended Features
Command).
Note 5: Optimal antenna / admittance / inductance for the Si4022
Note 6: With selective resonant antennas (see: Application Notes available from http://www.silabs.com/integration).
Si4022
TYPICAL PERFORMANCE DATA
Phasenoise measurements in the 868MHz ISM band
100, 50, 33% Charge pump current settings
(Ref. level: -70 dBc/Hz, 5 dB/div)
50% Charge pump current setting
(Ref. level: -60 dBc/Hz, 10 dB/div)
13:30:49 May 5, 2005
Phase Noise
L
11:52:47 May 5, 2005
Phase Noise
L
Mkr1
1.00000 MHz
Mkr4
5.00800 MHz
Carrier Power
-11.03 dBm Atten 1.1 dB
Carrier Power
-11.11 dBm Atten 0.00 dB
-101.95 dBc/Hz
-115.65 dBc/Hz
Ref -70.00dBc/Hz
5.00
dB/
Ref -60.00dBc/Hz
10.00
dB/
1
2
4
10 kHz
Frequency Offset
10 MHz
Value
10 kHz
Frequency Offset
10 MHz
Value
Marker
1
2
3
Trace
1
2
3
Type
Spot Freq
Spot Freq
Spot Freq
X Axis
Marker
Trace
Type
X Axis
10 kHz
151 kHz
1
1
1
MHz -101.95 dBc/Hz
MHz -107.05 dBc/Hz
MHz -109.98 dBc/Hz
1
2
3
4
2
2
2
2
Spot Freq
Spot Freq
Spot Freq
Spot Freq
-76.65 dBc/Hz
-86.95 dBc/Hz
1
MHz -107.11 dBc/Hz
5.008 MHz -115.65 dBc/Hz
UnmodulatedRFSpectrum
The output spectrum is measured at different frequencies. The output is loaded with 50 Ohm through a matching network.
At 915 MHz
At 868 MHz
10:26:50 May 5, 2005
Atten 10 dB
L
10:34:57 May 5, 2005
Atten 10 dB
L
Mkr1 868.0010 MHz
-12.2 dBm
Mkr1 915.0020 MHz
-14.09 dBm
Ref 0 dBm
Samp
Log
Ref 0 dBm
Samp
Log
1
10
10
dB/
dB/
VAvg
100
VAvg
100
W1 S2
S3 FC
AA
W1 S2
S3 FC
AA
Center 868 MHz
Res BW 10 kHz
Span 2 MHz
Sweep 40.74 ms (2001 pts)
Center 915 MHz
Res BW 10 kHz
Span 2 MHz
Sweep 40.74 ms (2001 pts)
VBW 10 kHz
VBW 10 kHz
Si4022
At 868 MHz with
180 kHz Deviation at 9.6 kbps
11:14:40 May 5, 2005
Atten10 dB
L
Ref0 dBm
Samp
Log
10
dB/
VAvg
100
W1 S2
S3 FC
AA
Center 868 MHz
Res BW 10 kHz
Span 2 MHz
Sweep 40.74 ms (2001 pts)
VBW 10 kHz
Antenna Tuning Characteristics
750–970 MHz
The antenna tuning characteristics was recorded in “max-hold” state of the spectrum analyzer. During the measurement, the
transmitters were forced to change frequencies by forcing an external reference signal to the XTL pin. While the carrier was changing
the antenna tuning circuit switched trough all the available states of the tuning circuit. The graph clearly demonstrates that while the
complete output circuit had about a 40 MHz bandwidth, the tuning allows operating in a 220 MHz band. In other words the tuning
circuit can compensate for 25% variation in the resonant frequency due to any process or manufacturing spread.
Si4022
CONTROL INTERFACE
Commands to the transmitters are sent serially. Data bits on pin SDI are shifted into the device upon the rising edge of the clock on
pin SCK whenever the chip select pin nSEL is low. When the nSEL signal is high, it initializes the serial interface. The number of bits
sent is an integer multiple of 8 (except for the Transmitter FIFO Write Command). All commands consist of a command code,
followed by a varying number of parameter or data bits. All data are sent MSB first (e.g. bit 15 for a 16-bit command). Bits having no
influence (don’t care) are indicated with X. The Power On Reset (POR) circuit sets default values in all control and command
registers.
Timing Specification
Symbol
tCH
Parameter
Minimum value [ns]
Clock high time
25
25
10
10
25
5
tCL
Clock low time
tSS
Select setup time (nSEL falling edge to SCK rising edge)
Select hold time (SCK falling edge to nSEL rising edge)
Select high time
tSH
tSHI
tDS
Data setup time (SDI transition to SCK rising edge)
Data hold time (SCK rising edge to SDI transition)
Data delay time
tDH
5
tOD
10
Timing Diagram
tSHI
tSS
nSEL
tCH
tCL
tOD
tSH
SCK
tDS
tDH
BIT15
BIT14
BIT13
BIT8
BIT7
BIT1
BIT0
BIT0
SDI
BIT15
SDO
BIT14
BIT13
BIT8
BIT7
BIT1
Si4022
Control Commands
Control Word
Related Parameters/Functions
Configuration Setting Command
Frequency Setting Command
frequency band and deviation, output power, crystal oscillator load capacitance
frequency of the local oscillator
crystal oscillator, synthesizer, power amplifier, low battery detector, wake-up timer,
clock output buffer
Power Managament Command
Transmitter FIFO Write Command
FIFO Setting Command
transmitter FIFO write
FIFO functions
bit rate
Data Rate Command
Low Battery and Microcontroller Clock
Divider Command
LBD voltage threshold and microcontroller clock division ratio
Wake-up Timer Command
wake-up time period
Extended Wake-up Timer Command
Extended Features Command
Status Register Read Command
wake-up time period finer adjustment
low frequency output clock, wake-up timer extra functions
transmitter status read
Note: In the following tables the POR column shows the default values of the command registers after power-on.
Configuration Setting Command
bit
15
1
14
0
13
0
12
1
11
bs
10
p2
9
8
7
6
5
4
3
2
1
0
POR
p1
p0
x3
x2
x1
x0
ms
m2
m1
m0
9082h
bs
Frequency Band [MHz]
Crystal Load
Capacitance [pF]
x3
x2
x1
x0
0
1
868
915
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
8.5
9.0
9.5
Output Power
10.0
….
p2
p1
p0
[dBm]
……
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
0
1
15.5
16.0
-3
-6
-9
-12
-15
-18
-21
The resulting output frequency can be calculated as:
– (-1)SIGN * (M + 1) * (20 kHz)
fout = f0
where:
The output power is given in the table as
relative to the maximum available power, which
depends on the actual antenna impedance.
(See: Antenna Application Note available from
http://www.silabs.com/integration).
f0
is the channel center frequency (see the
next command)
M is the three bit binary number <m2 : m0>
SIGN = (ms) XOR (FSK input)
Si4022
Frequency Setting Command
bit
15
1
14
0
13
1
12
0
11
10
9
8
7
6
5
4
3
2
1
0
POR
f11
f10
f9
f8
f7
f6
f5
f4
f3
f2
f1
f0
AD57h
The constant C is determined by
the selected band as:
The 12-bit parameter of the Frequency Setting
Command <f11 : f0> has the value F. The value F
should be in the range of 96 and 3903. When F is out
of range, the previous value is kept. The synthesizer
center frequency f 0 can be calculated as:
Band [MHz]
868
C
10
11
915
= 8 * 10 MHz * (C + F/4000)
f0
Power Management Command
bit
15
1
14
1
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
4
3
2
1
0
POR
ex
es
etr
eb
et
dc
C002h
Bit 5 <ex>:
Bit 4 <es>:
Bit 3 <etr>:
Enables the the crystal oscillator.
Enables the synthesizer.
Enables the power amplifier. If the ex and es bit is not set, it switches on the crystal oscillator and the
synthesizer as well.
In FIFO mode (bit fe is set in the FIFO Setting Command) setting this bit will roll out the content of the FIFO.
Bit 2 <eb>:
Enables the low battery detector.
Bit 1 <et>:
Bit 0 <dc>:
Enables the wake-up timer.
Disables the clock output buffer.
Note:
If faster operation is needed, then leave ex and es bit set to ‘1’ and toggle only the etr bit.
Power Saving Modes
The different operating modes of the chip depend on the following control bits:
Operating Mode
eb or et
es
etr
ex
Active (transmit)
Idle
X
X
1
x
0
0
0
1
0
0
0
x
1
0
0
Sleep
Standby
0
Transmitter FIFO Write Command
Bit
7
1
6
1
5
0
4
0
3
0
2
1
1
1
0
0
POR
-
With this command, the controller can write databits to the transmitter FIFO. Bit (fe) must be set in the FIFO Setting Command.
Si4022
Transmitter FIFO register write
nSEL
0
0
N-2
N-1
1
2
3
4
5
6
7
1
2
3
4
5
SCK
SDI
instruction
filling up FIFO
N data bits
Data Transmit Sequence Through the FSK Pin
Itispossibleto transmitdatawithouttheFIFObyusingtheFSK inputpin. In thatcasethe poweramplifiershouldbeenabledfirstwith
the Power Management Comand.
P o w e r M a n a g e m e n t c o m m a n d
nSEL
C 0 h
3 8 h
SCK
SDI
instruction
t
sx *
xtal osc. stable
Xtal osc staus
Internal operations
ex, es, etr = 1
t
sp *
synthesizer / PLL /
PA status
synthesizer on, PLL locked, PA ready to transmit
T X D A T A
d o n ' t c a r e
FSK
NOTE:
* See page 5 for the timing values
Note:
•
If the crystal oscillator was formerly switched off (ex=0), the internal oscillator needs tsx time, to switch on. The actual value depends on
the type of quartz crystal used.
•
If the synthesizer was formerly switched off (es=0), the internal PLL needs tsp startup time. Valid data can be transmitted only when the
internal locking process is finished.
Si4022
FIFO Setting Command
bit
15
1
14
1
13
0
12
0
11
1
10
1
9
1
8
0
7
6
0
5
4
3
2
1
0
POR
fe
f5
f4
f3
f2
f1
f0
CE00h
Bit 7 <fe>:
Enables the 64 bit transmit FIFO. Resetting this bit clears the contents of the FIFO.
FIFO IT level. The FIFO generates IT when number of the remaining data bits in the FIFO reaches this leve
Bit 5-0 <f5 : f0>:
Data Rate Command
bit
15
1
14
1
13
0
12
0
11
1
10
0
9
0
8
0
7
6
5
4
3
2
1
0
POR
cs
r6
r5
r4
r3
r2
r1
r0
C813h
The bit rate of the transmitted data stream is determined by the 7-bit value R (bits r6 to r0) and the 1 bit cs.
BR = 10 MHz / 29 / (R+1) / (1 + cs*7)
In the receiver set R according the next function:
R= (10 MHz / 29 /(1 + cs*7)/ BR) – 1
Apart from setting custom values, the standard bit rates from 600 bps to 115.2 kbps can be approximated with small error.
Low Battery and Microcontroller Clock Divider Command
bit
15
1
14
1
13
0
12
0
11
0
10
0
9
1
8
0
7
6
5
4
3
2
1
0
POR
d2
d1
d0
elfc
t3
t2
t1
t0
C213h
The 4-bit value T of t3-t0 determines the threshold voltage of the threshold voltage V of the detector:
lb
V = 2.0 V + T * 0.1 V
lb
Bit 4 <elfc>:
Enables low frequency (32 kHz) microcontroller output clock during sleep mode.
Clock divider configuration (valid only if the crystal oscillator is on):
Clock Output
Frequency [MHz]
d2
d1
d0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
1.25
1.66
2
2.5
3.33
5
10
Wake-Up Timer Command
bit
15
1
14
1
13
1
12
0
11
r3
10
r2
9
8
7
6
5
4
3
2
1
0
POR
E196h
r1
r0
m7
m6
m5
m4
m3
m2
m1
m0
The wake-up time period can be calculated by M <m13 : m0> , R <r3 : r0> and D <d1 : d0>:
= M * 2R-D ms
Twake-up
Si4022
Note:• The wake-up timer generates interrupts continuously at the programmed interval while the et bit is set.
Extended Wake-Up Timer Command
bit
15
1
14
1
13
0
12
0
11
0
10
0
9
1
8
1
7
6
5
4
3
2
1
0
POR
d1
d0 m13 m12 m11 m10 m9
m8
C300h
These bits can be used for further fine adjustment of the wake-up timer. The explanation of the bits can be found above.
Extended Features Command:
bit
15
1
14
0
13
1
12
1
11
0
10
0
9
0
8
0
7
6
5
0
4
3
2
1
0
POR
B0CAh
exlp ctls
dcal bw1 bw0 dsfi ewi
Bit 7 <exlp>:
Bit 6 <ctls>:
Bit 4 <dcal>:
Enables low power mode for the crystal oscillator.
Clock tail selection bit. Setting this bit selects 512 cycle long clock tail instead of the default 128.
Disables the wake-up timer autocalibration.
Bit 3-2 <bw1:bw0>: Select the bandwidth of the PLL.
bw1
0
bw0
0
PLL bandwidth
15 kHz
0
1
30 kHz
1
0
60 kHz
1
1
120 kHz
Bit 1 <dsfi>:
Bit 0 <ewi>:
Disables autosleep on FIFO interrupt if set to 1.
Enables the automatic wake-up on any interrupt event.
Status Register Read Command
bit
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
POR
-
With this command, it is possible to read the status register of the chip through the SDO pin.
FFIT
FFEM
FFOV
LBD
The number of data bits in the FIFO has gone below the preprogrammed limit
FIFO is empty
FIFO overflow
Low battery detect, the power supply voltage is below the preprogrammed limit
WK-UP
POR
Wake-up timer overflow
Power-on reset
Si4022
Status Register Read Sequence
nSEL
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
SDI
status out
FFIT
FFEM
FFOV
LBD
WK-UP
POR
SDO
Si4022
DualClockOutput
When the chip is switched into idle mode, the 10 MHz crystal oscillator starts. After oscillation ramp-up a 1 MHz clock signal is
available on the CLK pin. This (fast) clock frequency can be reprogrammed during operation with the Low Battery and Microcontroller
Clock Divider Command (page13). During startup and in sleep or standby mode (crystal oscillator disabled), the CLK output is pulled
to logic low.
On the same pin a low frequency clock signal can be obtained if the elfc bit is set in the Low Battery and Microcontroller Clock Divider
Command. The clock frequency is 32 kHz which is derived from the low-power RC oscillator of the wake-up timer. In order to use this
slow clock the wake-up timer should be enabled by setting the et bit in the Power Management Command (page 11) even if the wake-
up timer itself is not used.
Slow clock feature can be enabled by entering into sleep mode (page 11). Driving the output will increase the sleep mode supply
current. Actual worst-case value can be determined when the exact load and min/max operating conditions are defined. After power-
on reset the chip goes into sleep mode and the slow frequency clock appears on the CLK pin.
Switching back into fast clock mode can be done by setting the ex or etr bits in the approriate commands. It is important to leave bit
dc in the Power Management Command at its default state (0) otherwise there will be no clock signal on the CLK pin.
Switching between the fast and slow clock modes is glitch-free in a sense that either state of the clock lasts for at least a half cycle
of the fast clock. During switching the clock can be logic low once for an intermediate period i.e. for any time between the half cycle
of the fast and the slow clock.
Tslow
clock periods are not to scale
slow clock
fast clock
output
Tfast
0.5 * Tfast < Tx < 0.5 * Tslow
Tx
The clock switching synchronization circuit detects the falling edges of the clocks. One consequence is a latency of 0 to T
from the
slow + Tfast
occurrence of a clock change request (entering into sleep mode or interrupt) until the beginning of the intermediate length (T ) hxalf cycle. The
other is that both clocks should be up and running for the change to occur. Changing from fast to slow clock, it is automatically ensured by
entering into the sleep mode in the appropriate way provided that the wake-up timer is continouosly enabled. As the crystal oscillator is
normally stopped while the slow clock is used, when changing back to fast clock the crystal oscillator startup time has to pass first before the
above mentioned latency period starts. The startup condition is detected internally, so no software timing is necessary.
Wake-UpTimerCalibration
By default the wake-up timer is calibrated each time it is enabled by setting the et bit in the Power Management Command. After
timeout the timer can be stopped by resetting this bit otherwise it operates continuously. If the timer is programmed to run for longer
periods, at approximately every 40 seconds it performs additional self-calibration.
This feature can be disabled to avoid sudden changes in the actual wake-up time period. A suitable software algorithm can then
compensate for the gradual shift caused by temperature change.
Bit dcal in the Extended Features Command (page 14) controls the automatic calibration feature. It is reset to 0 at power-on and the
automatic calibration is enabled. This is necessary to compensate for process tolerances. After one calibration cycle further
(re)calibration can be disabled by setting this bit to 1.
Si4022
MATCHING NETWORK FOR A 50 OHM SINGLE ENDED OUTPUT
Matching Network Schematic
VDD
L3
to RFP
50 Ohm
load
3.9
6.8
C1 , C2 [pF]
L1 [nH]
C1
C2
L1
GND
100
L3 [nH]
to RFN
GND
RX-TX ALIGNMENT PROCEDURES
RX-TX frequency offset can be caused only by the differences in the actual reference frequency. To minimize these errors it is
suggested to use the same crystal type and the same PCB layout for the crystal placement on the RX and TX PCBs.
To verify the possible RX-TX offset it is suggested to measure the CLK output of both chips with a high level of accuracy. Do not
measure the output at the XTL pin since the measurement process itself will change the reference frequency. Since the carrier
frequencies are derived from the reference frequency, having identical reference frequencies and nominal frequency settings at the
TX and RX side there should be no offset if the CLK signals have identical frequencies.
It is possible to monitor the actual RX-TX offset using the AFC status report included in the status byte of the receiver. By reading out
the status byte from the receiver the actual measured offset frequency will be reported. In order to get accurate values the AFC has
to be disabled during the read by clearing the "en" bit in the AFC Control Command (bit 0).
Si4022
CRYSTAL SELECTION GUIDELINES
The crystal oscillator of the Si4022 requires a 10 MHz parallel mode crystal. The circuit contains an integrated load capacitor in order
to minimize the external component count. The internal load capacitance value is programmable from 8.5 pF to 16 pF in 0.5 pF steps.
With appropriate PCB layout, the total load capacitance value can be 10 pF to 20 pF so a variety of crystal types can be used.
When the total load capacitance is not more than 20 pF and a worst case 7 pF shunt capacitance (C ) value is expected for the crystal,
the oscillator is able to start up with any crystal having less than 300 ohms ESR (equivalent series l0oss resistance). However, lower
C0 and ESR values guarantee faster oscillator startup. It is recommended to keep the PCB parasitic capacitances on the XTL pin as
low as possible.
The crystal frequency is used as the reference of the PLL, which generates the RF carrier frequency (f ). Therefore f
is directly
c
proportional to the crystal frequency. The accuracy requirements for production tolerance, temperature driftcand aging can thus be
determined from the maximum allowable carrier frequency error.
Maximum XTAL Tolerances Including Temperature and Aging [ppm]
2.4 kbps
Bit Rate:
Bit Rate:
Bit Rate:
Bit Rate:
Transmitter Deviation [+/- kHz]
20
40
60
80
100
120
140
160
868
915
2
2
12
12
25
20
30
30
40
40
50
50
70
60
80
70
9.6 kbps
Transmitter Deviation [+/- kHz]
20
40
60
80
100
120
140
160
868
915
do not use
do not use
8
8
20
15
30
30
40
40
50
50
60
60
70
70
38.4 kbps
Transmitter Deviation [+/- kHz]
20
40
60
80
100
120
140
160
868
915
do not use do not use
do not use do not use
10
10
20
20
30
30
40
40
50
50
70
60
115.2 kbps
Transmitter Deviation [+/- kHz]
80 100
20
40
60
120
140
160
868
915
do not use do not use do not use do not use do not use
do not use do not use do not use do not use do not use
2
2
12
12
25
20
Whenever a low frequency error is essential for the application, it is possible to “pull” the crystal to the accurate frequency by
changing the load capacitor value. The widest pulling range can be achieved if the nominal required load capacitance of the crystal
is in the “midrange”, for example 16 pF. The “pull-ability” of the crystal is defined by its motional capacitance and C .
0
Note: There may be other requirements for the TX carrier accuracy with regards to the requirements as defined by standards and/or
channel separations.
Si4022
EXAMPLE APPLICATIONS: DATA PACKET TRANSMISSION
Data packet structure
An example data packet structure using theSi4022 –Si4022 pair for data transmission. This packet structure is an example of how to use the
high efficiency FIFO mode at the receiver side:
AA AA AA 2D D4
D0 D1 D2
DN
. . .
Preamble
Databytes (received in the
FIFO of the receiver)
Synchron pattern
The first 3 bytes compose a 24 bit length ‘01’ pattern to let enough time for the clock recovery of the receiver to lock. The next two bytes
compose a 16 bit synchron pattern which is essential for the receiver’s FIFO to find the byte synchron in the received bit stream. The
synchron patters is followed by the payload. The first byte transmitted after the synchron pattern (D 0 in the picture above) will be the first
received byte in the FIFO.
I mportant: The bytes of the data stream should follow each other continuously, otherwise the clock recovery circuit of the receiver side
will be unable to track.
Further details of packet structures can be found in the IA ISM-UGSB1 software development kit manual.
Si4022
PACKAGE INFORMATION
16-pin TSSOP
Si4022
ORDERING INFORMATION
Si4022UniversalISMBandFSKTransmitter
DESCRIPTION
ORDERING NUMBER
Si4022 16-pin TSSOP
die
Si4022-IC CC16
see Silicon Labs
RevA0
DemoBoardsandDevelopmentKits
DESCRIPTION
ORDERING NUMBER
ISM Chipset Development Kit
IA ISM – DK3
RelatedResources
DESCRIPTION
ORDERING NUMBER
Antenna Selection Guide
IA ISM – AN1
IA ISM – AN2
Antenna Development Guide
IA4322 Universal ISM Band FSK Receiver
seehttp://www.silabs.com/integrationfordetails
Note: Volume orders must include chip revision to be accepted.
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Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using
or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and
"Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories reserves the right to
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