SI4205-BMR [SILICON]
RF and Baseband Circuit, CMOS, 8 X 8 MM, LGA-32;
| 型号： | SI4205-BMR |
| 厂家： | 
SILICON |
| 描述： | RF and Baseband Circuit, CMOS, 8 X 8 MM, LGA-32 电信 电信集成电路 |
| 文件： | 总38页 (文件大小：681K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Aero I
AERO™ I TRANSCEIVER
FOR GSM AND GPRS WIRELESS COMMUNICATIONS
Features
Pin Assignments
(Top View)
Single 8 x 8 mm package
CMOS process technology
Quad-band support:
z GSM 850 Class 4, small MS
z E-GSM 900 Class 4, small MS
z DCS 1800 Class 1
Si4205-BM
(For pin description see page 33)
Integrated GSM/GPRS
transceiver including:
z PCS 1900 Class 1
z Low-IF receiver
28
27
26
25
24
23
22
32
31
GPRS Class 12 compliant
z Universal baseband interface
z Offset-PLL transmitter
z Dual RF synthesizer
Integrated VCOs, frequency
synthesizers, and tuning inductors
21
20
19
18
17
16
15
1
2
3
4
5
6
7
RFIGN
RFIGP
RFIDN
RFIDP
RFIPN
RFIPP
GND
3-wire serial interface
RXQN
RXIP
RXIN
TXIP
GND
2.7 V to 3.0 V operation
GND
TXIN
GND
GND
TXQP
TXQN
Applications
29
30
8
9
10
11
12
13
14
Multi-band GSM/GPRS digital cellular handsets
Multi-band GSM/GPRS wireless data modems
Ordering Information:
See page 34.
Description
The Aero I transceiver is a complete RF front end for multi-band GSM
and GPRS wireless communications. The transmit section interfaces
between the baseband processor and the power amplifier. The receive
section interfaces between the RF band-select SAW filters and the
baseband processor. All sensitive components, such as RF/IF VCOs,
loop filters, and tuning inductors, are completely integrated into a single
compact package.
Patents pending
Functional Block Diagram
Si4205
GSM
LNA
PGA
PGA
ADC
ADC
PGA
PGA
DAC
I
DCS
PCS
LNA
LNA
DAC
Q
XOUT
0 / 90
100 kHz
I
DET
GSM
PA
PA
I
DCS
PCS
Q
VC-TCXO
13 or 26 MHz
RF
PLL
IF
PLL
XIN
AFC
Rev. 1.0 12/03
Copyright © 2003 by Silicon Laboratories
Aero I
Aero I
2
Rev. 1.0
Aero I
TABLE OF CONTENTS
Section
Page
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Frequency Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
XOUT Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Pin Descriptions: Si4205-BM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Package Outline: Si4205-BM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Rev. 1.0
3
Aero I
Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Symbol
TA
Test Condition
Min
–20
2.7
Typ
25
Max
85
Unit
°C
Ambient Temperature
DC Supply Voltage
VDD
2.85
3.0
V
Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at 2.85 V and an operating temperature of 25 °C unless otherwise stated. Parameters are tested in
production unless otherwise stated.
Table 2. Absolute Maximum Ratings1,2
Parameter
Symbol
VDD
Value
–0.5 to 3.3
±10
Unit
V
DC Supply Voltage
3
Input Current
IIN
mA
V
3
Input Voltage
VIN
–0.3 to (V + 0.3)
DD
Operating Temperature Range
Storage Temperature Range
TOP
–40 to 95
–55 to 150
10
°C
TSTG
°C
4
RF Input Level
dBm
Notes:
1. Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation
should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2. The Si4205 device is high-performance RF integrated circuit with an ESD rating of < 2 kV. Handling and
assembly of this device should only be done at ESD-protected workstations.
3. For signals SCLK, SDI, SEN, PDN, XEN, and XIN.
4. At SAW filter output for all bands.
4
Rev. 1.0
Aero I
Table 3. DC Characteristics
(VDD = 2.7 to 3.0 V, TA = –20 to 85 °C)
Parameter
Symbol
IRX
Test Condition
Receive mode
Min
—
Typ
80
82
1
Max
Unit
mA
mA
mA
µA
1
Supply Current
111
107
2
ITX
Transmit mode
PDN = 0, XEN = 1
—
IXOUT
IPDN
—
PDN = 0, XEN = 0,
XBUF = 0, XPD1 = 1
—
5
80
2
High Level Input Voltage
VIH
VIL
IIH
0.7 VDD
—
—
—
—
—
—
0.3 VDD
10
V
V
2
Low Level Input Voltage
2
High Level Input Current
VIH = VDD = 3.0 V
VIL = 0 V,
–10
µA
µA
2
Low Level Input Current
IIL
–10
10
V
DD = 3.0 V
3
High Level Output Voltage
VOH
VOL
VOH
VOL
IOH = –500 µA
IOL = 500 µA
IOH = –10 mA
IOL = 10 mA
VDD–0.4
—
—
—
—
—
—
0.4
—
V
V
V
V
3
Low Level Output Voltage
4
High Level Output Voltage
VDD–0.4
—
4
Low Level Output Voltage
0.4
Notes:
1. Measured with load on XOUT pin of 10 pF and fREF = 13 MHz. Limits with XEN = 1 guaranteed by characterization.
2. For pins SCLK, SDI, SEN, XEN, and PDN.
3. For pins SDO, XOUT.
4. For pins DIAG1, DIAG2.
Rev. 1.0
5
Aero I
Table 4. AC Characteristics
(VDD = 2.7 to 3.0 V, TA = –20 to 85 °C)
Symbol
Test Condition
Min
Typ
Max
Unit
Parameter
SCLK Cycle Time
tCLK
tR
Figures 1, 3
Figures 1, 3
Figures 1, 3
Figures 1, 3
Figures 1, 3
Figure 2
35
—
—
10
10
—
—
15
10
10
12
12
10
130
10
—
—
10
7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15
10
—
13
26
—
50
50
—
—
10
10
—
—
—
—
—
—
—
—
27
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
pF
kΩ
pF
SCLK Rise Time
SCLK Fall Time
tF
SCLK High Time
tHI
SCLK Low Time
tLO
PDN Rise Time
tPR
PDN Fall Time
tPF
Figure 2
SDI Setup Time to SCLK↑
SDI Hold Time from SCLK↑
SEN↓ to SCLK↑ Delay Time
SCLK↑ to SEN↑ Delay Time
SEN↑ to SCLK↑ Delay Time
tSU
Figure 3
tHOLD
tEN1
tEN2
tEN3
tW1, tW3
Figure 3
Figure 3
Figures 3, 4
Figures 3, 4
Figures 3, 4
DGAIN bits only
Option 2 only
Figure 4
1
SEN Pulse Width
tW2
tCA
SCLK↓ to SDO Time
2
Digital Input Pin Capacitance
3
XIN Input Resistance
R
20
14
—
—
—
XIN
3
XIN Input Capacitance
C
XIN
3
XIN Input Sensitivity
V
0.5
—
—
V
PP
REF
3,4
XIN Input Frequency
fREF
XSEL = 0, DIV2 = 0
XSEL = 1, DIV2 = 1
MHz
MHz
Notes:
1. Two programming options are allowed for SEN. Either option may be used. In both cases, the SEN pulse width must be
at least 10 ns after writing all registers except after DGAIN is written. After DGAIN is written, SEN must be held high for
at least 130 µs. See “AN50: Aero Transceiver Programming Guide.”
2. For pins SCLK, SDI, SEN, XEN, and PDN.
3. For XIN pin.
4. The XSEL and DIV2 bits control internal divide-by-two circuits and do not effect the XOUT pin.
6
Rev. 1.0
Aero I
tR
tF
80%
SCLK 50%
20%
tHI
tLO
tCLK
Figure 1. SCLK Timing Diagram
tPR
tPF
80%
20%
PDN
Figure 2. PDN Timing Diagram
80%
50%
20%
D17
D16
A0
D17
SDI
tSU
tHOLD
80%
50%
20%
SCLK
tEN3
tR
tLO
tHI
tF
tEN2
tEN1
tCLK
80%
50%
20%
SEN
(option 1)
tW 1
80%
50%
20%
SEN
(option 2)
tW 2
tW 3
Figure 3. Serial Interface Write Timing Diagram
80%
50%
20%
A0
SDI
SDO
80%
50%
20%
OD17
OD16
OD0
tCA
80%
50%
20%
SCLK
SEN
tEN2
tEN3
80%
50%
20%
tW1
Figure 4. Serial Interface Read Timing Diagram
Rev. 1.0
7
Aero I
Table 5. Receiver Characteristics
(VDD = 2.7 to 3.0 V, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
GSM 850 band
E-GSM 900 band
DCS 1800 band
PCS 1900 band
GSM 850 band
E-GSM 900 band
DCS 1800 band
PCS 1900 band
GSM 850 band
E-GSM 900 band
DCS 1800 band
PCS 1900 band
GSM 850 band
E-GSM 900 band
DCS 1800 band
PCS 1900 band
GSM input
Min
869
925
1805
1930
—
Typ
—
Max
894
960
1880
1990
3.8
3.9
4.1
4.5
4.5
4.6
5.0
5.7
4.6
4.7
5.4
6.0
—
Unit
MHz
MHz
MHz
MHz
dB
1
f
GSM Input Frequency
IN
—
1
—
DCS or PCS Input Frequency
—
2,3
NF
2.9
3.0
3.3
3.7
3.6
3.7
4.2
4.9
3.7
3.8
4.6
5.2
–21
–25
–16
–15
40
Noise Figure at 25 °C
25
—
dB
—
dB
—
dB
2,3
NF
—
dB
Noise Figure at 75 °C
75
—
dB
—
dB
—
dB
2,3
NF
—
dB
Noise Figure at 85 °C
85
—
dB
—
dB
—
dB
2,3,4
DES
–25
–28
–21
–19
29
dBm
dBm
dBm
dBm
dBm
3 MHz Input Desensitization
3
DCS/PCS inputs
GSM input
—
2,3,4
DES
—
20 MHz Input Desensitization
20
DCS/PCS inputs
|f – f | ≥ 6 MHz,
—
2
IP2
IP3
IR
—
Input IP2
1,2
0
|f – f | = 100 kHz
2
1
2
|f – f | ≥ 800 kHz,
–18
–12
—
dBm
Input IP3
2
1
f = 2f – f
0
1
2
2,4
GSM Input
28
28
35
40
—
—
dB
dB
Image Rejection
DCS/PCS Inputs
GSM Input
2,5
CP
–28
–27
–23
–23
3
–23
–22
–18
–18
8.5
15.5
104
102
17
—
dBm
dBm
dBm
dBm
dB
1 dB Input Compression
MAX
DCS/PCS inputs
GSM Input
—
2,6
CP
—
1 dB Input Compression
MIN
DCS/PCS inputs
GSM input
—
2,6,7
G
12.5
19.5
109
107
—
Minimum Voltage Gain
MIN
DCS/PCS inputs
GSM input
10
dB
2,7
G
100
96
dB
Maximum Voltage Gain
MAX
DCS/PCS inputs
GSM input
dB
3,8
G
—
dB
LNA Voltage Gain
LNA
DCS/PCS inputs
GSM input
—
15
—
dB
∆G
13
17
21
dB
LNA Gain Control Range
LNA
DCS/PCS inputs
4
8
12
dB
8
Rev. 1.0
Aero I
Table 5. Receiver Characteristics (Continued)
(VDD = 2.7 to 3.0 V, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
13
3.2
—
Typ
16
Max
Unit
dB
∆G
19
4.8
—
Analog PGA Control Range
Analog PGA Step Size
Digital PGA Control Range
Digital PGA Step Size
APGA
4.0
63
dB
∆G
dB
DPGA
—
1
—
dB
9
DACFS[1:0] = 00
DACFS[1:0] = 01
DACFS[1:0] = 10
DACCM[1:0] = 00
DACCM[1:0] = 01
DACCM[1:0] = 10
0.7
1.5
2.6
0.8
1.05
1.15
—
1.0
2.0
3.5
1.0
1.25
1.35
—
1.3
2.5
4.4
1.2
1.45
1.55
16
5
V
Maximum Differential Output Voltage
PPD
PPD
V
V
PPD
9
V
Output Common Mode Voltage
V
V
9,10,11
mV
mV
%
Differential Output Offset Voltage
9,10,11
—
—
Differential Output Offset Voltage Drift
9,11
—
—
1
Baseband Gain Error
9,11
—
—
1
deg
kΩ
pF
µs
Baseband Phase Error
9
R
Single-ended
Single-ended
CSEL = 0
10
—
—
—
Output Load Resistance
L
9
C
—
10
22
16
1.5
1
Output Load Capacitance
L
12
—
—
Group Delay
CSEL = 1
—
—
µs
12
CSEL = 0
—
—
µs
Differential Group Delay
CSEL = 1
—
—
µs
3,13
From powerdown
—
200
220
µs
Powerup Settling Time
Notes:
1. GSM input pins RFIGP and RFIGN. DCS input pins RFIDP and RFIDN. PCS input pins RFIPP and RFIPN.
2. Measurement is performed with a 2:1 balun (50 Ω input, 200 Ω balanced output) and includes matching network and
PCB losses. Measured at max gain (AGAIN[2:0] =100b, LNAG[1:0] = 01b, LNAC[1:0] = 01b) unless otherwise noted.
Noise figure measurements are referred to 290 °K. Insertion loss of the balun is removed.
3. Specifications guaranteed by characterization using LQW15AN series matching inductors.
4. Input signal at balun is –102 dBm. SNR at baseband output is 9 dB.
5. AGAIN[2:0]=min=000b, LNAG[1:0] = max=01b, LNAC[1:0] =max= 01b.
6. AGAIN[2:0]=min=000b, LNAG[1:0] = min=00b, LNAC[1:0] = min=00b.
7. Voltage gain is defined as the differential rms voltage at the RXIP/RXIN pins or RXQP/RXQN pins divided by the rms
voltage at the balun input with DACFS[1:0] = 01 and CSEL = 1. Gain is 1.5 dB higher with CSEL = 0. Minimum and
maximum values do not include the variation in the DAC full scale voltage (also see Maximum Differential Output
Voltage specification).
8. Voltage gain is defined as the differential rms voltage at the LNA output divided by the rms voltage at the balun output.
9. Output pins RXIP, RXIN, RXQP, RXQN.
10. Specified as root sum square:
2 . Drift specification applies to dc offset
(RXIP – RXIN)2 + (RXQP – RXQN)
calibration and is guaranteed by characterization. See ZERODEL[2:0] in the register description.
11. The baseband signal path is entirely digital. Gain, phase, and offset errors at the baseband outputs are because of the
D/A converters. Offsets can be measured and calibrated out. See ZERODEL[2:0] in the register description.
12. Group delay is measured from antenna input to baseband outputs. Differential group delay is measured in-band.
13. Includes settling time of the frequency synthesizer. Settling to 5 degrees phase error measured at RXIP, RXIN, RXQP,
and RXQN pins.
Rev. 1.0
9
Aero I
Receive Path Magnitude Response (CSEL = 0)
Receive Path Magnitude Response (CSEL = 1)
0
0
−20
−20
−40
−60
−80
−40
−60
−80
−100
−120
0
50
100
150
200
250
300
350
400
0
50
100
150
200
250
300
350
400
100
100
Frequency (KHz)
Frequency (KHz)
Figure 5. Receive Path Magnitude Response (CSEL = 0 and CSEL = 1)
Receive Path Passband Magnitude Response (CSEL = 0)
Receive Path Passband Magnitude Response (CSEL = 1)
2
0
2
0
−2
−2
−4
−4
−6
−6
−8
−8
−10
−12
−14
−16
−10
−12
−14
−16
0
10
20
30
40
50
60
70
80
90
100
0
10
20
30
40
50
60
70
80
90
Frequency (KHz)
Frequency (KHz)
Figure 6. Receive Path Passband Magnitude Response (CSEL = 0 and CSEL = 1)
Receive Path Passband Group Delay (CSEL = 0)
Receive Path Passband Group Delay (CSEL = 1)
25
24
23
22
21
20
19
18
17
16
15
20
19
18
17
16
15
14
13
12
11
10
0
10
20
30
40
50
60
70
80
90
100
0
10
20
30
40
50
60
70
80
90
Frequency (KHz)
Frequency (KHz)
Figure 7. Receive Path Passband Group Delay (CSEL = 0 and CSEL = 1)
10
Rev. 1.0
Aero I
Table 6. Transmitter Characteristics
(VDD = 2.7 to 3.0 V, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
GSM 850 band
E-GSM 900 band
DCS 1800 band
PCS 1900 band
Min
824
880
1710
1850
0.88
1.1
26
Typ
—
Max
Unit
MHz
MHz
MHz
MHz
1
RFOG Output Frequency
849
915
1785
1910
2.2
1.4
35
—
2
RFOD Output Frequency
—
—
3,4
I/Q Differential Input Swing
—
V
PPD
3
I/Q Input Common-Mode
—
V
3,4
I/Q Differential Input Resistance
BBG[1:0] = 11
30
kΩ
kΩ
b
BBG[1:0] = 00
22
25
29
b
BBG[1:0] = 01
17
20
23
kΩ
b
Powered down
—
Hi-Z
—
—
kΩ
3,5
I/Q Input Capacitance
—
5
pF
3
I/Q Input Bias Current
13
16
19
µA
Sideband Suppression
Carrier Suppression
IM3 Suppression
67.7 kHz sinusoid
67.7 kHz sinusoid
67.7 kHz sinusoid
—
–46
–48
–57
1.9
5
–34
–33
–50
3.0
10
dBc
dBc
dBc
—
—
5
o
Phase Error
—
rms
o
—
PEAK
1,2
TXVCO Pushing
Open loop
—
100
200
—
kHz/V
1,2
TXVCO Pulling
VSWR 2:1, all phases,
open loop
—
—
kHz
PP
1,6
RFOG Output Modulation Spectrum
400 kHz offset
1.8 MHz offset
400 kHz offset
1.8 MHz offset
10 MHz offset
20 MHz offset
20 MHz offset
—
—
—
—
—
—
—
7
–65
–70
–65
–70
–160
–166
–163
9
–63
–68
–63
–65
–155
–164
–157
11
dBc
dBc
dBc
2,6
RFOD Output Modulation Spectrum
dBc
1,5,7
RFOG Output Phase Noise
dBc/Hz
dBc/Hz
dBc/Hz
dBm
2,5,7
RFOD Output Phase Noise
1
RFOG Output Power Level
Z = 50 Ω
L
2
RFOD Output Power Level
Z = 50 Ω
6
8
10
dBm
L
Rev. 1.0
11
Aero I
Table 6. Transmitter Characteristics (Continued)
(VDD = 2.7 to 3.0 V, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
2nd harmonic
Min
—
Typ
—
Max
–20
–10
150
Unit
dBc
dBc
µs
1,2
RF Output Harmonic Suppression
3rd harmonic
—
—
5,8
Powerup Settling Time
From powerdown
—
—
Notes:
1. Measured at RFOG pin.
2. Measured at RFOD pin.
3. Input pins TXIP, TXIN, TXQP, and TXQN.
4. Differential Input Swing is programmable with the BBG[1:0] bits in register 04h. Program these bits to the closest
appropriate value. The I/Q Input Resistance scales inversely with the BBG[1:0] setting.
5. Specifications guaranteed by characterization.
6. Measured with pseudo-random pattern. Carrier power and noise power < 1.8 MHz measured with 30 kHz RBW. Noise
power ≥ 1.8 MHz measured with 100 kHz RBW.
7. Measured with all 1s pattern.
8. Including settling time of the frequency synthesizer. Settling time measured at the RFOD and RFOG pins to 0.1 ppm
frequency error.
12
Rev. 1.0
Aero I
Table 7. Frequency Synthesizer Characteristics
(VDD = 2.7 to 3.0 V, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
1
f
GSM 850 band
E-GSM 900 band
DCS 1800 band
PCS 1900 band
GSM 850 band
E-GSM 900
1737.8
1849.8
1804.9
1929.9
1272
1279
1327
1423
—
—
—
1787.8
1919.8
1879.9
1989.9
1297
1314
1402
1483
—
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
RF1 VCO Frequency
RF1
—
—
1
f
—
RF2 VCO Frequency
RF2
—
DCS 1800 band
PCS 1900 band
GSM 850 band
—
—
1
f
896
798
IF VCO Frequency
IF
E-GSM 900 band
880–895 MHz
900–915 MHz
—
—
E-GSM 900 band
895–900 MHz
—
790
—
MHz
DCS 1800 band
PCS 1900 band
—
—
—
766
854
200
—
—
—
MHz
MHz
kHz
f
GSM input,
RFUP = 0
RF1 PLL Phase Detector Update
Frequency
φ
DCS/PCS inputs,
RFUP = 1
—
—
100
200
—
—
kHz
kHz
f
IF and RF2 PLL Phase Detector
Update Frequency
φ
2
Open Loop
—
—
—
—
—
—
—
—
—
—
—
—
500
400
300
400
100
100
–144
–126
–128
–95
–80
–80
—
—
kHz/V
kHz/V
kHz/V
RF1 VCO Pushing
2
RF2 VCO Pushing
2
—
IF VCO Pushing
2
VSWR = 2:1,
all phases, open loop
—
kHz
RF1 VCO Pulling
PP
2
—
kHz
RF2 VCO Pulling
PP
2
—
kHz
IF VCO Pulling
PP
2
3 MHz offset
400 kHz offset
400 kHz offset
3 MHz offset
–138
–121
–123
–83
–75
–70
dBc/Hz
dBc/Hz
dBc/Hz
dBc
RF1 PLL Phase Noise
2
RF2 PLL Phase Noise
2
IF PLL Phase Noise
2
RF1 PLL Spurious
2
400 kHz offset
400 kHz offset
dBc
RF2 PLL Spurious
2
dBc
IF PLL Spurious
Notes:
1. For the GSM input, the RF1 VCO is divided by two. During transmit, the IF VCO is divided by two.
2. Specifications are guaranteed by characterization.
Rev. 1.0
13
Aero I
Typical Application Schematic
RFOG
RFOD
DIAG1
DIAG2
XEN
XOUT
C1
C2
Z1
Z2
Z3
GSM900 IN
OUT+
OUT-
IN
L1
L2
L3
RXQP
GND
VDD
32
31
VDD
C8
GND
1
21
20
19
18
17
16
15
RXQN
RXIP
RXIN
TXIP
TXIN
TXQP
TXQN
RXQN
RXIP
RXIN
TXIP
RFIGN
RFIGP
RFIDN
RFIDP
RFIPN
RFIPP
GND
2
3
4
5
6
7
U1
C3
Si4205
TXIN
TXQP
TXQN
DCS 1800 IN
OUT+
OUT-
IN
GND
29
30
GND
GND
C4
C5
R1
XIN
VDD
C7
PCS 1900 IN
OUT+
OUT-
IN
SDI
SCLK
SENB
PDNB
SDO
GND
C6
Notes:
1. Connect pads on bottom of U1 to GND.
2. See “AN92: Aero™ I/Aero™ I+ Transceiver PCB Layout Guidelines” for details on the following:
z LNA matching network (C1–C6, L1–L3). Values should be custom tuned for a specific PCB layout and SAW filter to
optimize performance.
z Differential traces between the SAW filters (Z1–Z3) and transceiver (U1) pins 16–21.
z Detailed SAW filter requirements.
3. For the XIN input, no external ac coupling is required.
4. For optimum performance, connect pin 31 to ground plane of power amplifier through several vias close to pin.
14
Rev. 1.0
Aero I
Bill of Materials
Component
Value/Description
Supplier(s)
C1–C2
1.2 pF, ±0.1 pF, C0G
(GSM 850 and E-GSM 900)
Murata GRM36C0G series
Venkel C0402C0G500 series
C3–C4
C5–C6
1.2 pF, ±0.1 pF, C0G
(DCS 1800)
Murata GRM36C0G series
Venkel C0402C0G500 series
1.5 pF, ±0.1 pF, C0G
(PCS 1900)
Murata GRM36C0G series
Venkel C0402C0G500 series
C7
C8
L1
22 nF, ±20%, Z5U
10 pF, ±20%, C0G
24 nH, ±2%
Murata LQG15HN series (0402 size)
Murata LQW15AN series (0402 size)
L2
L3
6.8 nH, ±0.2 nH
5.6 nH, ±0.2 nH
Murata LQG15HN series (0402 size)
Murata LQW15AN series (0402 size)
Murata LQG15HN series (0402 size)
Murata LQW15AN series (0402 size)
R1
U1
Z1
100 Ω, ±5%
GSM/GPRS Transceiver
Silicon Laboratories Si4205
GSM 850 RX SAW Filter
(150 Ω balanced output)
Epcos B39881-B9001-C710 (5-pin, 1.4 x 2.0 mm)
Epcos B39881-B9004-E710 (6-pin, 1.6 x 2.0 mm)
Murata SAFEK881MFL0T00R00 (6-pin, 1.6 x 2.0 mm)
E-GSM 900 RX SAW Filter
(150 Ω balanced output)
Epcos B39941-B7820-C710 (5-pin, 1.4 x 2.0 mm)
Epcos B39941-B9017-K310 (6-pin, 1.6 x 2.0 mm)
Murata SAFEK942MFM0T00R00 (6-pin, 1.6 x 2.0 mm)
Z2
Z3
DCS 1800 RX SAW Filter
(150 Ω balanced output)
Epcos B39182-B7821-C710 (5-pin, 1.4 x 2.0 mm)
Epcos B39182-B9013-K310 (6-pin, 1.6 x 2.0 mm)
Murata SAFEK1G84FA0T00R00 (6-pin, 1.6 x 2.0 mm)
PCS 1900 RX SAW Filter
(150 Ω balanced output)
Epcos B39202-B7825-C710 (5-pin, 1.4 x 2.0 mm)
Epcos B39202-B9020-K310 (6-pin, 1.6 x 2.0 mm)
Murata SAFEK1G96FA0T00R00 (6-pin, 1.6 x 2.0 mm)
Rev. 1.0
15
Aero I
Functional Description
Si4205
GSM
LNA
PGA
PGA
ADC
ADC
PGA
PGA
DAC
I
DCS
PCS
LNA
LNA
DAC
Q
XOUT
0 / 90
100 kHz
I
DET
GSM
PA
PA
I
DCS
PCS
Q
VC-TCXO
13 or 26 MHz
RF
PLL
IF
PLL
XIN
AFC
Figure 8. Aero I Transceiver Block Diagram
The Aero I transceiver is the industry’s most integrated compatible with any supplier’s baseband subsystem.
RF front end for multi-band GSM/GPRS digital cellular
The transmit section is a complete up-conversion path
handsets and wireless data modems. The highly
from the baseband subsystem to the power amplifier,
integrated solution eliminates the IF SAW filter, external
and uses an offset phase-locked loop (PLL) with a fully
low noise amplifiers (LNAs) for three bands, transmit
integrated transmit VCO. The frequency synthesizer
and RF voltage controlled oscillator (VCO) modules,
uses Silicon Laboratories’ proven technology, which
and more than 70 other discrete components found in
includes integrated RF and IF VCOs, varactors, and
conventional designs.
loop filters.
The high level of integration obtained through high-
The unique integer-N PLL architecture produces a
performance packaging and fine line CMOS process
transient response that is superior in speed to
technology results in a solution with 50% less area and
fractional-N architectures without suffering the high
80% fewer components than competing solutions. A
phase noise or spurious modulation effects often
triple-band GSM transceiver using the Aero I
associated with those designs. This fast transient
response makes the Aero I transceiver well suited to
transceiver can be implemented with 15 components in
2
less than 1.2 cm of board area. This level of integration
GPRS multi-slot applications where channel switching
is an enabling force in lowering the cost, simplifying the
and settling times are critical.
design and manufacturing, and shrinking the form factor
While conventional solutions use BiCMOS or other
in next-generation GSM/GPRS voice and data
bipolar process technologies, the Aero I transceiver
terminals.
employs 100% CMOS process. This brings the dramatic
The receive section uses a digital low-IF architecture
cost savings and extensive manufacturing capacity of
that avoids the difficulties associated with direct
CMOS to the GSM market.
conversion while delivering lower solution cost and
reduced complexity. The baseband interface is
16
Rev. 1.0
Aero I
Receiver
Si4205
LNA
LNA
LNA
GSM
DCS
PCS
DAC
I
PGA
ADC
ADC
PGA
PGA
Q
PGA
DAC
DGAIN[5:0]
AGAIN[2:0]
CSEL
RXBAND[1:0]
LNAC[1:0]
LNAG[1:0]
100 kHz
DACCM[1:0]
DACFS[1:0]
ZERODEL[2:0]
0/90
NRF1[15:0]
RFUP
RF
PLL
Figure 9. Receiver Block Diagram
The Aero I transceiver uses
a
low-IF receiver with the AGAIN[2:0] bits in register 05h. The quadrature
architecture which allows for the on-chip integration of IF signal is digitized with high resolution A/D converters
the channel selection filters, eliminating the external RF (ADCs).
image reject filters and the IF SAW filter required in
The ADC output is downconverted to baseband with a
conventional superheterodyne architectures. Compared
digital 100 kHz quadrature LO signal. Digital decimation
to
a
direct-conversion architecture, the low-IF
and IIR filters perform channel selection to remove
blocking and reference interference signals. The
response of the IIR filter is programmable to a high
selectivity setting (CSEL = 0) or a low selectivity setting
(CSEL = 1). The low selectivity filter has a flatter group
delay response which may be desirable where the final
channelization filter is in the baseband chip. After
architecture has a much greater degree of immunity to
dc offsets, which can arise from RF local oscillator
(RFLO) self-mixing, 2nd-order distortion of blockers,
and device 1/f noise. This relaxes the common-mode
balance requirements on the input SAW filters, and
simplifies PC board design and manufacturing.
Three differential-input LNAs are integrated. The GSM channel selection, the digital output is scaled with a
input supports the GSM 850 (869–894 MHz) or E- digital PGA, which is controlled with the DGAIN[5:0] bits
GSM 900 (925–960 MHz) bands. The DCS input in register 05h.
supports the DCS 1800 (1805–1880 MHz) band. The
The LNAG[1:0], LNAC[1:0], AGAIN[2:0] and DGAIN[5:0]
PCS input supports the PCS 1900 (1930–1990 MHz)
bits must be set to provide a constant amplitude signal
band. For quad-band designs, SAW filters for the
to the baseband receive inputs. See “AN51: Aero
GSM 850 and E-GSM 900 bands should be connected
Transceiver AGC Strategy” for more details.
to a balanced combiner which drives the GSM input for
DACs drive a differential analog signal onto the RXIP,
both bands.
RXIN, RXQP, and RXQN pins to interface to standard
The LNA inputs are matched to the 150 Ω balanced-
output SAW filters through external LC matching
networks. The LNA gain is controlled with the
LNAG[1:0] and LNAC[1:0] bits in register 05h.
analog-input baseband ICs. No special processing is
required in the baseband for offset compensation or
extended dynamic range. The receive and transmit
baseband I/Q pins can be multiplexed together into a 4-
A quadrature image-reject mixer downconverts the RF wire interface. The common mode level at the receive I
signal to a 100 kHz intermediate frequency (IF) with the and Q outputs is programmable with the DACCM[1:0]
RFLO from the frequency synthesizer. The RFLO bits, and the full scale level is programmable with the
frequency is between 1737.8 to 1989.9 MHz, and is DACFS[1:0] bits in register 12h.
internally divided by 2 for GSM 850 and E-GSM 900
modes. The mixer output is amplified with an analog
programmable gain amplifier (PGA), which is controlled
Rev. 1.0
17
Aero I
Transmitter
Si4205
NIF[15:0]
PDIB
RF
PLL
IF
PLL
NRF2[15:0]
PDRB
y2
BBG[1:0]
SWAP
REG
TXIP
I
FIF[3:0]
RFOG
GSM
PA
PA
REG
TXIN
RFOD
I
DET
DCS/PCS
y1, 2
TXBAND[1:0]
Figure 10. Transmitter Block Diagram
TXQP
Q
TXQN
The transmit (TX) section consists of an I/Q baseband low-side injection is used for the DCS 1800 and
upconverter, an offset phase-locked loop (OPLL) and PCS 1900 bands. The I and Q signals are automatically
two output buffers that can drive external power swapped when switching bands. Therefore, there is no
amplifiers (PA), one for the GSM 850 (824 to 849 MHz) need for the customer to externally swap the I and Q
and E-GSM 900 (880 to 915 MHz) bands and one for signals. However, for additional layout flexibility, the
the DCS 1800 (1710 to 1785 MHz) and PCS 1900 SWAP bit in register 03h can be used to manually
(1850 to 1910 MHz) bands. The OPLL requires no exchange the I and Q signals.
external duplexer to attenuate transmitter noise or
Low-pass filters before the OPLL phase detector reduce
spurious signals in the receive band, saving both cost
the harmonic content of the quadrature modulator and
and power. Additionally, the output of the transmit VCO
feedback mixer outputs. The cutoff frequency of the
(TXVCO) is a constant-envelope signal that reduces the
filters is programmable with the FIF[3:0] bits in register
problem of spectral spreading caused by non-linearity in
04h, and should be set to the recommended settings
detailed in the register description.
the PA.
A quadrature mixer upconverts the differential in-phase
(TXIP, TXIN) and quadrature (TXQP, TXQN) signals
with the IFLO to generate a SSB IF signal that is filtered
and used as the reference input to the OPLL. The IFLO
frequency is generated between 766 and 896 MHz and
internally divided by 2 to generate the quadrature LO
signals for the quadrature modulator, resulting in an IF
between 383 and 448 MHz. For the E-GSM 900 band,
two different IFLO frequencies are required for spur
management. Therefore, the IF PLL must be
programmed per channel in the E-GSM 900 band. The
IFLO frequencies are defined in Table 7 on page 13.
The OPLL consists of a feedback mixer, a phase
detector, a loop filter, and a fully integrated TXVCO. The
TXVCO is centered between the DCS 1800 and
PCS 1900 bands, and its output is divided by 2 for the
GSM 850 and E-GSM 900 bands. The RFLO frequency
is generated between 1272 and 1483 MHz. To allow a
single VCO to be used for the RFLO, high-side injection
is used for the GSM 850 and E-GSM 900 bands, and
18
Rev. 1.0
Aero I
Frequency Synthesizer
Si4205
y65,
RF1
XIN
y1, 2
DIV2
I
DET
To
RX/TX
y130
RF2
RFUP
XOUT
XEN
NRF1[15:0]
RF2[15:0]
Self
Tune
N
RF PLL
IF PLL
yN
PDIB
PDRB
Power
PDN
Control
yN
SDI
SDO
Self
Tune
NIF[15:0]
Serial
I/O
SCLK
SEN
SDOSEL[4:0]
I
DET
To TX
Figure 11. Frequency Synthesizer Block Diagram
The Aero I transceiver integrates two complete PLLs
including VCOs, varactors, resonators, loop filters,
reference and VCO dividers, and phase detectors. The
RF PLL uses two multiplexed VCOs. The RF1 VCO is
used for receive mode, and the RF2 VCO is used for
transmit mode. The IF PLL is used only during transmit
mode. All VCO tuning inductors are also integrated.
The IF and RF output frequencies are set by
programming the N-Divider registers, N
, N
and
RF1
RF2
N . Programming the N-Divider register for either RF1
IF
or RF2 automatically selects the proper VCO. The
output frequency of each PLL is as follows:
fOUT = N × fφ
The DIV2 bit in register 31h controls a programmable
divider at the XIN pin to allow either a 13 or 26 MHz
reference frequency. For receive mode, the RF1 PLL
phase detector update rate (f ) should be programmed
φ
f = 100 kHz for DCS 1800 or PCS 1900 bands, and
φ
f = 200 kHz for GSM 850 and E-GSM 900 bands. For
φ
transmit mode, the RF2 and IF PLL phase detector
update rates are always f =200 kHz.
φ
Rev. 1.0
19
Aero I
Serial Interface
XOUT Buffer
A three-wire serial interface is provided to allow an The Aero I transceiver contains a reference clock buffer
external system controller to write the control registers to drive the baseband input. The clock signal from the
for dividers, receive path gain, powerdown settings, and VC-TCXO is capacitively coupled to the XIN pin. The
other controls. The serial control word is 24 bits in clock signal is not divided with the XSEL control.
length, comprised of an 18-bit data field and a 6-bit
address field as shown in Figure 12.
The XOUT buffer is a CMOS driver stage with
approximately 250 Ω of series resistance. This buffer is
enabled when the XEN hardware control (pin 26 on the
Si4205) is set high, independent of the PDN control pin.
To achieve complete powerdown during sleep, the XEN
Last bit
clocked in
pin must be set low, the XBUF bit in Register 12 must
D
D
D
D
D
D
D
D
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
5
A
4
A
3
A
2
A
1
A
0
17 16 15 14 13 12 11 10
be set to zero, and the XPD1 bit in Register 11 must be
set to one. During normal operation, these bits should
be set to their default values.
Address
Field
Data Field
Figure 12. Serial Interface Format
All registers must be written when the PDN pin is
asserted (low), except for register 22h. All serial
interface pins should be held at a constant level during
receive and transmit bursts to minimize spurious
emissions. This includes stopping the SCLK clock. A
timing diagram for the serial interface is shown in
Figure 3 on page 7.
When the serial interface is enabled (i.e., when SEN is
low), data and address bits on the SDI pin are clocked
into an internal shift register on the rising edge of SCLK.
Data in the shift register is then transferred on the rising
edge of SEN into the internal data register addressed in
the address field. The internal shift register ignores any
leading bits before the 24 required bits. The serial
interface is disabled when SEN is high.
Optionally, registers can be read as illustrated in
Figure 4 on page 7. The serial output data appears on
the SDO pin after writing the revision register with the
address to be read. Writing to any of the registers
causes the function of SDO to revert to its previously
programmed function.
20
Rev. 1.0
Aero I
Control Registers
Table 8. Register Summary
Bit
Reg Name
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1
D0
01h
02h
03h
04h
05h
11h
12h
19h
20h
21h
22h
23h
24h
31h
32h
Reset
Mode
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0
SWAP
0
AUTO
MODE[1:0]
Config
DIAG[1:0]
TXBAND[1:0] RXBAND[1:0]
FIF[3:0]
0
0
1
0
0
0
Transmit
Receive
Config
0
0
BBG[1:0]
DGAIN[5:0]
XPD1
0
AGAIN[2:0]
LNAC[1:0]
LNAG[1:0]
DPDS[2:0]
1
XBUF
0
XSEL
0
ZDBS
0
1
0
0
1
0
0
0
0
CSEL
DAC Config
Reserved
0
0
0
0
0
0
1
0
0
0
ZERODEL[2:0]
0
DACCM[1:0]
DACFS[1:0]
0
0
0
0
RX Master #1 RXBAND[1:0]
NRF1[15:0]
AGAIN[2:0]
RX Master #2
RX Master #3
0
0
DPDS[2:0]
0
LNAC[1:0]
LNAG[1:0]
0
0
DGAIN[5:0]
DGAIN[5:0]
0
0
0
0
0
0
0
0
0
0
TX Master #1 TXBAND[1:0]
N
RF2[15:0]
TX Master #2
Config
FIF[3:0]
NIF[13:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SDOSEL[3:0]
0
0
0
0
0
0
0
0
0
0
RFUP DIV2
0
0
0
1
Powerdown
0
0
0
0
0
RF1[15:0]
RF2[15:0]
0
0
PDIB PDRB
33h RF1 N Divider
34h RF2 N Divider
N
N
35h
3Ah
3Eh
3Fh
IF N Divider
Reserved
Reserved
Reserved
NIF[15:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
0
0
1
0
1
1
0
0
0
Notes:
1. Any register not listed here is reserved and should not be written. Writing to reserved registers may result in
unpredictable behavior.
2. Master registers 20h to 24h simplify programming the Aero I to support initiation of receive (RX) and transmit (TX)
operations with only two register writes.
3. See “AN50: Aero Transceiver Programming Guide” for detailed instructions on register programming.
Rev. 1.0
21
Aero I
Register 01h. Reset
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
Name
Bit
Name
Function
17:1
0
Reserved
RESET
Program to zero.
Chip Reset.
0 = Normal operation (default).
1 = Reset all registers to default values.
Note: See “Control Registers” on page 21 for more details. This register must be
written to 0 twice after a reset operation. This bit does not reset registers
31h to 35h.
Register 02h. Mode Control
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AUTO
MODE[1:0]
Name
Bit
Name
Function
17:3
2
Reserved
AUTO
Program to zero.
Automatic Mode Select.
0 = Manual. Mode is controlled by MODE[1:0] bits (default).
1 = Automatic. Last register write to N implies RX mode; Last register
RF1
write to N
implies TX mode. MODE[1:0] bits are ignored.
RF2
1:0
MODE[1:0]
Transmit/Receive/Cal Mode Select.
00 = Receive mode (default).
01 = Transmit mode.
10 = Calibration mode.
11 = Reserved.
Note: These bits are valid only when AUTO = 0.
Note: Calibration must be performed each time the power supply is applied. To initiate the calibration mode, set
MODE[1:0] = 10 and pulse the PDN pin high for at least 150 µs.
22
Rev. 1.0
Aero I
Register 03h. Configuration
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
DIAG[1:0]
SWAP
0
0
0
TXBAND[1:0]
RXBAND[1:0]
0
0
1
0
Name
Bit
Name
Function
17:14
13:12
Reserved
DIAG[1:0]
Program to zero.
DIAG1/DIAG2 Output Select.
DIAG1
LOW
LOW
HIGH
HIGH
DIAG2
LOW (default)
HIGH
LOW
HIGH
00 =
01 =
10 =
11 =
Note: These pins can be used to control antenna switch functions. These bits
must be programmed with the PDN pin is zero. The DIAG1/DIAG2 pins
are held at the desired value regardless of the state of the PDN pin.
11
SWAP
Transmit I/Q Swap.
0 = Normal (default).
1 = Swap I and Q for TXIP, TXIN, TXQP and TXQN pins.
10:8
7:6
Reserved
Program to zero.
TXBAND[1:0]
Transmit Band Select.
00 = GSM 850 or E-GSM 900 (default).
01 = DCS 1800.
10 = PCS 1900.
11 = Reserved.
5:4
RXBAND[1:0]
Receive Band Select.
00 = GSM input (default).
01 = DCS input.
10 = PCS input.
11 = Reserved.
3:2
1
Reserved
Reserved
Reserved
Program to zero.
Program to one.
Program to zero.
0
Rev. 1.0
23
Aero I
Register 04h. Transmit Control
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
0
0
0
1
BBG[1:0]
FIF[3:0]
0
0
0
0
Name
Bit
Name
Function
17:11
10
Reserved
Reserved
BBG[1:0]
Program to zero.
Program to one.
9:8
TX Baseband Input Full Scale Differential Input Voltage.
10 = Reserved.
11 = 2.0 V
00 = 1.6 V
01 = 1.2 V
.
PPD
(default).
PPD
.
PPD
Note: Refer to Table 6 for minimum and maximum values. Set this register to the
nearest value.
7:4
3:0
FIF[3:0]
TX IF Filter Cutoff Frequency.
0111 = Use for GSM 850, E-GSM 900 and PCS 1900 bands.
0110 = Use for DCS 1800 band.
Note: Use the recommended setting for each band. Other settings reserved.
Reserved
Program to zero.
24
Rev. 1.0
Aero I
Register 05h. Receive Gain
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
DGAIN[5:0]
0
AGAIN[2:0]
LNAC[1:0]
LNAG[1:0]
Name
Bit
Name
Function
17:14
13:8
Reserved
Program to zero.
DGAIN[5:0]
Digital PGA Gain Control.
00h = 0 dB (default).
01h = 1 dB.
...
3Fh = 63 dB.
Note: See “AN51: Aero Transceiver AGC Strategy” for details on setting the gain
registers.
7
Reserved
Program to zero.
6:4
AGAIN[2:0]
Analog PGA Gain Control.
000 = 0 dB (default).
001 = 4 dB.
010 = 8 dB.
011 = 12 dB.
100 = 16 dB.
101 = Reserved.
110 = Reserved.
111 = Reserved.
Note: See “AN51: Aero Transceiver AGC Strategy” for details on setting the gain
registers.
3:2
1:0
LNAC[1:0]
LNAG[1:0]
LNA Bias Current Control.
00 = Minimum current (default).
01 = Maximum current.
10 = Reserved.
11 = Reserved.
Note: Program these bits to the same value as LNAG[1:0].
LNA Gain Control.
00 = Minimum gain (default).
01 = Maximum gain.
10 = Reserved.
11 = Reserved.
Notes:
1. Program these bits to the same value as LNAC[1:0].
2. See “AN51: Aero Transceiver AGC Strategy” for details on setting the gain
registers.
Rev. 1.0
25
Aero I
Register 11h. Configuration
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
DPDS[2:0]
XPD1
1
XSEL
0
1
0
1
0
0
0
CSEL
Name
Bit
Name
Function
17:14
13:11
Reserved
Program to zero.
Data Path Delayed Start.
111= Use for GSM 850 and GSM 900 bands.
011= Use for DCS 1800 and PCS 1900 bands (default).
DPDS[2:0]
Note: Use the recommended setting for each band. Other settings reserved.
10
XPD1
Reference Buffer Powerdown.
0 = Reference buffer automatically enabled (default).
1 = Reference buffer disabled.
Note: This bit should be set to 0 during normal operation. To achieve lowest
powerdown current (IPDN), this bit should be set to 1. The XBUF bit in
Register 12h must also be set appropriately.
9
8
Reserved
XSEL
Program to one.
Reference Frequency Select.
0 = No divider. XIN = 13 MHz (default).
1 = Divide XIN by 2. XIN = 26 MHz.
Note: The internal clock should always be 13 MHz.
7
6
Reserved
Reserved
Reserved
Reserved
Reserved
CSEL
Program to zero.
Program to one.
Program to zero.
Program to one.
Program to zero.
5
4
3:1
0
Digital IIR Coefficient Select.
0 = High selectivity filter (default).
1 = Low selectivity filter.
26
Rev. 1.0
Aero I
Register 12h. DAC Configuration
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
0
0
0
1
XBUF
0
ZDBS
ZERODEL[2:0]
DACCM[1:0]
DACFS[1:0]
Name
Bit
Name
Function
17:11
10
Reserved
Reserved
XBUF
Program to zero.
Program to one.
9
Reference Buffer Power Control.
0 = Reference buffer disabled.
1 = Reference buffer automatically enabled (default).
Note: This bit should be set to 1 during normal operation. To achieve the lowest
powerdown current (IPDN), this bit should be set to 0. The XPD1 bit in
Register 11h must also be set appropriately.
8
7
Reserved
ZDBS
Program to zero.
ZERODEL Band Select.
0 = Use ZERODEL[2:0] settings corresponding to DCS/PCS column
(default).
1 = Use RXBAND[1:0] to determine ZERODEL[2:0] delay setting (GSM
or DCS/PCS).
6:4
ZERODEL[2:0]
RX Output Zero Delay.
Code
000:
001:
010:
011:
100:
101:
110:
111:
GSM
90 µs
DCS/PCS
130 µs
150 µs
170 µs
180 µs
190 µs
200 µs
220 µs
(default)
110 µs
130 µs
140 µs
150 µs
160 µs
180 µs
Reserved
Note: DAC input is forced to zero after PDN is deasserted. This feature can be
used by the baseband processor to cancel the Si4205 DAC dc offset.
Offsets induced on channels due to 13 MHz harmonics will not be
included in the calibrated value.
3:2
1:0
DACCM[1:0]
DACFS[1:0]
RX Output Common Mode Voltage.
00 = 1.0 V.
01 = 1.25 V (default).
10 = 1.35 V.
11 = Reserved.
RX Output Differential Full Scale Voltage.
00 = 1.0 V
01 = 2.0 V
10 = 3.5 V
PPD
PPD
PPD
(default).
11 = Reserved.
Rev. 1.0
27
Aero I
Register 19h. Reserved
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Name
Bit
17:0
Name
Function
Reserved
Program to zero.
Register 20h. RX Master #1
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
NRF1[15:0]
RXBAND[1:0]
Name
Notes:
1. See registers 03h and 33h for bit definitions.
2. When this register is written, the PDIB bit will be automatically set to 0, the PDRB bit will be set to 1 and the RFUP bit is
set as a function of RXBAND[1:0].
Register 21h. RX Master #2
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LNAC[1:0]
LNAG[1:0]
AGAIN[2:0]
0
DGAIN[5:0]
0
DPDS[2:0]
Name
Note: See registers 05h and 11h for bit definitions.
Register 22h. RX Master #3
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
DGAIN[5:0]
0
0
0
0
0
0
0
0
0
0
0
Name
Notes:
1. See register 05h for bit definitions.
2. The DGAIN[5:0] in register 22h can be changed without powering down.
28
Rev. 1.0
Aero I
Register 23h. TX Master #1
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
NRF2[15:0]
TXBAND[1:0]
Name
Notes:
1. See registers 03h and 34h for bit definitions.
2. When this register is written, the PDIB bit is automatically set to 1, and the PDRB bit is set to 1.
Register 24h. TX Master #2
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
NIF[13:0]
FIF[3:0]
Name
Note: See registers 04h and 35h for bit definitions.
Rev. 1.0
29
Aero I
Register 31h. Main Configuration
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
SDOSEL[3:0]
0
0
0
0
0
0
RFUP DIV2
0
0
1
Name
Bit
Name
Function
17:15
14:11
Reserved
Program to zero.
SDO Output Control Register.
The mux_output table is as follows:
SDOSEL[3:0]
0000 Connected to the Output Shift Register (default).
0001 Force the Output to Low.
0010 Reference Clock.
0011 Lock Detect (LDETB) Signal from Phase Detectors.
1111 High Impedance.
Notes:
1. SDO is high-impedance when PDN = 0.
2. SDO is Serial Data Output when in register read mode.
10:5
4
Reserved
RFUP
Program to zero.
RF PLL Update Rate (RF1 VCO only).
0 = 200 kHz update rate (Receive GSM modes).
1 = 100 kHz update rate (Receive DCS and PCS modes).
Note: This bit is set to 1 when register 20h D[17:16] = 01b or 10b (DCS 1800 or
PCS 1900 receive modes) and is set to 0 when D[17:16] = 00b or 11b
(GSM 850 or GSM 900 modes).
3
DIV2
Input Clock Frequency.
0 = No divider. XIN = 13 MHz.
1 = Divide XIN by 2. XIN = 26 MHz.
2:1
0
Reserved
Reserved
Program to zero.
Program to one.
30
Rev. 1.0
Aero I
Register 32h. Powerdown
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PDIB PDRB
Name
Bit
17:2
1
Name
Reserved
PDIB
Function
Program to zero.
Powerdown IF PLL.
0 = IF synthesizer powered down.
1 = IF synthesizer powered up when the PDN pin is high.
Notes:
1. The IF PLL is only used in transmit mode. Powerdown for receive mode.
2. This bit is set to 0 when register 20h is written (receive mode).
3. This bit is set to 1 when register 23h is written (transmit mode).
0
PDRB
Powerdown RF PLL.
0 = RF synthesizer powered down.
1 = RF synthesizer powered up when the PDN pin is high.
Notes:
1. This bit is set to 1 when register 20h is written (receive mode).
2. This bit is set to 1 when register 23h is written (transmit mode).
Register 33h. RF1 N Divider
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
Name
N
[15:0]
RF1
Bit
Name
Function
17:16
15:0
Reserved
Program to zero.
N
[15:0]
N Divider for RF PLL (RF1 VCO).
RF1
Used for receive mode.
Register 34h. RF2 N Divider
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
Name
N
[15:0]
RF2
Bit
Name
Function
17:16
15:0
Reserved
Program to zero.
N
[15:0]
N Divider for RF PLL (RF2 VCO).
RF2
Used for transmit mode.
Rev. 1.0
31
Aero I
Register 35h. IF N Divider
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
Name
N [15:0]
IF
Bit
Name
Function
17:16
15:0
Reserved
Program to zero.
N [15:0]
N Divider for IF Synthesizer.
Used for transmit mode.
IF
Register 3Ah. Reserved
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
Name
Bit
17:4
3
Name
Function
Reserved
Reserved
Reserved
Reserved
Program to zero.
Program to one.
Program to zero.
Program to one.
2:1
0
Register 3Eh. Reserved
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
Name
Bit
17:4
3:0
Name
Function
Reserved
Reserved
Program to zero.
Program to one.
Register 3Fh. Reserved
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
Name
Bit
17:5
4
Name
Function
Reserved
Reserved
Reserved
Program to zero.
Program to one.
Program to zero.
3:0
32
Rev. 1.0
Aero I
Pin Descriptions: Si4205-BM
28
27
26
25
24
23
22
32
31
21 RFIGN
RXQN
RXIP
RXIN
TXIP
1
2
3
4
5
6
7
20 RFIGP
19 RFIDN
GND
GND
18
17
16
RFIDP
RFIPN
RFIPP
TXIN
GND
GND
TXQP
TXQN
15 GND
29
30
8
9
10
11
12
13
14
Pin Number(s) Name
Description
1, 28
2, 3
4, 5
6, 7
8
RXQN, RXQP
Receive Q output (differential).
Receive I output (differential).
Transmit I input (differential).
Transmit Q input (differential).
RXIP, RXIN
TXIP, TXIN
TXQP, TXQN
XIN
Reference frequency input from crystal oscillator.
Supply voltage.
9, 32
10
VDD
PDN
Powerdown input (active low).
Serial data output.
11
SDO
12
SEN
Serial enable input (active low).
Serial clock input.
13
SCLK
14
SDI
Serial data input.
15, 29–31
16, 17
GND
Ground. Connect to ground plane on PCB.
RFIPP, RFIPN
PCS LNA input (differential).
Use for PCS 1900 band.
18, 19
20, 21
22
RFIDP, RFIDN
RFIGP, RFIGN
RFOD
DCS LNA input (differential).
Use for DCS 1800 band.
GSM LNA input (differential).
Used for GSM 850 or E-GSM 900 bands.
DCS and PCS transmit output to power amplifier.
Used for DCS 1800 and PCS 1900 bands.
23
RFOG
GSM transmit output to power amplifier.
Used for GSM 850 and E-GSM 900 bands.
24, 25
DIAG1, DIAG2
Diagnostic output.
Can be used as digital outputs to control antenna switch functions.
26
27
XEN
XOUT pin enable.
XOUT
Clock output to baseband.
Rev. 1.0
33
Aero I
Ordering Guide
Part Number Description
Operating
Temperature
Si4205-BM
Tri-band Transceiver
–20 to 85 °C
GSM 850 or E-GSM 900, DCS 1800, PCS 1900
Note: Add an “R” at the end of the part number to denote tape and reel option; 2500 quantity per
reel.
34
Rev. 1.0
Aero I
Package Outline: Si4205-BM
Figure 13. 32-Pin Land Grid Array (LGA)
Notes:
1. Dimensions in mm.
2. Approximate device weight is 196 mg.
Rev. 1.0
35
Aero I
Document Change List
Revision 0.9 to Revision 1.0
This document corresponds to Aero I (Si4205),
revision F.
Table 3 on page 5 updated.
z Updated Supply Current specification for powerdown
mode.
Table 4 on page 6 updated.
z Added Note 1.
z Clarified register writes for DGAIN bits.
Figure 3 on page 7 updated.
z Added SEN programming option.
Table 5 on page 8 updated.
z Updated 20 MHz GSM band desensitization
specification.
z Updated Voltage Gain specification.
"Bill of Materials‚" on page 15 updated.
"Ordering Guide‚" on page 34 updated.
"Package Outline: Si4205-BM‚" on page 35
updated.
z Added Note 1.
Rev. 1.0
36
Aero I
Notes:
Rev. 1.0
37
Aero I
Contact Information
Silicon Laboratories Inc.
4635 Boston Lane
Austin, Texas 78735
Tel:1+ (512) 416-8500
Fax:1+ (512) 416-9669
Toll Free:1+ (877) 444-3032
Email: Aeroinfo@silabs.com
Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed fea-
tures or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no war-
ranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume
any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applica-
tions intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a
situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended
or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
Silicon Laboratories, Silicon Labs, and Aero are trademarks of Silicon Laboratories Inc.
Other products or brand names mentioned herein are trademarks or registered trademarks of their respective holder.
38
Rev. 1.0
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