SI4206-BM [SILICON]
RF and Baseband Circuit, CMOS, 8 X 8 MM, LEAD FREE, LGA-32;
| 型号： | SI4206-BM |
| 厂家： | 
SILICON |
| 描述： | RF and Baseband Circuit, CMOS, 8 X 8 MM, LEAD FREE, LGA-32 电信 电信集成电路 |
| 文件： | 总40页 (文件大小：1136K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Aero I+
AERO™ I+ TRANSCEIVER
FOR GSM AND GPRS WIRELESS COMMUNICATIONS
Features
Pin Assignments
(Top View)
Single 8 x 8 mm package
CMOS process technology
Quad-band support:
z GSM 850 Class 4, small MS
z E-GSM 900 Class 4, small MS
z DCS 1800 Class 1
Si4206-BM
(Pin description, see page 35)
Integrated GSM/GPRS transceiver
including:
z Low-IF receiver
z Universal baseband interface
z Offset-PLL transmitter
z Dual RF synthesizer
z Digitally-controlled crystal oscillator
(DCXO)
z PCS 1900 Class 1
GPRS Class 12 compliant
28
27
26
25
24
23
22
32
31
3-wire serial interface
21
1
2
3
4
5
6
7
RFIGN
RFIGP
RFIDN
RFIDP
RFIPN
RFIPP
GND
BQP
BQN
GND
GND
2.7 V to 3.0 V operation
20
19
18
17
16
15
BIP
BIN
Integrated VCOs, frequency
synthesizers, and tuning inductors
XTAL1
XTAL2
XAFC
GND
9
GND
13
Applications
29
30
8
10
11
12
14
Multi-band GSM/GPRS digital cellular handsets
Multi-band GSM/GPRS wireless data modems
Description
Ordering Information:
See page 36.
The Aero I+ transceiver is a complete RF front end for multi-band GSM
and GPRS wireless communications. The transmit section interfaces
between the baseband processor and the power amplifier. The receive
section interfaces between the RF band-select SAW filters and the
baseband processor. All sensitive components, such as RF/IF VCOs,
loop filters, and tuning inductors, are completely integrated into a single
compact package. The Aero I+ includes a digitally-controlled crystal
oscillator (DCXO) function and completely integrates the reference
oscillator and varactor.
Patents pending
Functional Block Diagram
Si4206
GSM
LNA
PGA
PGA
ADC
ADC
PGA
PGA
DCS
PCS
LNA
LNA
I
100 kHz
0 / 90
Q
I
DET
GSM
DCS
PCS
PA
XOUT
XAFC
RF
PLL
IF
PLL
DCXO
Rev. 1.0 7/04
Copyright © 2004 by Silicon Laboratories
Aero I+
Aero I+
2
Rev. 1.0
Aero I+
TABLE OF CONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3. Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
4.1. Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4.2. Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.3. Frequency Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.4. DCXO Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.5. Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
4.6. XOUT Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
5. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
6. Pin Descriptions: Si4206-BM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
8. Package Outline: Si4206-BM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Rev. 1.0
3
Aero I+
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Symbol
TA
Test Condition
Min
–20
2.7
Typ
25
Max
85
Unit
°C
Ambient Temperature
DC Supply Voltage
VDD
2.85
3.0
V
Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at 2.85 V and an operating temperature of 25 °C unless otherwise stated. Parameters are tested in
production unless otherwise stated.
Table 2. Absolute Maximum Ratings1,2
Parameter
Symbol
VDD
Value
–0.5 to 3.3
±10
Unit
V
DC Supply Voltage
3
Input Current
IIN
mA
V
3
Input Voltage
VIN
–0.3 to (V + 0.3)
DD
Operating Temperature
Storage Temperature
TOP
–40 to 95
–55 to 150
10
°C
TSTG
°C
4
RF Input Level
dBm
Notes:
1. Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation
should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2. The Si4206 device is a high-performance RF integrated circuit with an ESD rating of < 2 kV. Handling and
assembly of this device should only be done at ESD-protected workstations.
3. For signals SCLK, SDI, SEN, PDN, XIN, XEN, XTALEN, and XDRVEN.
4. At SAW filter output for all bands.
4
Rev. 1.0
Aero I+
Table 3. DC Characteristics
(VDD = 2.7 to 3.0 V, TA = –20 to 85 °C)
Parameter
Symbol
IRX
Test Condition
Receive mode
Min
—
Typ
83
Max
115
109
6.0
Unit
mA
mA
mA
1
Supply Current
ITX
Transmit mode
PDN = 0, XEN = 1,
—
85
IXTAL13
—
4.0
f
= 13 MHz
XTAL
PDN = 0, XEN = 1,
= 26 MHz
IXTAL26
IPDN
—
—
5.0
5
7.0
80
mA
f
XTAL
PDN = 0, XEN = 0,
XBUF = 0, XPD1 = 1
µA
2
High Level Input Voltage
VIH
VIL
IIH
0.7 VDD
—
—
—
—
—
—
0.3 VDD
10
V
V
2
Low Level Input Voltage
2
High Level Input Current
VIH = VDD = 3.0 V
–10
µA
µA
2
Low Level Input Current
IIL
VIL = 0 V,
–10
10
VDD = 3.0 V
3
High Level Output Voltage
VOH
VOL
VOH
VOL
IOH = –500 µA
IOL = 500 µA
IOH = –10 mA
IOL = 10 mA
VDD–0.4
—
—
—
—
—
—
0.4
—
V
V
V
V
3
Low Level Output Voltage
4
High Level Output Voltage
VDD–0.4
—
4
Low Level Output Voltage
0.4
Notes:
1. Measured with load on XOUT pin of 10 pF and fXTAL = 13 MHz. Limits with XEN = 1 guaranteed by characterization.
Measured with XEN, XDRVEN, and XTALEN tied together and controlled simultaneously.
2. For pins SCLK, SDI, SEN, XEN, PDN, XDRVEN, and XTALEN.
3. For pins SDO, XOUT.
4. For pins DIAG1, DIAG2.
Rev. 1.0
5
Aero I+
Table 4. AC Characteristics
(VDD = 2.7 to 3.0 V, TA = –20 to 85 °C)
Symbol
Test Condition
Min
Typ
Max
Unit
Parameter
SCLK Cycle Time
tCLK
tR
Figures 1, 3
Figures 1, 3
Figures 1, 3
Figures 1, 3
Figures 1, 3
Figure 2
35
—
—
10
10
—
—
15
10
10
12
12
10
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
50
50
—
—
10
10
—
—
—
—
—
—
27
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
SCLK Rise Time
SCLK Fall Time
tF
SCLK High Time
tHI
SCLK Low Time
tLO
tPR
tPF
PDN Rise Time
PDN Fall Time
Figure 2
SDI Setup Time to SCLK↑
SDI Hold Time from SCLK↑
SEN↓ to SCLK↑ Delay Time
SCLK↑ to SEN↑ Delay Time
SEN↑ to SCLK↑ Delay Time
SEN Pulse Width
tSU
tHOLD
tEN1
tEN2
tEN3
tW
Figure 3
Figure 3
Figure 3
Figures 3, 4
Figures 3, 4
Figures 3, 4
Figure 4
SCLK↓ to SDO Time
tCA
*
Digital Input Pin Capacitance
*Note: For pins SCLK, SDI, SEN, XEN, PDN, XDRVEN, and XTALEN.
tR
tF
80%
50%
20%
SCLK
tHI
tLO
tCLK
Figure 1. SCLK Timing Diagram
tPR
tPF
80%
20%
PDN
Figure 2. PDN Timing Diagram
6
Rev. 1.0
Aero I+
80%
50%
20%
D17
D16
A0
SDI
SCLK
SEN
tSU
tHOLD
80%
50%
20%
tR
tLO
tHI
tF
tEN2
tEN3
tEN1
tCLK
80%
50%
20%
tW
Figure 3. Serial Interface Write Timing Diagram
80%
50%
20%
A0
SDI
SDO
80%
50%
20%
OD17
OD16
OD0
tCA
80%
50%
20%
SCLK
SEN
tEN2
tEN3
80%
50%
20%
tW
Figure 4. Serial Interface Read Timing Diagram
Rev. 1.0
7
Aero I+
Table 5. Receiver Characteristics
(VDD = 2.7 to 3.0 V, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
GSM 850 band
E-GSM 900 band
DCS 1800 band
PCS 1900 band
GSM 850 band
E-GSM 900 band
DCS 1800 band
PCS 1900 band
GSM 850 band
E-GSM 900 band
DCS 1800 band
PCS 1900 band
GSM 850 band
E-GSM 900 band
DCS 1800 band
PCS 1900 band
GSM input
Min
869
925
1805
1930
—
Typ
—
Max
894
960
1880
1990
3.8
3.9
4.1
4.5
4.5
4.6
5.0
5.7
4.6
4.7
5.4
6.0
—
Unit
MHz
MHz
MHz
MHz
dB
1
GSM Input Frequency
f
IN
—
1
DCS or PCS Input Frequency
—
—
2,3
Noise Figure at 25 °C
NF
NF
NF
2.9
3.0
3.3
3.7
3.6
3.7
4.2
4.9
3.7
3.8
4.6
5.2
–21
–25
–16
–15
40
25
75
85
—
dB
—
dB
—
dB
2,3
Noise Figure at 75 °C
—
dB
—
dB
—
dB
—
dB
2,3
Noise Figure at 85 °C
—
dB
—
dB
—
dB
—
dB
2,3,4
3 MHz Input Desensitization
DES
–25
–28
–20
–19
29
dBm
dBm
dBm
dBm
dBm
3
DCS/PCS inputs
GSM input
—
2,3,4
20 MHz Input Desensitization
DES
—
20
DCS/PCS inputs
|f – f | ≥ 6 MHz,
—
2
Input IP2
IP2
IP3
IR
—
1,2
0
|f – f | = 100 kHz
2
1
2
Input IP3
|f – f | ≥ 800 kHz,
–18
–12
—
dBm
2
1
f = 2f – f
0
1
2
2,4
Image Rejection
GSM Input
28
28
35
40
—
—
dB
dB
DCS/PCS Inputs
GSM Input
2,5
1 dB Input Compression
CP
–28
–27
–23
–23
3.0
10.0
100
96
–23
–22
–18
–18
8.5
15.5
104
102
17
—
dBm
dBm
dBm
dBm
dB
MAX
DCS/PCS inputs
GSM Input
—
2,6
1 dB Input Compression
CP
—
MIN
MIN
DCS/PCS inputs
GSM input
—
2,6,7
Minimum Voltage Gain
G
12.5
19.5
109
107
—
DCS/PCS inputs
GSM input
dB
2,7
Maximum Voltage Gain
G
dB
MAX
DCS/PCS inputs
GSM input
dB
3,8
G
—
dB
LNA Voltage Gain
LNA
DCS/PCS inputs
GSM input
—
15
—
dB
LNA Gain Control Range
∆G
13
17
21
dB
LNA
DCS/PCS inputs
4
8
12
dB
8
Rev. 1.0
Aero I+
Table 5. Receiver Characteristics (Continued)
(VDD = 2.7 to 3.0 V, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
13
Typ
16
Max
19
Unit
dB
Analog PGA Control Range
Analog PGA Step Size
Digital PGA Control Range
Digital PGA Step Size
∆G
APGA
3.2
—
4.0
63
4.8
—
dB
∆G
dB
DPGA
—
1
—
dB
9
Maximum Differential Output Voltage
DACFS[1:0] = 00
DACFS[1:0] = 01
DACFS[1:0] = 10
DACCM[1:0] = 00
DACCM[1:0] = 01
DACCM[1:0] = 10
0.7
1.5
2.6
0.8
1.05
1.15
—
1.0
2.0
3.5
1.0
1.25
1.35
—
1.3
2.5
4.4
1.2
1.45
1.55
16
V
PPD
PPD
V
V
PPD
9
Output Common Mode Voltage
V
V
V
9,10,11
Differential Output Offset Voltage
Differential Output Offset Voltage
mV
mV
—
—
5
9,10,11
Drift
9,11
Baseband Gain Error
—
—
10
—
—
—
—
—
—
—
—
1
1
%
deg
kΩ
pF
µs
9,11
Baseband Phase Error
9
Output Load Resistance
R
Single-ended
Single-ended
CSEL = 0
—
—
10
22
16
1.5
1
L
9
Output Load Capacitance
C
—
L
12
Group Delay
—
CSEL = 1
—
µs
12
Differential Group Delay
CSEL = 0
—
µs
CSEL = 1
—
µs
3,13
Powerup Settling Time
From powerdown
200
220
µs
Notes:
1. GSM input pins RFIGP and RFIGN. DCS input pins RFIDP and RFIDN. PCS input pins RFIPP and RFIPN.
2. Measurement is performed with a 2:1 balun (50 Ω input, 200 Ω balanced output) and includes matching network and
PCB losses. Measured at max gain (AGAIN[2:0] =100b, LNAG[1:0] = 01b, LNAC[1:0] = 01b) unless otherwise noted.
Noise figure measurements are referred to 290 °K. Insertion loss of the balun is removed.
3. Specifications guaranteed by characterization using LQW15AN series matching inductors.
4. Input signal at balun is –102 dBm. SNR at baseband output is 9 dB.
5. AGAIN[2:0]=min=000b, LNAG[1:0] = max=01b, LNAC[1:0] =max= 01b.
6. AGAIN[2:0]=min=000b, LNAG[1:0] = min=00b, LNAC[1:0] = min=00b.
7. Voltage gain is defined as the differential rms voltage at the BIP/BIN pins or BQP/BQN pins divided by the rms voltage
at the balun input with DACFS[1:0] = 01 and CSEL = 1. Gain is 1.5 dB higher with CSEL = 0. Minimum and maximum
values do not include the variation in the DAC full scale voltage (also see Maximum Differential Output Voltage
specification).
8. Voltage gain is defined as the differential rms voltage at the LNA output divided by the rms voltage at the balun output.
9. Output pins BIP, BIN, BQP, BQN.
10. Specified as root sum square:
2 . Drift specification applies to dc offset
(RXIP – RXIN)2 + (RXQP – RXQN)
calibration and is guaranteed by characterization. See ZERODEL[2:0] in the register description.
11. The baseband signal path is entirely digital. Gain, phase, and offset errors at the baseband outputs are because of the
D/A converters. Offsets can be measured and calibrated out. See ZERODEL[2:0] in the register description.
12. Group delay is measured from antenna input to baseband outputs. Differential group delay is measured in-band.
13. Includes settling time of the frequency synthesizer. Settling to 5 degrees phase error measured at BIP, BIN, BQP, and
BQN pins.
Rev. 1.0
9
Aero I+
Receive Path Magnitude Response (CSEL = 0)
Receive Path Magnitude Response (CSEL = 1)
0
0
−20
−20
−40
−60
−80
−40
−60
−80
−100
−120
0
50
100
150
200
250
300
350
400
0
50
100
150
200
250
300
350
400
Frequency (KHz)
Frequency (KHz)
Figure 8. Receive Path Magnitude Response
(CSEL = 1)
Figure 5. Receive Path Magnitude Response
(CSEL = 0)
Receive Path Passband Magnitude Response (CSEL = 1)
2
Receive Path Passband Magnitude Response (CSEL = 0)
2
0
−2
0
−2
−4
−4
−6
−6
−8
−8
−10
−12
−14
−16
−10
−12
−14
−16
0
10
20
30
40
50
60
70
80
90
100
0
10
20
30
40
50
60
70
80
90
100
Frequency (KHz)
Frequency (KHz)
Figure 9. Receive Path Passband Magnitude
Response (CSEL = 1)
Figure 6. Receive Path Passband Magnitude
Response (CSEL = 0)
Receive Path Passband Group Delay (CSEL = 1)
20
Receive Path Passband Group Delay (CSEL = 0)
25
19
18
17
16
15
14
13
12
11
10
24
23
22
21
20
19
18
17
16
15
0
10
20
30
40
50
60
70
80
90
100
0
10
20
30
40
50
60
70
80
90
100
Frequency (KHz)
Frequency (KHz)
Figure 10. Receive Path Passband Group Delay
(CSEL = 1)
Figure 7. Receive Path Passband Group Delay
(CSEL = 0)
10
Rev. 1.0
Aero I+
Table 6. Transmitter Characteristics
(VDD = 2.7 to 3.0 V, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
GSM 850 band
E-GSM 900 band
DCS 1800 band
PCS 1900 band
Min
824
880
1710
1850
0.88
1.1
16
Typ
—
Max
849
915
1785
1910
2.2
1.4
22
Unit
MHz
MHz
MHz
MHz
1
RFOG Output Frequency
—
2
RFOD Output Frequency
—
—
3,4
I/Q Differential Input Swing
—
V
PPD
3
I/Q Input Common Mode
—
V
3,4
I/Q Differential Input Resistance
BBG[1:0] = 11
19
kΩ
kΩ
b
BBG[1:0] = 00
14
17
20
b
BBG[1:0] = 01
12
15
18
kΩ
b
Powered down
—
Hi-Z
—
—
kΩ
3,5
I/Q Input Capacitance
—
5
pF
3
I/Q Input Bias Current
13
16
19
µA
Sideband Suppression
Carrier Suppression
IM3 Suppression
67.7 kHz sinusoid
67.7 kHz sinusoid
67.7 kHz sinusoid
—
–46
–48
–57
1.9
5
–34
–33
–50
3.0
10
dBc
dBc
dBc
—
—
5
o
Phase Error
—
rms
o
—
PEAK
1,2
TXVCO Pushing
Open loop
—
100
200
—
kHz/V
1,2
TXVCO Pulling
VSWR 2:1, all phases,
open loop
—
—
kHz
PP
1,6
RFOG Output Modulation Spectrum
400 kHz offset
1.8 MHz offset
400 kHz offset
1.8 MHz offset
10 MHz offset
20 MHz offset
20 MHz offset
—
—
—
—
—
—
—
7
–65
–70
–65
–70
–160
–166
–163
9
–63
–68
–63
–65
–155
–164
–157
11
dBc
dBc
dBc
2,6
RFOD Output Modulation Spectrum
dBc
1,5,7
RFOG Output Phase Noise
dBc/Hz
dBc/Hz
dBc/Hz
dBm
2,5,7
RFOD Output Phase Noise
1
RFOG Output Power Level
Z = 50 Ω
L
2
RFOD Output Power Level
Z = 50 Ω
6
8
10
dBm
L
Rev. 1.0
11
Aero I+
Table 6. Transmitter Characteristics (Continued)
(VDD = 2.7 to 3.0 V, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
2nd harmonic
Min
—
Typ
—
Max
–20
–10
150
Unit
dBc
dBc
µs
1,2
RF Output Harmonic Suppression
3rd harmonic
—
—
5,8
Powerup Settling Time
From powerdown
—
—
Notes:
1. Measured at RFOG pin.
2. Measured at RFOD pin.
3. Input pins BIP, BIN, BQP, and BQN.
4. Differential Input Swing is programmable with the BBG[1:0] bits in register 04h. Program these bits to the closest
appropriate value. The I/Q Input Resistance scales inversely with the BBG[1:0] setting.
5. Specifications guaranteed by characterization.
6. Measured with pseudo-random pattern. Carrier power and noise power < 1.8 MHz measured with 30 kHz RBW. Noise
power ≥ 1.8 MHz measured with 100 kHz RBW.
7. Measured with all 1s pattern.
8. Including settling time of the frequency synthesizer. Settling time measured at the RFOD and RFOG pins to 0.1 ppm
frequency error.
12
Rev. 1.0
Aero I+
Table 7. Frequency Synthesizer Characteristics
(VDD = 2.7 to 3.0 V, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
1
f
GSM 850 band
E-GSM 900 band
DCS 1800 band
PCS 1900 band
GSM 850 band
E-GSM 900
1737.8
1849.8
1804.9
1929.9
1272
1279
1327
1423
—
—
—
1787.8
1919.8
1879.9
1989.9
1297
1314
1402
1483
—
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
RF1 VCO Frequency
RF1
—
—
1
f
—
RF2 VCO Frequency
RF2
—
DCS 1800 band
PCS 1900 band
GSM 850 band
—
—
1
f
896
798
IF VCO Frequency
IF
E-GSM 900 band
880–895 MHz
900–915 MHz
—
—
E-GSM 900 band
895–900 MHz
—
790
—
MHz
DCS 1800 band
PCS 1900 band
—
—
—
766
854
200
—
—
—
MHz
MHz
kHz
f
GSM input,
RFUP = 0
RF1 PLL Phase Detector Update
Frequency
φ
DCS/PCS inputs,
RFUP = 1
—
—
100
200
—
—
kHz
kHz
f
IF and RF2 PLL Phase Detector
Update Frequency
φ
2
Open Loop
—
—
—
—
—
—
—
—
—
—
—
—
500
400
300
400
100
100
–144
–126
–128
–95
–80
–80
—
—
kHz/V
kHz/V
kHz/V
RF1 VCO Pushing
2
RF2 VCO Pushing
2
—
IF VCO Pushing
2
VSWR = 2:1,
all phases, open loop
—
kHz
RF1 VCO Pulling
PP
2
—
kHz
RF2 VCO Pulling
PP
2
—
kHz
IF VCO Pulling
PP
2
3 MHz offset
400 kHz offset
400 kHz offset
3 MHz offset
–138
–121
–123
–83
–75
–70
dBc/Hz
dBc/Hz
dBc/Hz
dBc
RF1 PLL Phase Noise
2
RF2 PLL Phase Noise
2
IF PLL Phase Noise
2
RF1 PLL Spurious
2
400 kHz offset
400 kHz offset
dBc
RF2 PLL Spurious
2
dBc
IF PLL Spurious
Notes:
1. For the GSM input, the RF1 VCO is divided by two. During transmit, the IF VCO is divided by two.
2. Specifications are guaranteed by characterization.
Rev. 1.0
13
Aero I+
Table 8. Reference Oscillator Characteristics
(VDD = 2.7 to 3.0 V, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
XSEL = 0, DIV2 = 0
XSEL = 1, DIV2 = 1
Min
—
—
0
Typ
13
Max
—
Unit
MHz
MHz
V
Crystal Oscillation Frequency
f
XTAL
26
—
AFC Input Voltage
V
—
2.5
—
AFC
*
AFC Capacitance Range
C
f
f
f
f
f
f
= 13 MHz
= 26 MHz
= 13 MHz
= 26 MHz
= 13 MHz
= 26 MHz
—
—
—
—
—
—
—
1.7
1.4
3.0
2.9
4.4
4.3
1.0
pF
VAR
XTAL
XTAL
XTAL
XTAL
XTAL
XTAL
—
pF
*
DAC Capacitance Range
C
—
pF
DAC
—
pF
*
Fixed Capacitance
C
—
pF
FIX
—
pF
Powerup Settling Time
t
V
= 0 to 1.25 V
—
ms
DCXO
CTL
*Note: Parameters relate to reference oscillator frequency tuning range depending on the crystal characteristics. See “AN83:
Selecting a Crystal for Aero™+/I+ Designs” for detailed instructions on crystal selection.
14
Rev. 1.0
Aero I+
2. Typical Application Schematic
RFOG
RFOD
DIAG1
DIAG2
PDNB
XEN
C1
C2
Z1
Z2
Z3
XOUT
GSM900 IN
OUT+
OUT-
IN
L1
L2
L3
VDD
GND
32
VDD
31
GND
C8
1
2
3
4
5
6
7
21
20
19
18
17
16
15
BQP
BQN
BIP
BQP
RFIGN
RFIGP
RFIDN
RFIDP
RFIPN
RFIPP
GND
BQN
BIP
U1
SI4206
C3
BIN
BIN
XTAL1
XTAL2
XAFC
DCS 1800 IN
OUT+
OUT-
IN
GND
X1
13/26MHz
GND
29
30
GND
VDD
C4
C5
VDD
GND
C7
XAFC
XTALEN
XDRVEN
SDO
PCS 1900 IN
OUT+
OUT-
IN
SENB
SCLK
SDI
GND
C6
Notes:
1. Connect pads on bottom of U1 to GND.
2. See “AN92: Aero™ I/Aero™ I+ Transceiver PCB Layout Guidelines” for details on the following:
z LNA matching network (C1–C6, L1–L3). Values should be custom tuned for a specific PCB layout and SAW filter to
optimize performance.
z Differential traces between the SAW filters (Z1–Z3) and transceiver (U1) pins 16–21.
z Detailed SAW filter requirements.
z Crystal connection to U1 pins 5–6.
3. XEN, XDRVEN, and XTALEN are recommended to be tied together and controlled simultaneously.
Rev. 1.0
15
Aero I+
3. Bill of Materials
Component
Value/Description
Supplier(s)
C1–C2
1.2 pF, ±0.1 pF, C0G
(GSM 850 and E-GSM 900)
Murata GRM36C0G series
Venkel C0402C0G500 series
C3–C4
C5–C6
1.2 pF, ±0.1 pF, C0G
(DCS 1800)
Murata GRM36C0G series
Venkel C0402C0G500 series
1.5 pF, ±0.1 pF, C0G
(PCS 1900)
Murata GRM36C0G series
Venkel C0402C0G500 series
C7
C8
L1
22 nF, ±20%, Z5U/X7R
10 pF, ±5%, C0G
24 nH, ±2%
Murata LQG15HN series (0402 size)
Murata LQW15AN series (0402 size)
L2
L3
6.8 nH, ±0.2 nH
5.6 nH, ±0.2 nH
Murata LQG15HN series (0402 size)
Murata LQW15AN series (0402 size)
Murata LQG15HN series (0402 size)
Murata LQW15AN series (0402 size)
U1
X1
GSM/GPRS Transceiver
13 or 26 MHz crystal
Silicon Laboratories Si4206
KDS 1BR13000AA0F
KSS CX96FFFBQAJ13
NDK W-168-237
Toyocom TN4-25999-r0-2
Z1
GSM 850 RX SAW Filter
(150 Ω balanced output)
EPCOS B39881-B9001-C710 (5-pin, 1.4 x 2.0 mm)
EPCOS B39881-B9004-E710 (6-pin, 1.6 x 2.0 mm)
Murata SAFEK881MFL0T00R00 (6-pin, 1.6 x 2.0 mm)
E-GSM 900 RX SAW Filter
(150 Ω balanced output)
EPCOS B39941-B7820-C710 (5-pin, 1.4 x 2.0 mm)
Murata SAFEK942MFM0T00R00 (6-pin, 1.6 x 2.0 mm)
Z2
Z3
DCS 1800 RX SAW Filter
(150 Ω balanced output)
EPCOS B39182-B7821-C710 (5-pin, 1.4 x 2.0 mm)
EPCOS B39182-B9013-K310 (6-pin, 1.6 x 2.0 mm)
Murata SAFEK1G84FA0T00R00 (6-pin, 1.6 x 2.0 mm)
PCS 1900 RX SAW Filter
(150 Ω balanced output)
EPCOS B39202-B7825-C710 (5-pin, 1.4 x 2.0 mm)
Murata SAFEK1G96FA0T00R00 (6-pin, 1.6 x 2.0 mm)
16
Rev. 1.0
Aero I+
4. Functional Description
Si4206
GSM
LNA
PGA
PGA
ADC
ADC
PGA
PGA
DCS
LNA
PCS
LNA
I
100 kHz
0 / 90
Q
I
DET
GSM
DCS
PCS
PA
XOUT
XAFC
RF
PLL
IF
PLL
DCXO
Figure 11. Aero I+ Transceiver Block Diagram
The Aero I+ transceiver is the industry’s most integrated from the baseband subsystem to the power amplifier,
RF front end for multi-band GSM/GPRS digital cellular and uses an offset phase-locked loop (PLL) with a fully
handsets and wireless data modems. The highly integrated transmit VCO. The frequency synthesizer
integrated solution eliminates the IF SAW filter, external uses Silicon Laboratories’ proven technology that
low noise amplifiers (LNAs) for three bands, transmit includes integrated RF and IF VCOs, varactors, and
and RF voltage-controlled oscillator (VCO) modules, loop filters.
and more than 70 other discrete components found in
conventional designs.
The unique integer-N PLL architecture produces a
transient response superior in speed to fractional-N
The high level of integration obtained through high- architectures without suffering the high phase noise or
performance packaging and fine line CMOS process spurious modulation effects often associated with those
technology results in a solution with 50% less area and designs. This fast transient response makes the Aero I+
80% fewer components than competing solutions. A transceiver well suited to GPRS multi-slot applications
triple-band GSM transceiver using the Aero I+ where channel switching and settling times are critical.
transceiver can be implemented with 15 components in
While conventional solutions use BiCMOS or other
2
less than 1.2 cm of board area. This level of integration
bipolar process technologies, the Aero I+ transceiver
is an enabling force in lowering the cost, simplifying the
employs 100% CMOS process. This brings the dramatic
design and manufacturing, and shrinking the form factor
cost savings and extensive manufacturing capacity of
in next-generation GSM/GPRS voice and data
CMOS to the GSM market.
terminals.
The receive section uses a digital low-IF architecture
that avoids the difficulties associated with direct
conversion while delivering lower solution cost and
reduced complexity. The baseband interface is
compatible with any supplier’s baseband subsystem.
The transmit section is a complete up-conversion path
Rev. 1.0
17
Aero I+
4.1. Receiver
Si4206
LNA
LNA
LNA
GSM
DCS
PCS
PGA
ADC
ADC
PGA
PGA
DAC
I
PGA
DAC
Q
CSEL DGAIN[5:0]
DACCM[1:0]
DACFS[1:0]
ZERODEL[2:0]
100 kHz
AGAIN[2:0]
0/90
RXBAND[1:0]
LNAC[1:0]
LNAG[1:0]
RF
PLL
DCXO
XOUT
NRF1[15:0]
RFUP
CDAC[5:0]
Figure 12. Receiver Block Diagram
The Aero I+ transceiver uses
a low-IF receiver converters (ADCs).
architecture that allows for on-chip integration of the
channel selection filters, eliminating the external RF
image reject filters and the IF SAW filter required in
conventional superheterodyne architectures. Compared
The ADC output is downconverted to baseband with a
digital 100 kHz quadrature LO signal. Digital decimation
and IIR filters perform channel selection to remove
blocking and reference interference signals. The
response of the IIR filter is programmable to a high
selectivity setting (CSEL = 0) or a low selectivity setting
(CSEL = 1). The low selectivity filter has a flatter group
delay response that may be desirable where the final
channelization filter is in the baseband chip. After
channel selection, the digital output is scaled with a
digital PGA, which is controlled with the DGAIN[5:0] bits
to
a
direct-conversion architecture, the low-IF
architecture has a much greater degree of immunity to
dc offsets that can arise from RF local oscillator (RFLO)
self-mixing, 2nd-order distortion of blockers, and device
1/f noise. This relaxes the common mode balance
requirements on the input SAW filters and simplifies PC
board design and manufacturing.
Three differential-input LNAs are integrated. The GSM in Register 05h.
input supports the GSM 850 (869–894 MHz) or E-
The LNAG[1:0], LNAC[1:0], AGAIN[2:0] and DGAIN[5:0]
GSM 900 (925–960 MHz) bands. The DCS input
supports the DCS 1800 (1805–1880 MHz) band. The
PCS input supports the PCS 1900 (1930–1990 MHz)
band.
bits must be set to provide a constant amplitude signal
to the baseband receive inputs. See “AN51: Aero
Transceiver AGC Strategy” for more details.
DACs drive a differential analog signal onto the BIP,
BIN, BQP, and BQN pins to interface to standard
analog-input baseband ICs. No special processing is
required in the baseband for offset compensation or
extended dynamic range. The receive and transmit
The LNA inputs are matched to the 200 Ω balanced-
output SAW filters through external LC matching
networks. The LNA gain is controlled with the
LNAG[1:0] and LNAC[1:0] bits in Register 05h.
A quadrature image-reject mixer downconverts the RF baseband I/Q pins are multiplexed together through the
signal to a 100 kHz intermediate frequency (IF) with the BIP, BIN, BQP, and BQN pins. The common mode
RFLO from the frequency synthesizer. The RFLO output level is programmable with the DACCM[1:0] bits,
frequency is between 1737.8 and 1989.9 MHz, and is and the full scale level is programmable with the
divided by two for GSM 850 and E-GSM 900 modes. DACFS[1:0] bits in Register 12h.
The mixer output is amplified with an analog
programmable gain amplifier (PGA), which is controlled
with the AGAIN[2:0] bits in Register 05h. The
quadrature IF signal is digitized with high resolution A/D
18
Rev. 1.0
Aero I+
4.2. Transmitter
Si4206
NRF2[15:0]
PDRB
NIF[15:0]
PDIB
RF
PLL
IF
PLL
BBG[1:0]
SWAP
y2
REG
RFOG
FIF[3:0]
PA
PA
I
GSM
REG
RFOD
I
DET
y1, 2
TXBAND[1:0]
Figure 13. Transmitter Block Diagram
DCS/PCS
Q
The transmit (TX) section consists of an I/Q baseband the DCS 1800 and PCS 1900 bands. The I and Q
upconverter, an offset phase-locked loop (OPLL), and signals are automatically swapped when switching
two 50 Ω output buffers that can drive external power bands. Therefore, there is no need for the customer to
amplifiers (PA), one for the GSM 850 (824–849 MHz) externally swap the I and O signals. However, for
and E-GSM 900 (880–915 MHz) bands and one for the additional layout flexibility, the SWAP bit in register 03h
DCS 1800 (1710–1785 MHz) and PCS 1900 (1850– can be used to manually exchange the I and Q signals.
1910 MHz) bands. The OPLL requires no external
Low-pass filters before the OPLL phase detector reduce
duplexer to attenuate transmitter noise and spurious
the harmonic content of the quadrature modulator and
signals in the receive band, saving both cost and power.
feedback mixer outputs. The cutoff frequency of the
Additionally, the output of the transmit VCO (TXVCO) is
filters is programmable with the FIF[3:0] bits in
a constant-envelope signal that reduces the problem of
Register 04h and should be set to the recommended
spectral spreading caused by non-linearity in the PA.
settings detailed in the register description.
A quadrature mixer upconverts the differential in-phase
(BIP, BIN) and quadrature (BQP, BQN) signals with the
IFLO to generate a SSB IF signal that is filtered and
used as the reference input to the OPLL. The IFLO
frequency is generated between 766 and 896 MHz. The
IFLO is divided by two to generate the quadrature LO
signals for the quadrature modulator, resulting in an IF
between 383 and 448 MHz. For the E-GSM 900 band,
two different IFLO frequencies are required for spur
management. Therefore, the IF PLL must be
programmed per channel in the E-GSM 900 band. The
IFLO frequencies are defined in Table 6 on page 11.
The OPLL consists of a feedback mixer, a phase
detector, a loop filter, and a fully integrated TXVCO. The
TXVCO is centered between the DCS 1800 and
PCS 1900 bands, and its output is divided by two for the
GSM 850 and E-GSM 900 bands. The Si4133T
generates the RFLO frequency between 1272 and
1483 MHz. To allow a single VCO to be used for the
RFLO, high-side injection is used for the GSM 850 and
E-GSM 900 bands, and low-side injection is used for
Rev. 1.0
19
Aero I+
4.3. Frequency Synthesizer
XTALEN
XAFC
Si4206
XTAL1
y65,
RF1
DCXO
y1, 2
To
RX/TX
I
y130
DET
XTAL2
RF2
DIV2
RFUP
CDAC[5:0]
RFPWR[1:0]
N
N
[15:0]
Self
RF1
XOUT
XEN
[15:0]
Tune
RF2
RF PLL
IF PLL
yN
yN
Power
PDIB
PDRB
PDN
Control
SDI
SDO
Self
N [15:0]
IF
Tune
Serial
I/O
SCLK
SEN
SDOSEL[3:0]
I
DET
To TX
Figure 14. Frequency Synthesizer Block Diagram
The Aero I+ transceiver integrates two complete PLLs A programmable divider in the input stage allows either
including VCOs, varactors, resonators, loop filters, a 13 or 26 MHz reference frequency depending on the
reference and VCO dividers, and phase detectors. The choice of crystal. A 26 MHz reference clock can be
RF PLL uses two multiplexed VCOs. The RF1 VCO is divided by 2 using the DIV2 bit in Register 31h. The RF
used for receive mode, and the RF2 VCO is used for PLL phase detector update rate (f ) can be programmed
φ
transmit mode. The IF PLL is used only during transmit with the RFUP bit in register 31h to either f = 100 kHz
φ
mode. All VCO tuning inductors are also integrated.
or f = 200 kHz. The IF PLL always uses f = 200 kHz.
φ
φ
Receive mode should use f = 100 kHz in DCS 1800
φ
The IF and RF output frequencies are set by
and PCS 1900 bands, and f = 200 kHz in the GSM 850
φ
programming the N-Divider registers, N
, N
, and
RF2
RF1
and E-GSM 900 bands. Transmit modes should always
N . Programming the N-Divider register for either RF1
IF
use f = 200 kHz.
φ
or RF2 automatically selects the proper VCO. The
output frequency of each PLL is as follows:
fOUT = N × fφ
20
Rev. 1.0
Aero I+
adjustments to compensate for aging may also be
performed over time to ensure accuracy.
4.4. DCXO Overview
The Aero I+ transceiver integrates the DCXO circuitry
required to generate a precise system reference clock
using only an external crystal resonator. (See
Figure 15.) An internal digitally programmable capacitor
array (CDAC) provides a coarse method of adjusting
The baseband determines the appropriate frequency
adjustment based on the receipt of the FCCH burst. The
baseband then adjusts the XAFC voltage using the
baseband AFC DAC (12 or 13-bit).
the reference frequency in discrete steps. An integrated The baseband AFC DAC can adjust CVAR to correct for
analog varactor (CVAR) allows for a fine and continuous frequency variations caused by temperature drift. The
adjustment of the reference frequency by an external step size per bit depends on the resolution of the AFC
control voltage (XAFC). This control voltage is supplied DAC and its output voltage range.
by the AFC DAC on the baseband IC. The complete
4.4.2. DCXO Crystal Selection
DCXO solution effectively replaces TCVCXO modules
The tuning range specifications listed in Table 8 on
typically required to provide a 13 or 26 MHz reference
page 14 for CDAC and CVAR assume that Aero I+ is
clock for the system.
used with a crystal that conforms to the crystal
parameters listed in the same table. Other crystals may
4.4.1. DCXO Tuning
The DCXO uses the CDAC and the CVAR to correct for be used with Aero I+ for cost and/or performance
both static and dynamic frequency errors, respectively. reasons. For example, using a higher sensitivity crystal
To compensate for crystal offset error, the CDAC extends the CVAR and the CDAC frequency
ensures a minimum of ±10 ppm frequency adjustment compensation range. However, care must be taken
capability. The CDAC is programmed using when using a more sensitive crystal because other
Register 28h.
system parameters are affected. Contact Silicon
Laboratories’ Application Support for assistance in
selecting other crystals.
The CDAC register (Register 28) may be programmed
during powerup or after an initial calibration. Periodic
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Figure 15. DCXO System Signal Routing Diagram
Rev. 1.0
21
Aero I+
4.5. Serial Interface
A three-wire serial interface is provided to allow an
external system controller to write the control registers
for dividers, receive path gain, power down settings,
and other controls. The serial control word is 24 bits in
length, comprised of an 18-bit data field and a 6-bit
address field as shown in Figure 16.
Last bit
clocked in
D
D
D
D
D
D
D
D
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
5
A
4
A
3
A
2
A
1
A
0
17 16 15 14 13 12 11 10
Address
Field
Data Field
Figure 16. Serial Interface Format
All registers must be written when the PDN pin is
asserted (low), except for Register 22h. All serial
interface pins should be held at a constant level during
receive and transmit bursts to minimize spurious
emissions. This includes stopping the SCLK clock. A
timing diagram for the serial interface is shown in
Figure 3 on page 7.
When the serial interface is enabled (i.e., when SEN is
low), data and address bits on the SDI pin are clocked
into an internal shift register on the rising edge of SCLK.
Data in the shift register is then transferred on the rising
edge of SEN into the internal data register addressed in
the address field. The internal shift register ignores any
leading bits before the 24 required bits. The serial
interface is disabled when SEN is high.
Optionally, registers can be read as illustrated in
Figure 4 on page 7. The serial output data appears on
the SDO pin after writing the revision register with the
address to be read. Writing to any of the registers
causes the function of SDO to revert to its previously
programmed function.
4.6. XOUT Buffer
The Aero I+ transceiver contains a reference clock
buffer to drive the baseband input. The XSEL control
has no effect on the buffered clock signal. The XOUT
buffer is a CMOS driver stage with approximately 250 Ω
of series resistance. This buffer is enabled when the
XEN pin is set high, independent of the PDN pin.
The XTALEN signal controls the powerup state of the
DCXO and must be enabled (XTALEN = 1) before the
XOUT signal can be sourced. To achieve complete
powerdown during sleep, the XEN pin must be set low,
the XBUF bit in Register 12 must be set to zero, and the
XPD1 bit in Register 11 must be set to one. During
normal operation, these bits should be set to their
default values.
22
Rev. 1.0
Aero I+
5. Control Registers
Table 9. Register Summary
Bit
Reg Name
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1
D0
01h
02h
03h
04h
05h
11h
12h
19h
20h
21h
22h
23h
24h
28h
31h
32h
Reset
Mode
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0
SWAP
0
AUTO
MODE[1:0]
Config
DIAG[1:0]
TXBAND[1:0] RXBAND[1:0]
FIF[3:0]
0
0
1
0
0
0
Transmit
Receive
Config
0
0
BBG[1:0]
DGAIN[5:0]
XPD1
0
0
AGAIN[2:0]
LNAC[1:0]
LNAG[1:0]
DPDS[2:0]
1
XBUF
0
XSEL
1
0
0
1
0
0
0
0
CSEL
DAC Config
Reserved
0
0
0
0
0
0
1
0
0
0
ZDBS
0
ZERODEL[2:0]
0
DACCM[1:0]
DACFS[1:0]
0
0
0
0
RX Master #1 RXBAND[1:0]
NRF1[15:0]
AGAIN[2:0]
RX Master #2
RX Master #3
0
0
DPDS[2:0]
0
LNAC[1:0]
LNAG[1:0]
0
0
DGAIN[5:0]
DGAIN[5:0]
0
0
0
0
0
0
0
0
0
TX Master #1 TXBAND[1:0]
NRF2[15:0]
NIF[13:0]
TX Master #2
CDAC
FIF[3:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CDAC[5:0]
Config
SDOSEL[3:0]
0
0
0
0
RFUP DIV2
0
0
0
0
Powerdown
0
0
0
0
PDIB PDRB
33h RF1 N Divider
34h RF2 N Divider
NRF1[15:0]
NRF2[15:0]
NIF[15:0]
35h
IF N Divider
Notes:
1. Any register not listed here is reserved and should not be written. Writing to reserved registers may result in
unpredictable behavior.
2. Master registers 20h to 24h simplify programming the Aero I+ to support initiation of receive (RX) and transmit (TX)
operations with only two register writes.
3. See “AN50: Aero Transceiver Programming Guide” for detailed instructions on register programming.
Rev. 1.0
23
Aero I+
Register 01h. Reset
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
Name
Bit
Name
Function
17:1
0
Reserved
RESET
Program to zero.
Chip Reset.
0 = Normal operation (default).
1 = Reset all registers to default values.
Note: This register must be written to 0 twice after a reset operation. This bit
does not reset registers 31h to 35h.
Register 02h. Mode Control
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AUTO
MODE[1:0]
Name
Bit
Name
Function
17:3
2
Reserved
AUTO
Program to zero.
Automatic Mode Select.
0 = Manual. Mode is controlled by MODE[1:0] bits (default).
1 = Automatic. Last register write to N implies RX mode; Last register
RF1
write to N
implies TX mode. MODE[1:0] bits are ignored.
RF2
1:0
MODE[1:0]
Transmit/Receive/Cal Mode Select.
00 = Receive mode (default).
01 = Transmit mode.
10 = Calibration mode.
11 = Reserved.
Note: These bits are valid only when AUTO = 0.
Note: Calibration must be performed each time the power supply is applied. To initiate the calibration mode, set
MODE[1:0] = 10 and pulse the PDN pin high for at least 150 µs.
24
Rev. 1.0
Aero I+
Register 03h. Configuration
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
DIAG[1:0]
SWAP
0
0
0
TXBAND[1:0]
RXBAND[1:0]
0
0
1
0
Name
Bit
Name
Function
17:14
13:12
Reserved
DIAG[1:0]
Program to zero.
DIAG1/DIAG2 Output Select.
DIAG1
LOW
LOW
HIGH
HIGH
DIAG2
LOW (default)
HIGH
LOW
HIGH
00 =
01 =
10 =
11 =
Note: These pins can be used to control antenna switch functions. These bits
must be programmed with the PDN pin is zero. The DIAG1/DIAG2 pins
will be held at the desired value regardless of the state of the PDN pin.
11
SWAP
Transmit I/Q Swap.
0 = Normal (default).
1 = Swap I and Q for TXIP, TXIN, TXQP, and TXQN pins.
10:8
7:6
Reserved
Program to zero.
TXBAND[1:0]
Transmit Band Select.
00 = GSM 850 or E-GSM 900 (default).
01 = DCS 1800.
10 = PCS 1900.
11 = Reserved.
5:4
RXBAND[1:0]
Receive Band Select.
00 = GSM input (default).
01 = DCS input.
10 = PCS input.
11 = Reserved.
3:2
1
Reserved
Reserved
Reserved
Program to zero.
Program to one.
Program to zero.
0
Rev. 1.0
25
Aero I+
Register 04h. Transmit Control
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
0
0
0
1
BBG[1:0]
FIF[3:0]
0
0
0
0
Name
Bit
Name
Function
17:11
10
Reserved
Reserved
BBG[1:0]
Program to zero.
Program to one.
9:8
TX Baseband Input Full Scale Differential Input Voltage.
10 = Reserved.
11 = 2.0 V
00 = 1.6 V
01 = 1.2 V
PPD
PPD
PPD
(default).
Note: Refer to Table 6 on page 11 for minimum and maximum values. Set this
register to the nearest value.
7:4
3:0
FIF[3:0]
TX IF Filter Cutoff Frequency.
0111 = Use for GSM 850, E-GSM 900 and PCS 1900 bands.
0110 = Use for DCS 1800 band.
Note: Use the recommended setting for each band. Other settings reserved.
Reserved
Program to zero.
26
Rev. 1.0
Aero I+
Register 05h. Receive Gain
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
DGAIN[5:0]
0
AGAIN[2:0]
LNAC[1:0]
LNAG[1:0]
Name
Bit
Name
Function
17:14
13:8
Reserved
Program to zero.
DGAIN[5:0]
Digital PGA Gain Control.
00h = 0 dB (default).
01h = 1 dB.
...
3Fh = 63 dB.
Note: See “AN51: Aero Transceiver AGC Strategy” for details on setting the gain
registers.
7
Reserved
Program to zero.
6:4
AGAIN[2:0]
Analog PGA Gain Control.
000 = 0 dB (default).
001 = 4 dB.
010 = 8 dB.
011 = 12 dB.
100 = 16 dB.
101 = Reserved.
110 = Reserved.
111 = Reserved.
Note: See “AN51: Aero Transceiver AGC Strategy” for details on setting the gain
registers.
3:2
1:0
LNAC[1:0]
LNAG[1:0]
LNA Bias Current Control.
00 = Minimum current (default).
01 = Maximum current.
10 = Reserved.
11 = Reserved.
Note: Program these bits to the same value as same as LNAG[1:0].
LNA Gain Control.
00 = Minimum gain (default).
01 = Maximum gain.
10 = Reserved.
11 = Reserved.
Notes:
1. Program these bits to the same value as LNAC[1:0].
2. See “AN51: Aero Transceiver AGC Strategy” for details on setting the gain
registers.
Rev. 1.0
27
Aero I+
Register 11h. Configuration
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
DPDS[2:0]
XPD1
1
XSEL
0
1
0
1
0
0
0
CSEL
Name
Bit
Name
Function
17:14
13:11
Reserved
Program to zero.
Data Path Delayed Start.
111= Use for GSM 850 and GSM 900 bands.
011= Use for DCS 1800 and PCS 1900 bands (default).
DPDS[2:0]
Note: Use the recommended setting for each band. Other settings reserved.
10
XPD1
Reference Buffer Powerdown.
0 = Reference buffer always powered up (default).
1 = Reference buffer powered down when not in use.
Note: This bit should be set to 0 during normal operation. To achieve lowest
Si4206 powerdown current (IPDN1), this bit should be set to 1.
9
8
Reserved
XSEL
Program to one.
Reference Frequency Select.
0 = No divider. XIN = 13 MHz (default).
1 = Divide XIN by 2. XIN = 26 MHz.
Note: The internal clock should always be 13 MHz.
7
6
Reserved
Reserved
Reserved
Reserved
Reserved
CSEL
Program to zero.
Program to one.
Program to zero.
Program to one.
Program to zero.
5
4
3:1
0
Digital IIR Coefficient Select.
0 = High selectivity filter (default).
1 = Low selectivity filter.
28
Rev. 1.0
Aero I+
Register 12h. DAC Configuration
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
0
0
0
1
XBUF
0
ZDBS
ZERODEL[2:0]
DACCM[1:0]
DACFS[1:0]
Name
Bit
Name
Function
17:11
10
Reserved
Reserved
XBUF
Program to zero.
Program to one.
9
Reference Buffer Power Control.
0 = Reference buffer powered down when not in use.
1 = Reference buffer always powered up (default).
Note: This bit should be set to 1 during normal operation. To achieve the lowest
Aero I+ powerdown current (IPDN1), this bit should be set to 0.
8
7
Reserved
ZDBS
Program to zero.
ZERODEL Band Select.
0 = Use ZERODEL[2:0] settings corresponding to DCS/PCS column
(default).
1 = Use RXBAND[1:0] to determine ZERODEL[2:0] delay setting (GSM
or DCS/PCS).
6:4
ZERODEL[2:0]
RX Output Zero Delay.
Code
000:
001:
010:
011:
100:
101:
110:
111:
GSM
90 µs
DCS/PCS
130 µs
150 µs
170 µs
180 µs
190 µs
200 µs
220 µs
(default)
110 µs
130 µs
140 µs
150 µs
160 µs
180 µs
Reserved
Note: DAC input is forced to zero after PDN is deasserted. This feature can be
used by the baseband processor to cancel the Si4206 DAC dc offset.
Offsets induced on channels due to 13 MHz harmonics will not be
included in the calibrated value.
3:2
1:0
DACCM[1:0]
DACFS[1:0]
RX Output Common Mode Voltage.
00 = 1.0 V.
01 = 1.25 V (default).
10 = 1.35 V.
11 = Reserved.
RX Output Differential Full Scale Voltage.
00 = 1.0 V
01 = 2.0 V
10 = 3.5 V
.
PPD
PPD
PPD
(default).
.
11 = Reserved.
Rev. 1.0
29
Aero I+
Register 19h. Reserved
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Name
Bit
17:0
Name
Function
Reserved
Program to zero.
Register 20h. RX Master #1
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
NRF1[15:0]
RXBAND[1:0]
Name
Notes:
1. See registers 03h and 33h for bit definitions.
2. When this register is written, the PDIB bit is automatically set to 0, the PDRB bit is set to 1 and the RFUP bit is set as a
function of RXBAND[1:0].
Register 21h. RX Master #2
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LNAC[1:0]
LNAG[1:0]
AGAIN[2:0]
0
DGAIN[5:0]
0
DPDS[2:0]
Name
Note: See registers 05h and 11h for bit definitions.
Register 22h. RX Master #3
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
DGAIN[5:0]
0
0
0
0
0
0
0
0
0
0
0
Name
Notes:
1. See register 05h for bit definitions.
2. The DGAIN[5:0] in register 22h can be changed without powering down.
30
Rev. 1.0
Aero I+
Register 23h. TX Master #1
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
NRF2[15:0]
TXBAND[1:0]
Name
Notes:
1. See registers 03h and 34h for bit definitions.
2. When this register is written, the PDIB bit is automatically set to 1, and the PDRB bit is set to 1.
Register 24h. TX Master #2
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
NIF[13:0]
FIF[3:0]
Name
Note: See registers 04h and 35h for bit definitions.
Rev. 1.0
31
Aero I+
Register 28h. CDAC (Si4134T)
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
0
0
0
0
0
0
0
0
Name
CDAC[5:0]
Bit
Name
Function
17:6
5:0
Reserved
Read as zero.
DCXO Coarse Frequency DAC Adjustment.
CDAC[5:0]
64 steps. 1.0 ppm typical per step. An increase in CDAC results in a
lower oscillating frequency. Likewise, a decrease in CDAC results in a
higher oscillating frequency.
000000 = Highest frequency
...
111111 = Lowest frequency
Register 31h. Main Configuration
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
SDOSEL[3:0]
0
0
0
0
0
0
RFUP DIV2
0
0
0
Name
Bit
Name
Function
17:15
14:11
Reserved
Program to zero.
SDO Output Control Register.
The mux_output table is as follows:
SDOSEL[3:0]
0000 Connected to the Output Shift Register (default).
0001 Force the Output to Low.
0010 Reference Clock.
0011 Lock Detect (LDETB) Signal from Phase Detectors.
1111 High Impedance.
Notes:
1. SDO is high-impedance when PDN = 0.
2. SDO is Serial Data Output when in register read mode.
10:5
4
Reserved
RFUP
Program to zero.
RF PLL Update Rate (RF1 VCO only).
0 = 200 kHz update rate (Receive GSM modes).
1 = 100 kHz update rate (Receive DCS and PCS modes).
Notes:
1. This bit is set to 1 when register 20h D[17:16] = 01b or 10b (DCS 1800 or
PCS 1900 receive modes) and is set to 0 when D[17:16] = 00b or 11b
(GSM 850 or GSM 900 modes).
2. This bit is set to 0 when register 23h is written (transmit mode)
3
DIV2
Input Clock Frequency.
0 = No divider. XIN = 13 MHz.
1 = Divide XIN by 2. XIN = 26 MHz.
2:0
Reserved
Program to zero.
32
Rev. 1.0
Aero I+
Register 32h. Powerdown
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PDIB PDRB
Name
Bit
17:2
1
Name
Reserved
PDIB
Function
Program to zero.
Powerdown IF PLL.
0 = IF synthesizer powered down.
1 = IF synthesizer powered up when the PDN pin is high.
Notes:
1. The IF PLL is only used in transmit mode. Powerdown for receive mode.
2. This bit is set to 0 when register 20h is written (receive mode).
3. This bit is set to 1 when register 23h is written (transmit mode).
0
PDRB
Powerdown RF PLL.
0 = RF synthesizer powered down.
1 = RF synthesizer powered up when the PDN pin is high.
Notes:
1. This bit is set to 1 when register 20h is written (receive mode).
2. This bit is set to 1 when register 23h is written (transmit mode).
Register 33h. RF1 N Divider
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
Name
N
[15:0]
RF1
Bit
Name
Function
17:16
15:0
Reserved
Program to zero.
N
[15:0]
N Divider for RF PLL (RF1 VCO).
RF1
Used for receive mode.
Register 34h. RF2 N Divider
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
Name
N
[15:0]
RF2
Bit
Name
Function
17:16
15:0
Reserved
Program to zero.
N
[15:0]
N Divider for RF PLL (RF2 VCO).
RF2
Used for transmit mode.
Rev. 1.0
33
Aero I+
Register 35h. IF N Divider
Bit
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
Name
N [15:0]
IF
Bit
Name
Function
17:16
15:0
Reserved
Program to zero.
N [15:0]
N Divider for IF PLL.
Used for transmit mode.
IF
34
Rev. 1.0
Aero I+
6. Pin Descriptions: Si4206-BM
28
27
26
25
24
23
22
32
31
21
1
2
3
4
5
6
7
RFIGN
RFIGP
RFIDN
RFIDP
RFIPN
RFIPP
GND
BQP
BQN
GND
GND
20
19
18
17
16
15
BIP
BIN
XTAL1
XTAL2
XAFC
GND
9
GND
13
29
30
8
10
11
12
14
Pin Number(s)
Name
BQP, BQN
BIP, BIN
XTAL1
XTAL2
XAFC
Description
1, 2
Transmit/Receive Q signal (differential).
Transmit/Receive I signal (differential).
Crystal input.
3, 4
5
6
Crystal output.
7
Baseband AFC signal input.
Crystal enable.
8
XTALEN
XDRVEN
SDO
9
10
XDRV enable.
Serial data output.
11
SEN
Serial enable input (active low).
Serial clock input.
12
SCLK
13
SDI
Serial data input.
14, 30, 32
15, 29, 31
16, 17
V
Supply voltage.
DD
GND
Ground. Connect to ground plane on PCB.
RFIPP, RFIPN PCS LNA input (differential).
Use for PCS 1900 band.
18, 19
20, 21
22
RFIDP, RFIDN DCS LNA input (differential).
Use for DCS 1800 band.
RFIGP, RFIGN GSM LNA input (differential).
Use for GSM 850 or E-GSM 900 bands.
RFOD
RFOG
DCS and PCS transmit output to power amplifier.
Use for DCS 1800 and PCS 1900 bands.
23
GSM transmit output to power amplifier.
Use for GSM 850 and E-GSM 900 bands.
24, 25
DIAG1, DIAG2 Diagnostic output.
Can be used as digital outputs to control antenna switch functions.
26
27
28
PDN
XEN
Powerdown input (active low).
XOUT pin enable.
XOUT
Clock output to baseband.
Rev. 1.0
35
Aero I+
7. Ordering Guide
Part Number Description
Operating
Temperature
Si4206-BM
Tri-band Transceiver with DCXO
–20 to 85 °C
GSM 850 or E-GSM 900, DCS 1800, PCS 1900
Note: Add an “R” at the end of the part number to denote tape and reel option; 2500 quantity per
reel. The Si4206 is a lead-free device.
36
Rev. 1.0
Aero I+
8. Package Outline: Si4206-BM
C
0.10
C
7.30
4x
(4x)
0.10
1.35±0.07
6x 0.80 (=4.80)
4x
8.00
4x 1.25
4x 0.35
A
Pin 1 Indicator
Pin 1
4x 0.35
2x 3.80
8.00
2x 1.75
28x 0.50 x 0.30
M
0.10
C
A
B
B
B
4x 0.50 x 0.50
2x 1.75
2x 3.80
M
0.10
C A
4x 1.20 x 1.20
M
0.10
C A B
Top View
Side View
Bottom View
Figure 17. 32-Pin Land Grid Array (LGA)
Notes:
1. Dimensions in mm.
2. Approximate device weight is 184 mg.
Rev. 1.0
37
Aero I+
DOCUMENT CHANGE LIST
Revision 0.81 to Revision 1.0
Table 8 on page 14 updated.
z CVAR Range, CDAC Range, and CFIX updated.
Functional Description text on page 19 updated.
Figure 15, “DCXO System Signal Routing
Diagram,” on page 21 updated.
"Ordering Guide" on page 36 updated.
Rev. 1.0
38
Aero I+
NOTES:
Rev. 1.0
39
Aero I+
CONTACT INFORMATION
Silicon Laboratories Inc.
4635 Boston Lane
Austin, Texas 78735
Tel:1+ (512) 416-8500
Fax:1+ (512) 416-9669
Toll Free:1+ (877) 444-3032
Email: Aeroinfo@silabs.com
Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed fea-
tures or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no war-
ranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume
any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applica-
tions intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a
situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended
or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
Silicon Laboratories, Silicon Labs, and Aero are trademarks of Silicon Laboratories Inc.
Other products or brand names mentioned herein are trademarks or registered trademarks of their respective holder.
40
Rev. 1.0
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