SI4300 [SILICON]
Dual-Band Monolithic Power Amplifier System; 双波段单片功率放大器系统
| 型号： | SI4300 |
| 厂家： | 
SILICON |
| 描述： | Dual-Band Monolithic Power Amplifier System |
| 文件： | 总2页 (文件大小：121K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si4300
Dual-Band Monolithic Power Amplifier System
Description
Features
2
The Si4300 is a complete, monolithic, high-power, and
high-performance power amplifier system that integrates
all functions and all components between the transmit
portion of the transceiver and antenna switch module
(ASM). The integrated circuit consists of two amplification
paths which supports GSM 900 and DCS 1800. These
amplifiers are General Packet Radio Service (GPRS) class
12 compatible and can be used in GPRS multi-slot
applications. The Si4300 integrates the input and output
matching networks, complete power control, thermal and
load mismatch protection, and many other features and
functions in a single, standard CMOS die on a ceramic
substrate.
- Small 25 mm package
(3.9 x 6.4 x 1.3 mm)
- Complete power control
- Thermal and load mismatch protection
- Harmonic filtering
- Input and output matching circuits
- Optimal average burst current (ABC)
for all power levels
- Low powerdown current during
receive and standby
- GPRS Class 12 compatible
- 3.0 to 4.8 V operation
- JEDEC moisture sensitivity level (MSL) 1
- RoHS compliant
Applications
- E-GSM 900 and DCS 1800 dual-band cellular
handsets
- GPRS data terminals
VBAT
Si4300
APC
Low Pass
Filter
Power
Control
RFIL
Matching
RFOL
Limiter
PA
Network
Harmonic
Filter
GND
Matching
Network
Limiter
PA
RFOH
RFIH
Harmonic
Filter
TLIMIT
PAEN
Monitor, Control,
and
I/O Interface
Temperature
and Voltage
Sensors
VDD
SHUTD
BSEL
Power Amplifier
Copyright © 2005 by Silicon Laboratories
11.10.05
Si4300
Dual-Band Monolithic Power Amplifier System
Selected Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
GSM
Input Power
PIN
Across all operating conditions
RBW = 100 kHz,
3.5
—
—
—
11
dBm
dBm
Output Noise Power
–72
f = 925 to 935 MHz
RBW = 100 kHz, f > 935 MHz, 6 dBm
POUT = over all power levels,
All combinations of the following:
—
—
—
–86
1.6:1
—
–84
1.8:1
dBm
Input VSWR
Ruggedness
no damage
or
P
IN = 3.5 to 11 dBm, APC < 2.0 V,
T
C = –20 to 85 °C, VBAT = 3.0 to 4.8 V,
Antenna VSWR ≤ 20:1, all angles
Post-PA loss ≥ 1.4 dB
permanent
degradation
DCS
Input Power
PIN
PNOISE
Across all operating conditions
RBW = 100 kHz,
3.5
—
—
—
9
dBm
dBm
Output Noise Power
–77
f = 1805–1880 MHz
RBW = 100 kHz, f > 1880 MHz
POUT = over all power levels,
All combinations of the following:
—
—
—
—
1.6:1
—
–77
1.8:1
dBm
Input VSWR
Ruggedness
no damage
or
P
IN = 3.5 to 9 dBm, APC < 2.0 V,
T
C = –20 to 85 °C, VBAT = 3.0 to 4.8 V,
Antenna VSWR ≤ 20:1, all angles
Post-PA loss ≥ 1.4 dB
permanent
degradation
Pin Assignments
Package Information
C
A
M
E
A
DETAIL
A
(Top View)
M
0.10
C
A B
(2X)
aaa
14
13
N/C
15
16
RFOH
PAEN
1
2
NC
C
B
C1
C1
S2
C2
P1
P4
S1
GND
BSEL
S3
S5
P2
P3
S4
D
3
4
5
12
11
10
RFIL
GND
RFIH
TLIMIT
SHUTD
VDD
DETAIL
0.10
B (10X)
17
18
VBAT
VBAT
M
C
A B
DETAIL
D (6X)
DETAIL
C (3X)
Bottom View
(2X)
M
0.10
C
A B
M
0.10
C A B
aaa
C
Top View
Side View
H2
L2
6
7
9
8
J2
K2
APC
N/C
GND
GND 19
h1
H1
J1
K1
L1
h2
20
NC
DETAIL
A
DETAIL
B
DETAIL
C
DETAIL D
RFOL
Dimension MIN NOM MAX Dimension MIN NOM MAX Dimension MIN NOM MAX
A
1.17 1.30 1.43
0.55 0.60 0.65
0.35 0.40 0.45
0.35 0.40 0.45
0.15 0.20 0.25
0.27 0.32 0.37
0.35 0.40 0.45
0.35 0.40 0.45
0.35 0.40 0.45
L1
L2
C1
C2
D
0.35 0.40 0.45
1.65 1.70 1.75
2.70 BSC
P3
P4
S1
S2
S3
S4
S5
aaa
0.30 BSC
1.60 BSC
1.60 BSC
0.80 BSC
0.15 BSC
0.50 BSC
1.50 BSC
0.10
H1
h1
H2
h2
J1
J2
K1
K2
2.60 BSC
6.40 BSC
E
3.90 BSC
M
2.90 BSC
P1
P2
1.70 BSC
0.50 BSC
Power Amplifier
Copyright © 2005 by Silicon Laboratories
11.10.05
Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders
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