SI4730-D50-GM [SILICON]
Audio Single Chip Receiver, ROHS COMPLIANT, QFN-20;
| 型号： | SI4730-D50-GM |
| 厂家： | 
SILICON |
| 描述： | Audio Single Chip Receiver, ROHS COMPLIANT, QFN-20 商用集成电路 |
| 文件： | 总34页 (文件大小：559K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si4730/31-D50
BROADCAST AM/FM RADIO RECEIVER
Features
Worldwide FM band support
(64–108 MHz)
Worldwide AM band support
(520–1710 kHz)
Excellent real-world performance
Integrated VCO
Advanced AM/FM seek tuning
AM/FM digital tuning
Automatic frequency control (AFC)
Automatic gain control (AGC)
Digital FM stereo decoder
Programmable AVC max gain
Programmable de-emphasis
Seven selectable AM channel filters
Advanced audio processing
No manual alignment necessary
Programmable reference clock
Volume control
Adjustable soft mute control
RDS/RBDS processor (Si4731 only)
I2S digital audio out
Ordering Information:
2-wire and 3-wire control interface
Integrated LDO regulator
Wide range of ferrite loop sticks and
air loop antennas supported
QFN package
See page 26.
Pin Assignments
Si4730/31
RoHS compliant
Not suitable for wall-plugged
consumer electronic applications*
*Note: For consumer electronics applications, use Si4730/31-D60 for worldwide
20 19 18 17
NC
FMI
1
16
CE and EN compliance.
2
15 DOUT
14 LOUT
13 ROUT
12 GND
11 VA
Applications
RFGND
AMI
3
4
5
GND
PAD
Cellular handsets
MP3 players
Portable navigation
Mobile Internet Devices Tablets
USB FM radio eBooks
RST
Description
6
7
8
9
10
The Si4730/31-D50 is the fourth generation digtial CMOS AM/FM radio receiver
IC from Silicon Labs. The Si4730/31-D50 integrates the complete tuner function
from antenna input to audio output.
This product, its features, and/or its
architecture is covered by one or more of
the following patents, as well as other
patents, pending and issued, both
foreign and domestic: 7,127,217;
Functional Block Diagram
Si473x
7,272,373;
7,355,476;
7,272,375;
7,426,376;
7,321,324;
7,471,940;
AMI
DOUT
RDS
(Si4731)
AM
ANT
LNA
AGC
DIGITAL
AUDIO
RFGND
7,339,503; 7,339,504.
DFS
GPO/DCLK
LOW-IF
ADC
ADC
DAC
DAC
ROUT
LOUT
FM
ANT
LNA
AGC
DSP
FMI
2.7– 5.5 V
VA
CONTROL
INTERFACE
LDO
AFC
VD
1.62–3.6 V
GND
Rev. 1.0 2/11
Copyright © 2011 by Silicon Laboratories
Si4730/31-D50
Si4730/31-D50
2
Rev. 1.0
Si4730/31-D50
TABLE OF CONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
3. Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4.2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4.3. FM Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.4. AM Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.5. Digital Audio Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.6. Stereo Audio Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.7. Received Signal Qualifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.8. De-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.9. Volume Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.10. Stereo DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.11. Soft Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.12. FM Hi-Cut Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
4.13. RDS/RBDS Processor (Si4731 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
4.14. Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
4.15. Seek . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
4.16. Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
4.17. Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4.18. GPO Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
4.19. Firmware Upgrades . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
4.20. Reset, Powerup, and Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
4.21. Programming with Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
5. Pin Descriptions: Si4730/31-GM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
7. Package Markings (Top Marks) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
7.1. Si4730/31 Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
7.2. Top Mark Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
8. Package Outline: Si4730/31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
9. PCB Land Pattern: Si4730/31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
10. Additional Reference Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Document Change List: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Rev. 1.0
3
Si4730/31-D50
1. Electrical Specifications
Table 1. Recommended Operating Conditions*
Parameter
Analog Supply Voltage
Symbol Test Condition
Min
2.7
Typ
—
Max
5.5
3.6
—
Unit
V
V
A
Digital and I/O Supply Voltage
V
1.62
10
—
V
D
Analog Power Supply Powerup Rise
Time
V
—
µs
ARISE
Digital Power Supply Powerup Rise
Time
V
10
—
—
µs
DRISE
Ambient Temperature
T
–20
25
85
C
A
*Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at VA = 3.3 V and 25 C unless otherwise stated. Parameters are tested in production unless
otherwise stated.
Table 2. Absolute Maximum Ratings1,2
Parameter
Analog Supply Voltage
Symbol
Value
–0.5 to 5.8
–0.5 to 3.9
10
Unit
V
V
A
Digital and I/O Supply Voltage
V
V
D
3
Input Current
I
mA
V
IN
3
Input Voltage
V
T
–0.3 to (V + 0.3)
IN
IO
Operating Temperature
Storage Temperature
–40 to 95
–55 to 150
0.4
C
C
OP
T
STG
4
RF Input Level
V
pK
Notes:
1. Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation
should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure beyond
recommended operating conditions for extended periods may affect device reliability.
2. The Si4730/31 device is a high-performance RF integrated circuit with certain pins having an ESD rating of < 2 kV
HBM. Handling and assembly of these devices should only be done at ESD-protected workstations.
3. For input pins DFS, SCLK, SEN, SDIO, RST, RCLK, GPO1, GPO2, GPO3, and DCLK.
4. At RF input pins FMI and AMI.
4
Rev. 1.0
Si4730/31-D50
Table 3. DC Characteristics
(VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
FM Mode
V Supply Current
I
—
—
—
7.5
8.5
8.4
9.7
11.1
11.1
mA
mA
mA
A
FMVA
FMVD
FMVD
1
V Supply Current
I
I
Digital Output Mode
D
V Supply Current
Analog Output Mode
D
AM Mode
V Supply Current
I
—
—
—
7.5
8.5
8.0
8.5
11.0
10.2
mA
mA
mA
A
AMVA
AMVD
AMVD
1
V Supply Current
I
I
Digital Output Mode
D
V Supply Current
Analog Output Mode
D
Powerdown and Interface
V Powerdown Current
I
—
—
4
15
10
µA
µA
V
A
APD
V Powerdown Current
I
SCLK, RCLK inactive
3
D
DOPD
2
2
High Level Input Voltage
V
0.7 x V
–0.3
–10
—
—
—
—
V + 0.3
D
IH
D
2
Low Level Input Voltage
V
0.3 x V
10
V
IL
D
High Level Input Current
I
V
= V = 3.6 V
µA
µA
IH
IN
D
2
Low Level Input Current
I
V
= 0 V,
IN
–10
10
IL
V = 3.6 V
D
3
High Level Output Voltage
V
I
= 500 µA
0.8 x V
—
—
—
—
V
V
OH
OUT
OUT
D
3
Low Level Output Voltage
V
I
= –500 µA
0.2 x V
OL
D
Notes:
1. Guaranteed by characterization.
2. For input pins SCLK, SEN, SDIO, RST, RCLK, DCLK, DFS, GPO1, GPO2, and GPO3.
3. For output pins SDIO, DOUT, GPO1, GPO2, and GPO3.
Rev. 1.0
5
Si4730/31-D50
Table 4. Reset Timing Characteristics1,2,3
(VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol
Min
100
30
Typ
—
Max
—
Unit
µs
RST Pulse Width and GPO1, GPO2/INT Setup to RST
GPO1, GPO2/INT Hold from RST
Important Notes:
t
SRST
t
—
—
ns
HRST
1. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is
high) does not occur within 300 ns before the rising edge of RST.
2. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high until
after the first start condition.
3. When selecting 3-wire mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the
rising edge of RST.
4. If GPO1 and GPO2 are actively driven by the user, then minimum tSRST is only 30 ns. If GPO1 or GPO2 is hi-Z, then
minimum tSRST is 100 µs, to provide time for on-chip 1 M devices (active while RST is low) to pull GPO1 high and
GPO2 low.
tHRST
tSRST
70%
30%
RST
70%
30%
GPO1
70%
30%
GPO2/
INT
Figure 1. Reset Timing Parameters for Busmode Select
6
Rev. 1.0
Si4730/31-D50
Table 5. 2-Wire Control Interface Characteristics1,2,3
(VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol Test Condition
Min
0
Typ
—
Max
400
—
Unit
kHz
µs
SCLK Frequency
SCLK Low Time
SCLK High Time
f
SCL
t
1.3
0.6
0.6
—
LOW
t
—
—
µs
HIGH
SCLK Input to SDIO Setup
t
t
—
—
µs
SU:STA
(START)
SCLK Input to SDIO Hold
0.6
—
—
µs
HD:STA
(START)
SDIO Input to SCLK Setup
t
t
100
0
—
—
—
—
900
—
ns
ns
µs
SU:DAT
4,5
SDIO Input to SCLK Hold
HD:DAT
SU:STO
SCLK input to SDIO Setup
t
0.6
(STOP)
STOP to START Time
SDIO Output Fall Time
t
1.3
—
—
—
µs
ns
BUF
t
250
f:OUT
Cb
----------
1pF
20 + 0.1
SDIO Input, SCLK Rise/Fall Time
t
t
—
300
ns
f:IN
r:IN
Cb
----------
1pF
20 + 0.1
SCLK, SDIO Capacitive Loading
Input Filter Pulse Suppression
Notes:
C
—
—
—
—
50
50
pF
ns
b
t
SP
1. When VD = 0 V, SCLK and SDIO are low impedance.
2. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is
high) does not occur within 300 ns before the rising edge of RST.
3. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high
until after the first start condition.
4. The Si4730/31 delays SDIO by a minimum of 300 ns from the VIH threshold of SCLK to comply with the minimum
tHD:DAT specification.
5. The maximum tHD:DAT has only to be met when fSCL = 400 kHz. At frequencies below 400 KHz, tHD:DAT may be
violated as long as all other timing parameters are met.
Rev. 1.0
7
Si4730/31-D50
tSU:STA tHD:STA
tLOW
tHIGH
tr:IN
tf:IN
tSP
tSU:STO
tBUF
70%
SCLK
30%
70%
SDIO
30%
tf:IN,
tf:OUT
START
tHD:DAT tSU:DAT
tr:IN
STOP
START
Figure 2. 2-Wire Control Interface Read and Write Timing Parameters
SCLK
SDIO
A6-A0,
R/W
D7-D0
D7-D0
START
ADDRESS + R/W
ACK
DATA
ACK
DATA
ACK
STOP
Figure 3. 2-Wire Control Interface Read and Write Timing Diagram
8
Rev. 1.0
Si4730/31-D50
Table 6. 3-Wire Control Interface Characteristics
(V = 2.7 to 5.5 V, V = 1.62 to 3.6 V, TA = –20 to 85 °C)
A
D
Parameter
Symbol
Test Condition
Min
0
Typ
—
—
—
—
—
—
—
—
—
Max
2.5
—
Unit
MHz
ns
SCLK Frequency
SCLK High Time
SCLK Low Time
f
CLK
t
25
25
20
10
10
2
HIGH
t
—
ns
LOW
SDIO Input, SEN to SCLKSetup
SDIO Input to SCLKHold
t
—
ns
S
t
—
ns
HSDIO
SEN Input to SCLKHold
t
—
ns
HSEN
SCLKto SDIO Output Valid
SCLKto SDIO Output High Z
SCLK, SEN, SDIO, Rise/Fall time
t
Read
Read
25
25
10
ns
CDV
t
2
ns
CDZ
t , t
—
ns
R
F
Note: When selecting 3-wire mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the
rising edge of RST.
70%
SCLK
30%
tR
tF
tHSDIO
tHIGH
tLOW
tHSEN
tS
70%
30%
tS
SEN
A6-A5,
R/W,
A4-A1
70%
30%
A7
A0
D15
D14-D1
D0
SDIO
Address In
Data In
Figure 4. 3-Wire Control Interface Write Timing Parameters
70%
30%
SCLK
SEN
tHSDIO
tCDV
tHSEN
tS
tCDZ
70%
30%
tS
70%
30%
A6-A5,
R/W,
A4-A1
A7
A0
D15
D14-D1
D0
SDIO
½ Cycle Bus
Turnaround
Address In
Data Out
Figure 5. 3-Wire Control Interface Read Timing Parameters
Rev. 1.0
9
Si4730/31-D50
Table 7. Digital Audio Interface Characteristics
(V = 2.7 to 5.5 V, V = 1.62 to 3.6 V, TA = –20 to 85 °C)
A
D
Parameter
Symbol Test Condition
Min
26
10
10
5
Typ
—
Max
1000
—
Unit
ns
DCLK Cycle Time
t
DCT
DCH
DCLK Pulse Width High
t
—
ns
DCLK Pulse Width Low
t
—
—
ns
DCL
DFS Set-up Time to DCLK Rising Edge
DFS Hold Time from DCLK Rising Edge
t
—
—
ns
SU:DFS
HD:DFS
t
5
—
—
ns
DOUT Propagation Delay from DCLK Falling
Edge
t
0
—
12
ns
PD:DOUT
tDCH
tDCL
DCLK
tDCT
DFS
tHD:DFS
tSU:DFS
DOUT
tPD:OUT
Figure 6. Digital Audio Interface Timing Parameters, I2S Mode
10
Rev. 1.0
Si4730/31-D50
Table 8. FM Receiver Characteristics1,2
(V = 2.7 to 5.5 V, V = 1.62 to 3.6 V, TA = –20 to 85 °C, 76–108 MHz)
A
D
Parameter
Symbol
Test Condition
Min
76
—
Typ
—
Max
108
3.5
—
Unit
MHz
Input Frequency
f
RF
3,4,5
Sensitivity
(S+N)/N = 26 dB
2.2
11
µV EMF
µV EMF
6
RDS Sensitivity
f = 2 kHz,
—
RDS BLER < 5%
6,7
6,7
LNA Input Resistance
3
4
4
5
5
6
k
LNA Input Capacitance
pF
6,8
Input IP3
100
40
35
60
35
72
—
—
15
35
55
—
—
70
45
—
—
105
50
50
70
—
—
—
—
—
—
90
1
dBµV EMF
3,4,6,7
m = 0.3
±200 kHz
±400 kHz
In-band
dB
dB
dB
dB
AM Suppression
Adjacent Channel Selectivity
Alternate Channel Selectivity
Spurious Response Rejection
6
3,4,7
80
—
mV
Audio Output Voltage
RMS
3,7,9
dB
Hz
Audio Output L/R Imbalance
Audio Frequency Response Low
6
–3 dB
–3 dB
—
30
—
—
—
—
0.5
80
54
—
—
6
—
kHz
dB
Audio Frequency Response High
7,9
42
63
58
0.1
75
50
34
30
Audio Stereo Separation
3,4,5,7
dB
Audio Mono S/N
4,5,6,7
dB
Audio Stereo S/N
3,7,9
%
Audio THD
6
De-emphasis Time Constant
FM_DEEMPHASIS = 2
FM_DEEMPHASIS = 1
f = ±400 kHz
µs
µs
3,4,5,6,12,13
Blocking Sensitivity
dBµV
dBµV
f = ±4 MHz
Notes:
1. Additional testing information is available in “AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure.”
Volume = maximum for all tests. Tested at RF = 98.1 MHz.
2. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic,
Layout, and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
3. F
= 1 kHz, 75 µs de-emphasis, MONO = enabled, and L = R unless noted otherwise.
MOD
4. f = 22.5 kHz.
5. B = 300 Hz to 15 kHz, A-weighted.
AF
6. Guaranteed by characterization.
7. V
= 1 mV.
EMF
8. |f – f | > 2 MHz, f = 2 x f – f . AGC is disabled.
2
1
0
1
2
9. f = 75 kHz.
10. At L and R
pins.
OUT
OUT
11. Analog audio output mode.
12. Blocker Amplitude = 100 dBµV
13. Sensitivity measured at (S+N)/N = 26 dB.
14. At temperature (25°C).
Rev. 1.0
11
Si4730/31-D50
Table 8. FM Receiver Characteristics1,2 (Continued)
(V = 2.7 to 5.5 V, V = 1.62 to 3.6 V, TA = –20 to 85 °C, 76–108 MHz)
A
D
Parameter
Symbol
Test Condition
f = ±400 kHz, ±800 kHz
f = ±4 MHz, ±8 MHz
Single-ended
Min
—
Typ
40
35
—
Max
—
Unit
dBµV
dBµV
k
3,4,5,6,12,13
Intermod Sensitivity
—
—
6,10
R
10
—
—
Audio Output Load Resistance
L
6,10
C
Single-ended
—
50
60
pF
Audio Output Load Capacitance
L
6
Seek/Tune Time
RCLK tolerance
= 100 ppm
—
—
ms/channel
6
Powerup Time
From powerdown
—
—
—
110
3
ms
dB
14
RSSI Offset
Input levels of 8 and
60 dBµV at RF Input
–3
Notes:
1. Additional testing information is available in “AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure.”
Volume = maximum for all tests. Tested at RF = 98.1 MHz.
2. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic,
Layout, and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
3. F
= 1 kHz, 75 µs de-emphasis, MONO = enabled, and L = R unless noted otherwise.
MOD
4. f = 22.5 kHz.
5. B = 300 Hz to 15 kHz, A-weighted.
AF
6. Guaranteed by characterization.
7. V
= 1 mV.
EMF
8. |f – f | > 2 MHz, f = 2 x f – f . AGC is disabled.
2
1
0
1
2
9. f = 75 kHz.
10. At L and R
pins.
OUT
OUT
11. Analog audio output mode.
12. Blocker Amplitude = 100 dBµV
13. Sensitivity measured at (S+N)/N = 26 dB.
14. At temperature (25°C).
12
Rev. 1.0
Si4730/31-D50
Table 9. 64–75.9 MHz Input Frequency FM Receiver Characteristics1,2,6
(V = 2.7 to 5.5 V, V = 1.62 to 3.6 V, TA = –20 to 85 °C)
A
D
Parameter
Symbol
Test Condition
Min
64
—
3
Typ
—
Max
75.9
—
5
Unit
MHz
µV EMF
k
Input Frequency
f
RF
3,4,5
Sensitivity
(S+N)/N = 26 dB
3.5
4
7
LNA Input Resistance
7
LNA Input Capacitance
4
5
6
pF
8
Input IP3
—
—
—
—
72
—
—
15
—
—
70
45
10
—
—
105
50
50
70
80
—
—
—
—
—
90
1
dBµV EMF
dB
3,4,7
m = 0.3
±200 kHz
±400 kHz
AM Suppression
dB
Adjacent Channel Selectivity
Alternate Channel Selectivity
dB
3,4,7
mV
Audio Output Voltage
RMS
3,7,9
dB
Audio Output L/R Imbalance
–3 dB
–3 dB
—
30
—
—
—
80
54
—
50
60
Hz
Audio Frequency Response Low
Audio Frequency Response High
—
kHz
3,4,5,7,10
63
0.1
75
50
—
dB
Audio Mono S/N
3,7,9
%
Audio THD
De-emphasis Time Constant
FM_DEEMPHASIS = 2
FM_DEEMPHASIS = 1
Single-ended
µs
µs
k
10
R
Audio Output Load Resistance
L
L
10
C
Single-ended
—
pF
Audio Output Load Capacitance
Seek/Tune Time
RCLK tolerance
= 100 ppm
—
ms/channel
Powerup Time
From powerdown
—
—
—
110
3
ms
dB
11
RSSI Offset
Input levels of 8 and
60 dBµV EMF
–3
Notes:
1. Additional testing information is available in “AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure.”
Volume = maximum for all tests. Tested at RF = 98.1 MHz.
2. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic,
Layout, and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
3. F
= 1 kHz, 75 µs de-emphasis, MONO = enabled, and L = R unless noted otherwise.
MOD
4. f = 22.5 kHz.
5. B = 300 Hz to 15 kHz, A-weighted.
AF
6. Guaranteed by characterization.
7. V
= 1 mV.
EMF
8. |f – f | > 2 MHz, f = 2 x f – f . AGC is disabled.
2
1
0
1
2
9. f = 75 kHz.
10. At L and R
pins.
OUT
OUT
11. At temperature (25 °C).
Rev. 1.0
13
Si4730/31-D50
Table 10. AM Receiver Characteristics1,2
(V = 2.7 to 5.5 V, V = 1.62 to 3.6 V, TA = –20 to 85 °C)
A
D
Parameter
Symbol
Test Condition
Min
520
—
Typ
—
Max
1710
35
Unit
kHz
Input Frequency
f
RF
3,5,6
Sensitivity
(S+N)/N = 26 dB
THD < 8%
25
300
40
60
60
0.1
—
µV EMF
6,7
Large Signal Voltage Handling
—
—
mV
RMS
RMS
6
Power Supply Rejection Ratio
∆V = 100 mVRMS, 100 Hz
—
—
dB
A
3,8
Audio Output Voltage
54
67
mV
3,5,8
Audio S/N
50
—
dB
3,8
Audio THD
—
0.5
450
110
%
6,9
Antenna Inductance
180
—
µH
ms
6
Powerup Time
From powerdown
—
Notes:
1. Additional testing information is available in “AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure.”
Volume = maximum for all tests. Tested at RF = 520 kHz.
2. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic,
Layout, and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
3. FMOD = 1 kHz, 30% modulation, 2 kHz channel filter.
4. Analog audio output mode.
5. B = 300 Hz to 15 kHz, A-weighted.
AF
6. Guaranteed by characterization.
7. See “AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure” for evaluation method.
8. V = 5 mVrms.
IN
9. Stray capacitance on antenna and board must be < 10 pF to achieve full tuning range at higher inductance levels.
14
Rev. 1.0
Si4730/31-D50
Table 11. Reference Clock and Crystal Characteristics
(V = 2.7 to 5.5 V, V = 1.62 to 3.6 V, TA = –20 to 85 °C)
A
D
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Reference Clock
1
RCLK Supported Frequencies
31.130
–100
1
32.768
—
40,000
100
kHz
2
RCLK Frequency Tolerance
ppm
REFCLK_PRESCALE
REFCLK
—
4095
31.130
32.768
34.406
kHz
Crystal Oscillator
Crystal Oscillator Frequency
—
–100
—
32.768
—
—
100
3.5
—
kHz
ppm
pF
2
Crystal Frequency Tolerance
Board Capacitance
ESR
—
—
40
C Single-ended
—
12
—
pF
L
Notes:
1. The Si4730/31 divides the RCLK input by REFCLK_PRESCALE to obtain REFCLK. There are some RCLK
frequencies between 31.130 kHz and 40 MHz that are not supported. For more details, see Table 6 of “AN332: Si47xx
Programming Guide”.
2. A frequency tolerance of ±50 ppm is required for FM seek/tune using 50 kHz channel spacing.
Rev. 1.0
15
Si4730/31-D50
2. Typical Application Schematic
Optional: Digital Audio Out
OPMODE: 0xB0, 0xB5
C9
GPO1
GPO2/INT
R3
R2
R1
GPO3/DCLK
DFS
DOUT
1
15
NC
DOUT
C2
C3
2
3
4
5
14
FM Antenna
FMI
LOUT
LOUT
13
RFGND
AMI
ROUT
ROUT
Si473x
12
L1
GND
D50
2.7 to 5.5 V
C1
11
RSTB
VA
VA
1.62 to 3.6 V
C4
VD
RSTB
RCLK
SDIO
SCLK
SENB
Optional: AM Air Loop Antenna
L2
GPO3
RCLK
T1
C3
X1
1
3
AMI
RFGND
C6
C5
Optional: For Crystal OSC
Notes:
1. Place C1 close to V pin.
A
2. All grounds connect directly to GND plane on PCB.
3. Pins 1 and 20 are no connects, leave floating.
4. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic,
Layout, and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
5. Pin 2 connects to the FM antenna interface, and pin 4 connects to the AM antenna interface.
6. Place Si4730/31 as close as possible to antenna and keep the FMI and AMI traces as short as possible.
16
Rev. 1.0
Si4730/31-D50
3. Bill of Materials
Table 12. Si4730/31-D50 Bill of Materials
Value/Description
Component
Supplier
Murata
C1
C2
C3
C4
L1
Supply bypass capacitor, 22 nF, ±20%, Z5U/X7R
Coupling capacitor, 1 nF, ±20%, Z5U/X7R
Murata
Coupling capacitor, 0.47 μF, ±20%, Z5U/X7R
Supply bypass capacitor, 100 nF, 10%, Z5U/X7R
Ferrite loop stick, 180–450 μH
Murata
Murata
Jiaxin
U1
R1
Si4730/31 AM/FM Radio Tuner
Silicon Laboratories
Venkel
Resistor, 600
(Optional for digital audio)
R2
R3
Resistor, 2 k
(Optional for digital audio)
Venkel
Venkel
Resistor, 2 k
(Optional for digital audio)
C5, C6
C9
Crystal load capacitors, 22 pF, ±5%, COG
(Optional for crystal oscillator option)
Venkel
Noise mitigating capacitor, 2~5 pF
(Optional for digital audio)
Murata
L2
Air Loop, 10–20 μH
Jiaxin
(Optional for AM Input)
T1
Transformer, 1:5 turns ratio
(Optional for AM Input)
Jiaxin, UMEC
Epson
X1
32.768 kHz crystal
(Optional for crystal oscillator option)
Rev. 1.0
17
Si4730/31-D50
4. Functional Description
4.1. Overview
Si473x
AMI
RFGND
DOUT
RDS
(Si4731)
AM
LNA
AGC
DIGITAL
AUDIO
ANT
DFS
GPO/DCLK
LOW-IF
ADC
ADC
DAC
DAC
ROUT
LOUT
FM
ANT
LNA
AGC
DSP
FMI
2.7– 5.5 V
VA
CONTROL
INTERFACE
LDO
AFC
VD
1.62–3.6 V
GND
Figure 7. Functional Block Diagram
The Si4730/31-D50 is Silicon Labs’ fourth generation fidelity, optimal performance, and design flexibility. The
fully integrated, 100% CMOS AM/FM radio receiver IC. chip provides excellent pilot rejection, selectivity, and
Offering unmatched integration and PCB space unmatched audio performance, and offers both the
savings, the Si4730/31 requires only two external manufacturer
components and less than 15 mm of board area, programmability and flexibility in the listening
excluding the antenna inputs. The Si4730/31 AM/FM experience.
and
the
end-user
extensive
2
radio provides the space savings and low power
consumption necessary for portable devices while
European Radio Data System (RDS) and the North
delivering the high performance and design simplicity
The Si4731 incorporates a digital processor for the
American Radio Broadcast Data System (RBDS)
including all required symbol decoding, block
desired for all AM/FM solutions.
Leveraging Silicon Laboratories' proven and patented synchronization, error detection, and error correction
Si4700/01 FM tuner's digital low intermediate frequency functions. Using this feature, the Si4731 enables
(low-IF) receiver architecture, the Si4730/31 delivers broadcast data such as station identification and song
superior RF performance and interference rejection in name to be displayed to the user.
both AM and FM bands. The high integration and
4.2. Operating Modes
complete system production test simplifies design-in,
increases
manufacturability.
system
quality,
and
improves The Si4730/31 operates in either an FM receive or an
AM receive mode. In FM mode, radio signals are
received on FMI and processed by the FM front-end
The Si4730/31 is a feature-rich solution that includes
advanced seek algorithms, soft mute, auto-calibrated
digital tuning, FM stereo processing, and advanced
audio processing.
circuitry. In AM mode, radio signals are received on AMI
and processed by the AM front-end circuitry. In addition
to the receiver mode, there is an audio output mode to
choose between an analog and/or digital audio output.
In the analog audio output mode, ROUT and LOUT are
used for the audio output pins. In the digital audio mode,
DOUT, DFS, and DCLK pins are used. Concurrent
analog/digital audio output mode is also available
requiring all five pins.
In addition, the Si4730/31 provides analog and digital
audio outputs and a programmable reference clock. The
device supports I C-compatible 2-wire control interface,
SPI, and a Si4700/01 backwards-compatible 3-wire
control interface.
2
The Si4730/31 utilizes digital processing to achieve high
18
Rev. 1.0
Si4730/31-D50
4.3. FM Receiver
4.5. Digital Audio Interface
The Si4730/31 FM receiver is based on the proven The digital audio interface operates in slave mode and
Si4700/01 FM tuner. The receiver uses a digital low-IF supports a variety of MSB-first audio data formats
2
architecture allowing the elimination of external including I S and left-justified modes. The interface has
components and factory adjustments. The Si4730/31 three pins: digital data input (DIN), digital frame
integrates a low noise amplifier (LNA) supporting the synchronization input (DFS), and
a
digital bit
worldwide FM broadcast band (64 to 108 MHz). An synchronization input clock (DCLK). The Si473x
AGC circuit controls the gain of the LNA to optimize supports a number of industry-standard sampling rates
sensitivity and rejection of strong interferers. An image- including 32, 40, 44.1, and 48 kHz. The digital audio
reject mixer downconverts the RF signal to low-IF. The interface enables low-power operation by eliminating
quadrature mixer output is amplified, filtered, and the need for redundant DACs and ADCs on the audio
digitized with high resolution analog-to-digital baseband processor.
converters (ADCs). This advanced architecture allows
4.5.1. Audio Data Formats
the Si4730/31 to perform channel selection, FM
The digital audio interface operates in slave mode and
demodulation, and stereo audio processing to achieve
supports three different audio data formats:
superior performance compared to traditional analog
2
I S
architectures.
Left-Justified
DSP Mode
4.4. AM Receiver
The highly-integrated Si4730/31 supports worldwide AM
band reception from 520 to 1710 kHz using a digital
low-IF architecture with a minimum number of external
components and no manual alignment required. This
digital low-IF architecture allows for high-precision
filtering offering excellent selectivity and SNR with
minimum variation across the AM band. The DSP also
provides adjustable channel step sizes in 1 kHz
increments, AM demodulation, soft mute, seven
different channel bandwidth filters, and additional
features, such as a programmable automatic volume
control (AVC) maximum gain allowing users to adjust
the level of background noise.
2
In I S mode, by default the MSB is captured on the
second rising edge of DCLK following each DFS
transition. The remaining bits of the word are sent in
order, down to the LSB. The left channel is transferred
first when the DFS is low, and the right channel is
transferred when the DFS is high.
In left-justified mode, by default the MSB is captured on
the first rising edge of DCLK following each DFS
transition. The remaining bits of the word are sent in
order, down to the LSB. The left channel is transferred
first when the DFS is high, and the right channel is
transferred when the DFS is low.
In DSP mode, the DFS becomes a pulse with a width of
1DCLK period. The left channel is transferred first,
followed right away by the right channel. There are two
options in transferring the digital audio data in DSP
mode: the MSB of the left channel can be transferred on
the first rising edge of DCLK following the DFS pulse or
on the second rising edge.
Similar to the FM receiver, the integrated LNA and AGC
optimize sensitivity and rejection of strong interferers
allowing better reception of weak stations.
The Si4730/31 provides highly-accurate digital AM
tuning without factory adjustments. To offer maximum
flexibility, the receiver supports a wide range of ferrite
loop sticks from 180–450 µH. An air loop antenna is
supported by using a transformer to increase the
effective inductance from the air loop. Using a 1:5 turn
ratio inductor, the inductance is increased by 25 times
and easily supports all typical AM air loop antennas
which generally vary between 10 and 20 µH.
In all audio formats, depending on the word size, DCLK
frequency, and sample rates, there may be unused
DCLK cycles after the LSB of each word before the next
DFS transition and MSB of the next word. If preferred,
the user can configure the MSB to be captured on the
falling edge of DCLK via properties. The number of
audio bits can be configured for 8, 16, 20, or 24 bits.
4.5.2. Audio Sample Rates
The device supports a number of industry-standard
sampling rates including 32, 40, 44.1, and 48 kHz. The
digital audio interface enables low-power operation by
eliminating the need for redundant DACs on the audio
baseband processor.
Rev. 1.0
19
Si4730/31-D50
INVERTED
(OFALL = 1)
DCLK
(OFALL = 0)
DCLK
DFS
LEFT CHANNEL
I2S
RIGHT CHANNEL
(OMODE = 0000)
1 DCLK
1 DCLK
n-2
DOUT
1
2
3
n-1
n
n-2
n-1
1
2
3
n
MSB
LSB
MSB
LSB
Figure 8. I2S Digital Audio Format
INVERTED
DCLK
(OFALL = 1)
(OFALL = 0)
DCLK
DFS
LEFT CHANNEL
RIGHT CHANNEL
n-2
Left-Justified
(OMODE = 0110)
DOUT
1
2
3
n-2
n-1
n
n-1
n
1
2
3
MSB
LSB
MSB
LSB
Figure 9. Left-Justified Digital Audio Format
(OFALL = 0)
DCLK
DFS
RIGHT CHANNEL
n-2
LEFT CHANNEL
n-2
DOUT
1
2
3
2
n-1
n
(OMODE = 1100)
(OMODE = 1000)
1
2
3
2
n-1
n
(MSB at 1st rising edge)
MSB
LSB
MSB
LSB
LEFT CHANNEL
n-2
1 DCLK
RIGHT CHANNEL
n-2
DOUT
1
3
n-1
n
1
3
n-1
n
(MSB at 2nd rising edge)
MSB
LSB
MSB
LSB
Figure 10. DSP Digital Audio Format
20
Rev. 1.0
Si4730/31-D50
4.6. Stereo Audio Processing
4.7. Received Signal Qualifiers
The output of the FM demodulator is a stereo The quality of a tuned signal can vary depending on
multiplexed (MPX) signal. The MPX standard was many factors including environmental conditions, time of
developed in 1961, and is used worldwide. Today's day, and position of the antenna. To adequately manage
MPX signal format consists of left + right (L+R) audio, the audio output and avoid unpleasant audible effects to
left – right (L–R) audio, a 19 kHz pilot tone, and the end-user, the Si473x monitors and provides
RDS/RBDS data as shown in Figure 11 below.
indicators of the signal quality. The Si473x monitors
signal quality metrics including RSSI, SNR, and
multipath interference on FM signals. These metrics are
used to optimize audio and signal processing and are
also reported to the host processor. The signal
processing algorithms can use either Silicon Labs'
optimized settings (recommended) or be customized to
modify performance.
Mono Audio
Left + Right
Stereo
Pilot
Stereo Audio
Left - Right
RDS/
RBDS
4.8. De-emphasis
0
15 19 23
38
53 57
Frequency (kHz)
Pre-emphasis and de-emphasis is a technique used by
FM broadcasters to improve the signal-to-noise ratio of
FM receivers by reducing the effects of high-frequency
interference and noise. When the FM signal is
Figure 11. MPX Signal Spectrum
4.6.1. Stereo Decoder
The Si4730/31's
integrated
stereo
decoder
transmitted,
a
pre-emphasis filter is applied to
automatically decodes the MPX signal using DSP
techniques. The 0 to 15 kHz (L+R) signal is the mono
output of the FM tuner. Stereo is generated from the
(L+R), (L–R), and a 19 kHz pilot tone. The pilot tone is
used as a reference to recover the (L–R) signal. Output
left and right channels are obtained by adding and
subtracting the (L+R) and (L–R) signals respectively.
The Si4731 uses frequency information from the 19 kHz
stereo pilot to recover the 57 kHz RDS/RBDS signal.
accentuate the high audio frequencies. The Si4730/31
incorporates a de-emphasis filter which attenuates high
frequencies to restore a flat frequency response. Two
time constants are used in various regions. The de-
emphasis time constant is programmable to 50 or
75 µs.
4.9. Volume Control
The audio output may be muted. Volume is adjusted
digitally by the RX_VOLUME property.
4.6.2. Stereo-Mono Blending
Adaptive noise suppression is employed to gradually
combine the stereo left and right audio channels to a
mono (L+R) audio signal as the signal quality degrades
to maintain optimum sound fidelity under varying
reception conditions. Three metrics, received signal
strength indicator (RSSI), signal-to-noise ratio (SNR),
4.10. Stereo DAC
High-fidelity stereo digital-to-analog converters (DACs)
drive analog audio signals onto the LOUT and ROUT
pins. The audio output may be muted.
4.11. Soft Mute
and
multipath
interference,
are
monitored
The soft mute feature is available to attenuate the audio
outputs and minimize audible noise in very weak signal
conditions. The soft mute feature is triggered by the
SNR metric. The SNR threshold for activating soft mute
is programmable, as are soft mute attenuation levels
and attack and release rates.
simultaneously in forcing a blend from stereo to mono.
The metric which reflects the minimum signal quality
takes precedence and the signal is blended
appropriately.
All three metrics have programmable stereo/mono
thresholds and attack/release rates detailed in “AN332:
Si47xx Programming Guide.” If a metric falls below its
mono threshold, the signal is blended from stereo to full
mono. If all metrics are above their respective stereo
thresholds, then no action is taken to blend the signal. If
a metric falls between its mono and stereo thresholds,
then the signal is blended to the level proportional to the
metric’s value between its mono and stereo thresholds,
with an associated attack and release rate.
Rev. 1.0
21
Si4730/31-D50
The Si4730/31 uses RSSI, SNR, and AFC to qualify
stations. Most of these variables have programmable
thresholds for modifying the seek function according to
customer needs.
4.12. FM Hi-Cut Control
Hi-cut control is employed on audio outputs with
degradation of the signal due to low SNR and/or
multipath interference. Two metrics, SNR and multipath
interference, are monitored concurrently in forcing hi-cut
of the audio outputs. Programmable minimum and
maximum thresholds are available for both metrics. The
transition frequency for hi-cut is also programmable with
up to seven hi-cut filter settings. Attack and release
rates for hi-cut are programmable for both metrics from
a range of 2 ms to 64 s. The level of hi-cut applied can
be monitored with the FM_RSQ_STATUS command.
Hi-cut can be disabled by setting the hi-cut filter to audio
bandwidth of 15 kHz.
RSSI is employed first to screen all possible candidate
stations. SNR and AFC are subsequently used in
screening the RSSI qualified stations. The more
thresholds the system engages, the higher the
confidence that any found stations will indeed be valid
broadcast stations. The Si4730/31 defaults set RSSI to
a mid-level threshold and add an SNR threshold set to a
level delivering acceptable audio performance. This
trade-off will eliminate very low RSSI stations while
keeping the seek time to acceptable levels. Generally,
the time to auto-scan and store valid channels for an
entire FM band with all thresholds engaged is very short
depending on the band content. Seek is initiated using
the FM_SEEK_START command. The RSSI, SNR, and
AFC threshold settings are adjustable using properties.
4.13. RDS/RBDS Processor (Si4731 Only)
The Si4731 implements an RDS/RBDS* processor for
symbol decoding, block synchronization, error
detection, and error correction.
The Si4731 device is user configurable and provides an
optional interrupt when RDS is synchronized, loses
synchronization, and/or the user configurable RDS
FIFO threshold has been met.
4.16. Reference Clock
The Si4730/31 reference clock is programmable,
supporting RCLK frequencies listed in Table 11,
“Reference Clock and Crystal Characteristics,” on
page 15. Refer to Table 3, “DC Characteristics,” on
page 5 for switching voltage levels and Table 11 for
frequency tolerance information.
The Si4731 reports RDS decoder synchronization
status and detailed bit errors in the information word for
each RDS block with the FM_RDS_STATUS command.
The range of reportable block errors is 0, 1–2, 3–5, or
6+. More than six errors indicates that the
corresponding block information word contains six or
more non-correctable errors or that the block checkword
contains errors.
An onboard crystal oscillator is available to generate the
32.768 kHz reference when an external crystal and load
capacitors are provided. Refer to "2. Typical Application
Schematic" on page 16. This mode is enabled using the
POWER_UP command. Refer to “AN332: Si47xx
Programming Guide”.
*Note: RDS/RBDS is referred to only as RDS throughout the
remainder of this document.
The Si4730/31 performance may be affected by data
activity on the SDIO bus when using the integrated
4.14. Tuning
The tuning frequency is directly programmed using the internal oscillator. SDIO activity results from polling the
FM_TUNE_FREQ and AM_TUNE_FREQ commands. tuner for status or communicating with other devices
The Si4730/31 supports channel spacing steps of that share the SDIO bus. If there is SDIO bus activity
10 kHz in FM mode and 1 kHz in AM mode.
while the Si4730/31 is performing the seek/tune
function, the crystal oscillator may experience jitter,
which may result in mistunes, false stops, and/or lower
4.15. Seek
The Si4730/31 seek functionality is performed SNR.
completely on-chip and will search up or down the
For best seek/tune results, Silicon Laboratories
selected frequency band for a valid channel. A valid
channel is qualified according to series of
recommends that all SDIO data traffic be suspended
during Si4730/31 seek and tune operations. This is
achieved by keeping the bus quiet for all other devices
on the bus, and delaying tuner polling until the tune or
seek operation is complete. The seek/tune complete
(STC) interrupt should be used instead of polling to
determine when a seek/tune operation is complete.
a
programmable signal indicators and thresholds. The
seek function can be made to stop at the band edge and
provide an interrupt, or wrap the band and continue
seeking until arriving at the original departure frequency.
The device sets interrupts with found valid stations or, if
the seek results in zero found valid stations, the device
indicates failure and again sets an interrupt. Refer to
“AN332: Si47xx Programming Guide”.
22
Rev. 1.0
Si4730/31-D50
For write operations, the user then sends an 8-bit data
byte on SDIO, which is captured by the device on rising
edges of SCLK. The Si4730/31 acknowledges each
data byte by driving SDIO low for one cycle, on the next
falling edge of SCLK. The user may write up to 8 data
bytes in a single 2-wire transaction. The first byte is a
command, and the next seven bytes are arguments.
4.17. Control Interface
A serial port slave interface is provided, which allows an
external controller to send commands to the Si4730/31
and receive responses from the device. The serial port
can operate in two bus modes: 2-wire mode and 3-wire
mode. The Si4730/31 selects the bus mode by sampling
the state of the GPO1 and GPO2 pins on the rising
edge of RST. The GPO1 pin includes an internal pull-up
resistor, which is connected while RST is low, and the
GPO2 pin includes an internal pull-down resistor, which
is connected while RST is low. Therefore, it is only
necessary for the user to actively drive pins which differ
from these states. See Table 13.
For read operations, after the Si4730/31 has
acknowledged the control byte, it will drive an 8-bit data
byte on SDIO, changing the state of SDIO on the falling
edge of SCLK. The user acknowledges each data byte
by driving SDIO low for one cycle, on the next falling
edge of SCLK. If a data byte is not acknowledged, the
transaction will end. The user may read up to 16 data
bytes in a single 2-wire transaction. These bytes contain
the response data from the Si4730/31. A 2-wire
transaction ends with the STOP condition, which occurs
when SDIO rises while SCLK is high.
Table 13. Bus Mode Select on Rising Edge of
RST
Bus Mode
2-Wire
GPO1
1
GPO2
0
0
For details on timing specifications and diagrams, refer
to Table 5, “2-Wire Control Interface Characteristics” on
page 7; Figure 2, “2-Wire Control Interface Read and
Write Timing Parameters,” on page 8, and Figure 3, “2-
Wire Control Interface Read and Write Timing Diagram,”
on page 8.
3-Wire
0 (must drive)
After the rising edge of RST, the pins GPO1 and GPO2
are used as general purpose output (O) pins, as
described in Section “4.18. GPO Outputs”. In any bus
mode, commands may only be sent after V and V
supplies are applied.
IO
DD
4.17.2. 3-Wire Control Interface Mode
When selecting 3-wire mode, the user must ensure that
a rising edge of SCLK does not occur within 300 ns
before the rising edge of RST.
In any bus mode, before sending a command or reading
a response, the user must first read the status byte to
ensure that the device is ready (CTS bit is high).
The 3-wire bus mode uses the SCLK, SDIO, and SEN_
pins. A transaction begins when the user drives SEN
low. Next, the user drives a 9-bit control word on SDIO,
which is captured by the device on rising edges of
SCLK. The control word consists of a 9-bit device
address (A7:A5 = 101b), a read/write bit (read = 1, write
= 0), and a 5-bit register address (A4:A0).
4.17.1. 2-Wire Control Interface Mode
When selecting 2-wire mode, the user must ensure that
SCLK is high during the rising edge of RST, and stays
high until after the first start condition. Also, a start
condition must not occur within 300 ns before the rising
edge of RST.
The 2-wire bus mode uses only the SCLK and SDIO
pins for signaling. A transaction begins with the START
condition, which occurs when SDIO falls while SCLK is
high. Next, the user drives an 8-bit control word serially
on SDIO, which is captured by the device on rising
edges of SCLK. The control word consists of a 7-bit
device address, followed by a read/write bit (read = 1,
write = 0). The Si4730/31 acknowledges the control
word by driving SDIO low on the next falling edge of
SCLK.
For write operations, the control word is followed by a
16-bit data word, which is captured by the device on
rising edges of SCLK.
For read operations, the control word is followed by a
delay of one-half SCLK cycle for bus turn-around. Next,
the Si4730/31 will drive the 16-bit read data word
serially on SDIO, changing the state of SDIO on each
rising edge of SCLK.
A transaction ends when the user sets SEN high, then
pulses SCLK high and low one final time. SCLK may
either stop or continue to toggle while SEN is high.
Although the Si4730/31 will respond to only a single
device address, this address can be changed with the
SEN pin (note that the SEN pin is not used for signaling
in 2-wire mode). Refer to “AN332: Si47xx Programming
Guide”
In 3-wire mode, commands are sent by first writing each
argument to register(s) 0xA1–0xA3, then writing the
command word to register 0xA0. A response is
retrieved by reading registers 0xA8–0xAF.
Rev. 1.0
23
Si4730/31-D50
For details on timing specifications and diagrams, refer
to Table 6, “3-Wire Control Interface Characteristics,” on
page 9; Figure 4, “3-Wire Control Interface Write Timing
Parameters,” on page 9, and Figure 5, “3-Wire Control
Interface Read Timing Parameters,” on page 9.
4.21. Programming with Commands
To ease development time and offer maximum
customization, the Si4730/31 provides a simple yet
powerful software interface to program the receiver. The
device is programmed using commands, arguments,
properties, and responses.
4.18. GPO Outputs
To perform an action, the user writes a command byte
and associated arguments, causing the chip to execute
the given command. Commands control an action such
as powerup the device, shut down the device, or tune to
a station. Arguments are specific to a given command
and are used to modify the command.
The Si4730/31 provides three general-purpose output
pins. The GPO pins can be configured to output a
constant low, constant high, or high-impedance. The
GPO pins can be reconfigured as specialized functions.
GPO2/INT can be configured to provide interrupts and
GPO3 can be configured to provide external crystal
support or as DCLK in digital audio output mode.
Properties are a special command argument used to
modify the default chip operation and are generally
configured immediately after powerup. Examples of
4.19. Firmware Upgrades
The Si4730/31 contains on-chip program RAM to properties are de-emphasis level, RSSI seek threshold,
accommodate minor changes to the firmware. This and soft mute attenuation threshold.
allows Silicon Labs to provide future firmware updates
to optimize the characteristics of new radio designs and
echoed after a command and associated arguments are
those already deployed in the field.
Responses provide the user information and are
issued. All commands provide a 1-byte status update,
indicating interrupt and clear-to-send status information.
4.20. Reset, Powerup, and Powerdown
For a detailed description of the commands and
Setting the RST pin low will disable analog and digital
properties for the Si4730/31, see “AN332: Si47xx
circuitry, reset the registers to their default settings, and
Programming Guide.”
disable the bus. Setting the RST pin high will bring the
device out of reset.
A powerdown mode is available to reduce power
consumption when the part is idle. Putting the device in
powerdown mode will disable analog and digital circuitry
while keeping the bus active.
24
Rev. 1.0
Si4730/31-D50
5. Pin Descriptions: Si4730/31-GM
20 19 18 17
NC
1
16
FMI 2
RFGND 3
AMI 4
15 DOUT
14 LOUT
13 ROUT
12 GND
11 VA
GND
PAD
RST 5
6
7
8
9
10
Pin Number(s)
Name
NC
Description
1, 20
No connect. Leave floating.
2
FMI
FM RF inputs. FMI should be connected to the antenna trace.
RF ground. Connect to ground plane on PCB.
AM RF input. AMI should be connected to the AM antenna.
Device reset (active low) input.
3
RFGND
AMI
4
5
RST
6
SEN
Serial enable input (active low).
7
SCLK
SDIO
RCLK
Serial clock input.
8
Serial data input/output.
9
External reference oscillator input.
10
V
Digital and I/O supply voltage.
D
11
V
Analog supply voltage. May be connected directly to battery.
Ground. Connect to ground plane on PCB.
Right audio line output in analog output mode.
Left audio line output in analog output mode.
Digital output data in digital output mode.
Digital frame synchronization input in digital output mode.
A
12, GND PAD
GND
ROUT
LOUT
DOUT
DFS
13
14
15
16
17
GPO3/DCLK General purpose output, crystal oscillator, or digital bit synchronous clock input
in digital output mode.
18
19
GPO2/INT
GPO1
General purpose output or interrupt pin.
General purpose output.
Rev. 1.0
25
Si4730/31-D50
6. Ordering Guide
Part Number*
Description
Package
Type
Operating
Temperature/Voltage
Si4730-D50-GM AM/FM Broadcast Radio Receiver
QFN
Pb-free
–20 to 85 °C
2.7 to 5.5 V
Si4731-D50-GM AM/FM Broadcast Radio Receiver with
RDS/RBDS
QFN
Pb-free
–20 to 85 °C
2.7 to 5.5 V
*Note: Add an “(R)” at the end of the device part number to denote tape and reel option.
26
Rev. 1.0
Si4730/31-D50
7. Package Markings (Top Marks)
7.1. Si4730/31 Top Mark
3050
DTTT
3150
DTTT
YWW
YWW
7.2. Top Mark Explanation
Mark Method:
YAG Laser
Line 1 Marking:
Part Number
30 = Si4730, 31 = Si4731.
Firmware Revision
Die Revision
50 = Firmware Revision 5.0.
D = Revision D Die.
Line 2 Marking:
Line 3 Marking:
TTT = Internal Code
Internal tracking code.
Circle = 0.5 mm Diameter Pin 1 Identifier.
(Bottom-Left Justified)
Y = Year
Assigned by the Assembly House. Corresponds to the last
significant digit of the year and work week of the mold date.
WW = Workweek
Rev. 1.0
27
Si4730/31-D50
8. Package Outline: Si4730/31
Figure 12 illustrates the package details for the Si4730/31. Table 14 lists the values for the dimensions shown in
the illustration.
Figure 12. 20-Pin Quad Flat No-Lead (QFN)
Table 14. Package Dimensions
Symbol
Millimeters
Nom
Symbol
Millimeters
Nom
Min
Max
Min
Max
A
A1
b
0.50
0.00
0.20
0.27
0.55
0.02
0.60
0.05
0.30
0.37
f
2.53 BSC
L
0.35
0.00
—
0.40
—
0.45
0.10
0.05
0.05
0.08
0.10
0.10
0.25
L1
c
0.32
aaa
bbb
ccc
ddd
eee
—
D
3.00 BSC
1.70
—
—
D2
e
1.65
1.75
—
—
0.50 BSC
3.00 BSC
1.70
—
—
E
—
—
E2
1.65
1.75
Notes:
1. All dimensions are shown in millimeters (mm) unless otherwise noted.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
28
Rev. 1.0
Si4730/31-D50
9. PCB Land Pattern: Si4730/31
Figure 13 illustrates the PCB land pattern details for the Si4730/31-D50-GM QFN. Table 15 lists the values for the
dimensions shown in the illustration.
Figure 13. PCB Land Pattern
Rev. 1.0
29
Si4730/31-D50
Table 15. PCB Land Pattern Dimensions
Symbol
Millimeters
Min Max
2.71 REF
1.60 1.80
Symbol
Millimeters
Min
Max
D
D2
e
GE
W
2.10
—
—
0.34
0.28
0.50 BSC
2.71 REF
X
—
E
Y
0.61 REF
E2
f
1.60
2.53 BSC
2.10
1.80
ZE
ZD
—
—
3.31
3.31
GD
—
Notes: General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on IPC-SM-782 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material
Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
Notes: Solder Mask Design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the
solder mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Notes: Stencil Design
1. A stainless steel, laser-cut, and electro-polished stencil with trapezoidal walls should
be used to assure good solder paste release.
2. The stencil thickness should be 0.125mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.
4. A 1.45 x 1.45 mm square aperture should be used for the center pad. This provides
approximately 70% solder paste coverage on the pad, which is optimum to assure
correct component stand-off.
Notes: Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification
for Small Body Components.
30
Rev. 1.0
Si4730/31-D50
10. Additional Reference Resources
Contact your local sales representatives for more information or to obtain copies of the following references:
AN332: Si47xx Programming Guide
AN383: Si47xx Antenna, Schematic, Layout, and Design Guidelines
AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure
Si47xx EVB User’s Guide
Customer Support Site: www.silabs.com
This site contains all application notes, evaluation board schematics and layouts, and evaluation software.
Please visit the Silicon Labs Technical Support web page:
https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support
request.
Rev. 1.0
31
Si4730/31-D50
DOCUMENT CHANGE LIST:
Revision 0.2 to Revision 1.0
Updated functional block diagram.
Updated specification tables.
Updated “2. Typical Application Schematic”.
Updated“Table 3. DC Characteristics”.
Added Section “4.6. Stereo Audio Processing”.
32
Rev. 1.0
Si4730/31-D50
NOTES:
Rev. 1.0
33
Si4730/31-D50
CONTACT INFORMATION
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Austin, TX 78701
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Email: FMinfo@silabs.com
Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep-
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Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
34
Rev. 1.0
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