SI4731-B20-GMR [SILICON]
Telecom Circuit, 1-Func, 3 X 3 MM, 0.55 MM HEIGHT, ROHS COMPLIANT, QFN-20;
| 型号： | SI4731-B20-GMR |
| 厂家： | 
SILICON |
| 描述： | Telecom Circuit, 1-Func, 3 X 3 MM, 0.55 MM HEIGHT, ROHS COMPLIANT, QFN-20 电信 电信集成电路 |
| 文件： | 总24页 (文件大小：180K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si473x-B20
BROADCAST MULTI-BAND RADIO RECEIVER
Features
FM band support: 76–108 MHz
AM band support: 520–1710 kHz
SW band support: 2.3–21.85 MHz
(Si4734/35)
LW band support: 153–279 kHz
(Si4734/35)
Adaptive noise suppression
AM/FM digital tuning
EN55020 compliant
No manual alignment necessary
Programmable reference clock
Volume control
Weather band support: 162.4–
162.55 MHz (Si4736/37/38/39)
1050 Hz alert tone detection
(Si4736/37/38/39)
Excellent real-world performance
Freq synthesizer with integrated VCO
Advanced seek tuning
Automatic frequency control (AFC)
Automatic gain control (AGC)
Integrated LDO regulator
Digital FM stereo decoder
Programmable de-emphasis
Programmable soft mute control
RDS/RBDS processor
(Si4731/35/37/39)
Optional digital audio output
(Si4731/35/37/39)
2-wire control interface
2.7 to 5.5 V supply voltage
Firmware upgradeable
Wide range of ferrite loop sticks and
air loop antennas supported
3 x 3 x 0.55 mm 20-pin QFN package
Pb-free/RoHS compliant
Ordering Information:
See page 18.
Pin Assignments
Si473x-GM
(Top View)
Applications
20 19 18 17
NC
FMI
1
16
Table and portable radios
Audio video receivers
Stereos
Mini/micro systems
CD/DVD players
Cellular handsets
Emergency radios
Clock radios
Modules
Mini HiFi
Boom boxes
2
15 DOUT
14 LOUT
13 ROUT
12 GND
11 VDD
RFGND
AMI
3
4
5
GND
PAD
RST
Portable media players
6
7
8
9
10
Si473x Product Selector Guide
Part
FM
AM
RDS
SW/LW
WB
Patents Pending
Si4730
Si4731
Si4734
Si4735
Si4736
Si4737
Si4738
Si4739
76 – 108 MHz
76 – 108 MHz
64 – 108 MHz
64 – 108 MHz
76 – 108 MHz
76 – 108 MHz
76 – 108 MHz
76 – 108 MHz
Notes:
1. Place Si473x as close as
possible to antenna jack and
keep the FMI and AMI traces as
short as possible.
2. Contact your local sales
representatives for more
information or to obtain
application notes.
Rev. 0.5 10/08
Copyright © 2008 by Silicon Laboratories
Si473x-B20
Si473x-B20
2
Rev. 0.5
Si473x-B20
TABLE OF CONTENTS
Section
Page
1. Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
3. Typical AM/FM Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
4. Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
5. Pin Descriptions: Si473x-GM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
7. Package Outline: Si473x QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
8. PCB Land Pattern: Si473x QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
9. Additional Reference Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Rev. 0.5
3
Si473x-B20
1. Product Overview
The Si473x receivers are the industry's first fully-integrated multiband radio receiver ICs from antenna input to
audio output. They require minimal external components with no factory alignment. The Si473x receivers reduce
the receiver footprint by >90% versus traditional AM/FM solutions. The Si473x also offer best-in-class performance
with the most features. The high integration and complete system production test simplifies design-in, increases
system quality, and improves manufacturability.
The Si473x receivers include advanced seek algorithms, adjustable soft mute, auto-calibrated digital tuning, and
FM stereo processing. In addition, the Si473x ICs provide a programmable reference clock and an I2C-compatible
2-wire control interface.
The Si4731/35/37/39 incorporates a digital processor for the European Radio Data System (RDS) and the North
American Radio Broadcast Data System (RBDS), including all required symbol decoding, block synchronization,
error detection, and error correction functions. Using these features, the Si4731/35/37/39 enables broadcast data
such as station identification and song name to be displayed to the end user.
2. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Symbol Test Condition
Min
2.7
1.5
10
Typ
—
Max
5.5
3.6
—
Unit
V
Supply Voltage
V
DD
Interface Supply Voltage
V
—
V
IO
DDRISE
Power Supply Powerup Rise Time
Interface Power Supply Powerup Rise Time
Ambient Temperature
V
—
µs
µs
C
V
10
—
—
IORISE
T
–20
25
85
A
Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at VDD = 3.3 V and 25 C unless otherwise stated. Parameters are tested in production unless
otherwise stated.
4
Rev. 0.5
Si473x-B20
Table 2. Absolute Maximum Ratings1,2
Parameter
Supply Voltage
Symbol
Value
–0.5 to 5.8
–0.5 to 3.9
10
Unit
V
V
DD
Interface Supply Voltage
V
V
IO
IN
3
Input Current
I
mA
V
3
Input Voltage
V
T
–0.3 to (V + 0.3)
IN
IO
Operating Temperature
Storage Temperature
–40 to 95
–55 to 150
0.4
C
C
OP
T
STG
4
RF Input Level
V
PK
Notes:
1. Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation
should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure beyond
recommended operating conditions for extended periods may affect device reliability.
2. The Si473x devices are high-performance RF integrated circuits with certain pins having an ESD rating of < 2 kV
HBM. Handling and assembly of these devices should only be done at ESD-protected workstations.
3. For input pins SCLK, SEN, SDIO, RST, RCLK, DCLK, DFS, GPO1, GPO2, and GPO3.
4. At RF input pins, FMI and AMI.
Rev. 0.5
5
Si473x-B20
Table 3. DC Characteristics
(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
FM Mode
Supply Current
Supply Current
I
I
I
—
—
—
19.2
19.8
19.9
22
23
23
mA
mA
mA
FM
FM
FM
1
Low SNR level
2
RDS Supply Current
WB Mode (Si4736/37/38/39 only)
Supply Current
I
I
—
—
19.2
19.8
22
23
mA
mA
FM
1
Supply Current
Low SNR level
FM
AM Mode (Si4730/31/34/35/36/37 only)
Supply Current
I
—
17.3
20.5
mA
AM
Supplies and Interface
Interface Supply Current
I
—
—
320
10
1
600
20
µA
µA
µA
V
IO
V
V
Powerdown Current
I
DDPD
DD
Powerdown Current
I
SCLK, RCLK inactive
—
10
IO
IOPD
3
High Level Input Voltage
V
0.7 x V
–0.3
–10
—
—
—
—
V
+ 0.3
IO
IH
IO
3
Low Level Input Voltage
V
0.3 x V
10
V
IL
IO
3
High Level Input Current
I
V
= V = 3.6 V
µA
µA
IH
IN
IO
3
Low Level Input Current
I
V
= 0 V,
IN
–10
10
IL
V
= 3.6 V
IO
4
High Level Output Voltage
V
I
= 500 µA
= –500 µA
0.8 x V
—
—
—
—
V
V
OH
OUT
IO
4
Low Level Output Voltage
V
I
0.2 x V
OL
OUT
IO
Notes:
1. LNA is automatically switched to higher current mode for optimum sensitivity in weak signal conditions.
2. Specifications are guaranteed by characterization.
3. For input pins SCLK, SEN, SDIO, RST, RCLK, DCLK, and DFS.
4. For output pins SDIO, DOUT, GPO1, GPO2, and GPO3.
6
Rev. 0.5
Si473x-B20
Table 4. Reset Timing Characteristics1,2
(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol
Min
100
30
Typ
—
Max
—
Unit
µs
RST Pulse Width and GPO1, GPO2/INT Setup to RST
GPO1, GPO2/INT Hold from RST
Important Notes:
t
SRST
t
—
—
ns
HRST
1. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is
high) does not occur within 300 ns before the rising edge of RST.
2. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high until
after the first start condition.
3. If GPO1 and GPO2 are actively driven by the user, then minimum tSRST is only 30 ns. If GPO1 or GPO2 is hi-Z, then
minimum tSRST is 100 µs to provide time for on-chip 1 M devices (active while RST is low) to pull GPO1 high and
GPO2 low.
tHRST
tSRST
70%
30%
RST
70%
30%
GPO1
70%
30%
GPO2/
INT
Figure 1. Reset Timing Parameters for Busmode Select
Rev. 0.5
7
Si473x-B20
Table 5. 2-Wire Control Interface Characteristics1,2,3
(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol Test Condition
Min
0
Typ
—
Max
400
—
Unit
kHz
µs
SCLK Frequency
SCLK Low Time
SCLK High Time
f
SCL
t
1.3
0.6
0.6
—
LOW
t
—
—
µs
HIGH
SCLK Input to SDIO Setup
t
t
—
—
µs
SU:STA
(START)
SCLK Input to SDIO Hold
0.6
—
—
µs
HD:STA
(START)
SDIO Input to SCLK Setup
t
t
100
0
—
—
—
—
900
—
ns
ns
µs
SU:DAT
4,5
SDIO Input to SCLK Hold
HD:DAT
SU:STO
SCLK input to SDIO Setup
t
0.6
(STOP)
STOP to START Time
SDIO Output Fall Time
t
1.3
—
—
—
µs
ns
BUF
t
250
f:OUT
Cb
----------
1pF
20 + 0.1
SDIO Input, SCLK Rise/Fall Time
t
t
—
300
ns
f:IN
Cb
r:IN
----------
1pF
20 + 0.1
SCLK, SDIO Capacitive Loading
Input Filter Pulse Suppression
Notes:
C
—
—
—
—
50
50
pF
ns
b
t
SP
1. When VIO = 0 V, SCLK and SDIO are low impedance.
2. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is
high) does not occur within 300 ns before the rising edge of RST.
3. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high
until after the first start condition.
4. The Si473x delays SDIO by a minimum of 300 ns from the VIH threshold of SCLK to comply with the minimum tHD:DAT
specification.
5. The maximum tHD:DAT has only to be met when fSCL = 400 kHz. At frequencies below 400 KHz, tHD:DAT may be
violated as long as all other timing parameters are met.
8
Rev. 0.5
Si473x-B20
tSU:STA tHD:STA
tLOW
tHIGH
tr:IN
tf:IN
tSP
tSU:STO
tBUF
70%
30%
SCLK
SDIO
70%
30%
tf:IN,
tf:OUT
START
tHD:DAT tSU:DAT
tr:IN
STOP
START
Figure 2. 2-Wire Control Interface Read and Write Timing Parameters
SCLK
A6-A0,
R/W
D7-D0
D7-D0
SDIO
START
ADDRESS + R/W
ACK
DATA
ACK
DATA
ACK
STOP
Figure 3. 2-Wire Control Interface Read and Write Timing Diagram
Rev. 0.5
9
Si473x-B20
Table 6. Digital Audio Interface Characteristics
(V = 2.7 to 5.5 V, V = 1.5 to 3.6 V, TA = –20 to 85 °C)
DD
IO
Parameter
Symbol Test Condition
Min
26
10
10
5
Typ
—
Max
1000
—
Unit
ns
DCLK Cycle Time
t
DCT
DCH
DCLK Pulse Width High
t
—
ns
DCLK Pulse Width Low
t
—
—
ns
DCL
DFS Set-up Time to DCLK Rising Edge
DFS Hold Time from DCLK Rising Edge
t
—
—
ns
SU:DFS
HD:DFS
t
5
—
—
ns
DOUT Propagation Delay from DCLK Falling
Edge
t
0
—
12
ns
PD:DOUT
tDCH
tDCL
DCLK
tDCT
DFS
tHD:DFS
tSU:DFS
DOUT
tPD:OUT
Figure 4. Digital Audio Interface Timing Parameters, I2S Mode
10
Rev. 0.5
Si473x-B20
Table 7. FM Receiver Characteristics1,2
(V = 2.7 to 5.5 V, V = 1.5 to 3.6 V, TA = –20 to 85 °C)
DD
IO
Parameter
Symbol
Test Condition
Min
76
Typ
—
Max
108
3.5
Unit
MHz
Input Frequency
f
RF
Sensitivity with Headphone
(S+N)/N = 26 dB
(S+N)/N = 26 dB
—
2.2
µV EMF
3,4,5
Network
3,4,5,6
Sensitivity with 50 Network
—
—
1.1
15
—
—
µV EMF
µV EMF
6
RDS Sensitivity
f = 2 kHz,
RDS BLER < 5%
6,7
LNA Input Resistance
3
4
4
5
5
6
k
6,7
LNA Input Capacitance
pF
6,8
Input IP3
100
40
35
60
35
72
—
—
15
25
55
—
—
70
45
10
—
105
50
50
70
—
80
—
—
—
—
63
58
0.1
75
50
—
—
—
—
—
—
—
90
1
dBµV EMF
3,4,6,7
m = 0.3
±200 kHz
±400 kHz
In-band
dB
dB
dB
dB
AM Suppression
Adjacent Channel Selectivity
Alternate Channel Selectivity
6
Spurious Response Rejection
3,4,7
mV
Audio Output Voltage
RMS
3,7,9
dB
Hz
kHz
dB
dB
dB
%
Audio Output L/R Imbalance
6
–3 dB
–3 dB
30
—
—
—
—
0.5
80
54
—
50
Audio Frequency Response Low
6
Audio Frequency Response High
7,9
Audio Stereo Separation
3,4,5,7,10
Audio Mono S/N
4,5,7,10,11
Audio Stereo S/N
3,7,9
Audio THD
6
De-emphasis Time Constant
FM_DEEMPHASIS = 2
FM_DEEMPHASIS = 1
Single-ended
µs
µs
6,10
R
k
pF
Audio Output Load Resistance
L
L
6,10
C
Single-ended
Audio Output Load Capacitance
Notes:
1. Additional testing information is available in “AN388: Si470x/1x/2x/3x/4x Evaluation Test Board Procedure.”
Volume = maximum for all tests. Tested at RF = 98.1 MHz.
2. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic,
Layout and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
3. F
= 1 kHz, 75 µs de-emphasis, MONO = enabled, and L = R unless noted otherwise.
MOD
4. f = 22.5 kHz.
5. B = 300 Hz to 15 kHz, A-weighted.
AF
6. Guaranteed by characterization.
7. V
= 1 mV.
EMF
8. |f – f | > 2 MHz, f = 2 x f – f . AGC is disabled.
2
1
0
1
2
9. f = 75 kHz.
10. At L and R
pins.
OUT
OUT
11. Analog audio output mode.
12. At temperature (25°C).
Rev. 0.5
11
Si473x-B20
Table 7. FM Receiver Characteristics1,2 (Continued)
(V = 2.7 to 5.5 V, V = 1.5 to 3.6 V, TA = –20 to 85 °C)
DD
IO
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
6
Seek/Tune Time
RCLK tolerance
= 100 ppm
—
—
80
ms/channel
6
Powerup Time
From powerdown
—
—
—
110
3
ms
dB
12
RSSI Offset
Input levels of 8 and
60 dBµV at RF Input
–3
Notes:
1. Additional testing information is available in “AN388: Si470x/1x/2x/3x/4x Evaluation Test Board Procedure.”
Volume = maximum for all tests. Tested at RF = 98.1 MHz.
2. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic,
Layout and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
3. F
= 1 kHz, 75 µs de-emphasis, MONO = enabled, and L = R unless noted otherwise.
MOD
4. f = 22.5 kHz.
5. B = 300 Hz to 15 kHz, A-weighted.
AF
6. Guaranteed by characterization.
7. V
= 1 mV.
EMF
8. |f – f | > 2 MHz, f = 2 x f – f . AGC is disabled.
2
1
0
1
2
9. f = 75 kHz.
10. At L and R
pins.
OUT
OUT
11. Analog audio output mode.
12. At temperature (25°C).
12
Rev. 0.5
Si473x-B20
Table 8. AM/SW/LW Receiver Characteristics1
(V = 2.7 to 5.5 V, V = 1.5 to 3.6 V, TA = –20 to 85 °C)
DD
IO
Parameter
Symbol
Test Condition
Long Wave (LW)
Medium Wave (AM)
Short Wave (SW)
(S+N)/N = 26 dB
THD < 8%
Min
153
520
2.3
—
Typ
—
Max
279
1710
21.85
35
Unit
kHz
f
—
kHz
Input Frequency
RF
—
MHz
2,3,4,5, 6
Sensitivity
25
µV EMF
5,7
Large Signal Voltage Handling
Power Supply Rejection Ratio
—
300
40
—
mV
RMS
RMS
ΔV = 100 mVRMS, 100 Hz
—
—
dB
DD
2,8
Audio Output Voltage
54
60
67
mV
2,3,4,6,8
Audio S/N
50
56
—
dB
2,4,8
Audio THD
—
0.1
2800
—
0.5
—
%
Long Wave (LW)
Medium Wave (AM)
From powerdown
—
µH
ms
Antenna Inductance
180
—
450
110
Powerup Time
—
Notes:
1. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic,
Layout and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
2. FMOD = 1 kHz, 30% modulation, A-weighted, 2 kHz channel filter.
3. B = 300 Hz to 15 kHz, A-weighted.
AF
4. f = 1000 kHz, f = 10 kHz.
RF
5. Guaranteed by characterization.
6. Analog audio output mode.
7. See “AN388: Si470X/1X/2X/3X/4X Evaluation Board Test Procedure” for evaluation method.
8. V = 5 mVrms.
IN
9. Stray capacitance on antenna and board must be < 10 pF to achieve full tuning range at higher inductance levels.
Rev. 0.5
13
Si473x-B20
Table 9. WB Receiver Characteristics1
(V = 2.7 to 5.5 V, VIO = 1.5 to 3.6V, T = 25 °C)
DD
A
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
f
162.4
—
162.55
MHz
R
Input Frequency
2,3
SINAD = 12 dB
±25 kHz
Mono
—
—
—
—
3
0.9
52
45
—
—
—
µV EMF
dB
Sensitivity
Adjacent Channel Selectivity
2,3,4,5
—
dB
Audio S/N
6
–3 dB
300
—
Hz
Audio Frequency Response Low
6
–3 dB
—
kHz
Audio Frequency Response High
Notes:
1. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic,
Layout and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
2. F
= 1 kHz.
MOD
3. f = 3 kHz.
4. V = 1 mV.
EMF
5. A-weighted.
6. Guaranteed by characterization
Table 10. Reference Clock and Crystal Characteristics
(V = 2.7 to 5.5 V, V = 1.5 to 3.6 V, TA = –20 to 85 °C)
DD
IO
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Reference Clock
1
RCLK Supported Frequencies
31.130
–100
1
32.768
—
40,000
100
kHz
2
RCLK Frequency Tolerance
ppm
REFCLK_PRESCALE
—
4095
REFCLK
31.130
32.768
34.406
kHz
Crystal Oscillator
Crystal Oscillator Frequency
—
–50
—
32.768
—
—
50
kHz
ppm
pF
2
Crystal Frequency Tolerance
Board Capacitance
—
3.5
Notes:
1. The Si473x divides the RCLK input by REFCLK_PRESCALE to obtain REFCLK. There are some RCLK frequencies
between 31.130 kHz and 40 MHz that are not supported. See “AN332: Si47xx Programming Guide,” Table 6 for more
details.
2. A frequency tolerance of ±50 ppm is required for FM seek/tune using 50 kHz channel spacing, SW seek/tune, and WB
tune.
14
Rev. 0.5
Si473x-B20
3. Typical AM/FM Application Schematic
GPO1
GPO2/INT
R1
R2
GPO3/DCLK
DFS
R3
15
DOUT
DOUT
Optional: Digital Audio Output
1
NC
2
FMI
FMIP
L1
14
13
12
11
LOUT
ROUT
LOUT/DFS
ROUT/DOUT
GND
3
RFGND
U1
Si473x-GM
4
5
AMI
AM antenna
VDD
C5
RST
VBATTERY
2.7 to 5.5 V
C1
RST
SEN
X1
GPO3
RCLK
C3
SCLK
SDIO
RCLK
VIO
C2
Optional: for crystal oscillator option
1.5 to 3.6 V
L2
RFGND
AMI
T1
C5
Optional: AM air loop antenna
Notes:
1. Place C1 close to V pin.
DD
2. All grounds connect directly to GND plane on PCB.
3. Pins 1 and 20 are no connects, leave floating.
4. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic,
Layout and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
5. Pin 2 connects to the FM antenna interface and pin 4 connects to the AM antenna interface.
6. RFGND should be locally isolated from GND.
7. Place Si473x as close as possible to antenna jack and keep the FMI and AMI traces as short as possible.
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Si473x-B20
4. Bill of Materials
Component(s)
Value/Description
Supplier
Murata
C1
C5
L1
Supply bypass capacitor, 22 nF, ±20%, Z5U/X7R
Coupling capacitor, 0.47 µF, ±20%, Z5U/X7R
Ferrite loop stick, 180–450 µH
Si473x AM/FM Radio Tuner
Murata
Jiaxin
U1
Silicon Laboratories
Optional Components
T1
L2
Transformer, 1–5 turns ratio
Jiaxin, UMEC
Various
Air loop antenna, 10–20 µH
C2, C3
Crystal load capacitors, 22 pF, ±5%, COG
(Optional: for crystal oscillator option)
Venkel
X1
R1
R2
R3
32.768 kHz crystal (Optional: for crystal oscillator option)
Resistor, 2 k(Optional: for digital audio)
Epson
Venkel
Venkel
Venkel
Resistor, 2 k(Optional: for digital audio)
Resistor, 600 (Optional: for digital audio)
16
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Si473x-B20
5. Pin Descriptions: Si473x-GM
20 19 18 17
NC
1
16
FMI 2
RFGND 3
AMI 4
15 DOUT
14 LOUT
13 ROUT
12 GND
11 VDD
GND
PAD
RST 5
6
7
8
9
10
Pin Number(s)
Name
NC
Description
1, 20
No connect. Leave floating.
2
FMI
FM/WB/SW RF inputs. FMI should be connected to the antenna trace.
RF ground. Connect to ground plane on PCB.
AM/SW/LW RF input. AMI should be connected to the AM antenna.
Device reset (active low) input.
3
RFGND
AMI
4
5
RST
6
SEN
Serial enable input (active low).
7
SCLK
SDIO
RCLK
Serial clock input.
8
Serial data input/output.
9
External reference oscillator input.
10
V
I/O supply voltage.
IO
11
V
Supply voltage. May be connected directly to battery.
Ground. Connect to ground plane on PCB.
Right audio line output in analog output mode.
Left audio line output in analog output mode.
Digital output data in digital output mode.
Digital frame synchronization input in digital output mode.
DD
12, GND PAD
GND
ROUT
LOUT
DOUT
DFS
13
14
15
16
17
GPO3/DCLK General purpose output, crystal oscillator, or digital bit synchronous clock input
in digital output mode.
18
19
GPO2/INT
GPO1
General purpose output or interrupt pin.
General purpose output.
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Si473x-B20
6. Ordering Guide
Part Number*
Description
Package
Type
Operating
Temperature
Si4730-B20-GM AM/FM Broadcast Radio Receiver
QFN
Pb-free
–20 to 85 °C
–20 to 85 °C
–20 to 85 °C
–20 to 85 °C
–20 to 85 °C
–20 to 85 °C
–20 to 85 °C
–20 to 85 °C
Si4731-B20-GM AM/FM Broadcast Radio Receiver with RDS/RBDS
Si4734-B20-GM AM/FM/SW/LW Broadcast Radio Receiver
QFN
Pb-free
QFN
Pb-free
Si4735-B20-GM AM/FM/SW/LW Broadcast Radio Receiver with
RDS/RBDS
QFN
Pb-free
Si4736-B20-GM AM/FM/WB Broadcast Radio Receiver
QFN
Pb-free
Si4737-B20-GM AM/FM/WB Broadcast Radio Receiver with
RDS/RBDS
QFN
Pb-free
Si4738-B20-GM FM/WB Broadcast Radio Receiver
QFN
Pb-free
Si4739-B20-GM FM/WB Broadcast Radio Receiver with RDS/RBDS
QFN
Pb-free
*Note: Add an “(R)” at the end of the device part number to denote tape and reel option; 2500 quantity per reel.
18
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Si473x-B20
7. Package Outline: Si473x QFN
Figure 5 illustrates the package details for the Si473x. Table 11 lists the values for the dimensions shown in the
illustration.
Figure 5. 20-Pin Quad Flat No-Lead (QFN)
Table 11. Package Dimensions
Symbol
Millimeters
Nom
Symbol
Millimeters
Nom
Min
Max
Min
Max
A
A1
b
0.50
0.00
0.20
0.27
0.55
0.02
0.60
0.05
0.30
0.37
f
2.53 BSC
L
0.35
0.00
—
0.40
—
0.45
0.10
0.05
0.05
0.08
0.10
0.10
0.25
L1
c
0.32
aaa
bbb
ccc
ddd
eee
—
D
3.00 BSC
1.70
—
—
D2
e
1.65
1.75
—
—
0.50 BSC
3.00 BSC
1.70
—
—
E
—
—
E2
1.65
1.75
Notes:
1. All dimensions are shown in millimeters (mm) unless otherwise noted.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
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19
Si473x-B20
8. PCB Land Pattern: Si473x QFN
Figure 6 illustrates the PCB land pattern details for the Si473x family. Table 12 lists the values for the dimensions
shown in the illustration.
Figure 6. PCB Land Pattern
20
Rev. 0.5
Si473x-B20
Table 12. PCB Land Pattern Dimensions
Symbol
Millimeters
Min Max
2.71 REF
1.60 1.80
Symbol
Millimeters
Min
Max
D
D2
e
GE
W
2.10
—
—
0.34
0.28
0.50 BSC
2.71 REF
X
—
E
Y
0.61 REF
E2
f
1.60
2.53 BSC
2.10
1.80
ZE
ZD
—
—
3.31
3.31
GD
—
Notes: General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on IPC-SM-782 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material
Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
Notes: Solder Mask Design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the
solder mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Notes: Stencil Design
1. A stainless steel, laser-cut, and electro-polished stencil with trapezoidal walls should
be used to assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.
4. A 1.45 x 1.45 mm square aperture should be used for the center pad. This provides
approximately 70% solder paste coverage on the pad, which is optimum to assure
correct component stand-off.
Notes: Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C
specification for Small Body Components.
Rev. 0.5
21
Si473x-B20
9. Additional Reference Resources
Contact your local sales representatives for more information or to obtain copies of the following references:
EN55020 Compliance Test Certificate
AN332: Si47xx Programming Guide
AN383: Si47xx Antenna, Schematic, Layout, and Design Layout Guidelines
AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure
22
Rev. 0.5
Si473x-B20
NOTES:
Rev. 0.5
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Si473x-B20
CONTACT INFORMATION
Silicon Laboratories Inc.
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Austin, TX 78701
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
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Email: FMinfo@silabs.com
Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep-
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quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
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Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
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