SI4738-B20-GMR [SILICON]
Telecom Circuit, 1-Func, QFN-20;
| 型号： | SI4738-B20-GMR |
| 厂家： | 
SILICON |
| 描述： | Telecom Circuit, 1-Func, QFN-20 电信 电信集成电路 |
| 文件： | 总38页 (文件大小：620K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si4736/37/38/39-B20
BROADCAST WEATHER BAND RADIO RECEIVER
Features
NOAA weather band support (162.4– No manual alignment necessary
162.55 MHz)
Worldwide FM band support
(76–108 MHz)
Programmable reference clock
Volume control
Programmable soft mute control
Programmable de-emphasis
RDS/RBDS processor (Si4737/39
only)
Optional digital audio output (Si47/39
only)
Optional digital audio output
(Si4737/39 only)
2-wire and 3-wire control interface
2.7 to 5.5 V supply voltage
Firmware upgradeable
3 x 3 x 0.55 mm 20-pin QFN package
Pb-free/RoHS compliant
Worldwide AM band support
(520–1710 kHz) (Si4736/37 only)
1050 Hz alert tone detection
Excellent real-world performance
Freq synthesizer with integrated VCO
Advanced AM/FM seek tuning
Automatic frequency control (AFC)
Automatic gain control (AGC)
Integrated LDO regulator
Digital FM stereo decoder
Adaptive noise suppression
AM/FM/WB digital tuning
Ordering Information:
See page 30.
Pin Assignments
Si4736/37/38/39-GM
(Top View)
Applications
Emergency radios
Table and portable radios
Stereos
Mini/micro systems
Portable media players
Boom boxes
Cellular handsets
Modules
Clock radios
Mini HiFi
20 19 18 17
NC
FMI
1
16
2
15 DOUT
14 LOUT
13 ROUT
12 GND
11 VDD
RFGND
AMI
3
4
5
GND
PAD
Description
RST
The Si4736/37/38/39 is the first digital CMOS AM/FM/WB radio receiver IC that
integrates the complete tuner function from antenna input to audio output.
6
7
8
9
10
Functional Block Diagram
Si473x
Patents pending
AMI
RDS
(Si4737/
39)
Notes:
DIGITAL
AUDIO
(Si4737/
39)
DOUT
AM
ANT
LNA
AGC
RFGND
1. To ensure proper operation and
receiver performance, follow the
guidelines in “AN383: Universal
Antenna Selection and Layout
Guidelines.” Silicon Laboratories will
evaluate schematics and layouts for
qualified customers.
DFS
GPO/DCLK
LOW-IF
FM/
WB
ANT
ADC
ADC
DAC
DAC
ROUT
LOUT
LNA
AGC
DSP
FMI
2. Place Si4736/37/38/39 as close as
possible to antenna jack and keep
the FMI and AMI traces as short as
possible.
2.7– 5.5 V
VDD
GND
CONTROL
INTERFACE
LDO
AFC
VIO
1.5–3.6 V
Rev. 1.0 4/08
Copyright © 2008 by Silicon Laboratories
Si4736/37/38/39-B20
Si4736/37/38/39-B20
2
Rev. 1.0
Si4736/37/38/39-B20
TABLE OF CONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
3. Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.3. FM Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.4. AM Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.5. SW Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.6. LW Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.7. Digital Audio Interface (Si4735 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.8. Stereo Audio Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4.9. De-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4.10. Stereo DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4.11. Soft Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4.12. RDS/RBDS Processor (Si4735 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4.13. Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
4.14. Seek . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
4.15. Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
4.16. Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
4.17. GPO Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
4.18. Firmware Upgrades . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
4.19. Reset, Power Up, and Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
4.20. Programming with Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
5. Commands and Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
6. Pin Descriptions: Si4734/35-GM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
8. Package Markings (Top Marks) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
8.1. Si4734/35 Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
8.2. Top Mark Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
9. Package Outline: Si4734/35 QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
10. PCB Land Pattern: Si4734/35 QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
11. Additional Reference Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Rev. 1.0
3
Si4736/37/38/39-B20
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Symbol Test Condition
Min
2.7
1.5
10
Typ
—
Max
5.5
3.6
—
Unit
V
Supply Voltage
V
DD
Interface Supply Voltage
V
—
V
IO
DDRISE
Power Supply Power-Up Rise Time
Interface Power Supply Power-Up Rise Time
Ambient Temperature
V
—
µs
µs
C
V
10
—
—
IORISE
T
–20
25
85
A
Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at VDD = 3.3 V and 25 C unless otherwise stated. Parameters are tested in production unless
otherwise stated.
Table 2. Absolute Maximum Ratings1,2
Parameter
Supply Voltage
Symbol
Value
–0.5 to 5.8
–0.5 to 3.9
10
Unit
V
V
DD
Interface Supply Voltage
V
V
IO
IN
3
Input Current
I
mA
V
3
Input Voltage
V
T
–0.3 to (VIO + 0.3)
–40 to 95
–55 to 150
0.4
IN
Operating Temperature
Storage Temperature
C
C
OP
T
STG
4
RF Input Level
V
pK
Notes:
1. Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation
should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure beyond
recommended operating conditions for extended periods may affect device reliability.
2. The Si4736/37/38/39 devices are high-performance RF integrated circuits with certain pins having an ESD rating of
< 2 kV HBM. Handling and assembly of these devices should only be done at ESD-protected workstations.
3. For input pins SCLK, SEN, SDIO, RST, RCLK, DCLK, DFS, GPO1, GPO2, and GPO3.
4. At RF input pins, FMI and AMI.
4
Rev. 1.0
Si4736/37/38/39-B20
Table 3. DC Characteristics
(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
FM Mode
Supply Current
Supply Current
I
I
I
—
—
—
—
19.2
19.8
19.9
18.0
22
23
mA
mA
mA
mA
FM
FM
FM
1
Low SNR level
2
RDS Supply Current
23
2
Supply Current
I
I
Digital Output Mode
20.5
FMD
WB Mode
Supply Current
Supply Current
Supply Current
I
I
—
—
—
19.2
19.8
17.2
22
23
mA
mA
mA
FM
FM
Low SNR level
20.5
FMD
AM Mode
Supply Current
I
Analog Output Mode
Digital Output Mode
—
—
17.3
15.5
20.5
20.5
mA
mA
AM
2
Supply Current
I
AMD
Supplies and Interface
Interface Supply Current
I
—
—
320
10
1
600
20
µA
µA
µA
V
IO
V
V
Powerdown Current
I
DDPD
DD
Powerdown Current
I
SCLK, RCLK inactive
—
10
IO
IOPD
3
High Level Input Voltage
V
0.7 x V
–0.3
–10
—
—
—
—
V
+ 0.3
IO
IH
IO
3
Low Level Input Voltage
V
0.3 x V
10
V
IL
IO
3
High Level Input Current
I
V
= V = 3.6 V
µA
µA
IH
IN
IO
3
Low Level Input Current
I
V
= 0 V,
IN
–10
10
IL
V
= 3.6 V
IO
4
High Level Output Voltage
V
I
= 500 µA
0.8 x V
—
—
—
—
V
V
OH
OUT
OUT
IO
4
Low Level Output Voltage
V
I
= –500 µA
0.2 x V
OL
IO
Notes:
1. LNA is automatically switched to higher current mode for optimum sensitivity in weak signal conditions.
2. Specifications are guaranteed by characterization.
3. For input pins SCLK, SEN, SDIO, RST, RCLK, DCLK, and DFS.
4. For output pins SDIO, DOUT, GPO1, GPO2, and GPO3.
Rev. 1.0
5
Si4736/37/38/39-B20
Table 4. Reset Timing Characteristics1,2,3
(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol
Min
100
30
Typ
—
Max
—
Unit
µs
RST Pulse Width and GPO1, GPO2/INT Setup to RST
GPO1, GPO2/INT Hold from RST
Important Notes:
t
SRST
t
—
—
ns
HRST
1. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is
high) does not occur within 300 ns before the rising edge of RST.
2. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high until
after the first start condition.
3. When selecting 3-wire or SPI modes, the user must ensure that a rising edge of SCLK does not occur within 300 ns
before the rising edge of RST.
4. If GPO1 and GPO2 are actively driven by the user, then minimum tSRST is only 30 ns. If GPO1 or GPO2 is hi-Z, then
minimum tSRST is 100 µs, to provide time for on-chip 1 M devices (active while RST is low) to pull GPO1 high and
GPO2 low.
tHRST
tSRST
70%
30%
RST
70%
30%
GPO1
70%
30%
GPO2/
INT
Figure 1. Reset Timing Parameters for Busmode Select
6
Rev. 1.0
Si4736/37/38/39-B20
Table 5. 2-Wire Control Interface Characteristics1,2,3
(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol Test Condition
Min
0
Typ
—
Max
400
—
Unit
kHz
µs
SCLK Frequency
SCLK Low Time
SCLK High Time
f
SCL
t
1.3
0.6
0.6
—
LOW
t
—
—
µs
HIGH
SCLK Input to SDIO Setup
t
t
—
—
µs
SU:STA
(START)
SCLK Input to SDIO Hold
0.6
—
—
µs
HD:STA
(START)
SDIO Input to SCLK Setup
t
t
100
0
—
—
—
—
900
—
ns
ns
µs
SU:DAT
4,5
SDIO Input to SCLK Hold
HD:DAT
SU:STO
SCLK input to SDIO Setup
t
0.6
(STOP)
STOP to START Time
SDIO Output Fall Time
t
1.3
—
—
—
µs
ns
BUF
t
250
f:OUT
Cb
----------
1pF
20 + 0.1
SDIO Input, SCLK Rise/Fall Time
t
t
—
300
ns
f:IN
r:IN
Cb
----------
1pF
20 + 0.1
SCLK, SDIO Capacitive Loading
Input Filter Pulse Suppression
Notes:
C
—
—
—
—
50
50
pF
ns
b
t
SP
1. When VIO = 0 V, SCLK and SDIO are low impedance.
2. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is
high) does not occur within 300 ns before the rising edge of RST.
3. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high
until after the first start condition.
4. The Si4736/37/38/39 delays SDIO by a minimum of 300 ns from the VIH threshold of SCLK to comply with the
minimum tHD:DAT specification.
5. The maximum tHD:DAT has only to be met when fSCL = 400 kHz. At frequencies below 400 kHz, tHD:DAT may be violated
as long as all other timing parameters are met.
Rev. 1.0
7
Si4736/37/38/39-B20
tSU:STA tHD:STA
tLOW
tHIGH
tr:IN
tf:IN
tSP
tSU:STO
tBUF
70%
30%
SCLK
SDIO
70%
30%
tf:IN,
tf:OUT
START
tHD:DAT tSU:DAT
tr:IN
STOP
START
Figure 2. 2-Wire Control Interface Read and Write Timing Parameters
SCLK
A6-A0,
R/W
D7-D0
D7-D0
SDIO
START
ADDRESS + R/W
ACK
DATA
ACK
DATA
ACK
STOP
Figure 3. 2-Wire Control Interface Read and Write Timing Diagram
8
Rev. 1.0
Si4736/37/38/39-B20
Table 6. 3-Wire Control Interface Characteristics
(V = 2.7 to 5.5 V, V = 1.5 to 3.6 V, TA = –20 to 85 °C)
DD
IO
Parameter
Symbol
Test Condition
Min
0
Typ
—
—
—
—
—
—
—
—
—
Max
2.5
—
Unit
MHz
ns
SCLK Frequency
SCLK High Time
SCLK Low Time
f
CLK
t
25
25
20
10
10
2
HIGH
t
—
ns
LOW
SDIO Input, SEN to SCLKSetup
SDIO Input to SCLKHold
t
—
ns
S
t
—
ns
HSDIO
SEN Input to SCLKHold
t
—
ns
HSEN
SCLKto SDIO Output Valid
SCLKto SDIO Output High Z
SCLK, SEN, SDIO, Rise/Fall time
t
Read
Read
25
25
10
ns
CDV
t
2
ns
CDZ
t , t
—
ns
R
F
Note: When selecting 3-wire mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the
rising edge of RST.
70%
SCLK
30%
tR
tF
tHSDIO
tHIGH
tLOW
tHSEN
tS
70%
30%
tS
SEN
A6-A5,
R/W,
A4-A1
70%
30%
A7
A0
D15
D14-D1
D0
SDIO
Address In
Data In
Figure 4. 3-Wire Control Interface Write Timing Parameters
70%
30%
SCLK
SEN
tHSDIO
tCDV
tHSEN
tS
tCDZ
70%
30%
tS
70%
30%
A6-A5,
R/W,
A4-A1
A7
A0
D15
D14-D1
D0
SDIO
½ Cycle Bus
Turnaround
Address In
Data Out
Figure 5. 3-Wire Control Interface Read Timing Parameters
Rev. 1.0
9
Si4736/37/38/39-B20
Table 7. SPI Control Interface Characteristics
(V = 2.7 to 5.5 V, V = 1.5 to 3.6 V, TA = –20 to 85 °C)
DD
IO
Parameter
Symbol
Test Condition
Min
0
Typ
—
—
—
—
—
—
—
—
—
Max
2.5
—
Unit
MHz
ns
SCLK Frequency
SCLK High Time
SCLK Low Time
f
CLK
t
25
25
15
10
5
HIGH
t
—
ns
LOW
SDIO Input, SEN to SCLKSetup
SDIO Input to SCLKHold
t
—
ns
S
t
—
ns
HSDIO
SEN Input to SCLKHold
t
—
ns
HSEN
SCLKto SDIO Output Valid
SCLKto SDIO Output High Z
SCLK, SEN, SDIO, Rise/Fall time
t
Read
Read
2
25
25
10
ns
CDV
t
2
ns
CDZ
t , t
—
ns
R
F
Note: When selecting SPI mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the
rising edge of RST.
70%
SCLK
30%
tR
tF
tHIGH
tLOW
tHSDIO
tHSEN
70%
30%
tS
SEN
tS
70%
30%
C7
C6–C1
C0
D7
D6–D1
D0
SDIO
Control Byte In
8 Data Bytes In
Figure 6. SPI Control Interface Write Timing Parameters
70%
30%
SCLK
tCDV
tS
tHSEN
tHSDIO
70%
30%
tS
SEN
tCDZ
70%
30%
SDIO
C7
C6–C1
C0
D7
D6–D1
D0
16 Data Bytes Out
(SDIO or GPO1)
Bus
Turnaround
Control Byte In
Figure 7. SPI Control Interface Read Timing Parameters
10
Rev. 1.0
Si4736/37/38/39-B20
Table 8. Digital Audio Interface Characteristics
(V = 2.7 to 5.5 V, V = 1.5 to 3.6 V, TA = –20 to 85 °C)
DD
IO
Parameter
Symbol Test Condition
Min
26
10
10
5
Typ
—
Max
1000
—
Unit
ns
DCLK Cycle Time
t
DCT
DCH
DCLK Pulse Width High
t
—
ns
DCLK Pulse Width Low
t
—
—
ns
DCL
DFS Set-up Time to DCLK Rising Edge
DFS Hold Time from DCLK Rising Edge
t
—
—
ns
SU:DFS
HD:DFS
t
5
—
—
ns
DOUT Propagation Delay from DCLK Falling
Edge
t
0
—
12
ns
PD:DOUT
tDCH
tDCL
DCLK
tDCT
DFS
tHD:DFS
tSU:DFS
DOUT
tPD:OUT
Figure 8. Digital Audio Interface Timing Parameters, I2S Mode
Rev. 1.0
11
Si4736/37/38/39-B20
Table 9. FM Receiver Characteristics1,2
(V = 2.7 to 5.5 V, V = 1.5 to 3.6 V, TA = –20 to 85 °C)
DD
IO
Parameter
Symbol
Test Condition
Min
76
Typ
—
Max
108
3.5
Unit
MHz
Input Frequency
f
RF
Sensitivity with Headphone Net-
(S+N)/N = 26 dB
(S+N)/N = 26 dB
—
2.2
µV EMF
3,4,5
work
3,4,5,6
Sensitivity with 50 Network
—
—
1.1
15
—
—
µV EMF
µV EMF
6
RDS Sensitivity
f = 2 kHz,
RDS BLER < 5%
6,7
LNA Input Resistance
3
4
4
5
5
6
k
6,7
LNA Input Capacitance
pF
6,8
Input IP3
100
40
35
60
35
72
—
—
15
25
55
—
—
70
45
10
—
105
50
50
70
—
80
—
—
—
—
63
58
0.1
75
50
—
—
—
—
—
—
—
90
1
dBµV EMF
3,4,6,7
m = 0.3
±200 kHz
±400 kHz
In-band
dB
dB
dB
dB
AM Suppression
Adjacent Channel Selectivity
Alternate Channel Selectivity
Spurious Response Rejection
6
3,4,7
mV
Audio Output Voltage
RMS
3,7,9
dB
Hz
kHz
dB
dB
dB
%
Audio Output L/R Imbalance
Audio Frequency Response Low
6
–3 dB
–3 dB
30
—
—
—
—
0.5
80
54
—
50
6
Audio Frequency Response High
7,9
Audio Stereo Separation
3,4,5,7,10
Audio Mono S/N
4,5,7,10,11
Audio Stereo S/N
3,7,9
Audio THD
6
De-emphasis Time Constant
FM_DEEMPHASIS = 2
FM_DEEMPHASIS = 1
Single-ended
µs
µs
6,10
R
k
pF
Audio Output Load Resistance
L
L
6,10
C
Single-ended
Audio Output Load Capacitance
Notes:
1. Additional testing information is available in Application Note AN388. Volume = maximum for all tests. Tested at
RF = 98.1 MHz.
2. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Antenna Selection and
Universal Layout Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
3. F
= 1 kHz, 75 µs de-emphasis, MONO = enabled, and L = R unless noted otherwise.
MOD
4. f = 22.5 kHz.
5. B = 300 Hz to 15 kHz, A-weighted.
AF
6. Guaranteed by characterization.
7. V
= 1 mV.
EMF
8. |f – f | > 2 MHz, f = 2 x f – f . AGC is disabled. Refer to "6. Pin Descriptions: Si4736/37/38/39-GM" on page 29.
2
1
0
1
2
9. f = 75 kHz.
10. At L and R
pins.
OUT
OUT
11. Analog audio output mode.
12. At temperature (25 °C).
12
Rev. 1.0
Si4736/37/38/39-B20
Table 9. FM Receiver Characteristics1,2 (Continued)
(V = 2.7 to 5.5 V, V = 1.5 to 3.6 V, TA = –20 to 85 °C)
DD
IO
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
6
Seek/Tune Time
RCLK tolerance
= 100 ppm
—
—
80
ms/channel
6
Powerup Time
From powerdown
—
—
—
110
3
ms
dB
12
RSSI Offset
Input levels of 8 and
60 dBµV at RF Input
–3
Notes:
1. Additional testing information is available in Application Note AN388. Volume = maximum for all tests. Tested at
RF = 98.1 MHz.
2. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Antenna Selection and
Universal Layout Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
3. F
= 1 kHz, 75 µs de-emphasis, MONO = enabled, and L = R unless noted otherwise.
MOD
4. f = 22.5 kHz.
5. B = 300 Hz to 15 kHz, A-weighted.
AF
6. Guaranteed by characterization.
7. V
= 1 mV.
EMF
8. |f – f | > 2 MHz, f = 2 x f – f . AGC is disabled. Refer to "6. Pin Descriptions: Si4736/37/38/39-GM" on page 29.
2
1
0
1
2
9. f = 75 kHz.
10. At L and R
pins.
OUT
OUT
11. Analog audio output mode.
12. At temperature (25 °C).
Table 10. WB Receiver Characteristics1
(V = 2.7 to 5.5 V, VIO = 1.5 to 3.6V, T = 25 °C)
DD
A
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
f
162.4
—
162.55
MHz
R
Input Frequency
2,3
SINAD = 12 dB
+/-25 kHz
Mono
—
—
—
—
3
0.9
52
45
—
—
—
µV EMF
dB
Sensitivity
Adjacent Channel Selectivity
2,3,4,5
—
dB
Audio S/N
6
–3 dB
300
—
Hz
Audio Frequency Response Low
6
–3 dB
—
kHz
Audio Frequency Response High
Notes:
1. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Universal Antenna Selection
and Layout Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
2. F
= 1 kHz.
MOD
3. f = 3 kHz.
4. V = 1 mV.
EMF
5. A-weighted.
6. Guaranteed by characterization
Rev. 1.0
13
Si4736/37/38/39-B20
Table 11. AM Receiver Characteristics1
(V = 2.7 to 5.5 V, V = 1.5 to 3.6 V, TA = –20 to 85 °C)
DD
IO
Parameter
Symbol
Test Condition
Min
520
—
Typ
—
Max
1710
35
Unit
kHz
Input Frequency
f
RF
2,3,4,5, 6
Sensitivity
(S+N)/N = 26 dB
THD < 8%
25
300
40
60
56
0.1
—
µV EMF
5,7
Large Signal Voltage Handling
Power Supply Rejection Ratio
—
—
mV
RMS
RMS
∆V = 100 mVRMS, 100 Hz
—
—
dB
DD
2,8
Audio Output Voltage
54
67
mV
2,3,4,6,8
Audio S/N
50
—
dB
2,4,8
Audio THD
—
0.5
450
110
%
5,9
Antenna Inductance
180
—
µH
ms
Powerup Time
From powerdown
—
Notes:
1. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Antenna Selection and
Universal Layout Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
2. FMOD = 1 kHz, 30% modulation, A-weighted, 2 kHz channel filter.
3. B = 300 Hz to 15 kHz, A-weighted.
AF
4. f = 1000 kHz, f = 10 kHz.
RF
5. Guaranteed by characterization.
6. Analog audio output mode.
7. See “AN388: Evaluation Board Test Procedure” for evaluation method.
8. V = 5 mVrms.
IN
9. Stray capacitance on antenna and board must be < 10 pF to achieve full tuning range at higher inductance levels.
14
Rev. 1.0
Si4736/37/38/39-B20
Table 12. Reference Clock and Crystal Characteristics
(V = 2.7 to 5.5 V, V = 1.5 to 3.6 V, TA = –20 to 85 °C)
DD
IO
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Reference Clock
*
RCLK Supported Frequencies
RCLK Frequency Tolerance
REFCLK_PRESCALE
REFCLK
31.130
–50
32.768
—
40000.0
50
kHz
ppm
1
—
4095
31.130
32.768
34.406
kHz
Crystal Oscillator
Crystal Oscillator Frequency
Crystal Frequency Tolerance*
Board Capacitance
—
–100
—
32.768
—
—
kHz
ppm
pF
100
3.5
—
*Note: The Si4736/37/38/39 divides the RCLK input by REFCLK_PRESCALE to obtain REFCLK. There are some RCLK
frequencies between 31.130 kHz and 40 MHz that are not supported. See AN332, Table 6 for more details.
15
Rev. 1.0
Si4736/37/38/39-B20
2. Typical Application Schematic
GPO1
GPO2/INT
R1
R2
GPO3/DCLK
DFS
R3
15
DOUT
DOUT
Optional: Digital Audio Output
1
NC
2
FMI
FMIP
L1
14
13
12
11
LOUT
ROUT
LOUT/DFS
ROUT/DOUT
GND
3
RFGND
U1
Si473x
4
5
AMI
AM antenna
VDD
C5
RST
VBATTERY
2.7 to 5.5 V
C1
Si4736/37 only
RST
SEN
X1
GPO3
RCLK
C3
SCLK
SDIO
RCLK
C2
Optional: for crystal oscillator option
VIO
1.5 to 3.6 V
L2
RFGND
AMI
T1
C5
Optional: AM air loop antenna
Notes:
1. Place C1 close to V pin.
DD
2. All grounds connect directly to GND plane on PCB.
3. Pins 1 and 20 are no connects, leave floating.
4. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Universal Antenna Selection and
Layout Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
5. Pin 2 connects to the FM antenna interface, and pin 4 connects to the AM antenna interface.
6. RFGND should be locally isolated from GND.
7. Place Si4736/37/38/39 as close as possible to antenna jack and keep the FMI and AMI traces as short as possible.
16
Rev. 1.0
Si4736/37/38/39-B20
3. Bill of Materials
Component(s)
Value/Description
Supplier
Murata
C1
C5
L1
Supply bypass capacitor, 22 nF, ±20%, Z5U/X7R
Coupling capacitor, 0.47 µF, ±20%, Z5U/X7R
Ferrite loop stick, 180–450 µH
Murata
Jiaxin
U1
Si4736/37/38/39 AM/FM/WB Radio Tuner
Optional Components
Silicon Laboratories
T1
L2
Transformer, 1–5 turns ratio
Jiaxin, UMEC
Various
Air loop antenna, 10–20 µH
C2, C3
Crystal load capacitors, 22 pF, ±5%, COG
(Optional: for crystal oscillator option)
Venkel
X1
R1
R2
R3
32.768 kHz crystal (Optional: for crystal oscillator option)
Resistor, 2 k(Optional: for digital audio)
Epson
Venkel
Venkel
Venkel
Resistor, 2 k(Optional: for digital audio)
Resistor, 600 (Optional: for digital audio)
Rev. 1.0
17
Si4736/37/38/39-B20
4. Functional Description
4.1. Overview
Si473x
AMI
RDS
(Si4737/
39)
DIGITAL
AUDIO
(Si4737/
39)
DOUT
AM
LNA
ANT
RFGND
DFS
GPO/DCLK
AGC
LOW-IF
FM/
WB
ANT
ADC
ADC
DAC
DAC
ROUT
LOUT
LNA
AGC
DSP
FMI
2.7– 5.5 V
VDD
GND
CONTROL
INTERFACE
LDO
AFC
VIO
1.5–3.6 V
Figure 9. Functional Block Diagram
The Si4736/37 and Si4738/39 are the industry's first wire control interface, SPI, and a Si4700/01 backwards-
fully integrated, 100% CMOS AM/FM/WB and FM/WB compatible, 3-wire control interface.
radio receiver ICs. Offering unmatched integration and
The Si4736/37/38/39 utilizes digital processing to
PCB space savings, the Si4736/37/38/39 requires only
achieve high fidelity, optimal performance, and design
2
two external components and less than 15 mm of
flexibility. The chip provides excellent pilot rejection,
board area, excluding the antenna inputs. The
selectivity, and unmatched audio performance, and
Si4736/37/38/39 AM/FM/WB radio provides the space
offers both the manufacturer and the end-user
savings and low power consumption necessary for
extensive programmability and flexibility in listening
portable devices while delivering the high performance
experience.
and design simplicity desired for all AM/FM/WB
The Si4737/39 incorporates a digital processor for the
solutions.
European Radio Data System (RDS) and the North
Leveraging Silicon Laboratories' proven and patented
American Radio Broadcast Data System (RBDS), and
Si4700/01 FM tuner's digital low intermediate frequency
includes all required symbol decoding, block
(low-IF) receiver architecture, the Si4736/37/38/39
synchronization, error detection, and error correction
delivers superior RF performance and interference
functions. Using this feature, the Si4737/39 enables
rejection in both AM and FM bands. The high integration
broadcast data such as station identification and song
and complete system production test simplifies design-
name to be displayed to the user.
in, increases system quality, and improves
manufacturability.
The Si4736/37/38/39 is a feature-rich solution including
1050 Hz tone detection, advanced seek algorithms, soft
mute, auto-calibrated digital tuning, and FM stereo
processing. In addition, the Si4736/37/38/39 provides
analog and digital audio outputs and a programmable
2
reference clock. The device supports I C-compatible, 2-
18
Rev. 1.0
Si4736/37/38/39-B20
4.2. Operating Modes
4.4. AM Receiver (Si4736/37)
The Si4736/37/38/39 operates in an FM receive, an AM The highly integrated Si4736/37 supports worldwide AM
receive, or a weather band receive mode. In FM mode band reception from 520 to 1710 kHz using a digital
and WB mode, radio signals are received on FMI (pin 2) low-IF architecture with a minimum number of external
and processed by the FM front-end circuitry. In AM components and no manual alignment required. This
mode, radio signals are received on AMI (pin 4) and digital low-IF architecture allows for high-precision
processed by the AM front-end circuitry. In addition to filtering and offers excellent selectivity and noise
the receiver mode, there is a clocking mode to choose suppression. The DSP also provides 9 or 10 kHz
to clock the Si473x from a reference clock or crystal. On channel selection, AM demodulation, soft mute, and
the Si4737/39, there is an audio output mode to choose additional features such as adjustable channel
between an analog and/or digital audio output. In the bandwidth settings. Similar to the FM receiver, the
analog audio output mode, pin 13 is ROUT, pin 14 is integrated LNA and AGC optimize sensitivity and
LOUT, and pin 17 is GPO3. In the digital audio mode, rejection of strong interferers allowing better reception
pin 15 is DOUT, pin 16 is DFS, and pin 17 is DCLK. of weak stations.
Concurrent analog/digital audio output mode requires
The Si4736/37 provides highly accurate digital AM
pins 13, 14, 15, 16, and 17. The receiver mode and the
tuning without factory adjustments. To offer maximum
audio output mode are set by the POWER_UP
flexibility, the receiver supports a wide range of ferrite
command listed in Table 12. Si473x Command
loop sticks from 180–450 µH. An air loop antenna is
Summary.
supported by using a transformer to increase the
effective inductance from the air loop. Using a 1:5 turn
4.3. FM Receiver
ratio inductor, the inductance is increased by 25 times
The Si4736/37/38/39 FM receiver is based on the
and easily supports all typical AM air loop antennas,
proven Si4700/01 FM tuner. The receiver uses a digital
which generally vary between 10 and 20 µH.
low-IF architecture, allowing the elimination of external
4.5. Weather Band Receiver
components
and
factory
adjustments.
The
Si4736/37/38/39 integrates a low noise amplifier (LNA)
supporting the worldwide FM broadcast band (76 to 108
MHz). An AGC circuit controls the gain of the LNA to
optimize sensitivity and rejection of strong interferers.
For testing purposes, the AGC can be disabled. Refer to
Section "5. Commands and Properties" on page 25 for
additional programming and configuration information.
An image-reject mixer downconverts the RF signal to
low-IF. The quadrature mixer output is amplified,
filtered, and digitized with high resolution analog-to-
digital converters (ADCs). This advanced architecture
allows the Si4736/37/38/39 to perform channel
selection, FM demodulation, and stereo audio
processing to achieve superior performance compared
to traditional analog architectures.
The Si4736/37/38/39 supports weather band reception
from 162.4 to 162.55 MHz. The highly integrated
Si4736/37/38/39 meets NOAA specification, receives all
seven NOAA specified frequencies, implements narrow-
band FM de-emphasis, and supports 1050 Hz alert tone
detection. In addition, the Si4736/37/38/39 provides
advanced features not available on conventional radios,
such as an AFC and a dynamic channel bandwidth filter.
The AFC locks on to the strongest signal within a
narrow, adjustable frequency range to compensate for
any potential frequency errors such as crystal tolerance
or transmit frequency errors. The AFC ensures the
channel filter is always centered on the desired channel
providing optimal reception. The dynamic channel
bandwidth feature utilizes a wide filter in strong signal
conditions to provide best sound quality and a narrower
filter in weak conditions to provide best sensitivity.
19
Rev. 1.0
Si4736/37/38/39-B20
In DSP mode, the DFS becomes a pulse with a width of
1DCLK period. The left channel is transferred first,
followed right away by the right channel. There are two
options in transferring the digital audio data in DSP
mode: the MSB of the left channel can be transferred on
the first rising edge of DCLK following the DFS pulse or
on the second rising edge.
4.6. Digital Audio Interface (Si4737/39
Only)
The digital audio interface operates in slave mode and
supports three different audio data formats:
2
I S
Left-Justified
In all audio formats, depending on the word size, DCLK
frequency and sample rates, there may be unused
DCLK cycles after the LSB of each word before the next
DFS transition and MSB of the next word. In addition, if
preferred, the user can configure the MSB to be
captured on the falling edge of DCLK via properties.
The number of audio bits can be configured for 8, 16,
20, or 24 bits.
DSP Mode
4.6.1. Audio Data Formats
2
In I S mode, by default the MSB is captured on the
second rising edge of DCLK following each DFS
transition. The remaining bits of the word are sent in
order, down to the LSB. The left channel is transferred
first when the DFS is low, and the right channel is
transferred when the DFS is high.
4.6.2. Audio Sample Rates
In Left-Justified mode, by default the MSB is captured
on the first rising edge of DCLK following each DFS
transition. The remaining bits of the word are sent in
order, down to the LSB. The left channel is transferred
first when the DFS is high, and the right channel is
transferred when the DFS is low.
The device supports a number of industry-standard
sampling rates including 32, 40, 44.1, and 48 kHz. The
digital audio interface enables low-power operation by
eliminating the need for redundant DACs on the audio
baseband processor.
INVERTED
(OFALL = 1)
DCLK
(OFALL = 0)
DCLK
DFS
LEFT CHANNEL
I2S
RIGHT CHANNEL
(OMODE = 0000)
1 DCLK
1 DCLK
n-2
DOUT
1
2
3
n-1
n
n-2
n-1
1
2
3
n
MSB
LSB
MSB
LSB
Figure 10. I2S Digital Audio Format
INVERTED
DCLK
(OFALL = 1)
(OFALL = 0)
DCLK
DFS
LEFT CHANNEL
RIGHT CHANNEL
n-2
Left-Justified
(OMODE = 0110)
DOUT
1
2
3
n-2
n-1
n
n-1
n
1
2
3
MSB
LSB
MSB
LSB
Figure 11. Left-Justified Digital Audio Format
(OFALL = 0)
DCLK
DFS
RIGHT CHANNEL
n-2
LEFT CHANNEL
n-2
DOUT
1
2
3
2
n-1
n
(OMODE = 1100)
(OMODE = 1000)
1
2
3
2
n-1
n
(MSB at 1st rising edge)
MSB
LSB
MSB
LSB
LEFT CHANNEL
n-2
1 DCLK
RIGHT CHANNEL
n-2
DOUT
1
3
n-1
n
1
3
n-1
n
LSB
(MSB at 2nd rising edge)
MSB
MSB
LSB
Figure 12. DSP Digital Audio Format
20
Rev. 1.0
Si4736/37/38/39-B20
4.7. Stereo Audio Processing
4.8. De-emphasis
The output of the FM demodulator is a stereo Pre-emphasis and de-emphasis is a technique used by
multiplexed (MPX) signal. The MPX standard was FM broadcasters to improve the signal-to-noise ratio of
developed in 1961, and is used worldwide. Today's FM receivers by reducing the effects of high-frequency
MPX signal format consists of left + right (L+R) audio, interference and noise. When the FM signal is
left – right (L–R) audio, a 19 kHz pilot tone, and transmitted,
a
pre-emphasis filter is applied to
RDS/RBDS data as shown in Figure 13 below.
accentuate the high audio frequencies. The
Si4736/37/38/39 incorporates a de-emphasis filter
which attenuates high frequencies to restore a flat
frequency response. Two time constants are used in
various regions. The de-emphasis time constant is
programmable to 50 or 75 µs and is set by the
FM_DEEMPHASIS property.
Mono Audio
Left + Right
Stereo
Pilot
Stereo Audio
Left - Right
RDS/
RBDS
4.9. Stereo DAC
High-fidelity stereo digital-to-analog converters (DACs)
drive analog audio signals onto the LOUT and ROUT
pins. The audio output may be muted. Volume is
adjusted digitally with the RX_VOLUME property.
0
15 19 23
38
53 57
Frequency (kHz)
Figure 13. MPX Signal Spectrum
4.7.1. Stereo Decoder
4.10. Soft Mute
The Si4736/37/38/39's integrated stereo decoder
automatically decodes the MPX signal using DSP
techniques. The 0 to 15 kHz (L+R) signal is the mono
output of the FM tuner. Stereo is generated from the
(L+R), (L–R), and a 19 kHz pilot tone. The pilot tone is
used as a reference to recover the (L–R) signal. Output
left and right channels are obtained by adding and
subtracting the (L+R) and (L–R) signals respectively.
The Si4737/39 uses frequency information from the
19 kHz stereo pilot to recover the 57 kHz RDS/RBDS
signal.
The soft mute feature is available to attenuate the audio
outputs and minimize audible noise in very weak signal
conditions. The softmute attenuation level is adjustable
using the FM_SOFT_MUTE_MAX_ATTENUATION and
AM_SOFT_MUTE_MAX_ATTENUATION properties.
4.11. RDS/RBDS Processor
(Si4737/39 Only)
The Si4737/39 implements an RDS/RBDS* processor
for symbol decoding, block synchronization, error
detection, and error correction.
4.7.2. Stereo-Mono Blending
The Si4737/39 device is user configurable and provides
an optional interrupt when RDS is synchronized, loses
synchronization, and/or the user configurable RDS
FIFO threshold has been met.
Adaptive noise suppression is employed to gradually
combine the stereo left and right audio channels to a
mono (L+R) audio signal as the signal quality degrades
to maintain optimum sound fidelity under varying
reception conditions. Stereo/mono status can be
monitored with the FM_RSQ_STATUS command. Mono
The Si4737/39 reports RDS decoder synchronization
status, and detailed bit errors in the information word for
each RDS block with the FM_RDS_STATUS command.
operation
can
be
forced
with
the The range of reportable block errors is 0, 1–2, 3–5, or
6+. More than six errors indicates that the
corresponding block information word contains six or
more non-correctable errors, or that the block
checkword contains errors.
FM_BLEND_MONO_THRESHOLD property.
*Note: RDS/RBDS is referred to only as RDS throughout the
remainder of this document.
21
Rev. 1.0
Si4736/37/38/39-B20
which may result in mistunes, false stops, and/or lower
SNR.
4.12. Tuning
The frequency synthesizer uses Silicon Laboratories’
proven technology, including a completely integrated VCO.
The frequency synthesizer generates the quadrature local
oscillator signal used to downconvert the RF input to a low
intermediate frequency. The VCO frequency is locked to
the reference clock and adjusted with an AFC servo loop
during reception. The tuning frequency can be directly
For best seek/tune results, Silicon Laboratories
recommends that all SDIO data traffic be suspended
during Si4736/37/38/39 seek and tune operations. This
is achieved by keeping the bus quiet for all other
devices on the bus, and delaying tuner polling until the
tune or seek operation is complete. The STC (seek/tune
complete) interrupt should be used instead of polling to
determine when a seek/tune operation is complete.
programmed
using
the
WB_TUNE_FREQ,
FM_TUNE_FREQ, and AM_TUNE_FREQ commands.
The Si4736/37/38/39 supports channel spacing of 25 kHz
in WB mode; 50, 100, or 200 kHz in FM mode; and 9 or
10 kHz in AM mode.
4.15. Control Interface
A serial port slave interface is provided, which allows an
external controller to send commands to the
Si4736/37/38/39 and receive responses from the
device. The serial port can operate in three bus modes:
2-wire mode, 3-wire mode, or SPI mode. The
Si4736/37/38/39 selects the bus mode by sampling the
state of the GPO1 and GPO2 pins on the rising edge of
RST. The GPO1 pin includes an internal pull-up resistor,
which is connected while RST is low, and the GPO2 pin
includes an internal pull-down resistor, which is
connected while RST is low. Therefore, it is only
necessary for the user to actively drive pins which differ
from these states. See Table 13.
4.13. Seek
Seek tuning will search up or down for a valid channel.
Valid channels are found when the receive signal
strength indicator (RSSI) and the signal-to-noise ratio
(SNR) values exceed the set threshold. Using the SNR
qualifier rather than solely relying on the more
traditional RSSI qualifier can reduce false stops and
increase the number of valid stations detected. Seek is
initiated
using
the
FM_SEEK_START
and
AM_SEEK_START commands. The RSSI and SNR
threshold settings are adjustable using properties (see
Table 15).
Table 13. Bus Mode Select on Rising Edge of
RST
Two seek options are available. The device will either
wrap or stop at the band limits. If the seek operation is
unable to find a channel, the device will indicate failure
and return to the channel selected before the seek
operation began.
Bus Mode
2-Wire
SPI
GPO1
GPO2
1
0
1
1 (must drive)
0
Seek is not available for weather band.
3-Wire
0 (must drive)
4.14. Reference Clock
The Si4736/37/38/39 reference clock is programmable,
supporting RCLK frequencies in Table 12. Refer to
Table 3, “DC Characteristics,” on page 5 for switching
After the rising edge of RST, the pins GPO1 and GPO2
are used as general purpose output (O) pins, as
described in Section “4.16. GPO Outputs”. In any bus
voltage
levels
and
Table 9,
“FM
Receiver
mode, commands may only be sent after V and V
IO
DD
Characteristics” on page 12 for frequency tolerance
information.
supplies are applied.
In any bus mode, before sending a command or reading
a response, the user must first read the status byte to
ensure that the device is ready (CTS bit is high).
An onboard crystal oscillator is available to generate the
32.768 kHz reference when an external crystal and load
capacitors are provided. Refer to "2. Typical Application
Schematic" on page 16. This mode is enabled using the
POWER_UP command, see Table 14, “Si473x
Command Summary,” on page 25.
4.15.1. 2-Wire Control Interface Mode
When selecting 2-wire mode, the user must ensure that
SCLK is high during the rising edge of RST, and stays
high until after the first start condition. Also, a start
condition must not occur within 300 ns before the rising
edge of RST.
The Si4736/37/38/39 performance may be affected by
data activity on the SDIO bus when using the integrated
internal oscillator. SDIO activity results from polling the
tuner for status or communicating with other devices
that share the SDIO bus. If there is SDIO bus activity
while the Si4736/37/38/39 is performing the seek/tune
function, the crystal oscillator may experience jitter,
The 2-wire bus mode uses only the SCLK and SDIO
pins for signaling. A transaction begins with the START
condition, which occurs when SDIO falls while SCLK is
high. Next, the user drives an 8-bit control word serially
22
Rev. 1.0
Si4736/37/38/39-B20
on SDIO, which is captured by the device on rising the Si4736/37/38/39 will drive the 16-bit read data word
edges of SCLK. The control word consists of a 7-bit serially on SDIO, changing the state of SDIO on each
device address, followed by a read/write bit (read = 1, rising edge of SCLK.
write = 0). The Si4736/37/38/39 acknowledges the
control word by driving SDIO low on the next falling
pulses SCLK high and low one final time. SCLK may
edge of SCLK.
A transaction ends when the user sets SEN high, then
either stop or continue to toggle while SEN is high.
Although the Si4736/37/38/39 will respond to only a
In 3-wire mode, commands are sent by first writing each
single device address, this address can be changed
argument to register(s) 0xA1–0xA3, then writing the
with the SEN pin (note that the SEN pin is not used for
command word to register 0xA0. A response is
signaling in 2-wire mode). When SEN = 0, the 7-bit
retrieved by reading registers 0xA8–0xAF.
device address is 0010001b. When SEN = 1, the
For details on timing specifications and diagrams, refer
address is 1100011b.
to Table 6, “3-Wire Control Interface Characteristics,” on
For write operations, the user then sends an 8-bit data
page 9; Figure 4, “3-Wire Control Interface Write Timing
byte on SDIO, which is captured by the device on rising
Parameters,” on page 9, and Figure 5, “3-Wire Control
edges of SCLK. The Si4736/37/38/39 acknowledges
Interface Read Timing Parameters,” on page 9.
each data byte by driving SDIO low for one cycle, on the
4.15.3. SPI Control Interface Mode
next falling edge of SCLK. The user may write up to 8
When selecting SPI mode, the user must ensure that a
data bytes in a single 2-wire transaction. The first byte is
rising edge of SCLK does not occur within 300 ns
a command, and the next seven bytes are arguments.
before the rising edge of RST.
For read operations, after the Si4736/37/38/39 has
acknowledged the control byte, it will drive an 8-bit data SPI bus mode uses the SCLK, SDIO, and SEN pins for
byte on SDIO, changing the state of SDIO on the falling read/write operations. The system controller can
edge of SCLK. The user acknowledges each data byte choose to receive read data from the device on either
by driving SDIO low for one cycle, on the next falling SDIO or GPO1. A transaction begins when the system
edge of SCLK. If a data byte is not acknowledged, the controller drives SEN = 0. The system controller then
transaction will end. The user may read up to 16 data pulses SCLK eight times, while driving an 8-bit control
bytes in a single 2-wire transaction. These bytes contain byte serially on SDIO. The device captures the data on
the response data from the Si4736/37/38/39.
rising edges of SCLK. The control byte must have one
of five values:
A 2-wire transaction ends with the STOP condition,
which occurs when SDIO rises while SCLK is high.
0x48 = write a command (controller drives 8
additional bytes on SDIO).
For details on timing specifications and diagrams, refer
to Table 5, “2-Wire Control Interface Characteristics” on 0x80 = read a response (device drives 1additional
page 7; Figure 2, “2-Wire Control Interface Read and
Write Timing Parameters,” on page 8, and Figure 3, “2-
Wire Control Interface Read and Write Timing Diagram,”
on page 8.
byte on SDIO).
0xC0 = read a response (device drives 16 additional
bytes on SDIO).
0xA0 = read a response (device drives 1 additional
4.15.2. 3-Wire Control Interface Mode
byte on GPO1).
When selecting 3-wire mode, the user must ensure that 0xE0 = read a response (device drives 16 additional
a rising edge of SCLK does not occur within 300 ns
before the rising edge of RST.
bytes on GPO1).
For write operations, the system controller must drive
exactly 8 data bytes (a command and seven arguments)
on SDIO after the control byte. The data is captured by
the device on the rising edge of SCLK.
The 3-wire bus mode uses the SCLK, SDIO, and SEN_
pins. A transaction begins when the user drives SEN
low. Next, the user drives a 9-bit control word on SDIO,
which is captured by the device on rising edges of
SCLK. The control word consists of a 9-bit device
address (A7:A5 = 101b), a read/write bit (read = 1, write
= 0), and a 5-bit register address (A4:A0).
For read operations, the controller must read exactly 1
byte (STATUS) after the control byte or exactly 16 data
bytes (STATUS and RESP1–RESP15) after the control
byte. The device changes the state of SDIO (or GPO1, if
specified) on the falling edge of SCLK. Data must be
captured by the system controller on the rising edge of
SCLK.
For write operations, the control word is followed by a
16-bit data word, which is captured by the device on
rising edges of SCLK.
For read operations, the control word is followed by a
delay of one-half SCLK cycle for bus turn-around. Next,
Keep SEN low until all bytes have transferred. A
transaction may be aborted at any time by setting SEN
23
Rev. 1.0
Si4736/37/38/39-B20
high and toggling SCLK high and then low. Commands
will be ignored by the device if the transaction is
aborted.
4.19. Programming with Commands
To ease development time and offer maximum
customization, the Si4736/37/38/39 provides a simple
For details on timing specifications and diagrams, refer yet powerful software interface to program the receiver.
to Figure 6 and Figure 7 on page 10.
The device is programmed using commands,
arguments, properties and responses.
4.16. GPO Outputs
To perform an action, the user writes a command byte
and associated arguments causing the chip to execute
the given command. Commands control an action such
as power up the device, shut down the device, or tune
to a station. Arguments are specific to a given command
and are used to modify the command. A complete list of
commands is available in Table 14, “Si473x Command
Summary,” on page 25.
The Si4736/37/38/39 provides three general-purpose
output pins. The GPO pins can be configured to output
a constant low, constant high, or high-impedance. The
GPO pins can be reconfigured as specialized functions.
GPO2/INT can be configured to provide interrupts and
GPO3 can be configured to provide external crystal
support or as DCLK in digital audio output mode. In
digital output mode (Si4737/39 only), pin 16 and pin 17
can be configured as DFS and DOUT, respectively.
Properties are a special command argument used to
modify the default chip operation and are generally
configured immediately after power up. Examples of
properties are de-emphasis level, RSSI seek threshold,
and soft mute attenuation threshold. A complete list of
properties is available in Table 15, “Si473x Property
Summary,” on page 26.
4.17. Firmware Upgrades
The Si4736/37/38/39 contains on-chip program RAM to
accommodate minor changes to the firmware. This
allows Silicon Laboratories to provide future firmware
updates to optimize the characteristics of new radio
designs and those already deployed in the field.
Responses provide the user information and are
echoed after a command and associated arguments are
issued. All commands provide a one-byte status update
indicating interrupt and clear-to-send status information.
For a detailed description of the commands and
properties for the Si4736/37/38/39, see “AN332:
Universal Programming Guide.”
4.18. Reset, Power Up, and Power Down
Setting the RST pin low will disable analog and digital
circuitry, reset the registers to their default settings, and
disable the bus. Setting the RST pin high will bring the
device out of reset.
A power down mode is available to reduce power
consumption when the part is idle. Putting the device in
power down mode will disable analog and digital
circuitry while keeping the bus active.
24
Rev. 1.0
Si4736/37/38/39-B20
5. Commands and Properties
Table 14. Si473x Command Summary
Cmd
Name
Description
Power up device and mode selection. Modes include AM or FM receive,
analog or digital output, and reference clock or crystal support.
0x01
POWER_UP
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x20
0x21
GET_REV
Returns revision information on the device.
Power down device.
POWER_DOWN
SET_PROPERTY
GET_PROPERTY
GET_INT_STATUS
PATCH_ARGS
Sets the value of a property.
Retrieves a property’s value.
Read interrupt status bits.
Reserved command used for firmware file downloads.
Reserved command used for firmware file downloads.
Selects the FM tuning frequency.
Begins searching for a valid frequency.
PATCH_DATA
FM_TUNE_FREQ
FM_SEEK_START
Queries the status of previous FM_TUNE_FREQ or FM_SEEK_START
command.
0x22
0x23
0x24
FM_TUNE_STATUS
FM_RSQ_STATUS
FM_RDS_STATUS
Queries the status of the Received Signal Quality (RSQ) of the current
channel.
Returns RDS information for current channel and reads an entry from the
RDS FIFO (Si4737/39 only).
0x40
0x41
AM_TUNE_FREQ
AM_SEEK_START
Tunes to a given AM frequency.
Begins searching for a valid frequency.
Queries the status of the already issued AM_TUNE_FREQ or AM_-
SEEK_START command.
0x42
AM_TUNE_STATUS
0x43
0x50
0x52
AM_RSQ_STATUS
WB_TUNE_FREQ
WB_TUNE_STATUS
Queries the status of the RSQ for the current channel.
Selects the WB tuning frequency.
Queries the status of the previous WB_TUNE_FREQ command.
Queries the status of the Received Signal Quality (RSQ) of the current chan-
nel.
0x53
WB_RSQ_STATUS
0x55
0x57
0x58
0x80
0x81
WB_ASQ_STATUS
WB_AGC_STATUS
Queries the status of the 1050 Hz alert tone.
Queries the status of the AGC.
WB_AGC_OVERRIDE Enable or disable the WB AGC.
GPO_CTL
GPO_SET
Configures GPO3 as output or Hi-Z.
Sets GPO3 output level (low or high).
Rev. 1.0
25
Si4736/37/38/39-B20
Table 15. Si473x Property Summary
Prop
Name
Description
Enables interrupt sources.
Default
0x0000
0x0000
0x0001
GPO_IEN
0x0102 DIGITAL_OUTPUT_FORMAT Configures the digital output format (Si4737/39 only).
Configures the digital output sample rate in 100 Hz steps. The
DIGITAL_OUTPUT_
SAMPLE_RATE
0x0104
digital output sample rate is disabled by default (Si4737/39
only).
0x0000
Sets frequency of reference clock in Hz. The range is 31130 to
34406 Hz, or 0 to disable the AFC. Default is 32768 Hz.
0x0201
REFCLK_FREQ
0x8000
0x0202
0x1100
REFCLK_PRESCALE
FM_DEEMPHASIS
Sets the prescaler value for RCLK input.
0x0001
0x0002
Sets de-emphasis time constant. Default is 75 us.
Sets RSSI threshold for stereo blend (Full stereo above thresh-
old, blend below threshold). To force stereo set this to 0. To
force mono set this to 127. Default value is 49 dBuV.
FM_BLEND_STEREO_
THRESHOLD
0x1105
0x1106
0x0031
0x001E
Sets RSSI threshold for mono blend (full mono below threshold,
blend above threshold). To force stereo set this to 0. To force
mono set this to 127. Default value is 30 dBuV.
FM_BLEND_MONO_
THRESHOLD
FM_MAX_TUNE_
ERROR
Sets the maximum freq error allowed before setting the AFC rail
(AFCRL) indicator. Default value is 30 kHz.
0x1108
0x1200
0x1201
0x1202
0x1203
0x1204
0x1207
0x1300
0x1302
0x1303
0x001E
0x0000
0x007F
0x0000
0x007F
0x0000
0x0081
0x0040
0x0010
0x0004
FM_RSQ_INT_
SOURCE
Configures interrupt related to RSQ metrics.
Sets high threshold for SNR interrupt.
Sets low threshold for SNR interrupt.
Sets high threshold for RSSI interrupt.
Sets low threshold for RSSI interrupt.
FM_RSQ_SNR_HI_
THRESHOLD
FM_RSQ_SNR_LO_
THRESHOLD
FM_RSQ_RSSI_HI_
THRESHOLD
FM_RSQ_RSSI_LO_
THRESHOLD
FM_RSQ_BLEND_
THRESHOLD
Sets the blend threshold for blend interrupt when boundary is
crossed.
Sets the attack and decay rates when entering and leaving soft
mute.
FM_SOFT_MUTE_RATE
FM_SOFT_MUTE_
MAX_ATTENUATION
Sets maximum attenuation during soft mute (dB). Set to 0 to dis-
able soft mute. Default is 16 dB.
FM_SOFT_MUTE_
SNR_THRESHOLD
Sets SNR threshold to engage soft mute. Default is 4 dB.
FM_SEEK_BAND_
BOTTOM
0x1400
0x1401
0x1402
Sets the bottom of the FM band for seek. Default is 8750.
Sets the top of the FM band for seek. Default is 10790.
Selects frequency spacing for FM seek.
0x222E
0x2A26
0x000A
FM_SEEK_BAND_TOP
FM_SEEK_FREQ_
SPACING
FM_SEEK_TUNE_
SNR_THRESHOLD
Sets the SNR threshold for a valid FM Seek/Tune. Default value
is 3 dB.
0x1403
0x1404
0x0003
0x0014
FM_SEEK_TUNE_
RSSI_TRESHOLD
Sets the RSSI threshold for a valid FM Seek/Tune. Default
value is 20 dBuV.
26
Rev. 1.0
Si4736/37/38/39-B20
Table 15. Si473x Property Summary (Continued)
Prop
Name
Description
Default
0x1500
RDS_INT_SOURCE
Configures RDS interrupt behavior.
0x0000
Sets the minimum number of RDS groups stored in the receive
RDS FIFO required before RDS RECV is set.
0x1501
0x1502
0x3100
RDS_INT_FIFO_COUNT
RDS_CONFIG
0x0000
0x0000
0x0000
Configures RDS setting.
Sets de-emphasis time constant. Can be set to 50 us. De-
emphasis is disabled by default.
AM_DEEMPHASIS
Selects the bandwidth of the channel filter for AM reception. The
choices are 6, 4, 3, or 2 (kHz). The default bandwidth is 2 kHz.
0x3102
0x3200
0x3201
0x3202
0x3203
0x3204
AM_CHANNEL_FILTER
AM_RSQ_INTERRUPTS
0x0003
0x0000
0x0000
0x0000
0x0000
0x0000
0x0040
0x0002
0x0010
0x000A
0x0208
0x06AE
0x000A
Configures interrupt related to RSQ metrics. All interrupts are
disabled by default.
AM_RSQ_SNR_HIGH_
THRESHOLD
Sets high threshold for SNR interrupt. The default is 0 dB.
Sets low threshold for SNR interrupt. The default is 0 dB.
Sets high threshold for RSSI interrupt. The default is 0 dB.
Sets low threshold for RSSI interrupt. The default is 0 dB.
AM_RSQ_SNR_LOW_
THRESHOLD
AM_RSQ_RSSI_HIGH_
THRESHOLD
AM_RSQ_RSSI_LOW_
THRESHOLD
Sets the rate of attack when entering or leaving soft mute. The
default is 278 dB/s.
0x3300 AM_SOFT_MUTE_RATE
0x3301 AM_SOFT_MUTE_SLOPE
Sets the AM soft mute slope. The bigger the number, the higher
the max attenuation level. Default value is a slope of 2.
AM_SOFT_MUTE_MAX_ Sets maximum attenuation during soft mute (dB). Set to 0 to dis-
0x3302
0x3303
0x3400
0x3401
0x3402
ATTENUATION
able soft mute. Default is 16 dB.
AM_SOFT_MUTE_SNR_
THRESHOLD
Sets SNR threshold to engage soft mute. Default is 10 dB.
AM_SEEK_BAND_
BOTTOM
Sets the bottom of the AM band for seek. Default is 520.
Sets the top of the AM band for seek. Firmware 1.0 incorrectly
defaults to 1721 kHz instead of 1710.
AM_SEEK_BAND_TOP
AM_SEEK_FREQ_
SPACING
Selects frequency spacing for AM seek. Default is 10 kHz spac-
ing.
Sets the SNR threshold for a valid AM Seek/Tune. If the value is
zero then SNR threshold is not considered when doing a seek. 0x0005
Default value is 5 dB.
AM_SEEK_SNR_
THRESHOLD
0x3403
0x3404
Sets the RSSI threshold for a valid AM Seek/Tune. If the value
is zero then RSSI threshold is not considered when doing a
seek. Default value is 25 dBuV.
AM_SEEK_RSSI_
THRESHOLD
0x0019
0x4000
0x4001
RX_VOLUME
Sets the output volume.
0x003F
0x0000
Mutes the audio output. L and R audio outputs may be muted
independently in FM mode.
RX_HARD_MUTE
Maximum change in frequencies from the WB_TUNE_FREQ to
which the AFC will lock.
0x5108 WB_MAX_TUNE_ERROR
0x000F
Rev. 1.0
27
Si4736/37/38/39-B20
Table 15. Si473x Property Summary (Continued)
Prop
Name
Description
Default
WB_RSQ_INTERRUPT_
SOURCE
Configures interrupts related to RSQ metrics. All interrupts are
disabled by default.
0x5200
0x0000
WB_RSQ_SNR_HIGH_
THRESHOLD
0x5201
0x5202
0x5203
0x5204
0x5600
Sets high threshold for SNR interrupt. The default is 0 dB.
Sets low threshold for SNR interrupt. The default is 0 dB.
Sets high threshold for RSSI interrupt. The default is 0 dB.
Sets low threshold for RSSI interrupt. The default is 0 dB.
0x007F
0x0000
0x007F
0x0000
0x0000
WB_RSQ_SNR_LOW_
THRESHOLD
WB_RSQ_RSSI_HIGH_
THRESHOLD
WB_RSQ_RSSI_LOW_
THRESHOLD
WB_ASQ_INTERRUPT_
SOURCE
Configures 1050 Hz alert tone interrupts. All interrupts are dis-
abled by default.
28
Rev. 1.0
Si4736/37/38/39-B20
6. Pin Descriptions: Si4736/37/38/39-GM
20 19 18 17
NC
1
16
FMI 2
RFGND 3
AMI 4
15 DOUT
14 LOUT
13 ROUT
12 GND
GND
PAD
RST 5
6
11 VDD
7
8
9
10
Pin Number(s)
Name
NC
Description
1, 20
No connect. Leave floating.
2
FMI
FM/WB RF inputs. FMI should be connected to the antenna trace.
RF ground. Connect to ground plane on PCB.
AM RF input. AMI should be connected to the AM antenna.
Device reset (active low) input.
3
RFGND
AMI
4
5
RST
6
SEN
Serial enable input (active low).
7
SCLK
SDIO
RCLK
Serial clock input.
8
Serial data input/output.
9
External reference oscillator input.
10
V
I/O supply voltage.
IO
11
V
Supply voltage. May be connected directly to battery.
Ground. Connect to ground plane on PCB.
Right audio line output in analog output mode.
Left audio line output in analog output mode.
Digital output data in digital output mode.
Digital frame synchronization input in digital output mode.
DD
12, GND PAD
GND
ROUT
LOUT
DOUT
DFS
13
14
15
16
17
GPO3/DCLK General purpose output, crystal oscillator, or digital bit synchronous clock input
in digital output mode.
18
19
GPO2/INT
GPO1
General purpose output or interrupt pin.
General purpose output.
Rev. 1.0
29
Si4736/37/38/39-B20
7. Ordering Guide
Part Number*
Description
Package
Type
Operating
Temperature
Si4736-B20-GM AM/FM/WB Broadcast Radio Receiver
QFN
Pb-free
–20 to 85 °C
–20 to 85 °C
Si4737-B20-GM AM/FM/WB Broadcast Radio Receiver with
RDS/RBDS
QFN
Pb-free
Si4738-B20-GM FM/WB Broadcast Radio Receiver
QFN Pb-free
QFN Pb-free
–20 to 85 °C
–20 to 85 °C
Si4739-B20-GM FM/WB Broadcast Radio Receiver with RDS/RBDS
*Note: Add an “(R)” at the end of the device part number to denote tape and reel option; 2500 quantity per reel.
30
Rev. 1.0
Si4736/37/38/39-B20
8. Package Markings (Top Marks)
8.1. Top Mark
3620
BTTT
YWW
3820 3920
BTTT BTTT
3720
BTTT
YWW
YWW
YWW
8.2. Top Mark Explanation
Mark Method:
YAG Laser
Line 1 Marking:
Part Number
36 = Si4736, 37 = Si4737, 38 = Si4738, 39 = Si4739
20 = Firmware Revision 2.0
B = Revision B Die
Firmware Revision
Die Revision
Line 2 Marking:
Line 3 Marking:
TTT = Internal Code
Internal tracking code
Circle = 0.5 mm Diameter Pin 1 Identifier
(Bottom-Left Justified)
Y = Year
Assigned by the Assembly House. Corresponds to the last sig-
nificant digit of the year and workweek of the mold date.
WW = Workweek
Rev. 1.0
31
Si4736/37/38/39-B20
9. Package Outline: Si4736/37/38/39 QFN
Figure 14 illustrates the package details for the Si4736/37/38/39. Table 16 lists the values for the dimensions
shown in the illustration.
Figure 14. 20-Pin Quad Flat No-Lead (QFN)
Table 16. Package Dimensions
Symbol
Millimeters
Nom
Symbol
Millimeters
Nom
Min
Max
Min
Max
A
A1
b
0.50
0.00
0.20
0.27
0.55
0.02
0.60
0.05
0.30
0.37
f
2.53 BSC
L
0.35
0.00
—
0.40
—
0.45
0.10
0.05
0.05
0.08
0.10
0.10
0.25
L1
c
0.32
aaa
bbb
ccc
ddd
eee
—
D
3.00 BSC
1.70
—
—
D2
e
1.65
1.75
—
—
0.50 BSC
3.00 BSC
1.70
—
—
E
—
—
E2
1.65
1.75
Notes:
1. All dimensions are shown in millimeters (mm) unless otherwise noted.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
32
Rev. 1.0
Si4736/37/38/39-B20
10. PCB Land Pattern: Si4736/37/38/39 QFN
Figure 15 illustrates the PCB land pattern details for the Si4736/37/38/39-GM. Table 17 lists the values for the
dimensions shown in the illustration.
Figure 15. PCB Land Pattern
Rev. 1.0
33
Si4736/37/38/39-B20
Table 17. PCB Land Pattern Dimensions
Symbol
Millimeters
Min Max
2.71 REF
1.60 1.80
Symbol
Millimeters
Min
Max
D
D2
e
GE
W
2.10
—
—
0.34
0.28
0.50 BSC
2.71 REF
X
—
E
Y
0.61 REF
E2
f
1.60
2.53 BSC
2.10
1.80
ZE
ZD
—
—
3.31
3.31
GD
—
Notes: General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on IPC-SM-782 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material
Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
Notes: Solder Mask Design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the
solder mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Notes: Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should
be used to assure good solder paste release.
2. The stencil thickness should be 0.125mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.
4. A 1.45 x 1.45 mm square aperture should be used for the center pad. This provides
approximately 70% solder paste coverage on the pad, which is optimum to assure
correct component stand-off.
Notes: Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C
specification for Small Body Components.
34
Rev. 1.0
Si4736/37/38/39-B20
11. Additional Reference Resources
EN55020 Compliance Test Certificate
AN231: Si4700/01 Headphone and Antenna Interface
AN332: Universal Programming Guide
AN383: Universal Antenna Selection and Layout Guidelines
AN386: Si473x Ferrite Loop Stick Antenna Interface
AN388: Si473x AM/FM Tuner Evaluation Board Test Procedure
AN389: Si473x EVB Quick-Start Guide
Si47xx Customer Support Site: http://www.mysilabs.com
This site contains all application notes, evaluation board schematics and layouts, and evaluation software. NDA
is required for access. To request access, register at http://www.mysilabs.com and send user’s first and last
name, company, NDA reference number, and mysilabs user name to fminfo@silabs.com. Silicon Labs
recommends an all lower case user name.
Rev. 1.0
35
Si4736/37/38/39-B20
DOCUMENT CHANGE LIST
Revision 0.4 to Revision 0.5
Updated Table 3, “DC Characteristics,” on page 5.
Updated Table 5, “2-Wire Control Interface
1,2,3
Characteristics
,” on page 7.
Updated Table 8, “Digital Audio Interface
Characteristics,” on page 11.
1,2
Updated Table 9, “FM Receiver Characteristics ,”
on page 12.
1
Updated Table 10, “WB Receiver Characteristics ,”
on page 13.
1
Updated Table 11, “AM Receiver Characteristics ,”
on page 14.
Updated Table 12, “Reference Clock and Crystal
Characteristics,” on page 15.
Updated "3. Bill of Materials" on page 17.
Added GPO_CTL and GPO_SET commands to
Table 13, “Bus Mode Select on Rising Edge of RST,”
on page 22.
Updated "11. Additional Reference Resources" on
page 35..
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NOTES:
Rev. 1.0
37
Si4736/37/38/39-B20
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