SI53019-A01AGMR_技术文档

Si53019-A01A

19-OUTPUT PCIE GEN 3 BUFFER

Features

 Nineteen 0.7 V current-mode,



Spread spectrum tolerable

HCSL PCIe Gen 3 outputs

 50 ps output-to-output skew

 100 MHz /133 MHz PLL

operation, supports PCIe and

QPI

 Fixed 0 ps input to output delay

 Low phase jitter (Intel QPI, PCIe

Gen 1/Gen 2/Gen 3/Gen 4

common clock compliant

 PLL bandwidth SW SMBUS

programming overrides the latch

value from HW pin

 Gen 3 SRNS Compliant

 100 ps input-to-output delay

 9 selectable SMBus addresses

 Fixed external feedback path

 8 dedicated OE pin

 Extended Temperature:

–40 to 85 °C

Ordering Information:

 Package: 72-pin QFN

See page 32.

 PLL or bypass mode

Applications

Pin Assignments

 Server

 Data Center

 Storage

 Network Security

Description

The Si53019-A01A is a 19-output, current mode HCSL differential clock

buffer that meets all of the performance requirements of the Intel

DB1900Z specification. The device is optimized for distributing reference

®

clocks for Intel QuickPath Interconnect (Intel QPI), PCIe Gen 1/Gen 2/

Gen 3/Gen 4, SAS, SATA, and Intel Scalable Memory Interconnect (Intel

SMI) applications. The VCO of the device is optimized to support

100 MHz and 133 MHz operation. Each differential output can be enabled

2

through I C for maximum flexibility and power savings. Measuring PCIe

clock jitter is quick and easy with the Silicon Labs PCIe Clock Jitter Tool.

Download it for free at www.silabs.com/pcie-learningcenter.

Patents pending

Rev. 1.5 7/17

Si53019-A01A

Functional Block Diagram

2

Rev. 1.5

Si53019-A01A

TABLE OF CONTENTS

Section

Page

1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

2.1. CLK_IN, CLK_IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

2.2. 100M_133M—Frequency Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

2.3. SA_0, SA_1—Address Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

2.4. CKPWRGD/PWRDN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

2.5. HBW_BYPASS_LBW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

2.6. Miscellaneous Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

3. Test and Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

3.1. Input Edge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

3.2. Termination of Differential Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

4. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

4.1. Byte Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

4.2. Block Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

4.3. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

5. Pin Descriptions: 72-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

6. Power Filtering Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

6.1. Ferrite Bead Power Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

8. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

9. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

9.1. 10x10 mm 72-QFN Package Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Rev. 1.5

3

Si53019-A01A

1. Electrical Specifications

1

Table 1. DC Operating Characteristics

V_{DD_A}= 3.3 V±5%, V_DD= 3.3 V±5%

Parameter

Symbol

VDD/VDD_A

Test Condition

Min

3.135

2.0

Max

Unit

V

3.3 V Core Supply Voltage

3.3 V Input High Voltage

3.3 V Input Low Voltage

3.3 V ±5%

3.465

V

+0.3

DD

V

IH

DD

V

VSS–0.3

–5

0.8

+5

+0.3

V

IL

2

Input Leakage Current

I

0 < VIN < V

μA

V

IL

DD

3

3.3 V Input High Voltage

V

0.7

V

IH_FS

DD

3

3.3 V Input Low Voltage

V

VSS–0.3

0

0.35

0.9

V

IL_FS

3.3 V Input Low Voltage

3.3 V Input Med Voltage

3.3 V Input High Voltage

V

IL_Tri

V

1.3

1.8

V

IM_Tri

V

2.4

V

IH_Tri

DD

4

3.3 V Output High Voltage

V

I

= –1 mA

= 1 mA

OL

2.4

—

V

OH

4

3.3 V Output Low Voltage

V

I

—

0.4

4.5

7

V

OL

5

Input Capacitance

C

2.5

pF

nH

°C

IN

5

Output Capacitance

C

2.5

OUT

Pin Inductance

Ambient Temperature

Notes:

L

—

T

No Airflow

–40

85

A

1. VDD_IO applies to the low-power NMOS push-pull HCSL compatible outputs.

2. Input Leakage Current does not include inputs with pull-up or pull-down resistors. Inputs with resistors should state

current requirements.

3. Internal voltage reference is to be used to guarantee V_IH_FS and V_IL_FS thresholds levels over full operating range.

4. Signal edge is required to be monotonic when transitioning through this region.

5. Ccomp capacitance based on pad metallization and silicon device capacitance. Not including pin capacitance.

4

Rev. 1.5

Si53019-A01A

1

Table 2. DIF 0.7 V AC Timing Characteristics (Non-Spread Spectrum Mode)

Parameter

Symbol

CLK 100 MHz, 133 MHz

Unit

Min

Typ

1.5

—

Max

2

Clock Stabilization Time

T

—

1.8

100

ms

ppm

ns

STAB

3,4,5

Long Term Accuracy

L

ACC

3,4,6

Absolute Host CLK Period (100 MHz)

Absolute Host CLK Period (133 MHz)

T

9.94900

7.44925

1.0

—

10.05100

7.55075

4.0

ABS

T

ns

ABS

3,4,7

Slew Rate

Edge_rate

3.0

7

V/ns

%

3,8,10,11

Slew Rate Matching

T

/

—

20

RISE_MAT

T

FALL_MAT

3,8,9

Rise Time Variation

∆ Trise

∆ Tfall

—

125

850

150

ps

3,8,9

Fall Time Variation

3,8,12

Voltage High (typ 0.7 V)

V

660

–150

750

15

mV

HIGH

3,8,13

Voltage Low (typ 0.7 V)

V

LOW

Notes:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. This is the time from the valid CLK_IN input clocks and the assertion of the PWRGD signal level at 1.8–2.0 V to the

time that stable clocks are output from the buffer chip (PLL locked).

3. Test configuration is Rs = 33.2 , Rp = 49.9, 2 pF for 100  transmission line; Rs = 27 , Rp = 42.2, 2 pF for 85 

transmission line.

4. Measurement taken from differential waveform.

5. Using frequency counter with the measurement interval equal or greater than 0.15 s, target frequencies are

99,750,00 Hz, 133,000,000 Hz.

6. The average period over any 1 μs period of time must be greater than the minimum and less than the maximum

specified period.

7. Measure taken from differential waveform on a component test board. The edge (slew) rate is measured from –150 mV

to +150 mV on the differential waveform. Scope is set to average because the scope sample clock is making most of

the dynamic wiggles along the clock edge Only valid for Rising CLOCK and Falling CLOCK. Signal must be monotonic

through the Vol to Voh region for Trise and Tfall.

8. Measurement taken from single-ended waveform.

9. Measured with oscilloscope, averaging off, using min max statistics. Variation is the delta between min and max.

10. Measured with oscilloscope, averaging on, The difference between the rising edge rate (average) of clock verses the

falling edge rate (average) of CLOCK.

11. Rise/Fall matching is derived using the following, 2*(Trise - Tfall) / (Trise + Tfall).

12. VHigh is defined as the statistical average High value as obtained by using the Oscilloscope VHigh Math function.

13. VLow is defined as the statistical average Low value as obtained by using the Oscilloscope VLow Math function.

14. Measured at crossing point where the instantaneous voltage value of the rising edge of CLK equals the falling edge of

CLK.

15. This measurement refers to the total variation from the lowest crossing point to the highest, regardless of which edge is

crossing.

16. The crossing point must meet the absolute and relative crossing point specifications simultaneously.

17. Vcross(rel) Min and Max are derived using the following, Vcross(rel) Min = 0.250 + 0.5 (Vhavg – 0.700), Vcross(rel)

Max = 0.550 – 0.5 (0.700 – Vhavg), (see Figure 4–5 for further clarification).

18. Vcross is defined as the total variation of all crossing voltages of Rising CLOCK and Falling CLOCK. This is the

maximum allowed variance in Vcross for any particular system.

19. Overshoot is defined as the absolute value of the maximum voltage.

20. Undershoot is defined as the absolute value of the minimum voltage.

Rev. 1.5

5

Si53019-A01A

1

Table 2. DIF 0.7 V AC Timing Characteristics (Non-Spread Spectrum Mode) (Continued)

Parameter

Symbol

CLK 100 MHz, 133 MHz

Unit

Min

Typ

850

—

Max

8

Maximum Voltage

V

—

–300

250

—

1150

—

mV

MAX

3,8,14,15,16

Minimum Voltage

V

MIN

Absolute Crossing Point Voltages

Total Variation of Vcross Over All

Vox

450

14

550

140

ABS

Total ∆ Vox

3,8,18

Edges

4

Vswing

DC

300

45

—

mV

%

V

3,4

Duty Cycle

55

3,8,19

Maximum Voltage (Overshoot)

Maximum Voltage (Undershoot)

V

—

V

+ 0.3

ovs

High

3,8,20

V

—

V

– 0.3

Low

V

uds

3,8

Ringback Voltage

V

0.2

N/A

V

rb

Notes:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. This is the time from the valid CLK_IN input clocks and the assertion of the PWRGD signal level at 1.8–2.0 V to the

time that stable clocks are output from the buffer chip (PLL locked).

3. Test configuration is Rs = 33.2 , Rp = 49.9, 2 pF for 100  transmission line; Rs = 27 , Rp = 42.2, 2 pF for 85 

transmission line.

4. Measurement taken from differential waveform.

5. Using frequency counter with the measurement interval equal or greater than 0.15 s, target frequencies are

99,750,00 Hz, 133,000,000 Hz.

6. The average period over any 1 μs period of time must be greater than the minimum and less than the maximum

specified period.

7. Measure taken from differential waveform on a component test board. The edge (slew) rate is measured from –150 mV

to +150 mV on the differential waveform. Scope is set to average because the scope sample clock is making most of

the dynamic wiggles along the clock edge Only valid for Rising CLOCK and Falling CLOCK. Signal must be monotonic

through the Vol to Voh region for Trise and Tfall.

8. Measurement taken from single-ended waveform.

9. Measured with oscilloscope, averaging off, using min max statistics. Variation is the delta between min and max.

10. Measured with oscilloscope, averaging on, The difference between the rising edge rate (average) of clock verses the

falling edge rate (average) of CLOCK.

11. Rise/Fall matching is derived using the following, 2*(Trise - Tfall) / (Trise + Tfall).

12. VHigh is defined as the statistical average High value as obtained by using the Oscilloscope VHigh Math function.

13. VLow is defined as the statistical average Low value as obtained by using the Oscilloscope VLow Math function.

14. Measured at crossing point where the instantaneous voltage value of the rising edge of CLK equals the falling edge of

CLK.

15. This measurement refers to the total variation from the lowest crossing point to the highest, regardless of which edge is

crossing.

16. The crossing point must meet the absolute and relative crossing point specifications simultaneously.

17. Vcross(rel) Min and Max are derived using the following, Vcross(rel) Min = 0.250 + 0.5 (Vhavg – 0.700), Vcross(rel)

Max = 0.550 – 0.5 (0.700 – Vhavg), (see Figure 4–5 for further clarification).

18. Vcross is defined as the total variation of all crossing voltages of Rising CLOCK and Falling CLOCK. This is the

maximum allowed variance in Vcross for any particular system.

19. Overshoot is defined as the absolute value of the maximum voltage.

20. Undershoot is defined as the absolute value of the minimum voltage.

6

Rev. 1.5

Si53019-A01A

Table 3. SMBus Characteristics

Parameter

Symbol

Test Condition

Min

—

Max

Unit

V

1

SMBus Input Low Voltage

V

0.8

ILSMB

IHSMB

1

SMBus Input High Voltage

V

2.1

—

V

DDSMB

1

SMBus Output Low Voltage

V

@ I

0.4

V

OLSMB

DDSMB

PULLUP

1

Nominal Bus Voltage

V

@ V

2.7

4

5.5

—

V

OL

1

SMBus sink Current

I

3 V to 5 V +/–10%

(Max V – 0.15) to (Min V + 0.15)

mA

ns

kHz

1

SCLK/SDAT Rise Time

t

—

1000

300

100

RSMB

IL

IH

1

SCLK/SDAT Fall Time

t

(Min V + 0.15) to (Max V – 0.15)

—

FSMB

IH

IL

1,2

SMBus Operating Frequency

f

Minimum Operating Frequency

—

MINSMB

Notes:

1. Guaranteed by design and characterization.

2. The differential input clock must be running for the SMBus to be active.

Table 4. Current Consumption

T_A= -40–85 °C; supply voltage V_DD= 3.3 V ±5%

Parameter

Symbol

Test Condition

Min

—

Typ

Max

350

15

Unit

mA

Operating Current

IDD

100 MHz, CL = Full Load, Rs=33 

All differential pairs tri-stated

310

6

VDD

Power Down Current IDD

—

VDDPD

Rev. 1.5

7

Si53019-A01A

Table 5. Clock Input Parameters

T_A= -40–85 °C; supply voltage V_DD= 3.3 V ±5%

Parameter

Symbol

Test Condition

Differential Inputs

Min

Typ

Max

Unit

Input High Voltage

V

600

800

1150

mV

IHDIF

(singled-ended measurement)

Input Low Voltage

V

Differential Inputs

(singled-ended measurement)

Vss-300

300

0

300

mV

IHDIF

Input Common Mode

Voltage

V

Common mode input voltage

—

1000

com

Input Amplitude

Input Slew Rate

Input Duty Cycle

V

Peak to Peak Value

300

0.4

45

—

50

1900

8

mV

V/ns

%

swing

dv/dt

Measured differentially

Measurement from differential wave

form

55

Input Jitter—Cycle to

Cycle

J

Differential measurement

—

125

ps

DFin

Input Frequency

F

V

= 3.3 V, bypass mode

33

90

—

100

150

110

147

33

MHz

kHz

ibyp

DD

F

= 3.3 V, 100 MHz PLL Mode

= 3.3 V, 133.33 MHz PLL Mode

iPLL

FiPLL

120

30

133.33

31.5

Input SS Modulation

Rate

f

Triangle Wave modulation

MODIN

8

Rev. 1.5

Si53019-A01A

Table 6. Output Skew, PLL Bandwidth and Peaking

T_A= -40–85 °C; supply voltage V_DD= 3.3 V ±5%

Parameter

Test Condition

Min

TYP

Max

Unit

CLK_IN, DIF[x:0]

Input-to-Output Delay in PLL Mode

Nominal Value

–100

20

100

ps

1,2,3,4

CLK_IN, DIF[x:0]

Input-to-Output Delay in Bypass Mode

Nominal Value

2.5

–50

–250

—

3.4

0

4.5

50

250

75

5

ns

ps

2,4,5

Input-to-Output Delay Variation in PLL Mode

2,4,5

Over voltage and temperature

Input-to-Output Delay Variation in Bypass Mode

—

15

3

2,4,5

Over voltage and temperature

Random differential spread spectrum tracking

error between 2 DB1900Z devices in Hi BW Mode

Random differential tracking error between 2

DB1900Z devices in Hi BW Mode

—

ps

(rms)

DIF[18:0]

Output-to-Output Skew across all Outputs

(Common to Bypass and PLL Mode)

0

20

50

ps

1,2,3,4,5

6

PLL Jitter Peaking

PLL Bandwidth

(HBW_BYPASS_LBW = 0)

—

0.4

0.1

0.7

2

2.0

2.5

1.4

4

dB

6

(HBW_BYPASS_LBW = 1)

7

(HBW_BYPASS_LBW = 0)

MHz

7

PLL Bandwidth

(HBW_BYPASS_LBW = 1)

Notes:

1. Measured into fixed 2 pF load cap. Input-to-output skew is measured at the first output edge following the

corresponding input.

2. Measured from differential cross-point to differential cross-point.

3. This parameter is deterministic for a given device.

4. Measured with scope averaging on to find mean value.

5. All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge

created by it.

6. Measured as maximum pass band gain. At frequencies within the loop BW, highest point of magnification is called

PLL jitter peaking.

7. Measured at 3 db down or half power point.

Rev. 1.5

9

Si53019-A01A

Table 7. Phase Jitter

Parameter

Test Condition

Min

Typ

Max

Unit

1,2,3

Phase Jitter

PLL Mode

PCIe Gen 1, Common Clock

—

30

86

ps

PCIe Gen 2 Low Band, Common Clock

—

1.0

2.6

3.0

3.1

1.0

0.71

1.0

0.5

0.3

0.2

ps

(RMS)

1,3,4,5

F < 1.5 MHz

PCIe Gen2 High Band, Common Clock

ps

(RMS)

1,3,4,5

1.5 MHz < F < Nyquist

PCIe Gen 3, Common Clock

(PLL BW 2–4 MHz, CDR = 10 MHz)

0.6

ps

(RMS)

1,3,4,5

PCIe Gen 3 Separate Reference No Spread, SRNS

(PLL BW of 2–4 or 2–5 MHz, CDR = 10 MHz)

0.42

0.6

ps

(RMS)

1,3,4,5

PCIe Gen 4, Common Clock

(PLL BW of 2–4 or 2–5 MHz, CDR = 10 MHz)

ps

(RMS)

1,4,5,8

®

Intel QPI & Intel SMI

0.25

0.17

0.15

ps

(RMS)

1,6,7

(4.8 Gbps or 6.4 Gb/s, 100 or 133 MHz, 12 UI)

Intel QPI & Intel SMI

(8 Gb/s, 100 MHz, 12 UI)

ps

(RMS)

1,6

Intel QPI & Intel SMI

(9.6 Gb/s, 100 MHz, 12 UI)

ps

(RMS)

1,6

Notes:

1. Post processed evaluation through Intel supplied Matlab* scripts. Defined for a BER of 1E-12. Measured values at a

smaller sample size have to be extrapolated to this BER target.

2. ζ = 0.54 implies a jitter peaking of 3 dB.

3. PCIe* Gen3 filter characteristics are subject to final ratification by PCISIG. Check the PCI-SIG for the latest

specification.

4. Measured on 100 MHz PCIe output using the template file in the Intel-supplied Clock Jitter Tool V1.6.3.

5. Measured on 100 MHz output using the template file in the Intel-supplied Clock Jitter Tool V1.6.3.

6. Measured on 100 MHz, 133 MHz output using the template file in the Intel-supplied Clock Jitter Tool V1.6.3.

7. These jitter numbers are defined for a BER of 1E-12. Measured numbers at a smaller sample size have to be

extrapolated to this BER target.

8. Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.5.

9. Download the Silicon Labs PCIe Clock Jitter Tool at www.silabs.com/pcie-learningcenter.

10

Rev. 1.5

Si53019-A01A

Table 7. Phase Jitter (Continued)

1,2,3

Additive Phase Jitter

Bypass Mode

PCIe Gen 1

—

4

—

ps

PCIe Gen 2 Low Band

0.08

ps

(RMS)

1,3,4,5

F < 1.5 MHz

PCIe Gen 2 High Band

1.5 MHz < F < Nyquist

—

1

—

ps

(RMS)

1,3,4,5

PCIe Gen 3

(PLL BW 2–4 MHz, CDR = 10 MHz)

0.27

0.25

0.08

0.07

ps

(RMS)

1,3,4,5

PCIe Gen 4, Common Clock

(PLL BW of 2–4 or 2–5 MHz, CDR = 10 MHz)

ps

(RMS)

1,4,5,8

1,6,7

Intel QPI & Intel® SMI

(4.8 Gbps or 6.4 Gb/s, 100 or 133 MHz, 12 UI)

ps

(RMS)

Intel QPI & Intel® SMI

(8 Gb/s, 100 MHz, 12 UI)

ps

(RMS)

1,6

Intel QPI & Intel® SMI

(9.6 Gb/s, 100 MHz, 12 UI)

ps

(RMS)

1,6

Notes:

1. Post processed evaluation through Intel supplied Matlab* scripts. Defined for a BER of 1E-12. Measured values at a

smaller sample size have to be extrapolated to this BER target.

2. ζ = 0.54 implies a jitter peaking of 3 dB.

3. PCIe* Gen3 filter characteristics are subject to final ratification by PCISIG. Check the PCI-SIG for the latest

specification.

4. Measured on 100 MHz PCIe output using the template file in the Intel-supplied Clock Jitter Tool V1.6.3.

5. Measured on 100 MHz output using the template file in the Intel-supplied Clock Jitter Tool V1.6.3.

6. Measured on 100 MHz, 133 MHz output using the template file in the Intel-supplied Clock Jitter Tool V1.6.3.

7. These jitter numbers are defined for a BER of 1E-12. Measured numbers at a smaller sample size have to be

extrapolated to this BER target.

8. Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.5.

9. Download the Silicon Labs PCIe Clock Jitter Tool at www.silabs.com/pcie-learningcenter.

Rev. 1.5

11

Si53019-A01A

Table 8. Clock Periods Differential Clock Outputs with SSC Disabled

SSC OFF

Center

Freq, MHz

Measurement Window

Unit

1 Clock

1 μs

0.1 s

1 μs

1 Clock

-C-C Jitter

AbsPer

Min

-SSC

Short

-ppm

Long

0 ppm

Period

+ppm

Long

+SSC

Short

+C-C

Jitter

AbsPer

Max

Term AVG Term AVG Nominal Term AVG Term AVG

Min

Max

100.00

133.33

9.94900

7.44925

9.99900

7.49925

10.00000 10.00100

10.05100

7.55075

ns

7.50000

7.50075

Table 9. Clock Periods Differential Clock Outputs with SSC Enabled

SSC ON

Center

Freq, MHz

Measurement Window

Unit

1 Clock

1 μs

0.1 s

1 μs

1 Clock

-C-C

Jitter

AbsPer

Min

-SSC

Short

-ppm

Long

0 ppm

Period

+ppm

Long

+SSC

Short

+C-C

Jitter

AbsPer

Max

Term AVG Term AVG Nominal Term AVG Term AVG

Min

Max

99.75

9.94906

7.44930

9.99906

7.49930

10.02406 10.02506 10.02607 10.05107 10.10107

ns

133.00

7.51805

7.51880

7.51955

7.53830

7.58830

Table 10. Absolute Maximum Ratings

Parameter

Symbol

Min

Max

Unit

1

3.3 V Core Supply Voltage

VDD/VDD_A

—

4.6

V

1,2

3.3 V Input High Voltage

VIH

VIL

V

+0.5 V

DD

1

3.3 V Input Low Voltage

–0.5

–65

2000

—

V

1

Storage Temperature

t

150

—

°C

V

s

3

Input ESD protection

ESD

Notes:

1. Consult manufacturer regarding extended operation in excess of normal dc operating parameters.

2. Maximum VIH is not to exceed maximum V_DD

3. Human body model.

.

12

Rev. 1.5

Si53019-A01A

2. Functional Description

Figure 1. Si53019-A01A Functional Block Diagram

Table 11. Functionality at Power Up (PLL Mode)

100M_133M

CLK_IN

(MHz)

Conditions

1

0

100

CLK_IN

133.33

Table 12. PLL Operating Mode Readback Table

HBW_BYPASS_LBW Byte 0, Bit 7 Byte 0, Bit 6

Mode

Low

Mid (Bypass)

High

0

1

0

1

PLL Low BW

Bypass

PLL High BW

Rev. 1.5

13

Si53019-A01A

Table 13. Tri-Level Input Thresholds

Parameter

Low

Voltage

<0.8 V

Mid

1.2<Vin<1.8 V

Vin>2.2 V

High

Table 14. Power Connections

Description

Pin Number

V

GND

DD

1

2

7

Analog PLL

Analog Input

DIF Outputs

8

21,31,45,58,68

26,44,63

Note: T_A= -40–85 °C; supply voltage V_DD= 3.3 V ±5%

Table 15. SMBus Addressing

SMBus Address

SMB_A1

SMB_A0

0

M

1

D8

DA

DE

C2

C4

C6

CA

CC

CE

0

M

1

0

M

1

0

1

M

1

14

Rev. 1.5

Si53019-A01A

2.1. CLK_IN, CLK_IN

The differential input clock is expected to be sourced from a clock synthesizer or PCH.

2.2. 100M_133M—Frequency Selection

The Si53019-A01A is optimized for lowest phase jitter performance at operating frequencies of 100 and 133 MHz.

100M_133M is a hardware input pin, which programs the appropriate output frequency of the differential outputs.

Note that the CLK_IN frequency must be equal to the CLK_OUT frequency, meaning Si53019-A01A is operated in

1:1 mode only. Frequency selection can be enabled by the 100M_133M hardware pin. An external pull-up or pull-

down resistor is attached to this pin to select the input/output frequency. The functionality is summarized in

Table 16.

Table 16. Frequency Program Table

100M_133M

Optimized Frequency (DIF_IN = DIF_x)

133.33 MHz

0

1

100.00 MHz

Note: All differential outputs transition from 100 to 133 MHz or from 133 to 100 MHz in a glitch free manner.

2.3. SA_0, SA_1—Address Selection

SA_0 and SA_1 are tri-level hardware pins, which program the appropriate address for the Si53019-A01A. The two

tri-level input pins can configure the device to nine different addresses.

Table 17. SMBus Address Table

SA_1

L

SA_0

L

SMBus Address

D8

DA

DE

C2

C4

C6

CA

CC

CE

L

M

H

L

M

H

L

M

H

L

H

M

H

Rev. 1.5

15

Si53019-A01A

2.4. CKPWRGD/PWRDN

CKPWRGD is asserted high and deasserted low. Deassertion of PWRGD (pulling the signal low) is equivalent to

indicating a power-down condition. CKPWRGD (assertion) is used by the Si53019-A01A to sample initial

configurations, such as frequency select condition and SA selections. After CKPWRGD has been asserted high for

the first time, the pin becomes a PWRDN (Power Down) pin that can be used to shut off all clocks cleanly and

instruct the device to invoke power-saving mode. PWRDN is a completely asynchronous active low input. When

entering power-saving mode, PWRDN should be asserted low prior to shutting off the input clock or power to

ensure all clocks shut down in a glitch free manner. When PWRDN is asserted low, all clocks will be disabled prior

to turning off the VCO. When PWRDN is deasserted high, all clocks will start and stop without any abnormal

behavior and will meet all AC and DC parameters.

Note: The assertion and deassertion of PWRDN is absolutely asynchronous.

Warning: Disabling of the CLK_IN input clock prior to assertion of PWRDN is an undefined mode and not recommended.

Operation in this mode may result in glitches, excessive frequency shifting, etc.

Table 18. CKPWRGD/PWRDN Functionality

CKPWRGD/

PWRDN

DIF_IN/

DINF_IN#

SMBus

EN bit

OE# Pin

DIF(5:12) Other DIF/

FBOUT_NC/ PLL State

FBOUT_NC#

DIF(5:12)#

DIF#

0

1

X

0

1

X

0

Hi-Z*

OFF

ON

Running

Hi-Z*

Running

Hi-Z*

Running

1

*Note: Due to external pull down resistors, Hi-Z results in Low/Low on the True/Complement outputs.

16

Rev. 1.5

Si53019-A01A

2.4.1. PWRDN Assertion

When PWRDN is sampled low by two consecutive rising edges of DIF, all differential outputs must be held Tri-

state/Tri-state on the next DIF high-to-low transition. The device will put all outputs in high impedance mode, and

all outputs will be pulled low by the external terminating resistors.

Figure 2. PWRDN Assertion

2.4.2. CKPWRGD Assertion

The power-up latency is to be less than 1.8 ms. This is the time from a valid CLK_IN input clock and the assertion

of the PWRGD signal to the time that stable clocks are output from the device (PLL locked). All differential outputs

stopped in a Tri-state/Tri-state condition resulting from power down must be driven high in less than 300 μs of

PWRDN deassertion to a voltage greater than 200 mV.

Figure 3. PWRDG Assertion (Pwrdown—Deassertion)

Rev. 1.5

17

Si53019-A01A

2.5. HBW_BYPASS_LBW

The HBW_BYPASS_LBW pin is a tri-level function input pin (refer to Table 1 for VIL_Tri, VIM_Tri, and VIH_Tri

signal levels). It is used to select between PLL high-bandwidth, PLL bypass mode, or PLL low-bandwidth mode. In

PLL bypass mode, the input clock is passed directly to the output stage, which may result in up to 50 ps of additive

cycle-to-cycle jitter (50 ps + input jitter) on the differential outputs. In the case of PLL mode, the input clock is

passed through a PLL to reduce high-frequency jitter. The PLL HBW, BYPASS, and PLL LBW modes may be

selected by asserting the HBW_BYPASS_LBW input pin to the appropriate level described in Table 19.

Table 19. PLL Bandwidth and Readback Table

HBW_BYPASS_LBW Pin

Mode

LBW

Byte 0, Bit 7

Byte 0, Bit 6

L

M

H

0

1

0

1

BYPASS

HBW

The Si53019-A01A has the ability to override the latch value of the PLL operating mode from hardware strap Pin 5

via the use of Byte 0 and Bits 2 and 1. Byte 0 Bit 3 must be set to 1 to allow the user to change Bits 2 and 1,

affecting the PLL. Bits 7 and 6 will always read back the original latched value. A warm reset of the system will

have to be accomplished if the user changes these bits.

2.6. Miscellaneous Requirements

Data Transfer Rate: 100 kbps (standard mode) is the base functionality required. Fast mode (400 kbps)

functionality is optional.

Logic Levels: SMBus logic levels are based on a percentage of V for the controller and other devices on the

DD

bus. Assume all devices are based on a 3.3 V supply.

Clock Stretching: The clock buffer must not hold/stretch the SCL or SDA lines low for more than 10 ms. Clock

stretching is discouraged and should only be used as a last resort. Stretching the clock/data lines for longer than

this time puts the device in an error/time-out mode and may not be supported in all platforms. It is assumed that all

data transfers can be completed as specified without the use of clock/data stretching.

General Call: It is assumed that the clock buffer will not have to respond to the “general call.”

Electrical Characteristics: All electrical characteristics must meet the standard mode specifications found in

Section 3 of the SMBus 2.0 specification.

Pull-Up Resistors: Any internal resistor pull-ups on the SDATA and SCLK inputs must be stated in the individual

data sheet. The use of internal pull-ups on these pins of below 100 K is discouraged. Assume that the board

designer will use a single external pull-up resistor for each line and that these values are in the 5–6 k range.

Assume one SMBus device per DIMM (serial presence detect), one SMBus controller, one clock buffer, one clock

driver plus one/two more SMBus devices on the platform for capacitive loading purposes.

Input Glitch Filters: Only fast mode SMBus devices require input glitch filters to suppress bus noise. The clock

buffer is specified as a standard mode device and is not required to support this feature. However, it is considered

a good design practice to include the filters.

PWRDN: If a clock buffer is placed in PWRDN mode, the SDATA and SCLK inputs must be Tri-stated and the

device must retain all programming information. I current due to the SMBus circuitry must be characterized and

DD

in the data sheet.

18

Rev. 1.5

Si53019-A01A

3. Test and Measurement Setup

3.1. Input Edge

Input edge rate is based on single-ended measurement. This is the minimum input edge rate at which the Si53019-

A01A is guaranteed to meet all performance specifications.

Table 20. Input Edge Rate

Frequency

100 MHz

133 MHz

Min

0.35

Max

N/A

Unit

V/ns

3.1.1. Measurement Points for Differential

Figure 4. Measurement Points for Rise Time and Fall Time

Figure 5. Single-ended Measurement Points for V , V , V

ovs uds rb

Rev. 1.5

19

Si53019-A01A

Figure 6. Differential (CLOCK–CLOCK) Measurement Points (T

3.2. Termination of Differential Outputs

, Duty Cycle, Jitter)

period

All differential outputs are to be tested into a 100  or 85  differential impedance transmission line. Source

terminated clocks have some inherent limitations as to the maximum trace length and frequencies that can be

supported. For CPU outputs, a maximum trace length of 10” and a maximum of 200 MHz are assumed. For SRC

clocks, a maximum trace length of 16” and maximum frequency of 100 MHz is assumed. For frequencies beyond

200 MHz, trace lengths must be restricted to avoid signal integrity problems.

Table 21. Differential Output Termination

Clock

IREF ( )

475

Board Trace Impedance

Rs

Rp

Unit



DIFF Clocks—50  configuration

DIFF Clocks—43  configuration

100

85

33+5%

50

412

27+5% 42.2 or 43.2



3.2.1. Termination of Differential Current Mode HCSL Outputs

Figure 7. 0.7 V Configuration Test Load Board Termination

20

Rev. 1.5

Si53019-A01A

4. Control Registers

4.1. Byte Read/Write

Reading or writing a register in an SMBus slave device in byte mode always involves specifying the register

number.

4.1.1. Byte Read

The standard byte read is as shown in Figure 8. It is an extension of the byte write. The write start condition is

repeated; then the slave device starts sending data, and the master acknowledges it until the last byte is sent. The

master terminates the transfer with a NAK, then a stop condition. For byte operation, the 2 x 7th bit of the

command byte must be set. For block operations, the 2 x 7th bit must be reset. If the bit is not set, the next byte

must be the byte transfer count.

Figure 8. Byte Read Protocol

4.1.2. Byte Write

Figure 9 illustrates a simple, typical byte write. For byte operation, the 2 x 7th bit of the command byte must be set.

For block operations, the 2 x 7th bit must be reset. If the bit is not set, the next byte must be the byte transfer count.

The count can be between 1 and 32. It is not allowed to be zero or to exceed 32.

Figure 9. Byte Write Protocol

Rev. 1.5

21

Si53019-A01A

4.2. Block Read/Write

4.2.1. Block Read

After the slave address is sent with the R/W condition bit set, the command byte is sent with the MSB = 0. The

slave acknowledges the register index in the command byte. The master sends a repeat start function. After the

slave acknowledges this, the slave sends the number of bytes it wants to transfer (>0 and <33). The master

acknowledges each byte except the last and sends a stop function.

Figure 10. Block Read Protocol

4.2.2. Block Write

After the slave address is sent with the R/W condition bit not set, the command byte is sent with the MSB = 0. The

lower seven bits indicate the register at which to start the transfer. If the command byte is 00h, the slave device will

be compatible with existing block mode slave devices. The next byte of a write must be the count of bytes that the

master will transfer to the slave device. The byte count must be greater than zero and less than 33. Following this

byte are the data bytes to be transferred to the slave device. The slave device always acknowledges each byte

received. The transfer is terminated after the slave sends the ACK and the master sends a stop function.

Figure 11. Block Write Protocol

22

Rev. 1.5

Si53019-A01A

4.3. Control Registers

Table 22. Byte 0: PLL Mode and Frequency Select Register

Bit Pin #

Name

Control Function

0

1

Type

Default

0

4

100M_133M#

Frequency Select

Readback

133 MHz

100 MHz

R

Latch

1

2

3

reserved

0

1

67/66 Output Enable DIF 16

70/69 Output Enable DIF 17

72/71 Output Enable DIF 18

Output control,

overrides OE# pin

4

5

6

7

Output control,

overrides OE# pin

1

Output control,

overrides OE# pin

1

5

PLL Mode 0

PLL Mode1

PLL operating mode

readback 0

See PLL operating

mode readback table

R

Latch

PLL operating mode

readback 1

Table 23. Byte 1: Output Enable Control Register

Bit

Pin #

Description

If Bit = 0

If Bit = 1

Enabled

Type

Default

0

19/20

Output Enable DIF 0

Output Enable DIF 1

Output Enable DIF 2

Output Enable DIF 3

Output Enable DIF 4

Output Enable DIF 5

Output Enable DIF 6

Output Enable DIF 7

Output control,

Hi-Z

RW

1

overrides OE# pin

1

2

3

4

5

6

7

22/23

24/25

27/28

29/30

32/33

35/36

39/38

Output control,

overrides OE# pin

Output control,

overrides OE# pin

Output control,

overrides OE# pin

Output control,

overrides OE# pin

Output control,

overrides OE# pin

Output control,

overrides OE# pin

Output control,

overrides OE# pin

Rev. 1.5

23

Si53019-A01A

Table 24. Byte 2: Output Enable Control Register

Bit

Pin #

Description

Control Function

If Bit = 0

If Bit = 1

Type

Default

0

42/41

Output Enable DIF 8

Output control,

Hi-Z

Enabled

RW

1

overrides OE# pin

1

2

3

4

5

6

7

47/46

50/49

53/52

56/55

60/59

62/61

65/64

Output Enable DIF 9

Output Enable DIF 10

Output Enable DIF 11

Output Enable DIF 12

Output Enable DIF 13

Output Enable DIF 14

Output Enable DIF 15

Output control,

overrides OE# pin

RW

1

Output control,

overrides OE# pin

Output control,

overrides OE# pin

Output control,

overrides OE# pin

Output control,

overrides OE# pin

Output control,

overrides OE# pin

Output control,

overrides OE# pin

Table 25. Byte 3: Output Enable Pin Status Readback Register

Bit

Pin #

Description

Control Function

If Bit = 0

If Bit = 1

Type

Default

0

34

OE_RB5

Real time readback OE# pin Low

of OE5

OE# pin

High

R

Real

Time

1

2

3

4

5

6

7

37

40

43

48

51

54

57

OE_RB6

OE_RB7

OE_RB8

OE_RB9

OE_RB10

OE_RB11

OE_RB12

Real time readback

of OE6

R

Real

Time

Real time readback

of OE7

Real

Time

Real time readback

of OE8

Real

Time

Real time readback

of OE9

Real

Time

Real time readback

of OE10

Real

Time

Real time readback

of OE11

Real

Time

Real time readback

of OE12

Real

Time

24

Rev. 1.5

Si53019-A01A

Table 26. Byte 4: Reserved Control Register

Bit

0

Pin #

Description

Control Function

Reserved

If Bit = 0

If Bit = 1

Type

Default

0

1

2

3

4

5

6

7

Table 27. Byte 5: Vendor/Revision Identification Control Register

Bit

0

Pin #

—

Description

Vendor ID Bit 0

Control Function

If Bit = 0

If Bit = 1

Type

R

Default

Vendor ID

1

0

1

—

Vendor ID Bit 1

R

2

—

Vendor ID Bit 2

R

0

3

—

Vendor ID Bit 3

R

0

4

—

Revision Code Bit 0

Revision Code Bit 1

Revision Code Bit 2

Revision Code Bit 3

Revision ID

–A01A = 0001

–A02A = 0010

R

X

5

—

R

6

—

R

7

—

R

Table 28. Byte 6: Device ID Control Register

Bit

0

Pin #

—

Description

Control Function

If Bit = 0

If Bit = 1

Type

R

Default

Device ID 0

1

0

1

0

1

—

Device ID 1

Device ID 2

R

2

—

R

3

—

Device ID 3

R

4

—

Device ID 4

R

5

—

Device ID 5

R

6

—

Device ID 6

R

7

—

Device ID 7 (MSB)

R

Rev. 1.5

25

Si53019-A01A

Table 29. Byte 7: Byte Count Register

Bit

0

Pin #

—

Description

BC0

Control Functions

If Bit = 0

If Bit = 1

Type

RW

Default

Writing to this register

configures how many

bytes will be read back. be read back by default.

Default value is 8 hex,

so 9 bytes (0 to 8) will

0

1

—

BC1

RW

2

3

4

—

BC2

BC3

BC4

RW

0

1

0

5

6

7

Reserved

0

26

Rev. 1.5

Si53019-A01A

5. Pin Descriptions: 72-Pin QFN

Rev. 1.5

27

Si53019-A01A

Table 30. Si53019-A01A 72-Pin QFN Descriptions

Pin #

Name

VDDA

GNDA

IREF

Type

Description

3.3 V 3.3 V power supply for PLL.

1

2

3

GND Ground for PLL.

OUT This pin establishes the reference for the differential current mode output

pairs. It requires a fixed precision resistor to ground. 475 is the

standard value for 100  differential impedance. Other impedances

require different values.

I,SE 3.3 V tolerant inputs for input/output frequency selection.An external pull-

4

5

100M_133M

up or pull-down resistor is attached to this pin to select the input/output

frequency.

High = 100 MHz output

Low = 133 MHz output

I, SE Tri-Level input for selecting the PLL bandwidth or bypass mode.

High = High BW mode

HBW_BYPASS_LBW

Med = Bypass mode

Low = Low BW mode

I

3.3 V LVTTL input to power up or power down the device.

6

7

8

PWRGD/PWRDN

GND

GND Ground for outputs.

VDD 3.3 V power supply for differential input receiver. This VDDR should be

treated as an analog power rail and filtered appropriately.

VDDR

I, DIF 0.7 V Differential TRUE input.

9

CLK_IN

SA_0

SDA

I, DIF 0.7 V Differential input.

10

11

12

13

14

15

I,PU 3.3 V LVTTL input selecting the address. Tri-level input.

I/O Open collector SMBus data.

I/O SMBus slave clock input.

SCL

I,PU 3.3 V LVTTL input selecting the address. Tri-level input.

SA_1

FB_IN

I/O True differential feedback input. Provides feedback signal to the PLL for

synchronization with the input clock to eliminate phase error.

I/O Complementary differential feedback input. Provides feedback signal to

the PLL for synchronization with the input clock to eliminate phase error.

16

17

18

FB_IN

I/O Complementary differential feedback output, provides feedback signal to

the PLL for synchronization with input clock to eliminate phase error.

FB_OUT

I/O True differential feedback output, provides feedback signal to the PLL for

synchronization with the input clock to eliminate phase error.

O, DIF 0.7 V Differential TRUE clock output.

O, DIF 0.7 V Differential Complimentary clock output.

VDD Power supply for differential outputs.

O, DIF 0.7 V Differential TRUE clock output.

19

20

21

22

DIF_0

VDD

DIF_1

28

Rev. 1.5

Si53019-A01A

Table 30. Si53019-A01A 72-Pin QFN Descriptions

Pin #

23

24

25

26

27

28

29

30

31

32

33

34

Name

DIF_1

DIF_2

GND

Type

Description

O, DIF 0.7 V Differential Complimentary clock output.

O, DIF 0.7 V Differential TRUE clock output.

O, DIF 0.7 V Differential Complimentary clock output.

GND Ground for outputs.

O, DIF 0.7 V Differential TRUE clock output.

O, DIF 0.7 V Differential Complimentary clock output.

O, DIF 0.7 V Differential TRUE clock output.

O, DIF 0.7 V Differential Complimentary clock output.

3.3 V 3.3 V power supply

DIF_3

DIF_4

VDD

O, DIF 0.7 V Differential TRUE clock output.

O, DIF 0.7 V Differential Complimentary clock output.

DIF_5

OE5

IN

Active low input for enabling DIF pair 5

1 = disable outputs, 0 = enable outputs

O, DIF 0.7 V Differential TRUE clock output.

35

36

37

DIF_6

OE6

O, DIF 0.7 V Differential Complimentary clock output.

IN

Active low input for enabling DIF pair 6

1 = disable outputs, 0 = enable outputs

O, DIF 0.7 V Differential TRUE clock output.

38

39

40

DIF_7

OE7

O, DIF 0.7 V Differential Complimentary clock output.

IN

Active low input for enabling DIF pair 7

1 = disable outputs, 0 = enable outputs

O, DIF 0.7 V Differential TRUE clock output.

41

42

43

DIF_8

OE8

O, DIF 0.7 V Differential Complimentary clock output.

IN

Active low input for enabling DIF pair 8

1 = disable outputs, 0 = enable outputs

GND Ground for outputs.

44

45

46

47

48

GND

VDD

3.3 V 3.3 V power supply

O, DIF 0.7 V Differential TRUE clock output.

O, DIF 0.7 V Differential Complimentary clock output.

DIF_9

OE9

IN

Active low input for enabling DIF pair 9

1 = disable outputs, 0 = enable outputs

O, DIF 0.7 V Differential TRUE clock output.

49

DIF_10

Rev. 1.5

29

Si53019-A01A

Table 30. Si53019-A01A 72-Pin QFN Descriptions

Pin #

50

Name

DIF_10

OE10

Type

Description

O, DIF 0.7 V Differential Complimentary clock output.

IN

Active low input for enabling DIF pair 10

1 = disable outputs, 0 = enable outputs

51

O, DIF 0.7 V Differential TRUE clock output.

52

53

54

DIF_11

OE11

O, DIF 0.7 V Differential Complimentary clock output.

IN

Active low input for enabling DIF pair 11

1 = disable outputs, 0 = enable outputs

O, DIF 0.7 V Differential TRUE clock output.

55

56

57

DIF_12

OE12

O, DIF 0.7 V Differential Complimentary clock output.

IN

Active low input for enabling DIF pair 12

1 = disable outputs, 0 = enable outputs

3.3 V 3.3 V power supply

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

VDD

O, DIF 0.7 V Differential TRUE clock output.

O, DIF 0.7 V Differential Complimentary clock output.

O, DIF 0.7 V Differential TRUE clock output.

O, DIF 0.7 V Differential Complimentary clock output.

GND Ground for outputs.

DIF_13

DIF_14

GND

O, DIF 0.7 V Differential TRUE clock output.

O, DIF 0.7 V Differential Complimentary clock output.

O, DIF 0.7 V Differential TRUE clock output.

O, DIF 0.7 V Differential Complimentary clock output.

3.3 V 3.3 V power supply

DIF_15

DIF_16

VDD

O, DIF 0.7 V Differential TRUE clock output.

O, DIF 0.7 V Differential Complimentary clock output.

O, DIF 0.7 V Differential TRUE clock output.

O, DIF 0.7 V Differential Complimentary clock output.

GND Ground for outputs.

DIF_17

DIF_18

GND

30

Rev. 1.5

Si53019-A01A

6. Power Filtering Example

6.1. Ferrite Bead Power Filtering

Recommended ferrite bead filtering equivalent to the following:

Figure 12. Schematic Example of the Si53019-A01A Power Filtering

Rev. 1.5

31

Si53019-A01A

7. Ordering Guide

Part Number

Lead-free

Package Type

Temperature

Si53019-A01AGM

Si53019-A01AGMR

72-pin QFN

Extended, –40 to 85 C

72-pin QFN—Tape and Reel

32

Rev. 1.5

Si53019-A01A

8. Package Outline

Figure 13 illustrates the package details for the Si53019-A01A. Table 31 lists the values for the dimensions shown

in the illustration.

Figure 13. 72-Pin Quad Flat No Lead (QFN) Package

1,2,3,4

Table 31. Package Diagram Dimensions

Dimension

Min

0.80

0.00

0.18

Nom

0.85

Max

0.90

0.05

0.30

Dimension

Min

5.90

0.30

Nom

6.00

0.40

0.10

0.08

0.10

0.05

Max

6.10

0.50

A

E2

L

A1

0.02

b

0.25

aaa

bbb

ccc

ddd

eee

D

10.00 BSC.

6.00

D2

5.90

6.10

e

E

0.50 BSC.

10.00 BSC.

Notes:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

3. This drawing conforms to JEDEC outline MO-220.

4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.

Rev. 1.5

33

Si53019-A01A

9. PCB Land Pattern

9.1. 10x10 mm 72-QFN Package Land Pattern

34

Rev. 1.5

Si53019-A01A

Table 32. PCB Land Pattern

Dimension

mm

9.90

0.50

0.30

0.85

6.10

C1

C2

E

X1

Y1

X2

Y2

Notes:

General

1. All dimensions shown are in millimeters (mm).

2. This Land Pattern Design is based on the IPC-7351 guidelines.

3. All dimensions shown are at Maximum Material Condition (MMC). Least Material

Condition (LMC) is calculated based on a Fabrication Allowance of 0.05mm.

Solder Mask Design

4. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder

mask and the metal pad is to be 60 m minimum, all the way around the pad.

Stencil Design

5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be

used to assure good solder paste release.

6. The stencil thickness should be 0.125 mm (5 mils).

7. The ratio of stencil aperture to land pad size should be 1:1 for all pads.

8. A 3x3 array of 1.45 mm square openings on 2.00 mm pitch should be used for the center

ground pad.

Card Assembly

9. A No-Clean, Type-3 solder paste is recommended.

10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for

Small Body Components.

Rev. 1.5

35

Si53019-A01A

DOCUMENT CHANGE LIST

Revision 1.0 to Revision 1.1

 Updated descriptions for pin15, pin16, pin17, and

pin18 in Table 30.

Revision 1.1 to Revision 1.2

 Updated Features on page 1.

 Updated Description on page 1.

 Updated specs in Table 7, “Phase Jitter,” on

page 10.

 Updated the package drawing and table.

Revision 1.2 to Revision 1.3

January 20, 2016

 Updated the package drawing and table.

 Updated the land pattern drawing and table.

 Correct specs in Table 1 on page 4.

Revision 1.3 to Revision 1.4

February 22, 2016

 Updated operating characteristics in Table 4,

Table 5, Table 6, and Table 14.

Revision 1.4 to Revision 1.5

July 20, 2017

 Updated Input Amplitude max spec in Table 5 to

1900 mV.

36

Rev. 1.5


型号：	SI53019-A01AGMR
厂家：	SILICON
描述：	PLL Based Clock Driver, 53019 Series, 38 True Output(s), 0 Inverted Output(s), QFN-72 驱动逻辑集成电路
文件：	总36页 (文件大小：983K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SI53019-A01AGMR [SILICON]

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