SI53156-A13AGM [SILICON]
Low Skew Clock Driver,;![SI53156-A13AGM](http://pdffile.icpdf.com/pdf2/p00284/img/icpdf/SI53156-A13A_1691006_icpdf.jpg)
型号: | SI53156-A13AGM |
厂家: | ![]() |
描述: | Low Skew Clock Driver, 驱动 逻辑集成电路 |
文件: | 总22页 (文件大小:448K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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Si53156-A13A
PCI-EXPRESS
G
EN 1, GEN 2, GEN 3, AND
G
EN
4
F
ANOUT
B
UFFER
Features
PCI-Express Gen 1, Gen 2, Gen 3,
and Gen 4 common clock compliant
Supports Serial ATA (SATA) at
100 MHz
Six PCI-Express buffered clock
outputs
Clock input spread tolerable
Supports LVDS outputs
100–210 MHz operation
Low power, push pull, differential
output buffers
Internal termination for maximum
integration
I2C support with readback
capabilities
Extended temperature:
–40 to 85 oC
3.3 V power supply
32-pin QFN package
Dedicated output enable pin for each
output
Ordering Information:
See page 17.
Applications
Network attached storage
Multi-function printers
Wireless access point
Routers
Pin Assignments
Description
The Si53156-A13A is a spread spectrum tolerant PCIe clock buffer that can
source six PCIe clocks simultaneously. The device has six hardware output
enable control inputs for enabling the respective differential outputs on the fly. The
device also features output enable control through I2C communication. I2C
programmability is also available to dynamically control skew, edge rate and
amplitude on the true, compliment, or both differential signals on the clock
outputs. This control feature enables optimal signal integrity as well as optimal
EMI signature on the clock outputs. Measuring PCIe clock jitter is quick and easy
with the Silicon Labs PCIe Clock Jitter Tool. Download it for free at
www.silabs.com/pcie-learningcenter.
32
31
30
29 28 27
26
25
VDD
24
23
VDD
1
2
3
4
5
6
7
8
DIFF5
OE2*
VDD
22
21
DIFF5
VDD
OE3*
33
GND
20 DIFF4
OE4*
OE5*
NC
19
DIFF4
18 DIFF3
VDD
17
DIFF3
9
10
11
12
13
14 15
16
Functional Block Diagram
*Note: Internal 100 kohm pull-up.
Patents pending
DIFF0
DIFF1
DIFF2
DIFFIN
DIFF3
DIFFIN
DIFF4
DIFF5
Control & Memory
SCLK
SDATA
Control
RAM
OE [5:0]
Rev. 1.0 5/17
Copyright © 2017 by Silicon Laboratories
Si53156-A13A
Si53156-A13A
2
Rev. 1.0
Si53156-A13A
TABLE OF CONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.1. OE Pin Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.2. OE Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.3. OE Deassertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
3. Test and Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
4. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
2
4.1. I C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
4.2. Data Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
5. Pin Descriptions: 32-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
7. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
8. Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Rev. 1.0
3
Si53156-A13A
1. Electrical Specifications
Table 1. DC Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
3.3 V Operating Voltage
VDD core
3.3 ± 5%
3.135
—
3.465
V
3.3 V Input High Voltage
3.3 V Input Low Voltage
Input High Voltage
V
Control input pins
Control input pins
SDATA, SCLK
2.0
—
—
—
—
V
+ 0.3
DD
V
V
V
V
IH
V
V
– 0.3
SS
0.8
IL
V
2.2
—
IHI2C
Input Low Voltage
V
SDATA, SCLK
—
—
1.0
ILI2C
Input High Leakage Current
Except internal pull-down
I
—
5
A
IH
resistors, 0 < V < V
IN
DD
Input Low Leakage Current
Except internal pull-up
resistors, 0 < V < V
I
–5
—
—
—
—
A
IL
IN
DD
3.3 V Output High Voltage
(Single-Ended Outputs)
V
I
= –1 mA
2.4
V
OH
OH
3.3 V Output Low Voltage
(Single-Ended Outputs)
V
I
= 1 mA
—
—
—
0.4
10
V
OL
OZ
OL
High-impedance Output
Current
I
–10
A
Input Pin Capacitance
Output Pin Capacitance
Pin Inductance
C
1.5
—
—
—
—
—
—
—
5
6
7
1
pF
pF
IN
C
OUT
L
nH
mA
IN
Power Down Current
I
_
DD PD
Dynamic Supply Current in
Fanout Mode
Differential clocks with 5”
traces and 2 pF load, fre-
quency at 100 MHz
I
—
—
45
mA
DD_3.3V
4
Rev. 1.0
Si53156-A13A
Table 2. AC Electrical Specifications
Parameter
DIFFIN at 0.7 V
Symbol
Condition
Min
Typ
Max
Unit
Input Frequency Range
f
100
0.6
—
—
210
4
MHz
V/ns
in
Rising and Falling Slew Rates for
Each Clock Output Signal in a
Given Differential Pair
T /T
Single ended measurement:
R
F
V
= 0.175 to V = 0.525 V
OL
OH
(Averaged)
Differential Input High Voltage
Differential Input Low Voltage
V
150
—
—
—
—
—
mV
mV
mV
IH
V
–150
550
IL
Crossing Point Voltage at 0.7 V
Swing
V
Single-ended measurement
Single-ended measurement
250
OX
Vcross Variation over all edges
Differential Ringback Voltage
Time before ringback allowed
Absolute maximum input voltage
Absolute minimum input voltage
V
—
–100
500
—
—
—
—
—
—
—
140
100
—
mV
mV
ps
V
OX
V
RB
STABLE
T
V
1.15
—
MAX
V
–0.3
45
V
MIN
Duty Cycle for Each Clock Output
Signal in a Given
Differential Pair
T
Measured at crossing point V
Determined as a fraction of
55
%
DC
OX
Rise/Fall Matching
T
—
—
20
%
RFM
2 x (T – T )/(T + T )
R
F
R
F
DIFF at 0.7 V
Duty Cycle
T
Measured at 0 V differential
Measured at 0 V differential
45
—
0
—
—
—
—
—
—
55
50
%
ps
ps
ps
ps
ps
DC
Clock Skew
T
SKEW
Additive Peak Jitter
Pk-Pk
10
Additive PCIe Gen 2 Phase Jitter RMS
10 kHz < F < 1.5 MHz
0
0.5
0.5
0.10
GEN2
1.5 MHz< F < Nyquist Rate
0
Additive PCIe Gen 3 Phase Jitter RMS
Additive PCIe Gen 4 Phase Jitter RMS
Includes PLL BW 2–4 MHz
(CDR = 10 MHz)
0
GEN3
GEN4
PCIe Gen 4
—
—
—
—
—
—
0.10
50
ps
ps
Additive Cycle to Cycle Jitter
Long-term Accuracy
T
Measured at 0 V differential
Measured at 0 V differential
CCJ
L
—
100
8
ppm
V/ns
ACC
Rising/Falling Slew rate
T / T
Measured differentially from
±150 mV
2.5
R
F
Crossing Point Voltage at 0.7 V
Swing
V
300
—
550
mV
OX
Notes:
1. Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.5.
2. Download the Silicon Labs PCIe Clock Jitter Tool at www.silabs.com/pcie-learningcenter.
Rev. 1.0
5
Si53156-A13A
Table 2. AC Electrical Specifications (Continued)
Parameter
Symbol
Condition
Min
Typ
Max
Unit
Enable/Disable and Setup
Clock Stabilization from Power-Up
T
Measured from the point when
–
—
5
ms
STABLE
both V and clock input are
DD
valid
Stopclock Set-up Time
T
10.0
—
—
ns
SS
Notes:
1. Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.5.
2. Download the Silicon Labs PCIe Clock Jitter Tool at www.silabs.com/pcie-learningcenter.
Table 3. Absolute Maximum Conditions
Parameter
Main Supply Voltage
Symbol
Condition
Min
Typ
Max Unit
V
Functional
—
—
—
—
—
4.6
4.6
150
85
V
DD_3.3V
Input Voltage
V
Relative to V
–0.5
–65
–40
V
DC
IN
SS
Temperature, Storage
T
Non-functional
Functional
°C
S
Industrial Temperature, Operating
Ambient
T
°C
A
Commercial Temperature, Operating
Ambient
T
Functional
0
—
85
°C
A
Temperature, Junction
T
Functional
—
—
—
—
—
150
17
35
—
°C
°C/W
°C/W
V
J
Dissipation, Junction to Case
Dissipation, Junction to Ambient
ESD Protection (Human Body Model)
Flammability Rating
Ø
JEDEC (JESD 51)
JEDEC (JESD 51)
JC
JA
Ø
—
ESD
JEDEC (JESD 22 - A114) 2000
UL (Class)
—
HBM
UL-94
V–0
Note: Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply
sequencing is not required.
6
Rev. 1.0
Si53156-A13A
2. Functional Description
2.1. OE Pin Definition
The OE pins are active high inputs used to enable and disable the output clocks. To enable the output clock, the
2
OE pin needs to be logic high and the I C output enable bit needs to be logic high. There are two methods to
2
disable the output clocks: the OE is pulled to a logic low, or the I C enable bit is set to a logic low. The OE pins are
required to be driven at all times even though they have an internal 100 k resistor.
2.2. OE Assertion
The OE signals are active high inputs used for synchronous stopping and starting the DIFF output clocks
respectively while the rest of the clock generator continues to function. The assertion of the OE signal by making it
logic high causes stopped respective DIFF outputs to resume normal operation. No short or stretched clock pulses
are produced when the clock resumes. The maximum latency from the assertion to active outputs is no more than
two to six output clock cycles.
2.3. OE Deassertion
When the OE pin is deasserted by making it logic low, the corresponding DIFF output is stopped, and the final output
state is driven low.
Rev. 1.0
7
Si53156-A13A
3. Test and Measurement Setup
This diagram shows the test load configuration for differential clock signals.
Figure 1. 0.7 V Differential Load Configuration
Figure 2. Differential Measurement for Differential Output Signals
(for AC Parameters Measurement)
8
Rev. 1.0
Si53156-A13A
Figure 3. Single-Ended Measurement for Differential Output Signals
(for AC Parameters Measurement)
Rev. 1.0
9
Si53156-A13A
4. Control Registers
2
4.1. I C Interface
2
2
To enhance the flexibility and function of the clock buffer, an I C interface is provided. Through the I C Interface,
various device functions are available, such as individual clock output enable. The registers associated with the I C
2
Interface initialize to their default setting at power-up. The use of this interface is optional. Clock device register
changes are normally made at system initialization, if any are required. Power management functions can only be
programed in program mode and not in normal operation modes.
4.2. Data Protocol
2
The I C protocol accepts byte write, byte read, block write, and block read operations from the controller. For block
write/read operation, access the bytes in sequential order from lowest to highest (most significant bit first) with the
ability to stop after any complete byte is transferred. For byte write and byte read operations, the system controller
can access individually indexed bytes.
The block write and block read protocol is outlined in Table 4 on page 10 while Table 5 on page 11 outlines byte
write and byte read protocol. The slave receiver address is 11010110 (D6h).
Table 4. Block Read and Block Write Protocol
Block Write Protocol
Description
Block Read Protocol
Description
Bit
1
Bit
1
Start
Start
8:2
9
Slave address—7 bits
Write
8:2
9
Slave address—7 bits
Write
10
Acknowledge from slave
Command Code—8 bits
Acknowledge from slave
Byte Count—8 bits
Acknowledge from slave
Data byte 1–8 bits
10
Acknowledge from slave
18:11
19
18:11 Command Code–8 bits
19
20
Acknowledge from slave
Repeat start
27:20
28
27:21 Slave address—7 bits
36:29
37
28
29
Read = 1
Acknowledge from slave
Data byte 2–8 bits
Acknowledge from slave
45:38
46
37:30 Byte Count from slave—8 bits
38 Acknowledge
46:39 Data byte 1 from slave—8 bits
47 Acknowledge
55:48 Data byte 2 from slave—8 bits
Acknowledge from slave
Data Byte/Slave Acknowledges
Data Byte N–8 bits
Acknowledge from slave
Stop
....
....
....
....
56
....
....
....
....
Acknowledge
Data bytes from slave/Acknowledge
Data Byte N from slave—8 bits
NOT Acknowledge
Stop
10
Rev. 1.0
Si53156-A13A
Table 5. Byte Read and Byte Write Protocol
Byte Write Protocol
Description
Byte Read Protocol
Description
Bit
Bit
1
Start
1
Start
8:2
9
Slave address–7 bits
Write
8:2
9
Slave address–7 bits
Write
10
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
Data byte–8 bits
10
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
Repeated start
18:11
19
18:11
19
27:20
28
20
Acknowledge from slave
Stop
27:21
28
Slave address–7 bits
Read
29
29
Acknowledge from slave
Data from slave–8 bits
NOT Acknowledge
Stop
37:30
38
39
Rev. 1.0
11
Si53156-A13A
Control Register 0. Byte 0
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset settings = 00000000
Bit
Name
Reserved
Function
7:0
Control Register 1. Byte 1
Bit
D7
D6
D5
D4
DIFF0_OE
R/W
D3
D2
DIFF1_OE
R/W
D1
D0
DIFF2_OE
R/W
Name
Type
R/W
R/W
R/W
R/W
R/W
Reset settings = 00010101
Bit
7:5
4
Name
Function
Reserved
DIFF0_OE
Output Enable for DIFF0.
0: Output disabled.
1: Output Enabled.
3
2
Reserved
DIFF1_OE
Output Enable for DIFF1.
0: Output disabled.
1: Output enabled.
1
0
Reserved
DIFF2_OE
Output Enable for DIFF2.
0: Output disabled.
1: Output enabled.
12
Rev. 1.0
Si53156-A13A
Control Register 2. Byte 2
Bit
D7
D6
D5
D4
D3
D2
D1
D0
DIFF3_OE
DIFF4_OE
DIFF5_OE
Name
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset settings = 11100000
Bit
Name
Function
7
DIFF3_OE
Output Enable for DIFF3.
0: Output disabled.
1: Output enabled.
6
5
DIFF4_OE
Output Enable for DIFF4.
0: Output disabled.
1: Output enabled.
DIFF5_OE
Reserved
Output Enable for DIFF5.
0: Output disabled.
1: Output enabled.
4:0
Control Register 3. Byte 3
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
Rev Code[3:0]
Vendor ID[3:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset settings = 00001000
Bit
Name
Function
7:4
Rev Code[3:0]
Vendor ID[3:0]
Program Revision Code.
3:0
Vendor Identification Code.
Rev. 1.0
13
Si53156-A13A
Control Register 4. Byte 4
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
BC[7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset settings = 00000110
Bit
Name
BC[7:0]
Function
7:0
Byte Count Register.
Control Register 5. Byte 5
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name DIFF_Amp_Sel DIFF_Amp_Cntl[2] DIFF_Amp_Cntl[1] DIFF_Amp_Cntl[0]
Type
R/W
R/W
R/W
R/W
R/W R/W R/W R/W
Reset settings = 11011000
Bit
Name
Function
7
DIFF_Amp_Sel
Amplitude Control for DIFF Differential Outputs.
0: Differential outputs with Default amplitude.
1: Differential outputs amplitude is set by Byte 5[6:4].
6
5
DIFF_Amp_Cntl[2]
DIFF_Amp_Cntl[1]
DIFF_Amp_Cntl[0]
Reserved
DIFF Differential Outputs Amplitude Adjustment.
000: 300 mV 001: 400 mV 010: 500 mV 011: 600 mV
100: 700 mV 101: 800 mV 110: 900 mV 111: 1000 mV
4
3:0
14
Rev. 1.0
Si53156-A13A
5. Pin Descriptions: 32-Pin QFN
32
31
30
29 28 27
26
25
VDD
24
23
VDD
1
2
3
4
5
6
7
8
DIFF5
OE2*
VDD
22
21
DIFF5
VDD
OE3*
33
GND
20 DIFF4
OE4*
OE5*
NC
19
DIFF4
18 DIFF3
VDD
17
DIFF3
9
10
11
12
13
14 15
16
*Note: Internal 100 kohm pull-up.
Figure 4. 32-Pin QFN
Table 6. Si53156-A13A 32-Pin QFN Descriptions
Pin #
Name
Type
Description
PWR 3.3 V power supply.
1
VDD
I,PU Active high input pin enables DIFF2 (internal 100 k pull-up).
2
OE2
Refer to Table 1 on page 4 for OE specifications.
PWR 3.3 V Power Supply
3
4
VDD
OE3
I,PU Active high input pin enables DIFF3 (internal 100 k pull-up).
Refer to Table 1 on page 4 for OE specifications.
I,PU Active high input pin enables DIFF4 (internal 100 k pull-up).
5
6
OE4
OE5
Refer to Table 1 on page 4 for OE specifications.
I,PU Active high input pin enables DIFF5 (internal 100 k pull-up).
Refer to Table 1 on page 4 for OE specifications.
NC No connect.
7
8
NC
PWR 3.3 V power supply.
VDD
O, DIF 0.7 V, 100 MHz differential clock.
O, DIF 0.7 V, 100 MHz differential clock.
O, DIF 0.7 V, 100 MHz differential clock.
9
DIFF0
DIFF0
DIFF1
10
11
Rev. 1.0
15
Si53156-A13A
Table 6. Si53156-A13A 32-Pin QFN Descriptions
Pin #
Name
Type
Description
12
DIFF1
O, DIF 0.7 V, 100 MHz differential clock.
PWR 3.3 V power supply.
13
14
15
16
17
18
19
20
21
22
23
24
25
26
VDD
DIFF2
DIFF2
VDD
O, DIF 0.7 V, 100 MHz differential clock.
O, DIF 0.7 V, 100 MHz differential clock.
PWR 3.3 V power supply.
DIFF3
DIFF3
DIFF4
DIFF4
VDD
O, DIF 0.7 V, 100 MHz differential clock.
O, DIF 0.7 V, 100 MHz differential clock.
O, DIF 0.7 V, 100 MHz differential clock.
O, DIF 0.7 V, 100 MHz differential clock.
PWR 3.3 V power supply.
DIFF5
DIFF5
VDD
O, DIF 0.7 V, 100 MHz differential clock.
O, DIF 0.7 V, 100 MHz differential clock.
PWR 3.3 V power supply.
SCLK
SDATA
I
SMBus compatible SCLOCK.
I/O SMBus compatible SDATA.
3.3 V LVTTL input. This pin is a level sensitive strobe used to determine
when latch inputs are valid and are ready to be sampled. A real-time
active low input for asserting power down (PDB) and disabling all outputs
27
CKPWRGD_PDB
I, PU
(internal 100 k pull-up).
28
29
VDD
PWR 3.3 V power supply.
0.7 V Differential True Input, typically 100 MHz. Input frequency range
DIFFIN
I
100 to 210 MHz.
0.7 V Differential Complement Input, typically 100 MHz. Input frequency
range 100 to 210 MHz.
30
31
DIFFIN
OE0
O
Active high input pin enables DIFF0 (internal 100 k pull-up).
Refer to Table 1 on page 4 for OE specifications.
I,PU
Active high input pin enables DIFF1 (internal 100 k pull-up).
32
33
OE1
I,PU
Refer to Table 1 on page 4 for OE specifications.
GND
GND Ground for bottom pad of the IC.
16
Rev. 1.0
Si53156-A13A
6. Ordering Guide
Part Number
Lead-free
Package Type
Temperature
Si53156-A13AGM
Si53156-A13AGMR
32-pin QFN
Extended, –40 to 85 C
Extended, –40 to 85 C
32-pin QFN—Tape and Reel
Rev. 1.0
17
Si53156-A13A
7. Package Outline
Figure 5 illustrates the package details for the Si53156-A13A. Table 7 lists the values for the dimensions shown in
the illustration.
Figure 5. 32-Pin Quad Flat No Lead (QFN) Package
Table 7. Package Diagram Dimensions
Min
Nom
Max
Dimension
A
A1
b
0.70
0.00
0.18
0.75
0.02
0.25
0.80
0.05
0.30
D
D2
e
E
E2
L
5.00 BSC
3.20
0.50 BSC
5.00 BSC
3.20
3.15
3.25
3.15
0.30
3.25
0.50
0.40
aaa
bbb
ccc
ddd
0.10
0.10
0.08
0.10
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
4. Coplanarity less than 0.08 mm.
5. Terminal #1 identifier and terminal numbering convention conform to JESD 95-1 SPP-012.
18
Rev. 1.0
Si53156-A13A
8. Land Pattern
Figure 6 illustrates the recommended land pattern details for the Si53156-A13A in a 32-pin QFN package. Table 8
lists the values for the dimensions shown in the illustration.
Figure 6. Land Pattern
Rev. 1.0
19
Si53156-A13A
Table 8. PCB Land Pattern Dimensions
Dimension
mm
4.01
4.01
3.20
3.20
0.50
0.26
0.86
S1
S
L1
W1
e
W
L
Notes:
General
1. All dimensions shown are in millimeters (mm).
2. This Land Pattern Design is based on the IPC-7351 guidelines.
Solder Mask Design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the
solder mask and the metal pad is to be 60 m minimum, all the way around the pad.
Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls
should be used to assure good solder paste release.
2. The stencil thickness should be 0.125mm (5 mils).
3. The ratio of stencil aperture to land pad size can be 1:1 for all perimeter pads.
4. A 3x3 array of 0.85mm square openings on a 1.00mm pitch can be used for the
center ground pad..
Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for Small Body Components.
20
Rev. 1.0
Si53156-A13A
DOCUMENT REVISION HISTORY
Revision 1.0
Initial “A13A” Revision derived from Si53156-A01A
data sheet.
21
Rev. 1.0
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intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical"
parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes
without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included
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