SI5323-C-GMR [SILICON]
Support Circuit, 1-Func, QFN-36;
| 型号： | SI5323-C-GMR |
| 厂家： | 
SILICON |
| 描述： | Support Circuit, 1-Func, QFN-36 ATM 异步传输模式 电信 电信集成电路 |
| 文件： | 总40页 (文件大小：1508K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si5323
PIN-PROGRAMMABLE PRECISION CLOCK
MULTIPLIER/JITTER ATTENUATOR
Features
Pin-selectable output frequencies
ranging from 8 kHz–708 MHz
Ultra-low jitter clock outputs as low
as 250 fs rms (12 kHz–20 MHz)
270 fs rms (50 kHz–80 MHz)
Integrated loop filter with selectable
loop bandwidth (60 Hz–8.4 kHz)
Meets ITU-T G.8251 and Telcordia
OC-192 GR-253-CORE jitter
specifications
Dual clock outputs with selectable
signal format (LVPECL, LVDS, CML,
CMOS)
Support for ITU G.709 FEC ratios
(255/238, 255/237, 255/236)
LOL, LOS alarm outputs
Pin-controlled output phase adjust
Single supply 1.8 ±5%, 2.5 or 3.3 V
±10% operation with high PSRR
On-chip voltage regulator
Ordering Information:
See page 33.
Hitless input clock switching with
phase build-out and digital hold
Small size: 6 x 6 mm 36-lead QFN
Applications
Pin Assignments
SONET/SDH OC-48/STM-16 and
OC-192/STM-64 line cards
GbE/10GbE, 1/2/4/8/10GFC line cards
ITU G.709 line cards
Optical modules
Test and measurement
Synchronous Ethernet
36 35 34 33 32 31 30 29 28
RST
FRQTBL
C1B
1
2
3
4
5
6
7
8
9
27 FRQSEL3
26
Description
FRQSEL2
25 FRQSEL1
C2B
24
23
FRQSEL0
BWSEL1
The Si5323 is a jitter-attenuating precision clock multiplier for high-speed
communication systems, including SONET OC-48/OC-192, Ethernet, and Fibre
Channel. The Si5323 accepts dual clock inputs ranging from 8 kHz to 707 MHz
and generates two equal frequency-multiplied clock outputs ranging from 8 kHz to
1050 MHz. The input clock frequency and clock multiplication ratio are selectable
from a table of popular SONET, Ethernet, and Fibre Channel rates. The Si5323 is
based on Silicon Laboratories' 3rd-generation DSPLL® technology, which
provides any-frequency synthesis and jitter attenuation in a highly integrated PLL
solution that eliminates the need for external VCXO and loop filter components.
The DSPLL loop bandwidth is digitally programmable, providing jitter performance
optimization at the application level. Operating from a single 1.8, 2.5, or 3.3 V
supply, the Si5323 is ideal for providing clock multiplication and jitter attenuation in
high performance timing applications.
GND
Pad
VDD
XA
22 BWSEL0
XB
21
20
19
CS_CA
INC
GND
DEC
AUTOSEL
10 11 12 13 14 15 16 17 18
Functional Block Diagram
Xtal or Refclock
CKOUT1
CKIN1
®
Signal Format
DSPLL
CKOUT2
CKIN2
Disable/BYPASS
Loss of Signal
Loss of Lock
Control
Signal Detect
VDD (1.8, 2.5, or 3.3 V)
GND
Frequency Select
Bandwidth Select
Rate Select
Manual//Auto Switch
Clock Select
Skew Control
Rev. 1.0 1/11
Copyright © 2011 by Silicon Laboratories
Si5323
Si5323
2
Rev. 1.0
Si5323
TABLE OF CONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.1. Three-Level (3L) Input Pins (No External Resistors) . . . . . . . . . . . . . . . . . . . . . . . . .9
1.2. Three-Level Input Pins (Example with External Resistors) . . . . . . . . . . . . . . . . . . . . .9
2. Typical Phase Noise Plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
2.1. Example: SONET OC-192 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.1. External Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.2. Further Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.3. Frequency Plan Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4. Pin Descriptions: Si5323 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
5. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
6. Package Outline: 36-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
7. Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
8. Si5323 Device Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Rev. 1.0
3
Si5323
1. Electrical Specifications
Table 1. Recommended Operating Conditions
(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC)
Parameter
Temperature Range
Supply Voltage
Symbol
Test Condition
Min
–40
Typ
25
Max
85
Unit
ºC
V
T
A
V
3.3 V nominal
2.5 V nominal
1.8 V nominal
2.97
2.25
1.71
3.3
2.5
1.8
3.63
2.75
1.89
DD
V
V
Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted.
Table 2. DC Characteristics
(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC)
Parameter
Supply Current
(Supply current is indepen-
dent of V
Symbol
Test Condition
Min
Typ
Max
Units
I
LVPECL Format
622.08 MHz Out
All CKOUTs Enabled
LVPECL Format
622.08 MHz Out
Only 1 CKOUT Enabled
CMOS Format
19.44 MHz Out
All CKOUTs Enabled
CMOS Format
—
251
279
mA
DD
1
)
DD
—
—
—
217
204
194
243
234
220
mA
mA
mA
1
19.44 MHz Out
Only CKOUT1 Enabled
CKIN Input Pins
Input Common Mode
Voltage
(Input Threshold Voltage)
V
1.8 V ±5%
2.5 V ±10%
3.3 V ±10%
Single-ended
0.9
1.0
1.1
20
0
—
—
—
40
—
—
1.4
1.7
1.95
60
V
V
ICM
V
Input Resistance
CKN
CKN
k
V
RIN
2
Input Voltage Level Limits
See note
V
DD
VIN
Single-ended Input Voltage
Swing
V
f
f
< 212.5 MHz
0.2
—
V
ISE
CKIN
PP
See Figure 2.
> 212.5 MHz
0.25
—
—
V
CKIN
PP
See Figure 2.
Notes:
1. LVPECL outputs require nominal VDD > 2.5 V.
2. No overshoot or undershoot.
3. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 3 on page 9. In most
designs, an external resistor voltage divider is recommended.
4
Rev. 1.0
Si5323
Table 2. DC Characteristics (Continued)
(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC)
Parameter
Differential Input
Symbol
Test Condition
< 212.5 MHz
Min
Typ
Max
Units
V
f
f
0.2
—
—
V
ID
CKIN
PP
Voltage Swing
See Figure 2.
> 212.5 MHz
0.25
—
—
V
CKIN
PP
See Figure 2.
1
Output Clocks (CKOUTn)
Common Mode
CKO
LVPECL 100 load
V
1.42
–
—
—
V
1.25
–
V
VCM
DD
DD
line-to-line
Differential Output Swing
CKO
CKO
LVPECL 100 load
1.1
0.5
1.9
V
VD
PP
PP
line-to-line
Single-ended Output Swing
Differential Output Voltage
LVPECL 100 load
—
0.93
500
—
V
VSE
line-to-line
CKO
CML 100 load
350
—
425
mV
PP
VD
line-to-line
Common Mode
Output Voltage
CKO
CML 100 load
V
–
V
VCM
DD
0.36
line-to-line
Differential
Output Voltage
CKO
LVDS 100 load
500
350
1.125
700
425
1.2
900
500
1.275
—
mV
VD
PP
line-to-line
Low swing LVDS 100 load
mV
PP
line-to-line
Common Mode
Output Voltage
CKO
LVDS 100 load
V
VCM
line-to-line
Differential Output
Resistance
CKO
CML, LVDS, LVPECL
—
—
200
RD
Output Voltage Low
Output Voltage High
CKO
CKO
CMOS
—
—
0.4
—
V
V
VOLLH
V
= 1.71 V
0.8 x V
VOHLH
DD
DD
CMOS
Output Drive Current
CKO
IO
CMOS
Driving into CKO
for out-
VOL
put low or CKO
for output
VOH
high. CKOUT+ and CKOUT–
shorted externally.
V
V
= 1.8 V
= 3.3 V
—
—
7.5
32
—
—
mA
mA
DD
DD
Notes:
1. LVPECL outputs require nominal VDD > 2.5 V.
2. No overshoot or undershoot.
3. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 3 on page 9. In most
designs, an external resistor voltage divider is recommended.
Rev. 1.0
5
Si5323
Table 2. DC Characteristics (Continued)
(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC)
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
2-Level LVCMOS Input Pins
Input Voltage Low
V
V
V
V
V
V
V
= 1.71 V
= 2.25 V
= 2.97 V
= 1.89 V
= 2.25 V
= 3.63 V
—
—
—
—
—
—
—
—
—
—
75
0.5
0.7
0.8
—
V
V
IL
DD
DD
DD
DD
DD
DD
—
V
Input Voltage High
V
1.4
1.8
2.5
—
V
IH
—
V
—
V
Input Low Current
Input High Current
I
50
50
—
µA
µA
k
IL
I
—
IH
Weak Internal Input Pull-up
Resistor
R
—
PUP
Weak Internal Input
Pull-down Resistor
R
—
75
—
k
PDN
3-Level Input Pins
Input Voltage Low
Input Voltage Mid
Input Voltage High
Input Low Current
Input Mid Current
Input High Current
Notes:
0.15 x VDD
V
—
0.45 x VDD
0.85 x VDD
–20
—
—
—
—
—
—
V
V
ILL
0.55 x VDD
V
IMM
V
—
—
2
V
IHH
3
I
µA
µA
µA
ILL
3
I
–2
IMM
3
I
—
20
IHH
1. LVPECL outputs require nominal VDD > 2.5 V.
2. No overshoot or undershoot.
3. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 3 on page 9. In most
designs, an external resistor voltage divider is recommended.
6
Rev. 1.0
Si5323
Table 2. DC Characteristics (Continued)
(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC)
Parameter
LVCMOS Output Pins
Output Voltage Low
Symbol
Test Condition
Min
Typ
Max
Units
V
I = 2 mA
—
—
—
—
—
—
—
0.4
0.4
—
V
V
OL
OH
OZ
O
V
V
= 1.71 V
DD
I = 2 mA
O
= 2.97 V
DD
Output Voltage High
V
I = –2 mA
V
V
– 0.4
V
O
DD
DD
V
= 1.71 V
DD
I = –2 mA
– 0.4
—
V
O
V
= 2.97 V
DD
Disabled Leakage Current
I
RST = 0
–100
100
µA
Single-Ended Reference Clock Input Pin XA (XB with cap to gnd)
Input Resistance
XA
XA
XTAL/RefCLK
RATE[1:0] = LM, ML, MH, or
HM
—
0
12
—
—
—
k
RIN
VIN
Input Voltage Level Limits
Input Voltage Swing
1.2
1.2
V
XA
0.5
V
PP
VPP
Differential Reference Clock Input Pins (XA/XB)
Input Resistance
XA/XB
XTAL/RefCLK
RATE[1:0] = LM, ML, MH, or
HM
—
0
12
—
—
k
RIN
VIN
Differential Input Voltage
Level Limits
XA/XB
1.2
V
Input Voltage Swing
XA
/XB
0.5
—
1.2
V
PP, each
VPP
VPP
Notes:
1. LVPECL outputs require nominal VDD > 2.5 V.
2. No overshoot or undershoot.
3. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 3 on page 9. In most
designs, an external resistor voltage divider is recommended.
V
SIGNAL +
Single-Ended
Peak-to-Peak Voltage
Differential I/Os
V
ICM , V
VISE,VOSE
SIGNAL – OCM
(SIGNAL +) – (SIGNAL –)
ICM, VOCM
Differential Peak-to-Peak Voltage
V ,VOD
ID
V
t
SIGNAL +
SIGNAL –
VID = (SIGNAL+) – (SIGNAL–)
Figure 1. Voltage Characteristics
Rev. 1.0
7
Si5323
80%
20%
CKIN, CKOUT
tF
tR
Figure 2. Rise/Fall Time Characteristics
8
Rev. 1.0
Si5323
1.1. Three-Level (3L) Input Pins (No External Resistors)
VDD
Si5323
75 k
Iimm
75 k
External Driver
Figure 3. Three-Level Input Pins
1.2. Three-Level Input Pins (Example with External Resistors)
VDD
18 k
VDD
Si5323
75 k
3L input current
18 k
75 k
External Driver
One of eight resistors from a Panasonic EXB-D10C183J
(or similar) resistor pack
Figure 4. Three-Level Input Pins
Table 3. Three-Level Input Pins1,2,3,4
Parameter
Input Low Current
Min
–30 µA
–11 µA
—
Max
—
Input Mid Current
Input High Current
Notes:
–11 µA
–30 µA
1. The current parameters are the amount of leakage that the 3L inputs can tolerate from an external driver using the
external resistor values indicated in this example. In most designs, an external resistor voltage divider is
recommended.
2. Resistor packs are only needed if the leakage current of the external driver exceeds the current specified in
Table 2, Iimm. Any resistor pack may be used (e.g., Panasonic EXB-D10C183J). PCB layout is not critical.
3. If a pin is tied to ground or V , no resistors are needed.
DD
4. If a pin is left open (no connect), no resistors are needed.
Rev. 1.0
9
Si5323
Table 4. AC Characteristics
(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC)
Parameter
CKIN Input Pins
Symbol
Test Condition
Min
Typ
Max
Units
Input Frequency
CKN
.008
40
2
—
—
—
710
60
MHz
%
F
Input Duty Cycle (Minimum Pulse
Width)
Whichever is smaller
(i.e., the 40%/60% limitation
applies only to high clock
frequencies)
—
ns
CKN
DC
Input Capacitance
CKN
—
—
—
—
3
pF
ns
CIN
Input Rise/Fall Time
CKN
20–80%
11
TRF
See Figure 2
CKOUTn Output Pins
Output Frequency (Output not
configured for CMOS or disable)
.008
—
—
—
—
710
212.5
8
MHz
MHz
ns
CK
OF
Maximum Output Frequency in
CMOS Format
CKO
FMC
CMOS Output
—
Single-ended Output Rise/Fall
(20–80%)
V
= 1.71
DD
Cload = 5 pF
CKO
TRF
CMOS Output
—
—
2
ns
V
= 2.97
DD
Cload = 5 pF
20 to 80 %, f
= 622.08
—
—
230
—
350
±40
ps
ps
Differential Output Rise/Fall Time
CKO
OUT
TRF
Output Duty Cycle Differential
Uncertainty
CKO
100 Load
Line to Line
DC
Measured at 50% Point
(not for CMOS)
LVCMOS Input Pins
Minimum Reset Pulse Width
Input Capacitance
t
1
—
—
—
3
µs
pF
RSTMIN
C
—
IN
LVCMOS Output Pins
Rise/Fall Times
t
C
= 20 pf
LOAD
—
—
25
—
ns
RF
See Figure 2
LOS
From last CKIN to LOS
—
750
—
µs
LOSn Trigger Window
TRIG
Time to Clear LOL after LOS Cleared t
f unchanged and XA/XB
10
ms
CLRLOL
in
stable.
LOS to LOL
10
Rev. 1.0
Si5323
Table 4. AC Characteristics (Continued)
(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC)
Parameter
PLL Performance
Symbol
Test Condition
Min
Typ
Max
Units
Lock Time
t
—
1.2
sec
Whenever RST, FRQTBL,
RATE, BWSEL, or FRQSEL
are changed, with valid CKIN
to LOL; BW = 100 Hz
LOCKHW
Output Clock Phase Change
t
After clock switch
—
—
200
—
ps
P_STEP
f3 128 kHz
Closed Loop Jitter Peaking
Jitter Tolerance
J
0.05
—
0.1
—
dB
PK
5000/
BW
ns pk-
pk
BW determined by
BWSEL[1:0]
J
TOL
Spurious Noise
Max spur @ n x f3
(n > 1, n x f3 < 100 MHz)
—
–93
300
–70
500
dBc
SP
SPUR
TEMP
Phase Change due to Temperature
Variation
Max phase changes from –
40 to +85 ºC
—
ps
t
Table 5. Performance Specifications1, 2, 3, 4, 5
(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC)
Parameter
Symbol
Test Condition
50 kHz–80 MHz
12 kHz–20 MHz
800 Hz–80 MHz
Min
—
Typ
Max
0.42
0.41
0.45
Unit
Jitter Generation
J
0.27
0.25
0.28
ps rms
ps rms
ps rms
GEN
f
= f
= 622.08 MHz,
IN
OUT
—
LVPECL Output Format
BW = 120 Hz
—
Phase Noise
CKO
1 kHz offset
10 kHz offset
100 kHz offset
1 MHz offset
—
—
—
—
–106
–121
–122
–132
–87
–100
–104
–119
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
PN
f
= f
= 622.08 MHz
IN
OUT
LVPECL Output Format
Notes:
1. BWSEL [1:0] loop bandwidth settings provided in Table 11 on page 27.
2. 114.285 MHz 3rd OT crystal used as XA/XB input.
3. VDD = 2.5 V
4. TA = 85 °C
5. Test condition: fIN = 622.08 MHz, fOUT = 622.08 MHz, LVPECL clock input: 1.19 Vppd with 0.5 ns rise/fall time
(20-80%), LVPECL clock output.
Rev. 1.0
11
Si5323
Table 6. Thermal Characteristics
(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Thermal Resistance
Junction to Ambient
Still Air
—
32
—
ºC/W
JA
Thermal Resistance
Junction to Case
Still Air
—
14
—
ºC/W
JC
Table 7. Absolute Maximum Ratings
Parameter
DC Supply Voltage
Symbol
Value
Unit
V
–0.5 to 3.8
V
V
DD
LVCMOS Input Voltage
V
–0.3 to (V + 0.3)
DD
DIG
CKINn Voltage Level Limits
XA/XB Voltage Level Limits
Operating Junction Temperature
Storage Temperature Range
CKN
0 to V
V
VIN
DD
XA
0 to 1.2
–55 to 150
–55 to 150
2
V
VIN
T
C
C
kV
JCT
T
STG
ESD HBM Tolerance (100 pF, 1.5 kΩ); All pins except
CKIN+/CKIN–
ESD MM Tolerance; All pins except CKIN+/CKIN–
ESD HBM Tolerance (100 pF, 1.5 kΩ); CKIN+/CKIN–
ESD MM Tolerance; CKIN+/CKIN–
150
V
V
V
750
100
Latch-Up Tolerance
JESD78 Compliant
Note: Permanent device damage may occur if the Absolute Maximum Ratings are exceeded. Functional operation should be
restricted to the conditions as specified in the operation sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods of time may affect device reliability.
12
Rev. 1.0
Si5323
2. Typical Phase Noise Plots
The following is the typical phase noise performance of the Si5323. The clock input source was a Rohde and
Schwarz model SML03 RF Generator. The phase noise analyzer was an Agilent model E5052B. The Si5323
operates at 3.3 V with an ac coupled differential PECL output and an ac coupled differential sine wave input from
the RF generator at 0 dBm. Note that, as with any PLL, the output jitter that is below the loop BW is caused by the
jitter at the input clock. The loop BW was 120 Hz.
2.1. Example: SONET OC-192
Figure 5. Typical Phase Noise Plot
Jitter Band
Jitter, RMS
SONET_OC48, 12 kHz to 20 MHz
250 fs
SONET_OC192_A, 20 kHz to 80 MHz
SONET_OC192_B, 4 to 80 MHz
SONET_OC192_C, 50 kHz to 80 MHz
Brick Wall, 800 Hz to 80 MHz
274 fs
166 fs
267 fs
274 fs
Note: SONET jitter bands include the SONET skirts. The phase noise plot is brick wall integration.
Rev. 1.0
13
Si5323
C4
C3
1 µF
System
Power
Supply
0.1 µF
Ferrite
Bead
C2
C1
0.1 µF
0.1 µF
VDD = 3.3 V
130
82
130
82
0.1 µF
CKOUT1+
CKOUT1–
CKIN1+
+
–
100
CKIN1–
0.1 µF
0.1 µF
Clock Outputs
CKOUT2+
CKOUT2–
+
–
Input
100
Clock
VDD = 3.3 V
Sources1
0.1 µF
130
82
130
82
CKIN2+
CKIN2–
LOS1
LOS2
LOL
CKIN_1 Loss of Signal
CKIN_2 Loss of Signal
PLL Loss of Lock Indicator
XA
XB
Option 1:
114.285 MHz Crystal
0.1 µF
Si5323
Option 2:
Ext. Refclk+
Ext. Refclk–
XA
XB
0.1 µF
VDD
15 k
RATE2
Crystal/Ref Clk Rate
VDD
VDD
VDD
15 k
VDD
Manual/Automatic Clock15 k
Selection (L)15 k
AUTOSEL2
CKSEL3
FRQTBL2
15 k
Input Clock Select
15 k
15 k
Frequency Table Select
VDD
15 k
G
N
D
15 k
Frequency Select
FRQSEL[3:0]2
BWSEL[1:0]2
INC
15 k
15 k
Bandwidth Select
GND
15 k
Skew Increment
P
A
Skew Decrement
DEC
VDD
D 4
15 k
SFOUT[1:0]2
DBL2_BY2
RST
Signal Format Select
VDD
15 k
Clock Output 2 Disable/ 15 k
Bypass Mode Control 15 k
Reset
Notes:
1. Assumes differential LVPECL termination (3.3 V) on clock inputs.
2. Denotes tri-level input pins with states designated as L (ground), M (VDD/2), and H (VDD).
3. Assumes manual input clock selection.
4. GND pad must be connected for normal operation.
Figure 6. Si5323 Typical Application Circuit
14
Rev. 1.0
Si5323
electrical format of the clock outputs is programmable to
support LVPECL, LVDS, CML, or CMOS loads. If not
3. Functional Description
The Si5323 is a jitter-attenuating precision clock required, the second clock output can be powered down
multiplier for high-speed communication systems, to minimize power consumption. The phase difference
including SONET OC-48/OC-192, Ethernet, and Fibre between the selected input clock and the output clocks
Channel. The Si5323 accepts dual clock inputs ranging is adjustable in 200 ps increments for system skew
from 8 kHz to 707 MHz and generates two frequency- control. For system-level debugging, a bypass mode is
multiplied clock outputs ranging from 8 kHz to available which drives the output clock directly from the
1050 MHz. The two input clocks are at the same input clock, bypassing the internal DSPLL. The device is
frequency and the two output clocks are at the same powered by a single 1.8, 2.5, or 3.3 V supply.
frequency. The input clock frequency and clock
3.1. External Reference
multiplication ratio are selectable from a table of popular
SONET, Ethernet, and Fibre Channel rates. In addition An external, 38.88 MHz clock or
a
low-cost
to providing clock multiplication in SONET and datacom 114.285 MHz 3rd overtone crystal is used as part of a
applications, the Si5323 supports SONET-to-datacom fixed-frequency oscillator within the DSPLL. This
frequency translations. Silicon Laboratories offers a PC- external reference is required for the device to perform
based software utility, DSPLLsim, that can be used to jitter attenuation. Silicon Laboratories recommends
look up valid Si5323 frequency translations. This utility using a high-quality crystal. Specific recommendations
can be downloaded from http://www.silabs.com/timing may be found in the Any-Frequency Precision Clock
(click on Documentation).
Family Reference Manual. An external clock from a high
quality OCXO or TCXO can also be used as a reference
for the device.
The Si5323 is based on Silicon Laboratories' 3rd-
®
generation DSPLL technology, which provides any-
frequency synthesis and jitter attenuation in a highly In digital hold, the DSPLL remains locked to this
integrated PLL solution that eliminates the need for external reference. Any changes in the frequency of this
external VCXO and loop filter components. The Si5323 reference when the DSPLL is in digital hold will be
PLL loop bandwidth is selectable via the BWSEL[1:0] tracked by the output of the device. Note that crystals
pins and supports a range from 60 Hz to 8.4 kHz. The can have temperature sensitivities.
DSPLLsim software utility can be used to calculate valid
3.2. Further Documentation
loop bandwidth settings for a given input clock
frequency/clock multiplication ratio.
Consult the Silicon Laboratories Any-Frequency
Precision Clock Family Reference Manual (FRM) for
detailed information about the Si5323. Additional design
support is available from Silicon Laboratories through
your distributor.
The Si5323 supports hitless switching between the two
input clocks in compliance with GR-253-CORE and GR-
1244-CORE that greatly minimizes the propagation of
phase transients to the clock outputs during an input
clock transition (<200 ps typ). Manual and automatic Silicon Laboratories has developed
a PC-based
revertive and non-revertive input clock switching options software utility called DSPLLsim to simplify device
are available via the AUTOSEL input pin. The Si5323 configuration, including frequency planning and loop
monitors both input clocks for loss-of-signal and bandwidth selection. The FRM and this utility can be
provides a LOS alarm when it detects missing pulses on downloaded from http://www.silabs.com/timing (click on
either input clock. The device monitors the lock status of Documentation).
the PLL. The lock detect algorithm works by
continuously monitoring the phase of the input clock in
relation to the phase of the feedback clock.
The Si5323 provides a digital hold capability that allows
the device to continue generation of a stable output
clock when the selected input reference is lost. During
digital hold, the DSPLL generates an output frequency
based on a historical average that existed a fixed
amount of time before the error event occurred,
eliminating the effects of phase and frequency
transients that may occur immediately preceding digital
hold.
The Si5323 has two differential clock outputs. The
Rev. 1.0
15
Si5323
3.3. Frequency Plan Tables
The Si5323 provides flexible frequency plans for SONET, Datacom, and interworking between the two (Table 8,
Table 9, and Table 10 respectively). Both CKINn inputs must be the same Fin frequency and CKOUTn outputs as
specified in the tables.
The following notes apply to Tables 8, 9, and 10:
1. All multiplication ratios are exact, but the frequency values are rounded.
2. For loop bandwidth settings, BWSEL[1:0], f3 values, and frequency operating ranges, consult the DSPLLsim
software configuration utility.
Table 8. SONET Clock Multiplication Settings (FRQTBL=L)
Plan #
FRQSEL
[3:0]
f
(MHz)
Mult Factor
f
* (MHz)
OUT
IN
0
1
LLLL
LLLM
LLLH
0.008
1
0.008
19.44
2430
2
4860
38.88
3
LLML
LLMM
LLMH
LLHL
9720
77.76
4
19440
155.52
311.04
622.08
19.44
5
38880
6
77760
7
LLHM
LLHH
LMLL
LMLM
LMLH
LMML
LMMM
LMMH
LMHL
LMHM
LMHH
LHLL
19.44
1
8
2
38.88
9
4
77.76
10
11
12
13
14
15
16
17
18
19
20
8
155.52
166.63
167.33
168.04
311.04
622.08
666.51
669.33
672.16
933.12
1049.76
8 x (255/238)
8 x (255/237)
8 x (255/236)
16
32
32 x (255/238)
32 x (255/237)
32 x (255/236)
48
LHLM
LHLH
54
16
Rev. 1.0
Si5323
Table 8. SONET Clock Multiplication Settings (FRQTBL=L) (Continued)
Plan #
FRQSEL
[3:0]
f
(MHz)
Mult Factor
f
* (MHz)
OUT
IN
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
LHML
LHMM
LHMH
LHHL
38.88
1
38.88
77.76
2
4
155.52
622.08
666.51
669.33
672.16
19.44
16
LHHM
LHHH
MLLL
16 x (255/238)
16 x (255/237)
16 x (255/236)
MLLM
MLLH
MLML
MLMM
MLMH
MLHL
MLHM
MLHH
MMLL
MMLM
MMLH
MMML
MMMM
MMMH
MMHL
MMHM
MMHH
MHLL
MHLM
MHLH
MHML
MHMM
MHMH
MHHL
77.76
1/4
1/2
38.88
1
77.76
2
2 x (255/238)
2 x (255/237)
2 x (255/236)
4
155.52
166.63
167.33
168.04
311.04
622.08
666.51
669.33
672.16
19.44
8
8 x (255/238)
8 x (255/237)
8 x (255/236)
1/8
155.52
1/4
38.88
1/2
77.76
1
155.52
166.63
167.33
168.04
311.04
622.08
666.51
669.33
672.16
255/238
255/237
255/236
2
4
4 x (255/238)
4 x (255/237)
4 x (255/236)
Rev. 1.0
17
Si5323
Table 8. SONET Clock Multiplication Settings (FRQTBL=L) (Continued)
Plan #
FRQSEL
[3:0]
f
(MHz)
Mult Factor
f
* (MHz)
OUT
IN
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
MHHM
MMHM
MHHH
MHML
HLLL
166.63
167.33
168.04
311.04
238/255
155.52
1
166.63
622.08
666.51
155.52
167.33
622.08
669.33
155.52
168.04
622.08
672.16
311.04
622.08
666.51
669.33
672.16
19.44
4 x (238/255)
4
237/255
MMHM
HLLM
MHML
HLLH
1
4 x (237/255)
4
236/255
MMHM
HLML
MHML
HLMM
HLMH
HLHL
1
4 x (236/255)
4
1
2
2 x (255/238)
2 x (255/237)
2 x (255/236)
1/32
HLHM
HLHH
HMLL
HMLM
HMLH
HMML
HMMM
HMMH
HMHL
HMHM
HMHH
HHLL
622.08
1/16
38.88
1/8
77.76
1/4
155.52
311.04
622.08
666.51
669.33
672.16
155.52
166.63
622.08
666.51
1/2
1
255/238
255/237
255/236
1/4 x 238/255
1/4
666.51
HMML
HHLM
HMMH
238/255
1
18
Rev. 1.0
Si5323
Table 8. SONET Clock Multiplication Settings (FRQTBL=L) (Continued)
Plan #
FRQSEL
[3:0]
f
(MHz)
Mult Factor
f
* (MHz)
OUT
IN
82
83
84
85
86
87
88
89
HHLH
HMML
HHML
HMMH
HHMM
HMML
HHMH
HMMH
669.33
1/4 x 237/255
155.52
1/4
167.33
622.08
669.33
155.52
168.04
622.08
672.16
237/255
1
1/4 x 236/255
1/4
672.16
236/255
1
Table 9. Datacom Clock Multiplication Settings (FRQTBL = M)
Plan # FRQSEL[3:0]
f
(MHz)
Mult Factor
f
* (MHz)
OUT
IN
0
1
LLLL
LLLM
LLLH
15.625
2
31.25
62.5
4
2
8
125
3
LLML
LLMM
LLMH
LLHL
16
250
4
25
17/4
106.25
125
5
5
6
25/4 x 66/64
161.13
164.36
172.64
173.37
176.1
176.84
212.5
425
7
LLHM
LLHH
LMLL
LMLM
LMLH
LMML
LMMM
LMMH
LMHL
LMHM
LMHH
LHLL
51/8 x 66/64
8
25/4 x 66/64 x 255/238
25/4 x 66/64 x 255/237
51/8 x 66/64 x 255/238
51/8 x 66/64 x 255/237
17/2
9
10
11
12
13
14
15
16
17
18
19
20
21
22
17
25 x 66/64
644.53
657.42
690.57
693.48
704.38
707.35
62.5
51/2 x 66/64
25 x 66/64 x 255/238
25 x 66/64 x 255/237
51/2 x 66/64 x 255/238
51/2 x 66/64 x 255/237
2
LHLM
LHLH
LHML
LHMM
31.25
4
125
8
250
Rev. 1.0
19
Si5323
Table 9. Datacom Clock Multiplication Settings (FRQTBL = M) (Continued)
Plan # FRQSEL[3:0]
f
(MHz)
Mult Factor
f
* (MHz)
OUT
IN
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
LHMH
LHHL
53.125
2
4
106.25
212.5
425
LHHM
LHHH
MLLL
8
106.25
3/2 x 66/64
164.36
176.1
3/2 x 66/64 x 255/238
3/2 x 66/64 x 255/237
2
MLLM
MLLH
176.84
212.5
MLML
MLMM
MLMH
MLHL
4
425
6 x 66/64
657.42
704.38
707.35
161.13
172.64
173.37
644.53
690.57
693.48
161.13
172.64
173.37
644.53
690.57
693.48
164.36
176.1
6 x 66/64 x 255/238
6 x 66/64 x 255/237
10/8 x 66/64
10/8 x 66/64 x 255/238
10/8 x 66/64 x 255/237
5 x 66/64
MLHM
MLHH
MMLL
MMLM
MMLH
MMML
MMMM
MMMH
MMHL
MMHM
MMHH
MHLL
125
5 x 66/64 x 255/238
5 x 66/64 x 255/237
66/64
156.25
66/64 x 255/238
66/64 x 255/237
4 x 66/64
4 x 66/64 x 255/238
4 x 66/64 x 255/237
66/64
MMMM
MMMH
MMHL
MMHM
MMHH
MHLL
159.375
66/64 x 255/238
66/64 x 255/237
4 x 66/64
176.84
657.4
4 x 66/64 x 255/238
4 x 66/64 x 255/237
4/5 x 64/66
704.38
707.35
125
MHLM
MHLH
MHML
MHMM
MHMH
MHHL
161.13
255/238
172.64
173.37
644.53
690.57
693.48
255/237
4
4 x 255/238
4 x 255/237
20
Rev. 1.0
Si5323
Table 9. Datacom Clock Multiplication Settings (FRQTBL = M) (Continued)
Plan # FRQSEL[3:0]
f
(MHz)
Mult Factor
f
* (MHz)
OUT
IN
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
MHHM
MHLH
MHML
MHMM
MHMH
MHHL
MHHH
HLLL
164.36
2/3 x 64/66
106.25
255/238
176.1
176.84
657.42
704.38
707.35
125
255/237
4
4 x 255/238
4 x 255/237
172.64
173.37
176.1
4/5 x 64/66 x 238/255
64/66 x 238/255
156.25
161.13
644.53
690.57
125
HLLM
HLLH
238/255
4 x 238/255
MHMM
HLML
HLMM
HLMH
HLHL
4
4/5 x 64/66 x 237/255
64/66 x 237/255
156.25
161.13
644.53
693.48
106.25
159.375
164.36
657.42
704.38
106.25
159.375
164.36
657.42
707.35
425
237/255
4 x 237/255
MHMM
HLHM
HLLL
4
2/3 x 64/66 x 238/255
64/66 x 238/255
HLLM
HLLH
238/255
4 x 238/255
MHMM
HLHH
HLMM
HLMH
HLHL
4
176.84
2/3 x 64/66 x 237/255
64/66 x 237/255
237/255
4 x 237/255
MHMM
HMLL
HMLM
HMLH
HMML
HMMM
HMMH
HMHL
HMHM
HMML
HMMM
HMMH
HMHL
4
212.5
425
2
1
425
644.53
1/5 x 64/66
1/4
125
161.13
644.53
690.57
693.48
106.25
164.36
657.42
704.38
707.35
1
255/238
255/237
1/6 x 64/66
1/4
657.42
1
255/238
255/237
Rev. 1.0
21
Si5323
Table 9. Datacom Clock Multiplication Settings (FRQTBL = M) (Continued)
Plan # FRQSEL[3:0]
f
(MHz)
Mult Factor
f
* (MHz)
OUT
IN
96
HMHH
HHLL
690.57
693.48
704.38
707.35
1/5 x 64/66 x 238/255
125
97
1/4 x 64/66 x 238/255
156.25
161.13
172.64
644.53
690.57
125
98
HHLM
HMML
HHLH
HMMM
HHML
HHMM
HHMH
HMML
HHHL
HMMM
HHHM
HHLL
1/4 x 238/255
99
1/4
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
238/255
1
1/5 x 64/66 x 237/255
1/4 x 64/66 x 237/255
156.25
161.13
173.37
644.53
693.48
106.25
159.375
164.36
176.1
1/4 x 237/255
1/4
237/255
1
1/6 x 64/66 x 238/255
1/4 x 64/66 x 238/255
HHLM
HMML
HHLH
HMMM
HHHH
HHMM
HHMH
HMML
HHHL
HMMM
1/4 x (238/255)
1/4
238/255
657.42
704.38
106.25
159.375
164.36
176.84
657.42
707.35
1
1/6 x 64/66 x 237/255
1/4 x 64/66 x 237/255
1/4 x (237/255)
1/4
237/255
1
22
Rev. 1.0
Si5323
Table 10. SONET to Datacom Clock Multiplication Settings
Plan #
FRQSEL[3:0]
f
(MHz)
Mult Factor
f
* (MHz)
OUT
IN
0
1
2
3
4
5
6
7
8
9
LLLL
LLLM
LLLH
LLML
LLMM
LLMH
LLHL
LLHM
LLHH
LMLL
0.008
3125
6480
25
51.84
53.125
62.5
53125/8
15625/2
53125/4
15625
106.25
125
78125/4
159375/8
53125/2
53125
156.25
159.375
212.5
425
Rev. 1.0
23
Si5323
Table 10. SONET to Datacom Clock Multiplication Settings (Continued)
Plan #
FRQSEL[3:0]
f
(MHz)
Mult Factor
f
* (MHz)
OUT
IN
10
11
12
13
14
15
16
17
LMLM
LMLH
LMML
LMMM
LMMH
LMHL
LMHM
LMHH
19.440
625/486
10625/3888
3125/972
25
53.125
62.5
106.25
125
10625/1944
3125/486
15625/1944
31875/3888
156.25
159.375
161.13
15625/1944 x
66/64
18
19
LHLL
31875/3888 x
66/64
164.36
172.64
LHLM
15625/1944 x
66/64 x 255/23
8
20
LHLH
31875/3888 x
66/64 x 255/23
8
176.1
21
22
23
LHML
LHMM
LHMH
10625/972
10625/486
212.5
425
15625/486 x 6
6/64
644.53
24
25
26
LHHL
LHHM
LHHH
31875/972 x 6
6/64
657.42
690.57
704.38
15625/486 x 6
6/64 x 255/238
31875/972 x 6
6/64 x 255/238
27
28
29
30
31
32
33
34
MLLL
MLLM
MLLH
MLML
MLMM
MLMH
MLHL
MLHM
27.000
1
250/91
11/4
2
27
74.17582
74.25
125
62.500
74.176
4
250
91/250
1
27
74.17582
74.25
91 x 11/250 x
4
24
Rev. 1.0
Si5323
Table 10. SONET to Datacom Clock Multiplication Settings (Continued)
Plan #
FRQSEL[3:0]
f
(MHz)
Mult Factor
f
* (MHz)
OUT
IN
35
36
MLHH
MMLL
74.250
4/11
27
4 x 250/11 x 9
1
74.17582
37
38
39
40
41
42
MMLM
MMLH
MMML
MMMM
MMMH
MMHL
1
74.25
106.25
125
77.760
10625/7776
3125/1944
15625/7776
31875/15552
156.25
159.375
161.13
15625/7776 x
66/64
43
44
MMHM
MMHH
31875/15552 x
66/64
164.36
172.64
15625/7776 x
66/64 x 255/23
8
45
MHLL
31875/15552 x
66/64 x 255/2
38
176.1
46
47
48
MHLM
MHLH
MHML
10625/3888
10625/1944
212.5
425
15625/1944 x
66/64
644.53
49
50
MHMM
MHMH
31875/3888 x
66/64
657.42
690.57
15625/1944 x
66/64 x 255/23
8
51
MHHL
31875/3888 x
66/64 x 255/23
8
704.38
Rev. 1.0
25
Si5323
Table 10. SONET to Datacom Clock Multiplication Settings (Continued)
Plan #
FRQSEL[3:0]
f
(MHz)
Mult Factor
f
* (MHz)
OUT
IN
52
53
54
MHHM
MHHH
HLLL
155.520
15625/15552
31875/31104
156.25
159.375
161.13
15625/15552 x
66/64
55
56
HLLM
HLLH
31875/31104 x
66/64
164.36
172.64
15625/15552 x
66/64 x 255/2
38
57
HLML
31875/31104 x
66/64 x 255/2
38
176.1
58
59
60
HLMM
HLMH
HLHL
10625/7776
10625/3888
212.5
425
15625/3888 x
66/64
644.53
61
62
HLHM
HLHH
31875/7776 x
66/64
657.42
690.57
15625/3888 x
66/64 x 255/23
8
63
HMLL
31875/7776 x
66/64 x 255/23
8
704.38
64
65
66
HMLM
HMLH
HMML
622.080
15625/15552 x
66/64
644.53
657.42
690.57
31875/31104 x
66/64
15625/15552 x
66/64 x 255/2
38
67
HMMM
31875/31104 x
66/64 x 255/2
38
704.38
26
Rev. 1.0
Si5323
3.3.1. Recommended Reset Guidelines
Follow the recommended RESET guidelines in Table 11 when reset should be applied to the device.
Table 11. Si5323 Pins and Reset
Pin #
Si5323 Pin
Name
Must Reset after Changing
2
FRQTBL
RATE0
Yes
11
14
15
19
20
22
23
24
25
26
27
30
33
Yes
DBL2_BY
RATE1
No
Yes
DEC
No
INC
No
BWSEL0
BWSEL1
FRQSEL0
FRQSEL1
FRQSEL2
FRQSEL3
SFOUT1
SFOUT0
Yes
Yes
Yes
Yes
Yes
Yes
No, but skew not guaranteed without Reset
No, but skew not guaranteed without Reset
Rev. 1.0
27
Si5323
4. Pin Descriptions: Si5323
36 35 34 33 32 31 30 29 28
RST
FRQTBL
C1B
1
27 FRQSEL3
26
2
3
4
5
6
7
8
9
FRQSEL2
25 FRQSEL1
C2B
24
23
FRQSEL0
BWSEL1
GND
Pad
VDD
XA
22 BWSEL0
XB
21
20
19
CS_CA
INC
GND
DEC
AUTOSEL
10 11 12 13 14 15 16 17 18
Pin assignments are preliminary and subject to change.
Table 12. Si5323 Pin Descriptions
Signal Level Description
Pin #
Pin Name
I/O
1
RST
I
LVCMOS
External Reset.
Active low input that performs external hardware reset of
device. Resets all internal logic to a known state. Clock
outputs are tristated during reset. After rising edge of RST
signal, the Si5323 will perform an internal self-calibration
when a valid input signal is present.
This pin has a weak pull-up.
2
FRQTBL
I
3-Level
Frequency Table Select.
Selects SONET/SDH, datacom, or SONET/SDH to datacom
frequency table.
L = SONET/SDH
M = Datacom
H = SONET/SDH to Datacom
This pin has a weak pull-up and weak pull-down and defaults
to M.
Some designs may require an external resistor voltage
divider when driven by an active device that will tristate.
3
C1B
O
LVCMOS
CKIN1 Loss of Signal.
Active high loss-of-signal indicator for CKIN1. Once
triggered, the alarm will remain active until CKIN1 is
validated.
0 = CKIN1 present
1 = LOS on CKIN1
28
Rev. 1.0
Si5323
Table 12. Si5323 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
4
C2B
O
LVCMOS
CKIN2 Loss of Signal.
Active high loss-of-signal indicator for CKIN2. Once
triggered, the alarm will remain active until CKIN2 is
validated.
0 = CKIN2 present
1 = LOS on CKIN2
5, 10,
32
V
V
Supply
Supply.
DD
DD
The device operates from a 1.8, 2.5, or 3.3 V supply. Bypass
capacitors should be associated with the following V pins:
DD
5
10
32
0.1 µF
0.1 µF
0.1 µF
A 1.0 µF should also be placed as close to device as is
practical.
7
6
XB
XA
I
Analog
External Crystal or Reference Clock.
External crystal should be connected to these pins to use
internal oscillator based reference. Refer to Family
Reference Manual for interfacing to an external reference.
External reference must be from a high-quality clock source
(TCXO, OCXO). Frequency of crystal or external clock is set
by the RATE pins.
8, 31
9
GND
GND
I
Supply
3-Level
Ground.
Must be connected to system ground. Minimize the ground
path impedance for optimal performance of this device.
AUTOSEL
Manual/Automatic Clock Selection.
Three level input that selects the method of input clock
selection to be used.
L = Manual
M = Automatic non-revertive
H = Automatic revertive
This pin has a weak pull-up and weak pull-down and defaults
to M.
Some designs may require an external resistor voltage
divider when driven by an active device that will tri-state.
11
15
RATE0
RATE1
I
3-Level
External Crystal or Reference Clock Rate.
Three level inputs that select the type and rate of external
crystal or reference clock to be applied to the XA/XB port.
Refer to the Family Reference Manual for settings. These
pins have both a weak pull-up and a weak pull-down and
default to M.
Some designs may require an external resistor voltage
divider when driven by an active device that will tri-state.
12
13
CKIN2+
CKIN2–
I
Clock Input 2.
Differential input clock. This input can also be driven with a
single-ended signal. Input frequency selected from a table of
values. The same frequency must be applied to CKIN1 and
CKIN2.
Rev. 1.0
29
Si5323
Table 12. Si5323 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
14
DBL2_BY
I
3-Level
Output 2 Disable/Bypass Mode Control.
Controls enable of CKOUT2 divider/output buffer path and
PLL bypass mode.
L = CKOUT2 enabled
M = CKOUT2 disabled
H = Bypass mode with CKOUT2 enabled
This pin has a weak pull-up and weak pull-down and defaults
to M.
Some designs may require an external resistor voltage
divider when driven by an active device that will tri-state.
16
17
CKIN1+
CKIN1–
I
Multi
Clock Input 1.
Differential input clock. This input can also be driven with a
single-ended signal. Input frequency selected from a table of
values. The same frequency must be applied to CKIN1 and
CKIN2.
18
19
LOL
O
LVCMOS
PLL Loss of Lock Indicator.
This pin functions as the active high PLL loss of lock
indicator.
0 = PLL locked
1 = PLL unlocked
DEC
I
LVCMOS
Skew Decrement.
A pulse on this pin decreases the input to output device skew
by 1/f
(approximately 200 ps). There is no limit on the
OSC
range of skew adjustment by this method. If both INC and
DEC are tied high, phase buildout is disabled and the device
maintains a fixed-phase relationship between the selected
input clock and the output clock during an input clock
transition. Detailed operations and timing characteristics for
this pin may be found in the Any-Frequency Precision Clock
Family Reference Manual.
This pin has a weak pull-down.
20
INC
I
LVCMOS
Skew Increment.
A pulse on this pin increases the input to output device skew
by 1/f
(approximately 200 ps). There is no limit on the
OSC
range of skew adjustment by this method. If both INC and
DEC are tied high, phase buildout is disabled and the device
maintains a fixed-phase relationship between the selected
input clock and the output clock during an input clock
transition. Detailed operations and timing characteristics for
this pin may be found in the Any-Frequency Precision Clock
Family Reference Manual.
Note: If NI_HS = 4, increment is not available.
This pin has a weak pull-down.
30
Rev. 1.0
Si5323
Table 12. Si5323 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
21
CS_CA
I/O
LVCMOS
Input Clock Select/Active Clock Indicator.
Input: If manual clock selection mode is chosen
(AUTOSEL = L), this pin functions as the manual input
clock selector. This input is internally deglitched to
prevent inadvertent clock switching during changes in
the CS input state.
0 = Select CKIN1
1 = Select CKIN2
If configured as an input, this pin must be set high or
low.
Output: If automatic clock selection mode is chosen
(AUTOSEL = M or H), this pin indicates which of the
two input clocks is currently the active clock. If alarms
exist on both CKIN1 and CKIN2, indicating that the
digital hold state has been entered, CA will indicate
the last active clock that was used before entering the
hold state.
0 = CKIN1 active input clock
1 = CKIN2 active input clock
23
22
BWSEL1
BWSEL0
I
3-Level
Bandwidth Select.
Three level inputs that select the DSPLL closed loop
bandwidth. Detailed operations and timing characteristics for
these pins may be found in the Any-Frequency Precision
Clock Family Reference Manual.
These pins have both weak pull-ups and weak pull-downs
and default to M.
Some designs may require an external resistor voltage
divider when driven by an active device that will tri-state.
27
26
25
24
FRQSEL3
FRQSEL2
FRQSEL1
FRQSEL0
I
3-Level
Multiplier Select.
Three level inputs that select the input clock and clock
multiplication ratio, depending on the FRQTBL setting.
Consult the Any-Frequency Precision Clock Family
Reference Manual or DSPLLsim configuration software for
settings, both available for download at
www.silabs.com/timing (click on Documentation).
These pins have both weak pull-ups and weak pull-downs
and default to M.
Some designs may require an external resistor voltage
divider when driven by an active device that will tri-state.
29
28
CKOUT1–
CKOUT1+
O
Multi
Clock Output 1.
Differential output clock with a frequency selected from a
table of values. Output signal format is selected by SFOUT
pins. Output is differential for LVPECL, LVDS, and CML
compatible modes. For CMOS format, both output pins drive
identical single-ended clock outputs.
Rev. 1.0
31
Si5323
Table 12. Si5323 Pin Descriptions (Continued)
Pin #
33
30
Pin Name
I/O
Signal Level
Description
SFOUT0
SFOUT1
I
3-Level
Signal Format Select.
Three level inputs that select the output signal format
(common mode voltage and differential swing) for both
CKOUT1 and CKOUT2.
SFOUT[1:0]
Signal Format
Reserved
HH
HM
HL
LVDS
CML
MH
MM
ML
LH
LVPECL
Reserved
LVDS—Low Swing
CMOS
LM
LL
Disable
Reserved
These pins have both weak pull-ups and weak pull-downs
and default to M.
Some designs may require an external resistor voltage
divider when driven by an active device that will tri-state.
CMOS outputs do not support bypass mode. LVPECL
outputs are not available when V = 1.8 V.
DD
34
35
CKOUT2–
CKOUT2+
O
Multi
Clock Output 2.
Differential output clock with a frequency selected from a
table of values. Output signal format is selected by SFOUT
pins. Output is differential for LVPECL, LVDS, and CML
compatible modes. For CMOS format, both output pins drive
identical single-ended clock outputs.
36
NC
—
—
No Connect.
These pins must be left unconnected for normal operation.
GND
PAD
GND
GND
Supply
Ground Pad.
The ground pad must provide a low thermal and electrical
impedance to a ground plane.
32
Rev. 1.0
Si5323
5. Ordering Guide
Ordering Part Number
Package
ROHS6, Pb-Free
Temperature Range
Si5323-C-GM
36-Lead 6 x 6 mm QFN
Evaluation Board
Yes
–40 to 85 °C
Si5322/23-EVB
Note: Add an “R” at the end of the device to denote tape and reel option (i.e., Si5323-C-GMR).
Package Outline: 36-Pin QFN
Rev. 1.0
33
Si5323
6. Package Outline: 36-Pin QFN
Figure 7 illustrates the package details for the Si5323. Table 13 lists the values for the dimensions shown in the
illustration.
Figure 7. 36-Pin Quad Flat No-Lead (QFN)
Table 13. Package Dimensions
Symbol
Millimeters
Symbol
Millimeters
Min
0.80
0.00
0.18
Nom
0.85
Max
0.90
0.05
0.30
Min
0.50
—
Nom
0.60
—
Max
0.70
12º
A
A1
b
L
0.02
0.25
aaa
bbb
ccc
ddd
eee
—
—
0.10
0.10
0.08
0.10
0.05
D
6.00 BSC
4.10
—
—
D2
e
3.95
4.25
—
—
0.50 BSC
6.00 BSC
4.10
—
—
E
—
—
E2
3.95
4.25
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MO-220, variation VJJD.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
34
Rev. 1.0
Si5323
7. Recommended PCB Layout
Figure 8. PCB Land Pattern Diagram
Figure 9. Ground Pad Recommended Layout
Rev. 1.0
35
Si5323
Table 14. PCB Land Pattern Dimensions
Dimension
MIN
MAX
e
E
0.50 BSC.
5.42 REF.
5.42 REF.
D
E2
D2
GE
GD
X
4.00
4.00
4.53
4.53
—
4.20
4.20
—
—
0.28
Y
0.89 REF.
ZE
ZD
—
—
6.31
6.31
Notes (General):
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on IPC-SM-782 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material
Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
Notes (Solder Mask Design):
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the
solder mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Notes (Stencil Design):
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be
used to assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.
4. A 4 x 4 array of 0.80 mm square openings on 1.05 mm pitch should be used for the
center ground pad.
Notes (Card Assembly):
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for
Small Body Components.
36
Rev. 1.0
Si5323
8. Si5323 Device Top Mark
Mark Method:
Font Size:
Laser
0.80 mm
Right-Justified
Line 1 Marking:
Line 2 Marking:
Si5323
C-GM
Customer Part Number
See Ordering Guide for options
C = Product Revision
G = Temperature Range –40 to 85 °C (RoHS6)
M = QFN Package
Line 3 Marking:
YYWWRF
YY = Year
WW = Work Week
R = Die Revision
F = Internal code
Assigned by the Assembly House. Corresponds to the year
and work week of the mold date.
Line 4 Marking:
Pin 1 Identifier
XXXX
Circle = 0.75 mm Diameter
Lower-Left Justified
Internal Code
Rev. 1.0
37
Si5323
NOTES:
38
Rev. 1.0
Si5323
DOCUMENT CHANGE LIST
Revision 0.1 to Revision 0.2
Changed LVTTL to LVCMOS in Table 7, “Absolute
Maximum Ratings,” on page 12.
Added Figure 5, “Typical Phase Noise Plot,” on page
13.
Updated Figure 6, “Si5323 Typical Application
Circuit,” on page 14 to show external reference
interface.
Added RATE0 and expanded the RATE[1:0]
description in 4. "Pin Descriptions: Si5323”.
Updated 5. "Ordering Guide" on page 33.
Added 7. "Recommended PCB Layout”.
Revision 0.2 to Revision 0.3
Changed 1.8 V operating range to ±5%.
Updated Table 1 on page 4.
Updated Table 7 on page 12.
Added table under Figure 5 on page 13.
Updated 3. "Functional Description" on page 15.
Clarified 4. "Pin Descriptions: Si5323" on page 28
including pull-up/pull-down.
Updated SFOUT values.
Revision 0.3 to Rev 1.0
Updated feature list on page 1.
Updated all Electrical Specification tables.
Updated Typical phase noise performance plot and
table values.
Added Section 3.3. "Frequency Plan Tables" on
page 16.
Updated package outline drawing.
Added ground pad layout drawing.
Added Top Device Mark section.
Updated Section 5. "Ordering Guide” table
Added product selection guide
Rev. 1.0
39
ClockBuilder Pro
One-click access to Timing tools,
documentation, software, source
code libraries & more. Available for
Windows and iOS (CBGo only).
www.silabs.com/CBPro
Timing Portfolio
www.silabs.com/timing
SW/HW
www.silabs.com/CBPro
Quality
www.silabs.com/quality
Support and Community
community.silabs.com
Disclaimer
Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers
using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific
device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories
reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy
or completeness of the included information. Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply
or express copyright licenses granted hereunder to design or fabricate any integrated circuits. The products must not be used within any Life Support System without the specific
written consent of Silicon Laboratories. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected
to result in significant personal injury or death. Silicon Laboratories products are generally not intended for military applications. Silicon Laboratories products shall under no
circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons.
Trademark Information
Silicon Laboratories Inc., Silicon Laboratories, Silicon Labs, SiLabs and the Silicon Labs logo, CMEMS®, EFM, EFM32, EFR, Energy Micro, Energy Micro logo and combinations
thereof, "the world’s most energy friendly microcontrollers", Ember®, EZLink®, EZMac®, EZRadio®, EZRadioPRO®, DSPLL®, ISOmodem ®, Precision32®, ProSLIC®, SiPHY®,
USBXpress® and others are trademarks or registered trademarks of Silicon Laboratories Inc. ARM, CORTEX, Cortex-M3 and THUMB are trademarks or registered trademarks of
ARM Holdings. Keil is a registered trademark of ARM Limited. All other products or brand names mentioned herein are trademarks of their respective holders.
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
USA
http://www.silabs.com
相关型号：
©2020 ICPDF网 联系我们和版权申明