SI5368B-B-GQR [SILICON]
暂无描述;
SILICON 
Si5368
PRELIMINARY DATA SHEET
ANY-RATE PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR
Description
Features
The Si5368 is a jitter-attenuating precision clock multiplier for
applications requiring sub 1 ps rms jitter performance. The
Si5368 accepts four clock inputs ranging from 2 kHz to
710 MHz and generates five independent, synchronous clock
outputs ranging from 2 kHz to 945 MHz and select
frequencies to 1.4 GHz. The device provides virtually any
frequency translation combination across this operating
range. The outputs are divided down separately from a
common source. The Si5368 input clock frequency and clock
multiplication ratio are programmable through an I2C or SPI
interface. The Si5368 is based on Silicon Laboratories' 3rd-
generation DSPLL® technology, which provides any-rate
frequency synthesis and jitter attenuation in a highly
integrated PLL solution that eliminates the need for external
VCXO and loop filter components. The DSPLL loop
bandwidth is digitally programmable, providing jitter
performance optimization at the application level. Operating
from a single 1.8 or 2.5 V supply, the Si5368 is ideal for
providing clock multiplication and jitter attenuation in high
performance timing applications.
ꢀ Generates any frequency from 2 kHz to 945 MHz
and select frequencies to 1.4 GHz from an input
frequency of 2 kHz to 710 MHz
ꢀ Ultra-low jitter clock outputs w/jitter generation as
low as 0.3 ps rms (50 kHz–80 MHz)
ꢀ Integrated loop filter with selectable loop bandwidth
(60 Hz to 8.4 kHz)
ꢀ Meets OC-192 GR-253-CORE jitter specifications
ꢀ Four clock inputs w/manual or automatically
controlled hitless switching
ꢀ Five clock outputs with selectable signal format
(LVPECL, LVDS, CML, CMOS)
ꢀ SONET frame sync switching and regeneration
ꢀ Support for ITU G.709 and custom FEC ratios
(255/238, 255/237, 255/236)
ꢀ LOL, LOS, FOS alarm outputs
ꢀ Digitally-controlled output phase adjust
Applications
2
ꢀ I C or SPI programmable settings
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
SONET/SDH OC-48/OC-192 line cards
GbE/10GbE, 1/2/4/8/10GFC line cards
ITU G.709 and custom FEC line cards
Wireless basestations
Data converter clocking
xDSL
ꢀ On-chip voltage regulator for 1.8 or 2.5 V ±10%
operation
ꢀ Small size: 14 x 14 mm 100-pin TQFP
ꢀ Pb-free, RoHS compliant
SONET/SDH + PDH clock synthesis
Test and measurement
Xtal or Refclock
CKIN1
CKIN2
÷ N31
÷ N32
÷ N33
÷ N34
÷ NC1
÷ NC2
CKOUT1
CKOUT2
®
DSPLL
CKIN3
CKIN4
÷ N2
÷ NC3
÷ NC4
÷ NFS
CKOUT3
I2C/SPI Port
Rate Select
CKOUT4
Clock Select
Latency Control
FSYNC Realignment
Device Interrupt
LOL/LOS/FOS Alarms
Control
Output Clock 2
CKOUT5/FS_OUT
VDD (1.8 or 2.5 V)
GND
Input Clock 3
Input Clock 4
Preliminary Rev. 0.3 3/07
Copyright © 2007 by Silicon Laboratories
Si5368
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si5368
Table 1. Performance Specifications
(VDD = 1.8 or 2.5 V ±10%, TA = –40 to 85 ºC)
Parameter
Temperature Range
Supply Voltage
Symbol
Test Condition
Min
–40
2.25
1.62
—
Typ
25
Max
85
Unit
ºC
V
T
A
V
2.5
1.8
394
2.75
1.98
435
DD
V
Supply Current
I
f
= 622.08 MHz
mA
DD
OUT
All CKOUTs enabled LVPECL
format output
Only CKOUT1 enabled
—
—
253
278
284
321
mA
mA
f
= 19.44 MHz
OUT
All CKOUTs enabled
CMOS format output
Only CKOUT1 enabled
Tristate/Sleep Mode
—
—
229
TBD
—
261
TBD
710
mA
mA
Input Clock Frequency
(CKIN1, CKIN2, CKIN3,
CKIN4)
CK
CK
CK
Input frequency and clock mul-
tiplication ratio determined by
programming device PLL divid-
ers. Consult Silicon Laborato-
ries configuration software
DSPLLsim or Any-Rate Preci-
sion Clock Family Reference
Manual at www.silabs.com/tim-
ing to determine PLL divider
settings for a given input fre-
quency/clock multiplication
ratio combination.
0.002
MHz
F
F
Input Clock Frequency
(CKIN3, CKIN4 used as
FSYNC inputs)
0.002
—
0.512
MHz
MHz
Output Clock Frequency
(CKOUT1, CKOUT2,
CKOUT3, CKOUT4, CKOUT5
used as fifth high-speed out-
put)
0.002
970
1213
—
—
—
945
1134
1417
OF
CKOUT5 used as frame sync
output (FS_OUT)
CK
0.002
—
710
MHz
OF
Input Clocks (CKIN1, CKIN2, CKIN3, CKIN4)
Differential Voltage Swing
Common Mode Voltage
CKN
CKN
0.25
0.9
1.0
—
—
—
—
—
—
—
1.9
1.4
1.7
11
V
PP
DPP
VCM
1.8 V ±10%
2.5 V ±10%
V
V
Rise/Fall Time
Duty Cycle
CKN
20–80%
ns
%
ns
TRF
CKN
Whichever is less
40
60
—
DC
50
Note: For a more comprehensive listing of device specifications, please consult the Silicon Laboratories Any-Rate Precision
Clock Family Reference Manual. This document can be downloaded from www.silabs.com/timing.
2
Preliminary Rev. 0.3
Si5368
Table 1. Performance Specifications (Continued)
(VDD = 1.8 or 2.5 V ±10%, TA = –40 to 85 ºC)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Output Clocks (CKOUT1, CKOUT2, CKOUT3, CKOUT4, CKOUT5/FS_OUT)
Common Mode
V
J
LVPECL
100 Ω load
line-to-line
V
– 1.42
—
—
—
V – 1.25
DD
V
OCM
DD
Differential Output Swing
Single Ended Output Swing
PLL Performance
V
1.1
1.9
V
DD
OD
V
0.5
0.93
Vpp
SE
Jitter Generation
f
= 622.08 MHz,
OUT
—
0.3
TBD
ps rms
GEN
LVPECL output format
50 kHz–80 MHz
12 kHz–20 MHz
—
—
—
0.3
TBD
0.1
ps rms
dB
Jitter Transfer
J
0.05
TBD
PK
External Reference Jitter
Transfer
J
TBD
dB
PKEXTN
Phase Noise
CKO
f
= 622.08 MHz
OUT
—
TBD
TBD
dBc/Hz
PN
100 Hz offset
1 kHz offset
—
—
—
—
—
—
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc
10 kHz offset
100 kHz offset
1 MHz offset
Subharmonic Noise
Spurious Noise
SP
SP
Phase Noise @ 100 kHz Offset
SUBH
SPUR
Max spur @ n x F3
dBc
(n > 1, n x F3 < 100 MHz)
Package
Thermal Resistance Junction
to Ambient
θ
Still Air
—
40
—
ºC/W
JA
Note: For a more comprehensive listing of device specifications, please consult the Silicon Laboratories Any-Rate Precision
Clock Family Reference Manual. This document can be downloaded from www.silabs.com/timing.
Preliminary Rev. 0.3
3
Si5368
155.52 MHz in, 622.08 MHz out
0
-20
-40
-60
-80
-100
-120
-140
-160
100
1000
10000
100000
1000000
10000000
100000000
Offset Frequency (Hz)
Figure 1. Typical Phase Noise Plot
Table 2. Absolute Maximum Ratings
Parameter
DC Supply Voltage
Symbol
Value
–0.5 to 2.75
Unit
V
V
DD
DIG
JCT
STG
LVCMOS Input Voltage
V
–0.3 to (V + 0.3)
V
DD
Junction Temperature
T
–55 to 150
–55 to 150
2
ºC
ºC
kV
V
Storage Temperature Range
ESD HBM Tolerance (100 pF, 1.5 kΩ)
ESD MM Tolerance
T
200
Latch-Up Tolerance
JESD78 Compliant
Note: Permanent device damage may occur if the Absolute Maximum Ratings are exceeded. Functional operation should be
restricted to the conditions as specified in the operation sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods of time may affect device reliability.
4
Preliminary Rev. 0.3
Si5368
2
Figure 2. Si5368 Typical Application Circuit (I C Control Mode)
Figure 3. Si5368 Typical Application Circuit (SPI Control Mode)
Preliminary Rev. 0.3
5
Si5368
the device to continue generation of a stable output
clock when the selected input reference is lost. During
digital hold, the DSPLL generates an output frequency
based on a historical average that existed a fixed
amount of time before the error event occurred,
eliminating the effects of phase and frequency transients
that may occur immediately preceding digital hold.
1. Functional Description
The Si5368 is a jitter-attenuating precision clock
multiplier for applications requiring sub 1 ps rms jitter
performance. The Si5368 accepts four clock inputs
ranging from 2 kHz to 710 MHz and generates five
independent, synchronous clock outputs ranging from
2 kHz to 945 MHz and select frequencies to 1.4 GHz.
The device provides virtually any frequency translation
combination across this operating range. Independent
dividers are available for every input clock and output
clock, so the Si5368 can accept input clocks at different
frequencies and it can generate output clocks at
different frequencies. The Si5368 input clock frequency
Fine phase adjustment is available and is set using the
FLAT register bits. The nominal range and resolution of
the FLAT[14:0] latency adjustment word are: ±110 ps
and 3.05 ps, respectively.
The Si5368 has five differential clock outputs. The
electrical format of the clock outputs is programmable to
support LVPECL, LVDS, CML, or CMOS loads. If not
required, unused clock outputs can be powered down to
minimize power consumption. The phase difference
between the selected input clock and the output clocks
is adjustable in 200 ps increments for system skew
control. In addition, the phase of one output clock may
be adjusted in relation to the phase of the other output
clock. The resolution varies from 800 ps to 2.2 ns
depending on the PLL divider settings. Consult the
DSPLLsim configuration software to determine the
phase offset resolution for a given input clock/clock
multiplication ratio combination. For system-level
debugging, a bypass mode is available which drives the
output clock directly from the input clock, bypassing the
internal DSPLL. The device is powered by a single 1.8
or 2.5 V supply.
and clock multiplication ratio are programmable through
2
an I C or SPI interface.
Optionally, the fifth clock
to 512 kHz
output can be configured as
a 2
SONET/SDH frame synchronization output that is
phase aligned with one of the high-speed output clocks.
Silicon Laboratories offers a PC-based software utility,
DSPLLsim, that can be used to determine the optimum
PLL divider settings for a given input frequency/clock
multiplication ratio combination that minimizes phase
noise and power consumption. This utility can be
downloaded from www.silabs.com/timing.
The Si5368 is based on Silicon Laboratories' 3rd-
®
generation DSPLL technology, which provides any-
rate frequency synthesis and jitter attenuation in a
highly integrated PLL solution that eliminates the need
for external VCXO and loop filter components. The
Si5368 PLL loop bandwidth is digitally programmable
and supports a range from 60 Hz to 8.4 kHz. The
DSPLLsim software utility can be used to calculate valid
loop bandwidth settings for a given input clock
frequency/clock multiplication ratio.
1.1. External Reference
An external, 38.88 MHz clock or
a
low-cost
114.285 MHz 3rd overtone crystal is used as part of a
fixed-frequency oscillator within the DSPLL. This
external reference is required for the device to perform
The Si5368 supports hitless switching between input jitter attenuation. Silicon Laboratories recommends
clocks in compliance with GR-253-CORE and GR-1244- using a high-quality crystal from TXC (www.txc.com.tw),
CORE that greatly minimizes the propagation of phase part number 7MA1400014. An external 38.88 MHz
transients to the clock outputs during an input clock clock from a high quality OCXO or TCXO can also be
transition (<200 ps typ). Manual, automatic revertive used as a reference for the device.
and non-revertive input clock switching options are
In digital hold, the DSPLL remains locked to this
available. The Si5368 monitors the four input clocks for
external reference. Any changes in the frequency of this
loss-of-signal and provides a LOS alarm when it detects
reference when the DSPLL is in digital hold, will be
missing pulses on any of the four input clocks. The
tracked by the output of the device. Note that crystals
device monitors the lock status of the PLL. The lock
can have temperature sensitivities.
detect algorithm works by continuously monitoring the
1.2. Further Documentation
phase of the input clock in relation to the phase of the
feedback clock. The Si5368 monitors the frequency of
CKIN1, CKIN3, and CKIN4 with respect to a reference
frequency applied to CKIN2, and generates a frequency
offset alarm (FOS) if the threshold is exceeded. This
FOS feature is available for SONET applications in
which both the monitored frequency on CKIN1, CKIN3,
and CKIN4 and the reference frequency are integer
multiples of 19.44 MHz. Both Stratum 3/3E and SONET
Minimum Clock (SMC) FOS thresholds are supported.
Consult the Silicon Laboratories Any-Rate Precision
Clock Family Reference Manual (FRM) for more
detailed information about the Si5368. The FRM can be
downloaded from www.silabs.com/timing.
Silicon Laboratories has developed
a PC-based
software utility called DSPLLsim to simplify device
configuration, including frequency planning and loop
bandwidth selection. This utility can be downloaded
from www.silabs.com/timing.
The Si5368 provides a digital hold capability that allows
6
Preliminary Rev. 0.3
Si5368
2. Pin Descriptions: Si5368
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
75
NC
NC
NC
NC
74
73
2
NC
3
RST
NC
NC
72
71
4
SDI
VDD
5
70
69
A2_SS
6
VDD
A1
A0
NC
GND
GND
7
68
67
8
9
C1B
66
65
NC
10
11
12
13
14
15
C2B
C3B
GND
GND
64
63
INT_ALM
CS0_C3A
GND
VDD
Si5368
62
61
VDD
SDA_SDO
VDD
XA
60
59
SCL
C2A
C1A
16
17
XB
58
57
18
19
20
21
GND
GND
GND PAD
CS1_C4A
NC
56
55
NC
INC
FS_ALIGN
NC
DEC
NC
22
23
54
53
NC
NC
NC
52
51
24
25
NC
NC
47
49 50
48
41
42 43 44 45 46
40
36
39
37 38
26 27 28 29 30 31 32 33 34 35
Table 3. Si5368 Pin Descriptions
Pin #
Pin Name
I/O Signal Level
Description
1, 2, 4, 20,
22, 23, 24,
25, 37, 47,
48, 50, 51,
52, 53, 56,
66, 67, 72,
73, 74, 75,
80, 85, 95
NC
No Connect.
These pins must be left unconnected for normal operation.
3
RST
I
LVCMOS External Reset.
Active low input that performs external hardware reset of
device. Resets all internal logic to a known state and forces the
device registers to their default value. Clock outputs are
tristated during reset. After rising edge of RST signal, the device
will perform an internal self-calibration.
This pin has a weak pull-up.
Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5368 Register Map.
Preliminary Rev. 0.3
7
Si5368
Table 3. Si5368 Pin Descriptions (Continued)
Pin #
Pin Name
I/O Signal Level
Description
5, 6, 15, 27,
62, 63, 76,
79, 81, 84,
86, 89, 91,
94, 96, 99,
100
V
Vdd
Supply
V
.
DD
DD
The device operates from a 1.8 or 2.5 V supply. Bypass capaci-
tors should be associated with the following V pins:
Pins
5, 6
15
DD
Bypass Cap
0.1 µF
0.1 µF
0.1 µF
0.1 µF
1.0 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
27
62, 63
76, 79
81, 84
86, 89
91, 94
96, 99, 100
7, 8, 14, 18,
19, 26, 28,
31, 33, 36,
38, 41, 43,
46, 64, 65
GND
C1B
GND
Supply
Ground.
This pin must be connected to system ground. Minimize the
ground path impedance for optimal performance.
9
O
LVCMOS CKIN1 Invalid Indicator.
This pin performs the CK1_BAD function if CK1_BAD_PIN = 1
and is tristated if CK1_BAD_PIN = 0. Active polarity is con-
trolled by CK_BAD_POL.
0 = No alarm on CKIN1.
1 = Alarm on CKIN1.
10
11
12
C2B
C3B
O
O
O
LVCMOS CKIN2 Invalid Indicator.
This pin performs the CK2_BAD function if CK2_BAD_PIN = 1
and is tristated if CK2_BAD_PIN = 0. Active polarity is con-
trolled by CK_BAD_POL.
0 = No alarm on CKIN2.
1 = Alarm on CKIN2.
LVCMOS CKIN3 Invalid Indicator.
This pin performs the CK3_BAD function if CK3_BAD_PIN = 1
and is tristated if CK3_BAD_PIN = 0. Active polarity is con-
trolled by CK_BAD_POL.
0 = No alarm on CKIN3.
1 = Alarm on CKIN3.
INT_ALM
LVCMOS Interrupt/Alarm Output Indicator.
This pin functions as a maskable interrupt output with active
polarity controlled by the INT_POL register bit. The INT output
function can be turned off by setting INT_PIN = 0. If the ALR-
MOUT function is desired instead on this pin, set
ALRMOUT_PIN = 1 and INT_PIN = 0.
0 = ALRMOUT not active.
1 = ALRMOUT active.
The active polarity is controlled by CK_BAD_POL. If no function
is selected, the pin tristates.
Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5368 Register Map.
8
Preliminary Rev. 0.3
Si5368
Table 3. Si5368 Pin Descriptions (Continued)
Pin #
Pin Name
I/O Signal Level
Description
13
57
CS0_C3A
CS1_C4A
I/O
LVCMOS Input Clock Select/CKIN3 or CKIN4 Active Clock Indicator.
If manual clock selection is chosen, and if CKSEL_PIN = 1, the
CKSEL pins control clock selection and the CKSEL_REG bits
are ignored.
CS[1:0]
00
Active Input Clock
CKIN1
01
CKIN2
10
CKIN3
11
CKIN4
If CKSEL_PIN = 0, the CKSEL_REG register bits control this
function and these inputs tristate. If these pins are not function-
ing as the CS[1:0] inputs and auto clock selection is enabled,
then they serve as the CKIN_n active clock indicator.
0 = CKIN3 (CKIN4) is not the active input clock
1 = CKIN3 (CKIN4) is currently the active input to the PLL
The CKn_ACTV_REG bit always reflects the active clock status
for CKIN_n. If CKn_ACTV_PIN = 1, this status will also be
reflected on the CnA pin with active polarity controlled by the
CK_ACTV_POL bit. If CKn_ACTV_PIN = 0, this output tristates.
This pin has a weak pull-down.
16
17
XA
XB
I
I
ANALOG External Crystal or Reference Clock.
External crystal should be connected to these pins to use exter-
nal oscillator based reference. If a single-ended external refer-
ence is used, ac couple reference clock to XA input and leave
XB pin floating. External reference must be from a high-quality
clock source (TCXO, OCXO). Frequency of crystal or external
clock is set by the RATE pins.
21
FS_ALIGN
LVCMOS FSYNC Alignment Control.
If FSYNC_ALIGN_PIN = 1 and CK_CONFIG = 1, a logic high
on this pin causes the FS_OUT phase to be realigned to the ris-
ing edge of the currently active input sync (CKIN_3 or CKIN_4).
If FSYNC_ALIGN_PIN = 0, this pin is ignored and the
FSYNC_ALIGN_REG bit performs this function.
0 = No realignment.
1 = Realign.
This pin has a weak pull-down.
29
30
CKIN4+
CKIN4–
I
MULTI
Clock Input 4.
Differential clock input. This input can also be driven with a sin-
gle-ended signal. CKIN4 serves as the frame sync input associ-
ated with the CKIN2 clock when CK_CONFIG_REG = 1.
Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5368 Register Map.
Preliminary Rev. 0.3
9
Si5368
Table 3. Si5368 Pin Descriptions (Continued)
Pin #
Pin Name
I/O Signal Level
Description
32
42
RATE1
RATE0
I
3-Level
External Crystal or Reference Clock Rate.
Three level inputs that select the type and rate of external crys-
tal or reference clock to be applied to the XA/XB port.
Settings:
HH = No Crystal or Reference Clock. Converts part to a Si5367
device. See Si5367 Data Sheet for operation.
(Wideband).
MM = 114.285 MHz 3rd OT crystal (Narrowband).
LM = 38.88 MHz external clock (Narrowband).
All others = Reserved.
34
35
CKIN2+
CKIN2–
I
I
MULTI
MULTI
Clock Input 2.
Differential input clock. This input can also be driven with a sin-
gle-ended signal.
39
40
CKIN3+
CKIN3–
Clock Input 3.
Differential clock input. This input can also be driven with a sin-
gle-ended signal. CKIN3 serves as the frame sync input associ-
ated with the CKIN1 clock when CK_CONFIG_REG = 1.
44
45
CKIN1+
CKIN1–
I
MULTI
Clock Input 1.
Differential clock input. This input can also be driven with a sin-
gle-ended signal.
49
LOL
O
LVCMOS PLL Loss of Lock Indicator.
This pin functions as the active high PLL loss of lock indicator if
the LOL_PIN register bit is set to one.
0 = PLL locked.
1 = PLL unlocked.
If LOL_PIN = 0, this pin will tristate.
Active polarity is controlled by the LOL_POL bit. The PLL lock
status will always be reflected in the LOL_INT read only register
bit.
54
DEC
I
LVCMOS Coarse Latency Decrement.
A pulse on this pin decreases the input to output device latency
by 1/fOSC (approximately 200 ps). Detailed operations and tim-
ing characteristics for this pin may be found in the Any-Rate
Precision Clock Family Reference Manual. There is no limit on
the range of latency adjustment by this method. Pin control is
enabled by setting INCDEC_PIN = 1 (default).
If INCDEC_PIN = 0, this pin is ignored and coarse output
latency is controlled via the CLAT register.
If both INC and DEC are tied high, phase buildout is disabled
and the device maintains a fixed-phase relationship between
the selected input clock and the output clock during an input
clock switch. Detailed operations and timing characteristics for
these pins may be found in the Any-Rate Precision Clock Fam-
ily Reference Manual.
This pin has a weak pull-down.
Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5368 Register Map.
10
Preliminary Rev. 0.3
Si5368
Table 3. Si5368 Pin Descriptions (Continued)
Pin #
Pin Name
I/O Signal Level
Description
55
INC
I
LVCMOS Coarse Latency Increment.
A pulse on this pin increases the input to output device latency
by 1/fOSC (approximately 200 ps). Detailed operations and tim-
ing characteristics for this pin may be found in the Any-Rate
Precision Clock Family Reference Manual. There is no limit on
the range of latency adjustment by this method. Pin control is
enabled by setting INCDEC_PIN = 1 (default).
If INCDEC_PIN = 0, this pin is ignored and coarse output
latency is controlled via the CLAT register.
If both INC and DEC are tied high, phase buildout is disabled
and the device maintains a fixed-phase relationship between
the selected input clock and the output clock during an input
clock switch. Detailed operations and timing characteristics for
these pins may be found in the Any-Rate Precision Clock Fam-
ily Reference Manual.
This pin has a weak pull-down.
58
59
C1A
C2A
O
O
LVCMOS CKIN1 Active Clock Indicator.
This pin serves as the CKIN1 active clock indicator. The
CK1_ACTV_REG bit always reflects the active clock status for
CKIN1. If CK1_ACTV_PIN = 1, this status will also be reflected
on the C1A pin with active polarity controlled by the
CK_ACTV_POL bit. If CK1_ACTV_PIN = 0, this output tristates.
LVCMOS CKIN2 Active Clock Indicator.
This pin serves as the CKIN2 active clock indicator. The
CK2_ACTV_REG bit always reflects the active clock status for
CKIN_2. If CK2_ACTV_PIN = 1, this status will also be reflected
on the C2A pin with active polarity controlled by the
CK_ACTV_POL bit. If CK2_ACTV_PIN = 0, this output tristates.
60
61
SCL
I
LVCMOS Serial Clock.
This pin functions as the serial port clock input for both SPI and
2
I C modes.
This pin has a weak pull-down.
SDA_SDO
I/O
LVCMOS Serial Data.
2
In I C microprocessor control mode (CMODE = 0), this pin func-
tions as the bidirectional serial data port.In SPI microprocessor
control mode (CMODE = 1), this pin functions as the serial data
output.
68
69
A0
A1
I
I
LVCMOS Serial Port Address.
2
In I C microprocessor control mode (CMODE = 0), these pins
function as hardware controlled address bits. In SPI micropro-
cessor control mode (CMODE = 1), these pins are ignored.
This pin has a weak pull-down.
70
A2_SS
LVCMOS Serial Port Address/Slave Select.
2
In I C microprocessor control mode (CMODE = 0), this pin func-
tions as a hardware controlled address bit.
In SPI microprocessor control mode (CMODE = 1), this pin
functions as the slave select input.
This pin has a weak pull-down.
Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5368 Register Map.
Preliminary Rev. 0.3
11
Si5368
Table 3. Si5368 Pin Descriptions (Continued)
Pin #
Pin Name
I/O Signal Level
Description
71
SDI
I
LVCMOS Serial Data In.
In SPI microprocessor control mode (CMODE = 1), this pin
functions as the serial data input.
2
In I C microprocessor control mode (CMODE = 0), this pin is
ignored.
This pin has a weak pull-down.
77
78
CKOUT3+
CKOUT3–
O
O
O
MULTI
MULTI
MULTI
Clock Output 3.
Differential clock output. Output signal format is selected by
SFOUT3_REG register bits. Output is differential for LVPECL,
LVDS, and CML compatible modes. For CMOS format, both
output pins drive identical single-ended clock outputs.
82
83
CKOUT1–
CKOUT1+
Clock Output 1.
Differential clock output. Output signal format is selected by
SFOUT1_REG register bits. Output is differential for LVPECL,
LVDS, and CML compatible modes. For CMOS format, both
output pins drive identical single-ended clock outputs.
87
88
FS_OUT–
FS_OUT+
Frame Sync Output.
Differential frame sync output or fifth high-speed clock output.
Output signal format is selected by SFOUT_FSYNC_REG reg-
ister bits. Output is differential for LVPECL, LVDS, and CML
compatible modes. For CMOS format, both output pins drive
identical single-ended clock outputs. Duty cycle and active
polarity are controlled by FSYNC_PW and FSYNC_POL bits,
respectively. Detailed operations and timing characteristics for
these pins may be found in the Any-Rate Precision Clock Fam-
ily Reference Manual.
90
CMODE
I
LVCMOS Control Mode.
2
Selects I C or SPI control mode for the device.
2
0 = I C Control Mode.
1 = SPI Control Mode.
92
93
CKOUT2+
CKOUT2–
O
MULTI
MULTI
Supply
Clock Output 2.
Differential clock output. Output signal format is selected by
SFOUT2_REG register bits. Output is differential for LVPECL,
LVDS, and CML compatible modes. For CMOS format, both
output pins drive identical single-ended clock outputs.
97
98
CKOUT4–
CKOUT4+
O
Clock Output 4.
Differential clock output. Output signal format is selected by
SFOUT4_REG register bits. Output is differential for LVPECL,
LVDS, and CML compatible modes. For CMOS format, both
output pins drive identical single-ended clock outputs.
GND PAD
GND PAD
GND
Ground Pad.
The ground pad must provide a low thermal and electrical
impedance to a ground plane.
Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5368 Register Map.
12
Preliminary Rev. 0.3
Si5368
3. Ordering Guide
Ordering Part
Number
Output Clock
Frequency Range
Package
Temperature Range
Si5368A-B-GQ
2 kHz–945 MHz
970–1134 MHz
1.213–1.417 GHz
100-Pin 14 x 14 mm TQFP
–40 to 85 °C
Si5368B-B-GQ
Si5368C-B-GQ
2 kHz–808 MHz
2 kHz–346 MHz
100-Pin 14 x 14 mm TQFP
100-Pin 14 x 14 mm TQFP
–40 to 85 °C
–40 to 85 °C
Preliminary Rev. 0.3
13
Si5368
4. Package Outline: 100-Pin TQFP
Figure 4 illustrates the package details for the Si5368. Table 4 lists the values for the dimensions shown in the
illustration.
Figure 4. 100-Pin Thin Quad Flat Package (TQFP)
Table 4. 100-Pin Package Diagram Dimensions
Dimension
Min
—
Nom
—
Max
1.20
0.15
1.05
0.27
0.20
Dimension
Min
Nom
Max
A
E
E1
E2
L
16.00 BSC.
A1
0.05
0.95
0.17
0.09
—
14.00 BSC.
A2
1.00
3.85
0.45
—
4.00
0.60
—
4.15
0.75
0.20
0.20
0.08
0.08
7º
b
0.22
c
D
—
aaa
bbb
ccc
ddd
θ
16.00 BSC.
14.00 BSC.
4.00
—
—
D1
—
—
D2
3.85
4.15
—
—
e
0.50 BSC.
0º
3.5º
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This package outline conforms to JEDEC MS-026, variant AED-HD.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body
Components.
14
Preliminary Rev. 0.3
Si5368
5. Recommended PCB Layout
Figure 5. PCB Land Pattern Diagram
Preliminary Rev. 0.3
15
Si5368
Table 5. PCB Land Pattern Dimensions
Dimension
MIN
MAX
e
E
0.50 BSC.
15.40 REF.
15.40 REF.
3.90
D
E2
D2
GE
GD
X
4.10
4.10
—
3.90
13.90
13.90
—
—
0.30
Y
1.50 REF.
—
ZE
ZD
R1
R2
16.90
16.90
—
0.15 REF
—
1.00
Notes (General):
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on IPC-7351 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition
(LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
Notes (Solder Mask Design):
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder
mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Notes (Stencil Design):
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be
used to assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.
4. A 4 x 4 array of 0.80 mm square openings on 1.05 mm pitch should be used for the center
ground pad.
Notes (Card Assembly):
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for
Small Body Components.
16
Preliminary Rev. 0.3
Si5368
DOCUMENT CHANGE LIST
Revision 0.1 to Revision 0.2
ꢀ Changed LVTTL to LVCMOS in Table 2, “Absolute
Maximum Ratings,” on page 4.
ꢀ Updated Figure 2 and Figure 3 on page 5.
ꢀ Updated “2. Pin Descriptions: Si5368”.
ꢁ Added RATE0 to pin description. By changing
RATE[1:0] the part can emulate a Si5367.
ꢁ Changed XA/XB pin description to support both
differential and single ended external REFCLK.
Revision 0.2 to Revision 0.3
ꢀ Added Figure 1, “Typical Phase Noise Plot,” on page
4.
ꢀ Updated Figure 2, “Si5368 Typical Application
2
Circuit (I C Control Mode),” and Figure 3, “Si5368
Typical Application Circuit (SPI Control Mode),” on
page 5 to show INC and DEC.
ꢀ Updated “2. Pin Descriptions: Si5368”.
ꢁ Changed font of register names to underlined italics.
ꢀ Updated "3. Ordering Guide" on page 13.
ꢀ Added “5. Recommended PCB Layout”.
Preliminary Rev. 0.3
17
Si5368
CONTACT INFORMATION
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Email: Clockinfo@silabs.com
Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep-
resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-
quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per-
sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap-
plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
Silicon Laboratories, Silicon Labs, and DSPLL are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
18
Preliminary Rev. 0.3
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