SI5369B-C-GQ [SILICON]
Processor Specific Clock Generator, 808MHz, CMOS, PQFP100, TQFP-100;
| 型号： | SI5369B-C-GQ |
| 厂家： | 
SILICON |
| 描述： | Processor Specific Clock Generator, 808MHz, CMOS, PQFP100, TQFP-100 时钟 外围集成电路 晶体 |
| 文件： | 总84页 (文件大小：1447K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si5369
ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER
ATTENUATOR
Features
Generates any frequency from 2 kHz Five clock outputs with selectable
to 945 MHz and select frequencies to
1.4 GHz from an input frequency of
2 kHz to 710 MHz
Ultra-low jitter clock outputs with jitter
generation as low as 300 fs rms
(12 kHz–20 MHz)
Integrated loop filter with selectable
loop bandwidth (4 Hz to 525 Hz)
Meets OC-192 GR-253-CORE jitter
specifications
Four clock inputs with manual or
automatically controlled hitless
switching and phase build-out
Supports holdover and freerun
modes of operation
signal format (LVPECL, LVDS, CML,
CMOS)
Support for ITU G.709 and custom
FEC ratios (253/226, 239/237,
255/238, 255/237, 255/236)
LOL, LOS, FOS alarm outputs
Digitally-controlled output phase
adjust
I2C or SPI programmable settings
On-chip voltage regulator for 1.8 V
±5%, 2.5 V ±10%, or 3.3 V ±10%
operation
Ordering Information:
See page 78.
Small size: 14 x 14 mm 100-pin
TQFP
Pb-free, RoHS compliant
SONET frame sync switching and
regeneration
Applications
SONET/SDH OC-48/STM-16/OC-
192/STM-64 line cards
OTN/WDM Muxponder, MSPP,
ROADM line cards
GbE/10GbE, 1/2/4/8/10G FC line cards SONET/SDH + PDH clock
synthesis
ITU G.709 and custom FEC line cards
Wireless repeaters/wireless backhaul
Data converter clocking
Test and measurement
Synchronous Ethernet
Broadcast video
Description
The Si5369 is a jitter-attenuating precision clock multiplier for applications
requiring sub 1 ps rms jitter performance. The Si5369 accepts four clock inputs
ranging from 2 kHz to 710 MHz and generates five clock outputs ranging from
2 kHz to 945 MHz and select frequencies to 1.4 GHz. The device provides
virtually any frequency translation combination across this operating range. The
outputs are divided down separately from a common source. The Si5369 input
clock frequency and clock multiplication ratio are programmable through an I2C or
SPI interface. The Si5369 is based on Silicon Laboratories' third-generation
DSPLL® technology, which provides any-frequency synthesis and jitter
attenuation in a highly integrated PLL solution that eliminates the need for
external VCXO and loop filter components. The DSPLL loop bandwidth is digitally
programmable, providing jitter performance optimization at the application level.
Operating from a single 1.8, 2.5 ,or 3.3 V supply, the Si5369 is ideal for providing
clock multiplication and jitter attenuation in high performance timing applications.
Rev. 1.0 1/13
Copyright © 2013 by Silicon Laboratories
Si5369
Si5369
Functional Block Diagram
Xtal or Refclock
CKIN1
CKIN2
÷ N31
÷ N32
÷ N33
÷ N34
÷ NC1_LS
÷ NC2_LS
÷ NC3_LS
CKOUT1
CKOUT2
®
÷ N1_HS
DSPLL
CKIN3/FSYNC1
CKIN4
÷ N2
CKOUT3
CKOUT4
CKOUT5
I2C/SPI Port
Rate Select
÷ NC4_LS
÷ NC5_LS
Clock Select
Control
Skew Control
Device Interrupt
LOL/LOS/FOS Alarms
VDD (1.8, 2.5, or 3.3 V)
GND
2
Rev. 1.0
Si5369
TABLE OF CONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical Phase Noise Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
3.1. External Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
3.2. Further Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
5. Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
6. Pin Descriptions: Si5369 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
8. Package Outline: 100-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
9. Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
10. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Rev. 1.0
3
Si5369
1. Electrical Specifications
Table 1. Recommended Operating Conditions1
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Ambient Temperature
T
-40
25
85
C
V
A
2
Supply Voltage during
Normal Operation
V
3.3 V Nominal
2.97
3.3
3.63
DD
2.5 V Nominal
1.8 V Nominal
2.25
1.71
2.5
1.8
2.75
1.89
V
V
Notes:
1. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 ºC unless otherwise stated.
2. The LVPECL and CMOS output formats draw more current than either LVDS or CML; however, there are restrictions in
the allowed output format pin settings so that the maximum power dissipation for the TQFP devices is limited when
they are operated at 3.3 V. When there are four enabled LVPECL or CMOS outputs, the fifth output must be disabled.
When there are five enabled outputs, there can be no more than three outputs that are either LVPECL or CMOS.
V
SIGNAL +
Single-Ended
Peak-to-Peak Voltage
V
ICM , VOCM
Differential I/Os
VISE,VOSE
SIGNAL –
(SIGNAL +) – (SIGNAL –)
Differential Peak-to-Peak Voltage
V ,VOD
ID
VICM, VOCM
t
SIGNAL +
SIGNAL –
VID = (SIGNAL+) – (SIGNAL–)
Figure 1. Differential Voltage Characteristics
80%
20%
CKIN, CKOUT
tF
tR
Figure 2. Rise/Fall Time Characteristics
4
Rev. 1.0
Si5369
Table 2. DC Characteristics
(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
1,6
Supply Current
I
LVPECL Format
622.08 MHz Out
—
394
435
mA
DD
All CKOUTs Enabled
LVPECL Format
622.08 MHz Out
1 CKOUT Enabled
—
—
—
—
253
278
229
165
284
400
261
—
mA
mA
mA
mA
CMOS Format
19.44 MHz Out
All CKOUTs Enabled
CMOS Format
19.44 MHz Out
1 CKOUT Enabled
Disable Mode
2
CKINn Input Pins
Input Common Mode
Voltage (Input Thresh-
old Voltage)
V
1.8 V ± 5%
2.5 V ± 10%
3.3 V ± 10%
Single-ended
0.9
1
—
—
—
40
—
1.4
1.7
1.95
60
V
V
ICM
1.1
20
0.2
V
Input Resistance
CKN
k
RIN
Single-Ended Input
Voltage Swing
(See Absolute Specs)
V
f
f
f
< 212.5 MHz
—
V
V
V
V
ISE
CKIN
PP
PP
PP
PP
See Figure 1.
> 212.5 MHz
0.25
0.2
—
—
—
—
—
—
CKIN
See Figure 1.
< 212.5 MHz
CKIN
Differential Input
Voltage Swing
(See Absolute Specs)
V
ID
See Figure 1.
fCKIN > 212.5 MHz
See Figure 1.
0.25
Notes:
1. Current draw is independent of supply voltage
2. No under- or overshoot is allowed.
3. LVPECL outputs require nominal VDD ≥ 2.5 V.
4. This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx Family
Reference Manual for more details.
5. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz.
6. The LVPECL and CMOS output formats draw more current than either LVDS or CML; however, there are restrictions in
the allowed output format pin settings so that the maximum power dissipation for the TQFP devices is limited when
they are operated at 3.3 V. When there are four enabled LVPECL or CMOS outputs, the fifth output must be disabled.
When there are five enabled outputs, there can be no more than three outputs that are either LVPECL or CMOS.
Rev. 1.0
5
Si5369
Table 2. DC Characteristics (Continued)
(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
3,5,6
Output Clocks (CKOUTn)
Common Mode
CKO
LVPECL 100 load
V
–1.42
—
—
V –1.25
DD
V
VCM
DD
line-to-line
Differential Output
Swing
CKO
LVPECL 100 load
1.1
0.5
1.9
0.93
500
—
V
VD
PP
line-to-line
Single Ended Output
Swing
CKO
LVPECL 100 load
—
V
VSE
PP
line-to-line
Differential Output Volt-
age
CKO
CML 100 load
350
—
425
mV
VD
PP
line-to-line
Common Mode
Output Voltage
CKO
CML 100 load
V
–0.36
DD
V
VCM
line-to-line
Differential Output Volt-
age
CKO
LVDS
100 load line-to-line
500
350
1.125
700
425
1.2
900
500
1.275
—
mV
mV
VD
PP
PP
Low Swing LVDS
100 load line-to-line
Common Mode
Output Voltage
CKO
LVDS 100 load
V
VCM
line-to-line
Differential
Output Resistance
CKO
CML, LVPECL, LVDS
—
—
200
RD
Output Voltage Low
CKO
CKO
CMOS
—
—
0.4
—
V
V
VOLLH
Output Voltage High
V
= 1.71 V
0.8 x V
DD
VOHLH
DD
CMOS
Notes:
1. Current draw is independent of supply voltage
2. No under- or overshoot is allowed.
3. LVPECL outputs require nominal VDD ≥ 2.5 V.
4. This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx Family
Reference Manual for more details.
5. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz.
6. The LVPECL and CMOS output formats draw more current than either LVDS or CML; however, there are restrictions in
the allowed output format pin settings so that the maximum power dissipation for the TQFP devices is limited when
they are operated at 3.3 V. When there are four enabled LVPECL or CMOS outputs, the fifth output must be disabled.
When there are five enabled outputs, there can be no more than three outputs that are either LVPECL or CMOS.
6
Rev. 1.0
Si5369
Table 2. DC Characteristics (Continued)
(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
CKO
Test Condition
Min
Typ
Max
Unit
Output Drive Current
(CMOS driving into
ICMOS[1:0] = 11
—
7.5
—
mA
IO
V
= 1.8 V
DD
CKO
or CKO
high. CKOUT+ and
CKOUT– shorted exter-
nally)
for output low
VOL
ICMOS[1:0] = 10
= 1.8 V
—
—
—
—
—
—
—
5.5
3.5
1.75
32
—
—
—
—
—
—
—
mA
mA
mA
mA
mA
mA
mA
for output
VOH
V
DD
ICMOS[1:0] = 01
= 1.8 V
V
DD
ICMOS[1:0] = 00
= 1.8 V
V
DD
ICMOS[1:0] = 11
= 3.3 V
V
DD
ICMOS[1:0] = 10
= 3.3 V
24
V
DD
ICMOS[1:0] = 01
= 3.3 V
16
V
DD
ICMOS[1:0] = 00
8
V
= 3.3 V
DD
2-Level LVCMOS Input Pins
Input Voltage Low
V
V
V
V
V
V
V
= 1.71 V
= 2.25 V
= 2.97 V
= 1.89 V
= 2.25 V
= 3.63 V
—
—
—
—
—
—
—
—
0.5
0.7
0.8
—
V
V
V
V
V
V
IL
DD
DD
DD
DD
DD
DD
—
Input Voltage High
V
1.4
1.8
2.5
IH
—
—
Notes:
1. Current draw is independent of supply voltage
2. No under- or overshoot is allowed.
3. LVPECL outputs require nominal VDD ≥ 2.5 V.
4. This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx Family
Reference Manual for more details.
5. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz.
6. The LVPECL and CMOS output formats draw more current than either LVDS or CML; however, there are restrictions in
the allowed output format pin settings so that the maximum power dissipation for the TQFP devices is limited when
they are operated at 3.3 V. When there are four enabled LVPECL or CMOS outputs, the fifth output must be disabled.
When there are five enabled outputs, there can be no more than three outputs that are either LVPECL or CMOS.
Rev. 1.0
7
Si5369
Table 2. DC Characteristics (Continued)
(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
3-Level Input Pins
Input Voltage Low
Symbol
Test Condition
Min
Typ
Max
Unit
4
V
—
—
—
0.15 x V
0.55 x V
V
V
ILL
DD
Input Voltage Mid
Input Voltage High
V
0.45 x
IMM
DD
V
DD
V
0.85 x
—
—
V
IHH
ILL
V
DD
Input Low Current
Input Mid Current
Input High Current
I
See Note 4
See Note 4
See Note 4
–20
–2
—
—
—
—
+2
20
µA
µA
µA
I
IMM
I
—
IHH
LVCMOS Output Pins
Output Voltage Low
V
IO = 2 mA
—
—
—
—
—
—
0.4
0.4
—
V
V
V
V
OL
V
= 1.71 V
DD
Output Voltage Low
Output Voltage High
Output Voltage High
Notes:
IO = 2 mA
= 2.97 V
V
DD
V
IO = –2 mA
= 1.71 V
V
V
–0.4
OH
DD
DD
V
DD
IO = –2 mA
= 2.97 V
–0.4
—
V
DD
1. Current draw is independent of supply voltage
2. No under- or overshoot is allowed.
3. LVPECL outputs require nominal VDD ≥ 2.5 V.
4. This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx Family
Reference Manual for more details.
5. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz.
6. The LVPECL and CMOS output formats draw more current than either LVDS or CML; however, there are restrictions in
the allowed output format pin settings so that the maximum power dissipation for the TQFP devices is limited when
they are operated at 3.3 V. When there are four enabled LVPECL or CMOS outputs, the fifth output must be disabled.
When there are five enabled outputs, there can be no more than three outputs that are either LVPECL or CMOS.
8
Rev. 1.0
Si5369
Table 3. AC Specifications
(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Single-Ended Reference Clock Input Pin XA (XB with cap to GND)
Input Resistance
XA
RATE[1:0] = LM, MH,
ac coupled
—
12
—
—
k
RIN
Input Voltage Swing
XA
RATE[1:0] = LM, MH,
ac coupled
0.5
1.2
V
VPP
PP
Differential Reference Clock Input Pins (XA/XB)
Input Voltage Swing
CKINn Input Pins
Input Frequency
XA/XB
RATE[1:0] = LM, MH
0.5
—
2.4
V
VPP
PP
CKN
0.002
40
—
—
710
60
MHz
%
F
Input Duty Cycle
(Minimum Pulse
Width)
CKN
Whichever is smaller
(i.e., the 40% / 60%
limitation applies only
to high frequency
clocks)
DC
2
—
—
—
—
3
ns
pF
ns
Input Capacitance
CKN
—
—
CIN
Input Rise/Fall Time
CKN
20–80%
11
TRF
See Figure 2
CKOUTn Output Pins
(See ordering section for speed grade vs frequency limits)
Output Frequency
(Output not config-
ured for CMOS or
Disabled)
CKO
CKO
N1 6
N1 = 5
N1 = 4
0.002
970
—
—
—
—
945
1134
1.4
MHz
MHz
GHz
MHz
F
1.213
—
Maximum Output
Frequency in CMOS
Format
212.5
F
Output Rise/Fall
(20–80 %) @
622.08 MHz output
CKO
Output not configured for
CMOS or Disabled
See Figure 2
—
230
350
ps
TRF
Notes:
1. Input to output phase skew after an ICAL is not controlled and can assume any value.
2. Lock and settle time performance is dependent on the frequency plan and the XAXB reference frequency. Please visit
the Silicon Labs Technical Support web page at: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx
to submit a technical support request regarding the lock time of your frequency plan.
Rev. 1.0
9
Si5369
Table 3. AC Specifications (Continued)
(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Output Rise/Fall
(20–80%) @
212.5 MHz output
CKO
CMOS Output
—
—
8
ns
TRF
TRF
V
= 1.71
DD
C
= 5 pF
LOAD
Output Rise/Fall
(20–80%) @
212.5 MHz output
CKO
CMOS Output
= 2.97
—
—
—
—
2
ns
ps
V
DD
C
= 5 pF
LOAD
Output Duty Cycle
Uncertainty @
622.08 MHz
CKO
100 Load
Line-to-Line
Measured at 50% Point
(Not for CMOS)
±40
DC
LVCMOS Input Pins
Minimum Reset Pulse
Width
t
1
—
—
—
µs
ms
pF
RSTMN
Reset to Microproces-
sor Access Ready
t
—
—
10
3
READY
Input Capacitance
LVCMOS Output Pins
Rise/Fall Times
C
in
t
C
= 20pf
LOAD
—
—
25
—
—
ns
RF
See Figure 2
LOSn Trigger Window
LOS
From last CKINn to
Internal detection of LOSn
N3 ≠ 1
4.5 x N3
T
CKIN
TRIG
Time to Clear LOL
after LOS Cleared
t
LOS to LOL
Fold = Fnew
Stable Xa/XB reference
—
—
10
—
—
ms
CLRLOL
Device Skew
Output Clock Skew
t
of CKOUTn to of
CKOUT_m, CKOUTn
and CKOUT_m at same
frequency and signal
format
100
ps
SKEW
PHASEOFFSET = 0
CKOUT_ALWAYS_ON = 1
SQ_ICAL = 1
Notes:
1. Input to output phase skew after an ICAL is not controlled and can assume any value.
2. Lock and settle time performance is dependent on the frequency plan and the XAXB reference frequency. Please visit
the Silicon Labs Technical Support web page at: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx
to submit a technical support request regarding the lock time of your frequency plan.
10
Rev. 1.0
Si5369
Table 3. AC Specifications (Continued)
(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Phase Change due to
Temperature
Variation
t
Max phase changes from
–40 to +85 °C
—
300
500
ps
TEMP
1
PLL Performance
(fin = fout = 622.08 MHz; BW = 7 Hz; LVPECL, XAXB = 114.285 MHz)
2
Lock Time
t
Start of ICAL to of LOL
—
—
0.8
4.2
1.0
5.0
s
s
LOCKMP
2
Settle Time
t
Start of ICAL to F
SETTLE
OUT
within 5 ppm of final value
Output Clock Phase
Change
t
After clock switch
—
200
—
ps
P_STEP
f3 128 kHz
Closed Loop Jitter
Peaking
J
—
0.05
—
0.1
—
dB
PK
Jitter Tolerance
J
Jitter Frequency Loop
5000/BW
ns pk-pk
TOL
Bandwidth
100 Hz Offset
1 kHz Offset
—
—
—
—
—
—
–95
–110
–117
–118
–131
–67
—
—
—
—
—
—
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc
Phase Noise
fout = 622.08 MHz
10 kHz Offset
100 kHz Offset
1 MHz Offset
CKO
PN
Spurious Noise
SP
Max spur @ n x F3
SPUR
(n 1, n x F3 < 100 MHz)
Notes:
1. Input to output phase skew after an ICAL is not controlled and can assume any value.
2. Lock and settle time performance is dependent on the frequency plan and the XAXB reference frequency. Please visit
the Silicon Labs Technical Support web page at: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx
to submit a technical support request regarding the lock time of your frequency plan.
Rev. 1.0
11
Si5369
Table 4. Microprocessor Control
(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
2
I C Bus Lines (SDA, SCL)
Input Voltage Low
VIL
—
—
—
—
—
—
0.25 x V
V
V
V
V
V
I2C
DD
Input Voltage High
VIH
0.7 x V
0.1 x V
V
DD
I2C
DD
DD
Hysteresis of Schmitt
trigger inputs
VHYS
V
= 1.8 V
DD
—
I2C
V
V
= 2.5 or 3.3 V
0.05 x V
—
—
DD
DD
Output Voltage Low
VOL
V
= 1.8 V
0.2 x V
DD
I2C
DD
IO = 3 mA
= 2.5 or 3.3 V
IO = 3 mA
—
—
0.4
V
DD
12
Rev. 1.0
Si5369
Table 4. Microprocessor Control (Continued)
(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
SPI Specifications
Duty Cycle, SCLK
Cycle Time, SCLK
Rise Time, SCLK
Fall Time, SCLK
Low Time, SCLK
High Time, SCLK
t
SCLK = 10 MHz
40
100
—
—
—
—
—
—
—
—
60
—
25
25
—
—
25
%
ns
ns
ns
ns
ns
ns
DC
t
c
t
20–80%
20–80%
20–20%
80–80%
r
t
—
f
t
30
30
—
lsc
t
hsc
Delay Time, SCLK Fall
to SDO Active
t
d1
d2
d3
Delay Time, SCLK Fall
to SDO Transition
t
—
—
25
20
25
20
25
—
—
—
—
—
—
—
25
25
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
Delay Time, SS Rise
to SDO Tri-state
t
Setup Time, SS to
SCLK Fall
t
su1
Hold Time, SS to
SCLK Rise
t
h1
Setup Time, SDI to
SCLK Rise
t
su2
Hold Time, SDI to
SCLK Rise
t
h2
Delay Time between
Slave Selects
t
cs
Rev. 1.0
13
Si5369
Table 5. Jitter Generation
*
Parameter
Symbol
Min
Typ
Max
GR-253-
Specification
Unit
Test Condition
Measurement
Filter
DSPLL
2
BW
Jitter Gen
OC-192
JGEN
0.02–80 MHz
120 Hz
120 Hz
120 Hz
120 Hz
—
—
—
—
—
—
—
—
4.2
.27
3.7
.14
4.4
.26
3.5
.27
—
—
—
—
—
—
—
—
30
N/A
10
ps
PP
ps
rms
4–80 MHz
ps
PP
N/A
10
ps
rms
0.05–80 MHz
0.12–20 MHz
ps
PP
1.0
ps
rms
Jitter Gen
OC-48
JGEN
40.2
4.02
ps
PP
ps
rms
*Note: Test conditions:
1. fIN = fOUT = 622.08 MHz
2. Clock input: LVPECL
3. Clock output: LVPECL
4. PLL bandwidth: 120 Hz
5. 114.285 MHz 3rd OT crystal used as XA/XB input
6. DD = 2.5 V
7. TA = 85 °C
V
8. Jitter integration bands include low-pass (-20 dB/dec) and high-pas (-60 dB/dec) roll-offs per Telecordia GR-253-
CORE.
14
Rev. 1.0
Si5369
Table 6. Thermal Characteristics
(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Value
Unit
Thermal Resistance Junction to Ambient
Still Air
31
C°/W
JA
Table 7. Absolute Maximum Ratings*
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
DC Supply Voltage
V
–0.5
—
—
—
—
—
—
—
3.8
V
DD
LVCMOS Input Voltage
V
–0.3
0
V
+0.3
DD
V
V
DIG
CKINn Voltage Level Limits
XA/XB Voltage Level Limits
Operating Junction Temperature
Storage Temperature Range
CKN
V
DD
VIN
XA
0
1.2
150
150
—
V
VIN
T
–55
–55
2
ºC
ºC
kV
JCT
T
STG
ESD HBM Tolerance
(100 pF, 1.5 k); All pins except
CKIN+/CKIN–
ESD MM Tolerance; All pins
except CKIN+/CKIN–
150
700
100
—
—
—
—
—
—
V
V
V
ESD HBM Tolerance
(100 pF, 1.5 k); CKIN+/CKIN–
ESD MM Tolerance;
CKIN+/CKIN–
Latch-up Tolerance
JESD78 Compliant
*Note: Permanent device damage may occur if the Absolute Maximum Ratings are exceeded. Functional operation should be
restricted to the conditions as specified in the operation sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods of time may affect device reliability.
Rev. 1.0
15
Si5369
2. Typical Phase Noise Performance
Figure 3. Broadcast Video*
*Note: Phase noise plot RMS jitter value used brick wall integration.
Jitter Bandwidth
10 Hz to 20 MHz
Jitter (peak-peak)
Jitter (RMS)
5.24 ps
484
Note: Number of samples: 8.91E9
16
Rev. 1.0
Si5369
Figure 4. OTN/SONET/SDH Phase Noise*
*Note: Phase noise plot RMS jitter value uses brick wall integration.
Jitter Bandwidth
Jitter, RMS
266 fs
SONET_OC48, 12 kHz to 20 MHz
SONET_OC192_A, 20 kHz to 80 MHz
SONET_OC192_B, 4 MHz to 80 MHz
SONET_OC192_C, 50 kHz to 80 MHz
Brick Wall_800 Hz to 80 MHz
283 fs
155 fs
275 fs
287 fs
Note: Jitter integration bands include low-pass (–20 dB/Dec) and hi-pass (–60 dB/Dec) roll-offs
per Telecordia GR-253-CORE.
Rev. 1.0
17
Si5369
Figure 5. Wireless Base Station Phase Noise*
*Note: Phase noise plot RMS jitter value uses brick wall integration.
Jitter Bandwidth
10 Hz to 20 MHz
Jitter (peak-peak)
Jitter (RMS)
7.28 ps
581
Note: Number of samples: 8.91E9
18
Rev. 1.0
Si5369
Figure 6. 10 GbE Phase Noise*
*Note: Phase noise plot RMS jitter value uses brick wall integration.
Jitter Bandwidth
Jitter (RMS)
10 kHz to 10 MHz
238 fs
Rev. 1.0
19
Si5369
C10
System
Power
Supply
Option 1:
Crystal
Option 2:
Ext. Refclk
Ferrite
Bead
1 µF
C1–9
0.1 µF
0.1 µF
VDD = 3.3 V
0.1 µF
130
82
130
CKIN1+
0.1 µF
100
0.1 µF
+
–
CKOUT1+
CKOUT1–
CKIN1–
82
0.1 µF
CKOUT4+
+
–
+
–
Input
Clock
Sources*
Clock
Outputs
100
VDD = 3.3 V
CKOUT4–
FS_OUT+
0.1 µF
0.1 µF
130
82
130
82
CKIN4+
CKIN4–
Si5369
100
FS_OUT–
0.1 µF
Interrupt/Alarm Output
Indicator
INT_ALM
CnB
CKINn Invalid Indicator
(n = 1 to 3)
INC
INC
PLL Loss of Lock
Indicator
LOL
DEC
DEC
Rate
Serial Port
Address
I2C
A[2:0]
SDA
SCL
RATE[1:0]
CMODE
RST
Serial Data
Interface
Control Mode (L)
Reset
Serial Clock
*Note: Assumes differential LVPECL termination (3.3 V) on clock inputs.
2
Figure 7. Si5369 Typical Application Circuit (I C Control Mode)
C10
System
Option 1:
Crystal
Option 2:
Ext. Refclk
Power
Supply
Ferrite
Bead
1 µF
C1–9
0.1 µF
0.1 µF
VDD = 3.3 V
0.1 µF
130
82
130
82
CKIN1+
CKIN1–
0.1 µF
100
0.1 µF
CKOUT1+
CKOUT1–
+
–
0.1 µF
+
–
+
–
CKOUT4+
Input
Clock
Clock
Sources*
Outputs
100
VDD = 3.3 V
CKOUT4–
FS_OUT+
0.1 µF
0.1 µF
130
82
130
82
CKIN4+
CKIN4–
100
Si5369
FS_OUT–
0.1 µF
Interrupt/Alarm Output
Indicator
INT_ALM
CnB
CKINn Invalid Indicator
(n = 1 to 3)
PLL Loss of Lock
Indicator
LOL
INC
INC
DEC
Rate
SS
SDO
SDI
Slave Select
DEC
Serial Data
Out
RATE[1:0]
CMODE
RST
SPI
Interface
Serial Data
In
Control Mode (H)
Reset
SCL
Serial Clock
*Note: Assumes differential LVPECL termination (3.3 V) on clock inputs.
Figure 8. Si5369 Typical Application Circuit (SPI Control Mode)
Rev. 1.0
20
Si5369
a historical average that existed a fixed amount of time
before the error event occurred, eliminating the effects of
phase and frequency transients that may occur
immediately preceding digital hold.
3. Functional Description
The Si5369 is a jitter-attenuating precision clock multiplier
for applications requiring sub 1 ps rms jitter performance.
The Si5369 accepts four clock inputs ranging from 2 kHz
to 710 MHz and generates five clock outputs ranging from
2 kHz to 945 MHz and select frequencies to 1.4 GHz. The
device provides virtually any frequency translation
combination across this operating range. Independent
dividers are available for every input clock and output
clock, so the Si5369 can accept input clocks at different
frequencies and it can generate output clocks at different
frequencies. The Si5369 input clock frequency and clock
The Si5369 has five differential clock outputs. The
electrical format of the clock outputs is programmable to
support LVPECL, LVDS, CML, or CMOS loads. If not
required, unused clock outputs can be powered down to
minimize power consumption. The phase difference
between the selected input clock and the output clocks is
adjustable in 200 ps increments for system skew control.
In addition, the phase of one output clock may be
adjusted in relation to the phase of the other output clock.
The resolution varies from 800 ps to 2.2 ns depending on
the PLL divider settings. Consult the DSPLLsim
configuration software to determine the phase offset
resolution for a given input clock/clock multiplication ratio
combination. For system-level debugging, a bypass mode
is available which drives the output clock directly from the
input clock, bypassing the internal DSPLL. The device is
powered by a single 1.8, 2.5, or 3.3 V supply.
2
multiplication ratio are programmable through an I C or
SPI interface. Optionally, the fifth clock output can be
configured as a 2 to 512 kHz SONET/SDH frame
synchronization output that is phase aligned with one of
the high-speed output clocks. Silicon Laboratories offers a
PC-based software utility, DSPLLsim, that can be used to
determine the optimum PLL divider settings for a given
input frequency/clock multiplication ratio combination that
minimizes phase noise and power consumption. This
3.1. External Reference
utility
can
be
downloaded
from
http://www.silabs.com/timing (click on Documentation).
An external clock or a low-cost 114.285 MHz 3rd overtone
crystal is typically used as part of a fixed-frequency
oscillator within the DSPLL. This external reference is
required for the device to operate. Silicon Laboratories
The Si5369 is based on Silicon Laboratories' 3rd-
®
generation DSPLL technology, which provides any-
frequency synthesis and jitter attenuation in a highly
integrated PLL solution that eliminates the need for
external VCXO and loop filter components. The Si5369
PLL loop bandwidth is digitally programmable and
supports a range from 4 to 525 Hz. The DSPLLsim
recommends using
a high-quality crystal. Specific
recommendations may be found in the Family Reference
Manual. An external clock from a high-quality OCXO or
TCXO can also be used as a reference for the device.
software utility can be used to calculate valid loop If there is a need to use a reference oscillator instead of
bandwidth settings for a given input clock frequency/clock a crystal, Silicon Labs does not recommend using
MEMS based oscillators. Instead, Silicon Labs
recommends the Si530EB121M109DG, which is a very
low jitter/wander, LVPECL, 2.5 V crystal oscillator. The
very low loop BW of the Si5369 means that it can be
susceptible to XAXB reference sources that have high
wander. Experience has shown that in spite of having
low jitter, some MEMs oscillators have high wander, and
these devices should be avoided. Contact Silicon Labs
for details.
In digital hold, the DSPLL remains locked to this external
reference. Any changes in the frequency of this
reference when the DSPLL is in digital hold, will be
tracked by the output of the device. Note that crystals
can have temperature sensitivities.
multiplication ratio.
The Si5369 supports hitless switching between input
clocks in compliance with GR-253-CORE and GR-1244-
CORE that greatly minimizes the propagation of phase
transients to the clock outputs during an input clock
transition (<200 ps typ). Manual, automatic revertive and
non-revertive input clock switching options are available.
The Si5369 monitors the four input clocks for loss-of-
signal and provides a LOS alarm when it detects missing
pulses on any of the four input clocks. The device
monitors the lock status of the PLL. The lock detect
algorithm works by continuously monitoring the phase of
the input clock in relation to the phase of the feedback
clock. The Si5369 monitors the frequency of CKIN1,
CKIN2, CKIN3, and CKIN4 with respect to a selected
reference frequency and generates a frequency offset
alarm (FOS) if the threshold is exceeded. This FOS
feature is available for SONET applications in which both
the monitored frequency on CKIN1, CKIN3, and CKIN4
and the reference frequency are integer multiples of 19.44
MHz. Both Stratum 3/3E and SONET Minimum Clock
(SMC) FOS thresholds are supported.
3.2. Further Documentation
Consult the Silicon Laboratories Any-Frequency
Precision Clock Family Reference Manual (FRM) for
detailed information about the Si5369. Additional design
support is available from Silicon Laboratories through
your distributor.
Silicon Laboratories has developed
a
PC-based
software utility called DSPLLsim to simplify device
configuration, frequency planning, and loop bandwidth
selection. The FRM and this utility can be downloaded
The Si5369 provides a digital hold capability that allows
the device to continue generation of a stable output clock
when the selected input reference is lost. During digital
hold, the DSPLL generates an output frequency based on
from
http://www.silabs.com/timing;
click
on
Documentation.
Rev. 1.0
21
Si5369
4. Register Map
All register bits that are not defined in this map should always be written with the specified Reset Values. The
writing to these bits of values other than the specified Reset Values may result in undefined device behavior.
Registers not listed, such as Register 64, should never be written to.
Register
D7
D6
D5
D4
D3
D2
D1
D0
0
FREE_RUN
CKOUT_
ALWAYS_
ON
BYPASS_
REG
1
2
CK_PRIOR4 [1:0]
CK_PRIOR3 [1:0]
CK_PRIOR2 [1:0]
CK_PRIOR1 [1:0]
BWSEL_REG [3:0]
3
CKSEL_REG [1:0]
AUTOSEL_REG [1:0]
ICMOS [1:0]
DHOLD
SQ_ICAL
4
HIST_DEL [4:0]
SFOUT1_REG [2:0]
5
SFOUT2_REG [2:0]
SFOUT4_REG [2:0]
SFOUT5_REG [2:0]
6
SFOUT3_REG [2:0]
FOSREFSEL [2:0]
7
8
HLOG_4 [1:0]
HLOG_3 [1:0]
HLOG_2 [1:0]
HLOG_1 [1:0]
HLOG_5 [1:0]
9
HIST_AVG [4:0]
10
DSBL5_
REG
DSBL4_
REG
DSBL3_
REG
DSBL2_
REG
DSBL1_
REG
11
19
20
PD_CK4
VALTIME [1:0]
CK3_BAD_ CK2_BAD_ CK1_BAD_
PD_CK3
PD_CK2
PD_CK1
FOS_EN
FOS_THR [1:0]
LOCKT [2:0]
LOL_PIN
ALR-
INT_PIN
MOUT_PIN
PIN
PIN
PIN
21
22
CK4_ACT-
V_PIN
CK3_ACT-
V_PIN
CK2_ACT-
V_PIN
CK1_ACT- CKSEL_PIN
V_PIN
CK_ACTV_
POL
CK_BAD_
POL
LOL_POL
INT_POL
23
24
LOS4_MSK LOS3_MSK
FOS4_MSK FOS3_MSK
LOS2_MSK LOS1_MSK LOSX_MSK
FOS2_MSK FOS1_MSK
NC1_LS [19:16]
LOL_MSK
25
26
27
28
29
30
31
N1_HS [2:0]
NC1_LS [15:8]
NC1_LS [7:0]
NC2_LS [19:16]
NC3_LS [19:16]
NC2_LS [15:8]
NC2_LS [7:0]
22
Rev. 1.0
Si5369
Register
32
D7
D6
D5
D4
D3
D2
D1
D0
NC3_LS [15:8]
33
NC3_LS [7:0]
34
NC4_LS [19:16]
NC5_LS [19:16]
N2_LS [19:16]
35
NC4_LS [15:8]
NC4_LS [7:0]
36
37
38
NC5_LS [15:8]
NC5_LS [7:0]
39
40
N2_HS [2:0]
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
128
N2_LS [15:8]
N2_LS [7:0]
N31_ [18:16]
N31_[15:8]
N31_ [7:0]
N32_ [18:16]
N33_[18:16]
N34_[18:16]
N31_ [15:8]
N32_[7:0]
N33_[15:8]
N33_[7:0]
N34_[15:8]
N34_[7:0]
CLKIN2RATE_[2:0]
CLKIN1RATE[2:0]
CLKIN3RATE[2:0]
CLKIN4RATE_[2:0]
CK4_ACT-
V_REG
CK3_ACT-
V_REG
CK2_ACT-
V_REG
CK1_ACT-
V_REG
129
130
LOS4_INT
FOS4_INT
LOS3_INT
FOS3_INT
LOS2_INT
FOS2_INT
LOS1_INT
FOS1_INT
LOSX_INT
LOL_INT
DIGHOLD-
VALID
131
LOS4_FLG LOS3_FLG LOS2_FLG LOS1_FLG LOSX_FLG
Rev. 1.0
23
Si5369
Register
D7
D6
D5
D4
D3
D2
D1
D0
132
134
135
136
137
138
FOS4_FLG FOS3_FLG FOS2_FLG FOS1_FLG
PARTNUM_RO [11:4]
LOL_FLG
PARTNUM_RO [3:0]
ICAL
REVID_RO [3:0]
RST_REG
FASTLOCK
LOS4_EN
[1:1]
LOS3_EN
[1:1]
LOS2_EN
[1:1]
LOS1_EN
[1:1]
139
LOS4_EN
[0:0]
LOS3_EN
[0:0]
LOS2_EN
[0:0]
LOS1_EN
[0:0]
FOS4_EN
FOS3_EN
FOS2_EN
FOS1_EN
140
141
142
143
144
INDEPENDENTSKEW1 [7:0]
INDEPENDENTSKEW2 [7:0]
INDEPENDENTSKEW3 [7:0]
INDEPENDENTSKEW4 [7:0]
INDEPENDENTSKEW5 [7:0]
24
Rev. 1.0
Si5369
5. Register Descriptions
Register 0.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
FREE_RUN CKOUT_ALWAYS_ON
BYPASS_REG
R/W
R
R/W
R/W
R
R
R
R
Reset value = 0001 0100
Bit
7
Name
Function
Reserved
FREE_RUN
6
Free Run.
Internal to the device, route XA/XB to CKIN2. This allows the device to lock to its
external reference.
0: Disable Free Run
1: Enable
5
CKOUT_ALWAYS_ON CKOUT Always On.
This will bypass the SQ_ICAL function. Output will be available even if SQ_ICAL
is on and ICAL is not complete or successful. See Table 8.
0: Squelch output until part is calibrated (ICAL).
1: Provide an output. Note: The frequency may be significantly off until the part
is calibrated.
4:2
1
Reserved
BYPASS_REG
Bypass Register.
This bit enables or disables the PLL bypass mode. Use is only valid when the
part is in digital hold or before the first ICAL.
0: Normal operation
1: Bypass mode. Selected input clock is connected to CKOUT buffers, bypass-
ing PLL.
0
Reserved
Rev. 1.0
25
Si5369
Register 1.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
CK_PRIOR4 [1:0]
R/W
CK_PRIOR3 [1:0]
R/W
CK_PRIOR2 [1:0]
R/W
CK_PRIOR1 [1:0]
R/W
Reset value = 1110 0100
Bit
Name
CK_PRIOR4 [1:0] CK_PRIOR 4.
Function
7:6
Selects which of the input clocks will be 4th priority in the autoselection state
machine.
00: CKIN1 is 4th priority.
01: CKIN2 is 4th priority.
10: CKIN3 is 4th priority.
11: CKIN4 is 4th priority.
5:4
3:2
1:0
CK_PRIOR3 [1:0] CK_PRIOR 3.
Selects which of the input clocks will be 3rd priority in the autoselection state
machine.
00: CKIN1 is 3rd priority.
01: CKIN2 is 3rd priority.
10: CKIN3 is 3rd priority.
11: CKIN4 is 3rd priority.
CK_PRIOR2 [1:0] CK_PRIOR 2.
Selects which of the input clocks will be 2nd priority in the autoselection state
machine.
00: CKIN1 is 2nd priority.
01: CKIN2 is 2nd priority.
10: CKIN3 is 2nd priority.
11: CKIN4 is 2nd priority.
CK_PRIOR1 [1:0] CK_PRIOR 1.
Selects which of the input clocks will be 1st priority in the autoselection state
machine.
00: CKIN1 is 1st priority.
01: CKIN2 is 1st priority.
10: CKIN3 is 1st priority.
11: CKIN4 is 1st priority.
26
Rev. 1.0
Si5369
Register 2.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
BWSEL_REG [3:0]
R/W
R
R
R
R
Reset value = 0100 0010
Bit
Name
BWSEL_REG [3:0] BWSEL_REG.
Function
7:4
Selects nominal f3dB bandwidth for PLL. See the DSPLLsim for settings. After
BWSEL_REG is written with a new value, an ICAL is required for the change to
take effect.
3:0
Reserved
Register 3.
Bit
D7
D6
D5
DHOLD
R/W
D4
SQ_ICAL
R/W
D3
D2
D1
D0
Name
Type
CKSEL_REG [1:0]
R/W
R
R
R
R
Reset value = 0000 0101
Bit
Name
CKSEL_REG [1:0] CKSEL_REG.
If the device is operating in manual register-based clock selection mode
Function
7:6
(AUTOSEL_REG = 00), and CKSEL_PIN = 0, then these bits select which input
clock will be the active input clock. If CKSEL_PIN = 1, the CKSEL[1:0] input pins
continue to control clock selection and CKSEL_REG is of no consequence.
00: CKIN_1 selected.
01: CKIN_2 selected.
10: CKIN_3 selected.
11: CKIN_4 selected.
5
DHOLD
DHOLD.
Forces the part into digital hold. This bit overrides all other manual and automatic
clock selection controls.
0: Normal operation.
1: Force digital hold mode. Overrides all other settings and ignores the quality of all
of the input clocks.
4
SQ_ICAL
Reserved
SQ_ICAL.
This bit determines if the output clocks will remain enabled or be squelched (dis-
abled) during an internal calibration. See Table 8.
0: Output clocks enabled during ICAL.
1: Output clocks disabled during ICAL.
3:0
Rev. 1.0
27
Si5369
Register 4.
Bit
D7
D6
AUTOSEL_REG [1:0]
R/W
D5
D4
D3
D2
HIST_DEL [4:0]
R/W
D1
D0
Name
Type
R
Reset value = 0001 0010
Bit
7:6 AUTOSEL_REG [1:0] AUTOSEL_REG [1:0].
Selects method of input clock selection to be used.
Name
Function
00: Manual (either register or pin controlled. See CKSEL_PIN).
01: Automatic Non-Revertive
10: Automatic Revertive
11: Reserved
5
Reserved
4:0
HIST_DEL [4:0]
HIST_DEL [4:0].
Selects amount of delay to be used in generating the history information MHIST,
the value of M used during Digital Hold.
28
Rev. 1.0
Si5369
Register 5.
Bit
D7
ICMOS [1:0]
R/W
D6
D5
D4
SFOUT2_REG [2:0]
R/W
D3
D2
D1
D0
Name
Type
SFOUT1_REG [2:0]
R/W
Reset value = 1110 1101
Bit
Name
Function
7:6
ICMOS [1:0]
ICMOS [1:0].
When the output buffer is set to CMOS mode, these bits determine the output buf-
fer drive strength. The first number below refers to 3.3 V operation; the second to
1.8 V operation. These values assume CKOUT+ is tied to CKOUT-.
00: 8 mA/2 mA
01: 16 mA/4 mA
10: 24 mA/6 mA
11: 32 mA (3.3 V operation)/8mA (1.8 V operation)
5:3
SFOUT2_REG [2:0] SFOUT2_REG [2:0]
Controls output signal format and disable for CKOUT2 output buffer. The LVPECL
and CMOS output formats draw more current than either LVDS or CML; however,
there are restrictions in the allowed output format pin settings so that the maximum
power dissipation for the TQFP devices is limited when they are operated at 3.3 V.
When there are four enabled LVPECL or CMOS outputs, the fifth output must be
disabled. When there are five enabled outputs, there can be no more than three
outputs that are either LVPECL or CMOS.
000: Reserved
001: Disable
010: CMOS
011: Low swing LVDS
100: Reserved
101: LVPECL
110: CML
111: LVDS
2:0
SFOUT1_REG [2:0] SFOUT1_REG [2:0]
Controls output signal format and disable for CKOUT1 output buffer. The LVPECL
and CMOS output formats draw more current than either LVDS or CML; however,
there are restrictions in the allowed output format pin settings so that the maximum
power dissipation for the TQFP devices is limited when they are operated at 3.3 V.
When there are four enabled LVPECL or CMOS outputs, the fifth output must be
disabled. When there are five enabled outputs, there can be no more than three
outputs that are either LVPECL or CMOS.
000: Reserved
001: Disable
010: CMOS
011: Low swing LVDS
100: Reserved
101: LVPECL
110: CML
111: LVDS
Rev. 1.0
29
Si5369
Register 6.
Bit
D7
D6
D5
D4
SFOUT4_REG [2:0]
R/W
D3
D2
D1
SFOUT3_REG [2:0]
R/W
D0
Name
Type
R
R
Reset value = 0010 1100
Bit
7:6
5:3
Name
Function
Reserved
SFOUT4_REG [2:0] SFOUT4_REG [2:0].
Controls output signal format and disable for CKOUT4 output buffer. The LVPECL
and CMOS output formats draw more current than either LVDS or CML; however,
there are restrictions in the allowed output format pin settings so that the maxi-
mum power dissipation for the TQFP devices is limited when they are operated at
3.3 V. When there are four enabled LVPECL or CMOS outputs, the fifth output
must be disabled. When there are five enabled outputs, there can be no more
than three outputs that are either LVPECL or CMOS.
000: Reserved
001: Disable
010: CMOS
011: Low swing LVDS
100: Reserved
101: LVPECL
110: CML
111: LVDS
2:0
SFOUT3_REG [2:0] SFOUT3_REG [2:0].
Controls output signal format and disable for CKOUT3 output buffer. The LVPECL
and CMOS output formats draw more current than either LVDS or CML; however,
there are restrictions in the allowed output format pin settings so that the maxi-
mum power dissipation for the TQFP devices is limited when they are operated at
3.3 V. When there are four enabled LVPECL or CMOS outputs, the fifth output
must be disabled. When there are five enabled outputs, there can be no more
than three outputs that are either LVPECL or CMOS.
000: Reserved
001: Disable
010: CMOS
011: Low swing LVDS
100: Reserved
101: LVPECL
110: CML
111: LVDS
30
Rev. 1.0
Si5369
Register 7.
Bit
D7
D6
D5
D4
SFOUT5_REG [2:0]
R/W
D3
D2
D1
D0
Name
Type
FOSREFSEL [2:0]
R/W
R
R
Reset value = 0010 1010
Bit
7:6
5:3
Name
Function
Reserved.
SFOUT5_REG [2:0] SFOUT5_REG [2:0]
Controls output signal format and disable for CKOUT5 output buffer. The
LVPECL and CMOS output formats draw more current than either LVDS or CML;
however, there are restrictions in the allowed output format pin settings so that
the maximum power dissipation for the TQFP devices is limited when they are
operated at 3.3 V. When there are four enabled LVPECL or CMOS outputs, the
fifth output must be disabled. When there are five enabled outputs, there can be
no more than three outputs that are either LVPECL or CMOS.
000: Reserved
001: Disable
010: CMOS
011: Low swing LVDS
100: Reserved
101: LVPECL
110: CML
111: LVDS
2:0
FOSREFSEL [2:0]
FOSREFSEL [2:0].
Selects which input clock is used as the reference frequency for Frequency Off-
Set (FOS) alarms.
000: XA/XB (External reference)
001: CKIN1
010: CKIN2
011: CKIN3
100: CKIN4
101: Reserved
110: Reserved
111: Reserved
Rev. 1.0
31
Si5369
Register 8.
Bit
D7
HLOG_4[1:0]
R/W
D6
D5
HLOG_3[1:0]
R/W
D4
D3
HLOG_2[1:0]
R/W
D2
D1
HLOG_1[1:0]
R/W
D0
Name
Type
Reset value = 0000 0000
Bit
Name
Function
7:6
HLOG_4 [1:0] HLOG_4 [1:0].
00: Normal operation
01: Holds CKOUT4 output at static logic 0. Entrance and exit from this state will occur
without glitches or runt pulses.
10: Holds CKOUT4 output at static logic 1. Entrance and exit from this state will occur
without glitches or runt pulses.
11: Reserved
5:4
3:2
1:0
HLOG_3 [1:0] HLOG_3 [1:0].
00: Normal operation
01: Holds CKOUT3 output at static logic 0. Entrance and exit from this state will occur
without glitches or runt pulses.
10: Holds CKOUT3 output at static logic 1. Entrance and exit from this state will occur
without glitches or runt pulses.
11: Reserved.
HLOG_2 [1:0] HLOG_2 [1:0].
00: Normal operation
01: Holds CKOUT2 output at static logic 0. Entrance and exit from this state will occur
without glitches or runt pulses.
10: Holds CKOUT2 output at static logic 1. Entrance and exit from this state will occur
without glitches or runt pulses.
11: Reserved.
HLOG_1 [1:0] HLOG_1 [1:0].
00: Normal operation
01: Holds CKOUT1 output at static logic 0. Entrance and exit from this state will occur
without glitches or runt pulses.
10: Holds CKOUT1 output at static logic 1. Entrance and exit from this state will occur
without glitches or runt pulses.
11: Reserved
32
Rev. 1.0
Si5369
Register 9.
Bit
D7
D6
D5
HIST_AVG [4:0]
R/W
D4
D3
D2
D1
D0
Name
Type
HLOG_5 [1:0]
R/W
R
Reset value = 1100 0000
Bit
Name
HIST_AVG [4:0] HIST_AVG [4:0].
Function
7:3
Selects amount of averaging time to be used in generating MHIST, the value of M
used
during digital hold. See Family Reference Manual for settings.
2
Reserved
1:0
HLOG_5 [1:0]
HLOG_5 [1:0].
00: Normal Operation
01: Holds CKOUT5 output at static logic 0. Entrance and exit from this state will occur
without glitches or runt pulses.
10: Holds CKOUT5 output at static logic 1. Entrance and exit from this state will
occur without glitches or runt pulses.
11: Reserved
Rev. 1.0
33
Si5369
Register 10.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
DSBL5_REG Reserved DSBL4_REG DSBL3_REG DSBL2_REG DSBL1_REG
R
R/W
R
R/W
R/W
R
R
R
Reset value = 0000 0000
Bit
7:6
5
Name
Function
Reserved
DSBL5_REG
DSBL5_REG.
This bit controls the powerdown and disable of the CKOUT5 output buffer. If disable
mode is selected, the NC5_LS output divider is also powered down.
0: CKOUT5 enabled.
1: CKOUT5 disabled.
4
3
Reserved
DSBL4_REG
DSBL4_REG.
This bit controls the powerdown and disable of the CKOUT4 output buffer. If disable
mode is selected, the NC4 output divider is also powered down.
0'b=CKOUT4 enabled
1'b=CKOUT4 disabled
2
1
0
DSBL3_REG
DSBL2_REG
DSBL1_REG
DSBL3_REG.
This bit controls the powerdown and disable of the CKOUT3 output buffer. If disable
mode is selected, the NC3 output divider is also powered down.
0: CKOUT3 enabled
1: CKOUT3 disabled
DSBL2_REG.
This bit controls the powerdown and disable of the CKOUT2 output buffer. If disable
mode is selected, the NC2 output divider is also powered down.
0: CKOUT2 enabled
1: CKOUT2 disabled
DSBL1_REG.
This bit controls the powerdown and disable of the CKOUT1 output buffer. If disable
mode is selected, the NC1 output divider is also powered down.
0: CKOUT1 enabled
1: CKOUT1 disabled
34
Rev. 1.0
Si5369
Register 11.
Bit
D7
D6
D5
D4
D3
PD_CK4
R/W
D2
PD_CK3
R/W
D1
PD_CK2
R/W
D0
PD_CK1
R/W
Name
Type
R
R
R
R
Reset value = 0100 0000
Bit
7:4
3
Name
Function
Reserved
PD_CK4
PD_CK4.
This bit controls the powerdown of the CKIN4 input buffer.
0: CKIN4 enabled
1: CKIN4 disabled
2
1
0
PD_CK3
PD_CK2
PD_CK1
PD_CK3.
This bit controls the powerdown of the CKIN3 input buffer.
0: CKIN3 enabled
1: CKIN3 disabled
PD_CK2.
This bit controls the powerdown of the CKIN2 input buffer.
0: CKIN2 enabled
1: CKIN2 disabled
PD_CK1.
This bit controls the powerdown of the CKIN1 input buffer.
0: CKIN1 enabled
1: CKIN1 disabled
Rev. 1.0
35
Si5369
Register 19.
Bit
D7
D6
D5
D4
VALTIME [1:0]
R/W
D3
D2
D1
LOCKT [2:0]
R/W
D0
Name FOS_EN
FOS_THR [1:0]
R/W
Type
R/W
Reset value = 0010 1100
Bit
Name
Function
7
FOS_EN
FOS_EN.
Frequency offset enable globally disables FOS. See the individual FOS enables (FOS-
x_EN, register 139).
00: FOS disable
01: FOS enabled by FOSx_EN
6:5
4:3
2:0
FOS_THR [1:0] FOS_THR [1:0].
Frequency Offset at which FOS is declared:
00: ± 11 to 12 ppm Stratum 3/3E compliant, with a Stratum 3/3E used for REFCLK.
01: ± 48 to 49 ppm (SMC).
10: ± 30 ppm SONET Minimum Clock (SMC), with a Stratum 3/3E used for REFCLK.
11: ± 200 ppm
VALTIME [1:0] VALTIME [1:0].
Sets amount of time for input clock to be valid before the associated alarm is removed.
00: 2 ms
01: 100 ms
10: 200 ms
11: 13 s
LOCKT [2:0]
LOCKT [2:0].
Sets retrigger interval for one shot monitoring phase detector output. One shot is trig-
gered by phase slip in DSPLL. Refer to the Family Reference Manual for more details.
000: 106 ms
001: 53 ms
010: 26.5 ms
011: 13.3 ms
100: 6.6 ms
101: 3.3 ms
110: 1.66 ms
111: 833 µs
36
Rev. 1.0
Si5369
Register 20.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
ALRMOUT_PIN CK3_BAD_PIN CK2_BAD_PIN CK1_BAD_PIN LOL_PIN INT_PIN
R/W R/W R/W R/W R/W R/W
R
R
Reset value = 0011 1100
Bit
7:6
5
Name
Function
Reserved
ALRMOUT_PIN ALRMOUT_PIN.
The ALRMOUT status can be reflected on the ALRMOUT output pin. The request to
reflect the interrupt status on this pin (INT_PIN=1) overrides the ALRMOUT_PIN
request.
0: ALRMOUT not reflected on output pin. Output pin disabled if INT_PIN=0.
1: ALRMOUT reflected to output pin if INT_PIN=0. If INT_PIN=1, interrupt status
appears on the output pin and ALRMOUT is not available on an output pin.
4
3
2
1
0
CK3_BAD_PIN CK3_BAD_PIN.
The CK3_BAD status can be reflected on the C3B output pin.
0: C3B output pin tristated
1: C3B status reflected to output pin
CK2_BAD_PIN CK2_BAD_PIN.
The CK2_BAD status can be reflected on the C2B output pin.
0: C2B output pin tristated
1: C2B status reflected to output pin
CK1_BAD_PIN CK1_BAD_PIN.
The CK1_BAD status can be reflected on the C1B output pin.
0: C1B output pin tristated
1: C1B status reflected to output pin
LOL_PIN
INT_PIN
LOL_PIN.
The LOL_INT status bit can be reflected on the LOL output pin.
0: LOL output pin tristated
1: LOL_INT status reflected to output pin
INT_PIN.
Reflects the interrupt status on the INT output pin.
0: Interrupt status not displayed on INT output pin. If ALRMOUT_PIN = 0, output pin is
tristated.
1: Interrupt status reflected to output pin. ALRMOUT_PIN ignored.
Rev. 1.0
37
Si5369
Register 21.
Bit
D7 D6 D5
D4
D3
D2
D1
D0
Name
Type
CK4_ACTV_PIN CK3_ACTV_PIN CK2_ACTV_PIN CK1_ACTV_PIN CKSEL_ PIN
R
R
R
R/W
R/W
R/W
R/W
R/W
Reset value = 1111 1111
Bit
7:5
4
Name
Function
Reserved
CK4_ACTV_PIN
CK4_ACTV_PIN.
If the CKSEL[1]/CK4_ACTV pin is functioning as the CK4_ACTV output (see
CKSEL[1]/CK4_ACTV pin description on CK4_ACTV), the CK4_ACTV_REG sta-
tus bit can be reflected to the CK4_ACTV output pin using the CK4_ACTV_PIN
enable function.
0: CK4_ACTV output pin tristated
1: CK4_ACTV status reflected to output pin.
3
2
CK3_ACTV_PIN
CK2_ACTV_PIN
CK3_ACTV_PIN.
If the CKSEL[0]/CK3_ACTV pin is functioning as the CK3_ACTV output (see
CKSEL[0]/CK3_ACTV pin description on CK3_ACTV), the CK3_ACTV_REG sta-
tus bit can be reflected to the CK3_ACTV output pin using the CK3_ACTV_PIN
enable function.
0: CK3_ACTV output pin tristated.
1: CK3_ACTV status reflected to output pin.
CK2_ACTV_PIN.
The CK2_ACTV_REG status bit can be reflected to the CK2_ACTV output pin
using the
CK2_ACTV_PIN enable function.
0: CK2_ACTV output pin tristated.
1: CK2_ACTV status reflected to output pin.
1
0
CK1_ACTV_PIN
CKSEL_PIN
CK1_ACTV_PIN.
The CK1_ACTV_REG status bit can be reflected to the CK1_ACTV output pin
using the CK1_ACTV_PIN enable function.
0: CK1_ACTV output pin tristated.
1: CK1_ACTV status reflected to output pin.
CKSEL_PIN.
If manual clock selection is being used, clock selection can be controlled via the
CKSEL_REG[1:0] register bits or the CKSEL[1:0] input pins. The CKx_ACTV_PIN
bits in this register are of consequence only when CKSEL_PIN is 1.
0: CKSEL pins ignored. CKSEL_REG[1:0] register bits control clock selection.
1: CKSEL[1:0] input pins controls clock selection.
38
Rev. 1.0
Si5369
Register 22.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
CK_ACTV_POL CK_BAD_ POL LOL_POL INT_POL
R/W R/W R/W R/W
R
R
R
R
Reset value = 1101 1111
Bit
7:4
3
Name
Function
Reserved
CK_ACTV_ POL CK_ACTV_POL.
Sets the active polarity for the CK1_ACTV, CK2_ACTV, CK3_ACTV, and CK4_ACTV
signals when reflected on an output pin.
0: Active low
1: Active high
2
CK_BAD_ POL CK_BAD_POL.
Sets the active polarity for the C1B, C2B, C3B, and ALRMOUT signals when reflected
on output pins.
0: Active low
1: Active high
1
0
LOL_POL
INT_POL
LOL_POL.
Sets the active polarity for the LOL status when reflected on an output pin.
0: Active low
1: Active high
INT_POL.
Sets the active polarity for the interrupt status when reflected on the INT_ALM output
pin.
0: Active low
1: Active high
Rev. 1.0
39
Si5369
Register 23.
Bit
D7
D6
D5
D4
LOS4_MSK
R/W
D3
LOS3_MSK
R/W
D2
LOS2_ MSK
R/W
D1
LOS1_ MSK
R/W
D0
LOSX_ MSK
R/W
Name
Type
R
R
R
Reset value = 0001 1111
Bit
7:5
4
Name
Function
Reserved
LOS4_MSK LOS4_MSK.
Determines if a LOS on CKIN4 (LOS4_FLG) is used in the generation of an interrupt.
Writes to this register do not change the value held in the LOS4_FLG register.
0: LOS4 alarm triggers active interrupt on INT output (if INT_PIN=1).
1: LOS4_FLG ignored in generating interrupt output.
3
2
1
0
LOS3_MSK LOS3_MSK.
Determines if a LOS on CKIN3 (LOS3_FLG) is used in the generation of an interrupt.
Writes to this register do not change the value held in the LOS3_FLG register.
0: LOS3 alarm triggers active interrupt on INT output (if INT_PIN=1).
1: LOS3_FLG ignored in generating interrupt output.
LOS2_MSK LOS2_MSK.
Determines if a LOS on CKIN2 (LOS2_FLG) is used in the generation of an interrupt.
Writes to this register do not change the value held in the LOS2_FLG register.
0: LOS2 alarm triggers active interrupt on INT output (if INT_PIN=1).
1: LOS2_FLG ignored in generating interrupt output.
LOS1_MSK LOS1_MSK.
Determines if a LOS on CKIN1 (LOS1_FLG) is used in the generation of an interrupt.
Writes to this register do not change the value held in the LOS1_FLG register.
0: LOS1 alarm triggers active interrupt on INT output (if INT_PIN=1).
1: LOS1_FLG ignored in generating interrupt output.
LOSX_MSK LOSX_MSK.
Determines if a LOS on XA/XB(LOSX_FLG) is used in the generation of an interrupt.
Writes to this register do not change the value held in the LOSX_FLG register.
0: LOSX alarm triggers active interrupt on INT output (if INT_PIN=1).
1: LOSX_FLG ignored in generating interrupt output.
40
Rev. 1.0
Si5369
Register 24.
Bit
D7
D6
D5
D4
FOS4_MSK FOS3_MSK
R/W R/W
D3
D2
FOS2_MSK
R/W
D1
FOS1_MSK
R/W
D0
LOL_MSK
R/W
Name
Type
R
R
R
Reset value = 0011 1111
Bit
7:5
4
Name
Function
Reserved
FOS4_MSK FOS4_MSK.
Determines if the FOS4_FLG is used to in the generation of an interrupt. Writes to this
register do not change the value held in the FOS4_FLG register.
0: FOS4 alarm triggers active interrupt on INToutput (if INT_PIN = 1).
1: FOS4_FLG ignored in generating interrupt output.
3
2
1
0
FOS3_MSK FOS3_MSK.
Determines if the FOS3_FLG is used in the generation of an interrupt. Writes to this
register do not change the value held in the FOS3_FLG register.
0: FOS3 alarm triggers active interrupt on INT output (if INT_PIN = 1).
1: FOS3_FLG ignored in generating interrupt output.
FOS2_MSK FOS2_MSK.
Determines if the FOS2_FLG is used in the generation of an interrupt. Writes to this reg-
ister do not change the value held in the FOS2_FLG register.
0: FOS2 alarm triggers active interrupt on INT output (if INT_PIN = 1).
1: FOS2_FLG ignored in generating interrupt output.
FOS1_MSK FOS1_MSK.
Determines if the FOS1_FLG is used in the generation of an interrupt. Writes to this reg-
ister do not change the value held in the FOS1_FLG register.
0: FOS1 alarm triggers active interrupt on INT output (if INT_PIN = 1).
1: FOS1_FLG ignored in generating interrupt output.
LOL_MSK
LOL_MSK.
Determines if the LOL_FLG is used in the generation of an interrupt. Writes to this regis-
ter do not change the value held in the LOL_FLG register.
0: LOL alarm triggers active interrupt on INT output (if INT_PIN = 1).
1: LOL_FLG ignored in generating interrupt output.
Rev. 1.0
41
Si5369
Register 25.
Bit
D7
D6
N1_HS [2:0]
R/W
D5
D4
D3
D2
D1
D0
Name
Type
NC1_LS [19:16]
R/W
R
Reset value = 0010 0000
Bit
Name
Function
7:5
N1_HS [2:0]
N1_HS [2:0].
Sets value for N1 high speed divider which drives NCn_LS (n = 1 to 4) low-speed
divider.
000: N1 = 4 Note: Changing the coarse skew via the INC pin is disabled for this value.
001: N1 = 5
010: N1 = 6
011: N1 = 7
100: N1 = 8
101: N1 = 9
110: N1 = 10
111: N1 = 11
4
Reserved
3:0
NC1_LS [19:16] NC1_LS [19:0].
Sets value for NC1 low-speed divider, which drives CKOUT1 output. Must be 0 or odd.
00000000000000000000 = 1
00000000000000000001 = 2
00000000000000000011 = 4
00000000000000000101 = 6
...
20
11111111111111111111 = 2
20
Valid divider values=[1, 2, 4, 6, ..., 2 ].
Register 26.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
NC1_LS [15:8]
R/W
Reset value = 0000 0000
Bit
Name
Function
7:0
NC1_LS [15:8] NC1_LS [15:8].
See Register 25.
42
Rev. 1.0
Si5369
Register 27.
Bit
D7
D6
D5
D4
NC1_LS [7:0]
R/W
D3
D2
D1
D0
Name
Type
Reset value = 0011 0001
Bit
Name
NC1_LS [7:0] NC1_LS [7:0].
See Register 25.
Function
7:0
Register 28.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
NC2_LS [19:16]
R/W
R
R
R
R
Reset value = 0000 0000
Bit
7:4
3:0
Name
Function
Reserved
NC1_LS [19:0] NC2_LS [19:16].
Sets value for NC2 low-speed divider, which drives CKOUT2 output. Must be 0 or odd.
00000000000000000000 = 1
00000000000000000001 = 2
00000000000000000011 = 4
00000000000000000101 = 6
...
20
11111111111111111111 = 2
20
Valid divider values = [1, 2, 4, 6, ..., 2 ]
Rev. 1.0
43
Si5369
Register 29.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
NC2_LS [15:8]
R/W
Type
Reset value = 0000 0000
Bit
Name
Function
7:0
NC2_LS [15:8] NC2_LS [15:8].
See Register 28.
Register 30.
Bit
D7
D6
D5
D4
NC2_LS [7:0]
R/W
D3
D2
D1
D0
Name
Type
Reset value = 0011 0001
Bit
Name
NC2_LS [7:0] NC2_LS [7:0].
See Register 28.
Function
7:0
44
Rev. 1.0
Si5369
Register 31.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
NC3_LS [19:16]
R/W
R
R
R
R
Reset value = 0000 0000
Bit
7:4
3:0
Name
Function
Reserved
NC3_LS [19:0] NC3_LS [19:0.
Sets value for NC3 low-speed divider, which drives CKOUT3 output. Must be 0 or odd.
00000000000000000000 = 1
00000000000000000001 = 2
000000000000000000011 = 4
000000000000000000101 = 6
...
20
11111111111111111111 = 2
20
Valid divider values = [1, 2, 4, 6, ..., 2 ].
Register 32.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
NC3_LS [15:8]
R/W
Reset value = 0000 0000
Bit
Name
Function
7:0
NC3_LS [15:8] NC3_LS [15:8].
See Register 31.
Rev. 1.0
45
Si5369
Register 33.
Bit
D7
D6
D5
D4
NC3_LS [7:0]
R/W
D3
D2
D1
D0
Name
Type
Reset value = 0011 0001
Bit
Name
NC3_LS [7:0] NC3_LS [7:0].
See Register 31.
Function
7:0
Register 34.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
NC4_LS [19:16]
R/W
R
R
R
R
Reset value = 0000 0000
Bit
7:4
3:0
Name
Function
Reserved
NC4_LS [19:0] NC4_LS [19:0].
Sets value for NC4 low-speed divider, which drives CKOUT4 output. Must be 0 or odd.
00000000000000000000 = 1
00000000000000000001 = 2
000000000000000000011 = 4
000000000000000000101 = 6
...
20
11111111111111111111 = 2
20
Valid divider values = [1, 2, 4, 6, ..., 2 ].
46
Rev. 1.0
Si5369
Register 35.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
NC4_LS [15:8]
R/W
Reset value = 0000 0000
Bit
Name
Function
7:0
NC4_LS [15:8] NC4_LS [15:8].
See Register 34.
Register 36.
Bit
D7
D6
D5
D4
NC4_LS [7:0]
R/W
D3
D2
D1
D0
Name
Type
Reset value = 0011 0001
Bit
Name
NC4_LS [7:0] NC4_LS [7:0].
See Register 34.
Function
7:0
Rev. 1.0
47
Si5369
Register 37.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
NC5_LS [19:16]
R/W
R
R
R
R
Reset value = 0000 0000
Bit
7:4
3:0
Name
Function
Reserved
NC5_LS [19:0] NC5_LS [19:0].
Sets value for NC5 low-speed divider, which drives CKOUT5 output. Must be 0 or odd.
When CK_CONFIG=0:
00000000000000000000 = 1
00000000000000000001 = 2
000000000000000000011 = 4
000000000000000000101 = 6
...
20
11111111111111111111 = 2
20
Valid divider values = [1, 2, 4, 6, ..., 2 ].
When CK_CONFIG = 1, maximum value limited to 2 .:
19
00000000000000000000 = 1
00000000000000000001 = 2
000000000000000000011 = 4
000000000000000000101 = 6
...
19
01111111111111111111 = 2
19
Valid divider values = [1, 2, 4, 6, ..., 2 ].
Register 38.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
NC5_LS [15:8]
R/W
Reset value = 0000 0000
Bit
Name
Function
7:0
NC5_LS [15:8] NC5_LS [15:8].
See Register 37.
48
Rev. 1.0
Si5369
Register 39.
Bit
D7
D6
D5
D4
NC5_LS [7:0]
R/W
D3
D2
D1
D0
Name
Type
Reset value = 0011 0001
Bit
Name
NC5_LS [7:0] NC5_LS [7:0].
See Register 37.
Function
7:0
Register 40.
Bit
D7
D6
N2_HS [2:0]
R/W
D5
D4
D3
D2
D1
D0
Name
Type
N2_LS [19:16]
R/W
R
Reset value = 1100 0000
Bit
Name
Function
7:5
N2_HS [2:0] N2_HS [2:0].
Sets value for N2 high speed divider which drives NCn_LS (n = 1 to 4) low-speed divider.
000:4
001:5
010:6
011:7
100:8
101:9
110:10
111:11.
4
Reserved
3:0 N2_LS [19:16] NC2_LS [19:0].
Sets value for N2 low-speed divider, which drives phase detector.
00000000000000000001 = 2
000000000000000000011 = 4
000000000000000000101 = 6
...
20
11111111111111111111 = 2
20
Valid divider values = [2, 4, 6, ..., 2 ].
Rev. 1.0
49
Si5369
Register 41.
Bit
D7
D6
D5
D4
N2_LS [15:8]
R/W
D3
D2
D2
D2
D1
D0
D0
D0
Name
Type
Reset value = 0000 0000
Bit
Name
N2_LS [15:8] N2_LS [15:8].
See Register 40.
Function
7:0
Register 42.
Bit
D7
D6
D5
D4
D3
D1
Name
Type
N2_LS [7:0]
R/W
Reset value = 1111 1001
Bit
Name
Function
7:0
N2_LS [7:0] N2_LS [7:0].
See Register 40.
Register 43.
Bit
D7
D6
D5
D4
D3
D1
N31 [18:16]
R/W
Name
Type
R
R
R
R
R
Reset value = 0000 0000
Bit
7:3
2:0
Name
Function
Reserved
N31 [18:0]
N31 [18:0].
Sets value for input divider for CKIN1.
0000000000000000000 = 1
0000000000000000001 = 2
0000000000000000010 = 3
...
19
1111111111111111111 = 2
19
Valid divider values=[1, 2, 3, ..., 2 ].
50
Rev. 1.0
Si5369
Register 44.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
N31 [15:8]
R/W
Reset value = 0000 0000
Bit
Name
Function
7:0
N31 [15:8]
N31 [15:8].
See Register 43.
Register 45.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
N31 [7:0]
R/W
Reset value = 0000 1001
Bit
Name
Function
7:0
N31 [7:0]
N31 [7:0].
See Register 43.
Rev. 1.0
51
Si5369
Register 46.
Bit
D7
D6
D5
D4
D3
D2
D1
N32_[18:16]
R/W
D0
Name
Type
R
R
R
R
R
Reset value = 0000 0000
Bit
7:3
2:0
Name
Function
Reserved
N32_[18:0] N32_[18:0].
Sets value for input divider for CKIN2.
0000000000000000000 = 1
0000000000000000001 = 2
0000000000000000010 = 3
...
19
1111111111111111111 = 2
19
Valid divider values=[1, 2, 3, ..., 2 ].
Register 47.
Bit
D7
D6
D5
D4
N32_[15:8]
R/W
D3
D2
D1
D0
Name
Type
Reset value = 0000 0000
Bit
Name
N32_[15:8] N32_[15:8].
See Register 46.
Function
7:0
52
Rev. 1.0
Si5369
Register 48.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
N32_[7:0]
R/W
Reset value = 0000 1001
Bit
Name
Function
7:0
N32_[7:0]
N32_[7:0].
See Register 46.
Register 49.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
N33_[18:0]
R/W
R
R
R
R
R
Reset value = 0000 0000
Bit
Name
N33_[18:0] N33_[18:0].
Function
18:0
Sets value for input divider for CKIN3.
0000000000000000000 = 1
0000000000000000001 = 2
0000000000000000010 = 3
...
19
1111111111111111111 = 2
19
Valid divider values=[1, 2, 3, ..., 2 ].
Rev. 1.0
53
Si5369
Register 50.
Bit
D7
D6
D5
D4
N33_[15:8]
R/W
D3
D2
D1
D0
Name
Type
Reset value = 0000 0000
Bit
Name
N33_[15:8] N33_[15:8].
See Register 49.
Function
7:0
Register 51.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
N33_[7:0]
R/W
Reset value = 0000 1001
Bit
Name
Function
7:0
N33_[7:0]
N33_[7:0].
See Register 49.
54
Rev. 1.0
Si5369
Register 52.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
N34_[18:16]
R/W
R
R
R
R
R
Reset value = 0000 0000
Bit
7:3
2:0
Name
Function
Reserved
N34_[18:0] N34_[18:0].
Sets value for input divider for CKIN4.
0000000000000000000 = 1
0000000000000000001 = 2
0000000000000000010 = 3
...
19
1111111111111111111 = 2
19
Valid divider values=[1, 2, 3, ..., 2 ].
Register 53.
Bit
D7
D6
D5
D4
N34_[15:8]
R/W
D3
D2
D1
D0
Name
Type
Reset value = 0000 0000
Bit
Name
N34_[15:8] N34_[15:8].
See Register 52.
Function
7:0
Rev. 1.0
55
Si5369
Register 54.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
N34_[7:0]
R/W
Reset value = 0000 1001
Bit
Name
N34_[15:8] N34_[7:0].
See Register 52.
Function
7:0
Register 55.
Bit
D7
D6
D5
D4
D3
D2
D1
CLKIN1RATE[2:0]
R/W
D0
Name
Type
CLKIN2RATE_[2:0]
R/W
R
R
Reset value = 0000 0000
Bit
7:6
5:3
Name
Function
Reserved
CLKIN2RATE[2:0] CLKIN2RATE[2:0].
CKINn frequency selection for FOS alarm monitoring.
000: 10–27 MHz
001: 25–54 MHz
002: 50–105 MHz
003: 95–215 MHz
004: 190–435 MHz
005: 375–710 MHz
006: Reserved
007: Reserved
2:0 CLKIN1RATE [2:0] CLKIN1RATE[2:0].
CKINn frequency selection for FOS alarm monitoring.
000: 10–27 MHz
001: 25–54 MHz
002: 50–105 MHz
003: 95–215 MHz
004: 190–435 MHz
005: 375–710 MHz
006: Reserved
007: Reserved
56
Rev. 1.0
Si5369
Register 56.
Bit
D7
D6
D5
D4
CLKIN4RATE_[2:0]
R/W
D3
D2
D1
D0
Name
Type
CLKIN3RATE[2:0]
R/W
R
R
Reset value = 0000 0000
Bit
7:6
5:3
Name
Function
Reserved
CLKIN4RATE[2:0] CLKIN4RATE[2:0].
CKINn frequency selection for FOS alarm monitoring.
000: 10–27 MHz
001: 25–54 MHz
002: 50–105 MHz
003: 95–215 MHz
004: 190–435 MHz
005: 375–710 MHz
006: Reserved
007: Reserved
2:0 CLKIN3RATE [2:0] CLKIN3RATE[2:0].
CKINn frequency selection for FOS alarm monitoring.
000: 10–27 MHz
001: 25–54 MHz
002: 50–105 MHz
003: 95–215 MHz
004: 190–435 MHz
005: 375–710 MHz
006: Reserved
007: Reserved
Rev. 1.0
57
Si5369
Register 128.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
CK4_ACTV_REG CK3_ACTV_REG CK2_ACTV_REG CK1_ACTV_REG
R
R
R
R
R
R
R
R
Reset value = 0010 0000
Bit
7:4
3
Name
Function
Reserved
CK4_ACTV_REG CK4_ACTV_REG.
Indicates if CKIN4 is currently the active clock for the PLL input.
0: CKIN4 is not the active input clock. Either it is not selected or LOS4_INT is 1.
1: CKIN_4 is the active input clock.
2
1
0
CK3_ACTV_REG CK3_ACTV_REG.
Indicates if CKIN3 is currently the active clock for the PLL input.
0: CKIN3 is not the active input clock - either it is not selected or LOS3_INT is 1.
1: CKIN3 is the active input clock.
CK2_ACTV_REG CK2_ACTV_REG.
Indicates if CKIN2 is currently the active clock for the PLL input.
0: CKIN2 is not the active input clock. Either it is not selected or LOS2_INT is 1.
1: CKIN2 is the active input clock.
CK1_ACTV_REG CK1_ACTV_REG.
Indicates if CKIN1 is currently the active clock for the PLL input.
0: CKIN1 is not the active input clock. Either it is not selected or LOS1_INT is 1.
1: CKIN1 is the active input clock.
58
Rev. 1.0
Si5369
Register 129.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
LOS4_INT LOS3_INT
Name
Type
LOS2_INT LOS1_INT LOSX_INT
R
R
R
R
R
R
R
R
Reset value = 0001 1110
Bit
7:5
4
Name
Function
Reserved
LOS4_INT LOS4_INT.
Indicates the LOS status on CKIN4.
0: Normal operation.
1: Internal loss-of-signal alarm on CKIN4 input.
3
2
1
0
LOS3_INT LOS3_INT.
Indicates the LOS status on CKIN3.
0: Normal operation.
1: Internal loss-of-signal alarm on CKIN3 input.
LOS2_INT LOS2_INT.
Indicates the LOS status on CKIN2.
0: Normal operation.
1: Internal loss-of-signal alarm on CKIN2 input.
LOS1_INT LOS1_INT.
Indicates the LOS status on CKIN1.
0: Normal operation.
1: Internal loss-of-signal alarm on CKIN1 input.
LOSX_INT LOSX_INT.
Indicates the LOS status of the external reference on the XA/XB pins.
0: Normal operation.
1: Internal loss-of-signal alarm on XA/XB reference clock input.
Rev. 1.0
59
Si5369
Register 130.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
LOL_INT
R
Name
Type
DIGHOLDVALID
R
FOS4_INT FOS3_INT FOS2_INT FOS1_INT
R
R
R
R
R
R
Reset value = 0000 0001
Bit
7
Name
Function
Reserved
6
DIGHOLDVALID Digital Hold Valid.
Indicates if the digital hold circuit has enough samples of a valid clock to meet digital
hold specifications.
0: Indicates digital filter has not been filled. The digital hold output frequency (from the
filter) is not valid.
1: Indicates digital hold filter has been filled. The digital hold output frequency is valid.
5
4
Reserved
FOS4_INT
FOS4_INT.
CKIN4 Frequency Offset Status.
0: Normal operation.
1: Internal frequency offset alarm on CKIN4 input.
3
2
1
0
FOS3_INT
FOS2_INT
FOS1_INT
LOL_INT
FOS3_INT.
CKIN3 Frequency Offset Status.
0: Normal operation.
1: Internal frequency offset alarm on CKIN3 input.
FOS2_INT.
CKIN2 Frequency Offset Status.
0: Normal operation.
1: Internal frequency offset alarm on CKIN2 input.
FOS1_INT.
CKIN1 Frequency Offset Status.
0: Normal operation.
1: Internal frequency offset alarm on CKIN1 input.
LOL_INT.
PLL Loss of Lock Status.
0: PLL locked.
1: PLL unlocked.
60
Rev. 1.0
Si5369
Register 131.
Bit
D7
D6
D5
D4
LOS4_FLG
R/W
D3
LOS3_FLG
R/W
D2
LOS2_FLG
R/W
D1
LOS1_FLG
R/W
D0
LOSX_FLG
R/W
Name
Type
R
R
R
Reset value = 0001 1111
Bit
7:5
4
Name
Function
Reserved
LOS4_FLG LOS4_FLG.
CKIN4 Loss-of-Signal Flag.
0: Normal operation.
1: Held version of LOS4_INT. Generates active output interrupt if output interrupt pin is
enabled (INT_PIN=1) and if not masked by LOS4_MSK bit. Flag cleared by writing
location to 0.
3
2
1
0
LOS3_FLG LOS3_FLG.
CKIN3 Loss-of-Signal Flag.
0: Normal operation.
1: Held version of LOS3_INT. Generates active output interrupt if output interrupt pin is
enabled (INT_PIN=1) and if not masked by LOS3_MSK bit. Flag cleared by writing
location to 0.
LOS2_FLG LOS2_FLG.
CKIN2 Loss-of-Signal Flag.
0: Normal operation.
1: Held version of LOS2_INT. Generates active output interrupt if output interrupt pin is
enabled (INT_PIN=1) and if not masked by LOS2_MSK bit. Flag cleared by writing
location to 0.
LOS1_FLG LOS1_FLG.
CKIN1 Loss-of-Signal Flag.
0: Normal operation.
1: Held version of LOS1_INT. Generates active output interrupt if output interrupt pin is
enabled (INT_PIN=1) and if not masked by LOS1_MSK bit. Flag cleared by writing
location to 0.
LOSX_FLG LOSX_FLG.
External reference (signal on pins XA/XB) Loss-of-Signal Flag.
0: Normal operation.
1: Held version of LOSX_INT. Generates active output interrupt if output interrupt pin is
enabled (INT_PIN=1) and if not masked by LOSX_MSK bit. Flag cleared by writing
location to 0.
Rev. 1.0
61
Si5369
Register 132.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
FOS4_FLG FOS3_FLG FOS2_FLG FOS1_FLG LOL_FLG
R
R
R/W
R/W
R/W
R/W
R/W
R
Reset value = 0000 0010
Bit
7:6
5
Name
Function
Reserved
FOS4_FLG FOS4_FLG.
CLKIN_4 Frequency Offset Flag.
0: Normal operation.
1: Held version of FOS4_INT. Generates active output interrupt if output interrupt pin is
enabled (INT_PIN=1) and if not masked by FOS4_MSK bit. Flag cleared by writing
location to 0.
4
3
2
1
0
FOS3_FLG FOS3_FLG.
CLKIN_3 Frequency Offset Flag.
0: Normal operation.
1: Held version of FOS3_INT. Generates active output interrupt if output interrupt pin is
enabled (INT_PIN=1) and if not masked by FOS3_MSK bit. Flag cleared by writing
location to 0.
FOS2_FLG FOS2_FLG.
CLKIN_2 Frequency Offset Flag.
0: Normal operation.
1: Held version of FOS2_INT. Generates active output interrupt if output interrupt pin is
enabled (INT_PIN = 1) and if not masked by FOS2_MSK bit. Flag cleared by writing
location to 0.
FOS1_FLG FOS1_FLG.
CLKIN_1 Frequency Offset Flag.
0: Normal operation.
1: Held version of FOS1_INT. Generates active output interrupt if output interrupt pin is
enabled (INT_PIN = 1) and if not masked by FOS1_MSK bit. Flag cleared by writing
location to 0.
LOL_FLG
Reserved
LOL_FLG.
PLL Loss of Lock Flag.
0: PLL locked
1: Held version of LOL_INT. Generates active output interrupt if output interrupt pin is
enabled (INT_PIN = 1) and if not masked by LOL_MSK bit. Flag cleared by writing
location to 0.
62
Rev. 1.0
Si5369
Register 134.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
PARTNUM_RO [11:4]
R
Reset value = 0000 0100
Bit
Name
Function
7:0
PARTNUM_RO [11:0] PARTNUM_RO [11:0].
Device ID:
0000 0100 0100'b=Si5369
Register 135.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
PARTNUM_RO [3:0]
R
REVID_RO [3:0]
R
Type
Reset value = 0100 0010
Bit
Name
Function
7:4
PARTNUM_RO [3:0] PARTNUM_RO [3:0].
See Register 134.
3:0
REVID_RO [3:0]
REVID_RO [3:0].
Indicates revision number of device.
0000: Revision A
0001: Revision B
0010: Revision C
Other codes: Reserved
Rev. 1.0
63
Si5369
Register 136.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name RST_REG
ICAL
R/W
Type
R/W
R
R
R
R
R
R
Reset value = 0000 0000
Bit
Name
Function
7
RST_REG
RST_REG.
Internal Reset.
0: Normal operation.
1: Reset of all internal logic. Outputs tristated or disabled during reset.
6
ICAL
ICAL.
Start an Internal Calibration Sequence.
For proper operation, the device must go through an internal calibration sequence. ICAL
is a self-clearing bit. Writing a one to this location initiates an ICAL. The calibration is
complete once the LOL alarm goes low. A valid stable clock (within 100 ppm) must be
present to begin ICAL.
Note: Any divider, CLKINn_RATE or BWSEL_REG changes require an ICAL to take effect.
Changes in SFOUTn_REG, PD_CKn, or DSBLn_REG will cause a random change in skew
until an ICAL is completed.
0: Normal operation.
1: Writing a "1" initiates internal self-calibration. Upon completion of internal self-
calibration, ICAL is internally reset to zero.
5:0
Reserved
64
Rev. 1.0
Si5369
Register 137.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
FASTLOCK
R/W
Name
Type
R
R
R
R
R
R
R
Reset value = 0000 0000
Bit
7:1
0
Name
Function
Reserved
FASTLOCK
Do not modify.
This bit must be set to 1 to enable FASTLOCK. This improves initial lock time by
dynamically changing the loop bandwidth.
Register 138.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
LOS4_EN[1:1] LOS3_EN[1:1] LOS2_EN[1:1] LOS1_EN [1:1]
R
R
R
R
R/W
R/W
R/W
R/W
Reset value = 0000 1111
Bit
7:4
3
Name
Function
Reserved
LOS4_EN [1:0] LOS4_EN [1:0].
Note: LOS1_EN is split between two registers.
00: Disable LOS monitoring.
01: Reserved.
10: Enable LOSA monitoring.
11: Enable LOS monitoring.
LOSA is a slower and less sensitive version of LOS. See the Family Reference Man-
ual for details.
2
LOS3_EN [1:0] LOS3_EN [1:0].
Note: LOS1_EN is split between two registers.
00: Disable LOS monitoring.
01: Reserved.
10: Enable LOSA monitoring.
11: Enable LOS monitoring.
LOSA is a slower and less sensitive version of LOS. See the Family Reference Man-
ual for details.
Rev. 1.0
65
Si5369
1
LOS2_EN [1:0] LOS2_EN [1:0].
Note: LOS1_EN is split between two registers.
00: Disable LOS monitoring.
01: Reserved.
10: Enable LOSA monitoring.
11: Enable LOS monitoring.
LOSA is a slower and less sensitive version of LOS. See the Family Reference Man-
ual for details.
0
LOS1_EN [1:0] LOS1_EN [1:0].
Note: LOS1_EN is split between two registers.
00: Disable LOS monitoring.
01: Reserved.
10: Enable LOSA monitoring.
11: Enable LOS monitoring.
LOSA is a slower and less sensitive version of LOS. See the Family Reference Man-
ual for details.
66
Rev. 1.0
Si5369
Register 139.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name LOS4_EN [0:0] LOS3_EN [0:0] LOS2_EN [0:0] LOS1_EN [0:0] FOS4_EN FOS3_EN FOS2_EN FOS1_EN
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset value = 1111 1111
Bit
Name
LOS4_EN [0:0] LOS4_EN [0:0].
Function
7
Enable CKIN1 LOS Monitoring on the Specified Input (1 of 2).
Note: LOS1_EN is split between two registers.
00: Disable LOS monitoring.
01: Reserved.
10: Enable LOSA monitoring.
11: Enable LOS monitoring.
LOSA is a slower and less sensitive version of LOS. See the family reference manual
for details.
6
5
4
LOS3_EN [0:0] LOS3_EN [0:0].
Enable CKIN1 LOS Monitoring on the Specified Input (1 of 2).
Note: LOS1_EN is split between two registers.
00: Disable LOS monitoring.
01: Reserved.
10: Enable LOSA monitoring.
11: Enable LOS monitoring.
LOSA is a slower and less sensitive version of LOS. See the family reference manual
for details.
LOS2_EN [0:0] LOS2_EN.
Enable CKIN1 LOS Monitoring on the Specified Input (1 of 2).
Note: LOS1_EN is split between two registers.
00: Disable LOS monitoring.
01: Reserved.
10: Enable LOSA monitoring.
11: Enable LOS monitoring.
LOSA is a slower and less sensitive version of LOS. See the family reference manual
for details.
LOS1_EN [0:0] LOS1_EN [0:0].
Enable CKIN1 LOS Monitoring on the Specified Input (1 of 2).
Note: LOS1_EN is split between two registers.
00: Disable LOS monitoring.
01: Reserved.
10: Enable LOSA monitoring.
11: Enable LOS monitoring.
LOSA is a slower and less sensitive version of LOS. See the family reference manual
for details.
Rev. 1.0
67
Si5369
Bit
Name
Function
3
FOS4_EN
FOS3_EN
FOS2_EN
FOS1_EN
FOS4_EN.
Enables FOS on a Per Channel Basis.
0: Disable FOS monitoring.
1: Enable FOS monitoring.
2
1
0
FOS3_EN.
Enables FOS on a Per Channel Basis.
0: Disable FOS monitoring.
1: Enable FOS monitoring.
FOS2_EN.
Enables FOS on a Per Channel Basis.
0: Disable FOS monitoring.
1: Enable FOS monitoring.
FOS1_EN.
Enables FOS on a Per Channel Basis.
0: Disable FOS monitoring.
1: Enable FOS monitoring.
Register 140.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
INDEPENDENTSKEW1[7:0]
R/W
Type
Reset value = 0000 0000
Bit
Name
INDEPENDENTSKEW1[7:0] INDEPENDENTSKEW1 [7:0].
Function
7:0
8 bit field that represents a twos complement of the phase offset in
terms of clocks from the high speed output divider.
68
Rev. 1.0
Si5369
Register 141.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
INDEPENDENTSKEW2[7:0]
R/W
Type
Reset value = 0000 0001
Bit
Name
INDEPENDENTSKEW2[7:0] INDEPENDENTSKEW2.
Function
7:0
8 bit field that represents a twos complement of the phase offset in terms
of clocks from the high speed output divider.
Register 142.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
INDEPENDENTSKEW3 [7:0]
R/W
Type
Reset value = 0000 0000
Bit
Name
INDEPENDENTSKEW3[7:0] INDEPENDENTSKEW3 .
Function
7:0
8 bit field that represents a twos complement of the phase offset in terms
of clocks from the high speed output divider.
Register 143.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
INDEPENDENTSKEW4[7:0]
R/W
Type
Reset value = 0000 0000
Bit
Name
INDEPEND-ENTSKEW4[7:0] INDEPENDENTSKEW4.
Function
7:0
8 bit field that represents a twos complement of the phase offset in terms
of clocks from the high speed output divider.
Rev. 1.0
69
Si5369
Register 144.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
INDEPENDENTSKEW5[7:0]
R/W
Type
Reset value = 0000 0000
Bit
Name
INDEPENDENTSKEW5[7:0] INDEPENDENTSKEW5.
Function
7:0
8 bit field that represents a twos complement of the phase offset in terms
of clocks from the high speed output divider when CK_CONFIG = 0.
70
Rev. 1.0
Si5369
Table 8. CKOUT_ALWAYS_ON and SQICAL Truth Table
CKOUT_ALWAYS_ON SQICAL
Results
Output to Output Skew
Preserved?
0
0
0
1
CKOUT OFF until after the first ICAL
N
Y
CKOUT OFF until after the first successful
ICAL (i.e., when LOL is low)
1
1
0
1
CKOUT always ON, including during an ICAL
CKOUT always ON, including during an ICAL
N
Y
Table 9 lists all of the register locations that should be followed by an ICAL after their contents are changed.
Table 9. Register Locations Requiring ICAL
Addr
Register
0
0
BYPASS_REG
CKOUT_ALWAYS_ON
CK_PRIOR4
CK_PRIOR3
CK_PRIOR2
CK_PRIOR1
BWSEL_REG
HIST_DEL
ICMOS
1
1
1
1
2
4
5
7
FOSREFSEL
HIST_AVG
DSBL5_REG
DSBL4_REG
DSBL3_REG
DSBL2_REG
DSBL1_REG
PD_CK2
9
10
10
10
10
10
11
11
19
19
19
19
25
26
28
31
34
37
PD_CK1
FOS_EN
FOS_THR
VALTIME
LOCKT
N1_HS
NC1_LS
NC2_LS
NC3_LS
NC4_LS
NC5_LS
Rev. 1.0
71
Si5369
Table 9. Register Locations Requiring ICAL
Addr
Register
40
40
43
46
49
51
55
55
56
56
N2_HS
N2_LS
N31
N32
N33
N34
CLKIN2RATE
CLKIN1RATE
CLKIN4RATE
CLKIN3RATE
72
Rev. 1.0
Si5369
6. Pin Descriptions: Si5369
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
75
NC
NC
NC
NC
74
73
2
NC
3
RST
NC
NC
72
71
4
SDI
VDD
5
70
69
A2_SS
6
VDD
A1
A0
NC
GND
GND
7
68
67
8
9
C1B
66
65
NC
10
11
12
13
14
15
C2B
C3B
GND
GND
64
63
INT_ALM
CS0_C3A
GND
VDD
Si5369
62
61
VDD
SDA_SDO
VDD
XA
60
59
SCL
C2A
C1A
16
17
XB
58
57
18
19
20
21
GND
GND
NC
GND PAD
CS1_C4A
NC
56
55
GND
GND
NC
GND
NC
22
23
54
53
NC
NC
NC
52
51
24
25
NC
NC
47
49 50
48
41
42 43 44 45 46
40
36
39
37 38
26 27 28 29 30 31 32 33 34 35
Table 10. Si5369 Pin Descriptions
Pin #
Pin Name
I/O Signal Level
Description
1, 2, 4, 20,
22, 23, 24,
25, 37, 47,
48, 50, 51,
52, 53, 56,
66, 67, 72,
73, 74, 75,
80, 85, 95
3
NC
No Connect.
These pins must be left unconnected for normal operation.
I
LVCMOS External Reset.
RST
Active low input that performs external hardware reset of
device. Resets all internal logic to a known state and forces the
device registers to their default value. Clock outputs are dis-
abled during reset. The part must be programmed after a reset
or power-on to get a clock output. See Family Reference Man-
ual for details.
This pin has a weak pull-up.
Note: Internal register names are indicated by underlined italics, e.g., INT_PIN. See Si5369 Register Map.
Rev. 1.0
73
Si5369
Table 10. Si5369 Pin Descriptions (Continued)
Pin #
Pin Name
I/O Signal Level
Description
5, 6, 15, 27,
62, 63, 76,
79, 81, 84,
86, 89, 91,
94, 96, 99,
100
V
Vdd
Supply
V
.
DD
DD
The device operates from a 1.8, 2.5, or 3.3 V supply. Bypass
capacitors should be associated with the following V pins:
Pins
5, 6
15
DD
Bypass Cap
0.1 µF
0.1 µF
0.1 µF
0.1 µF
1.0 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
27
62, 63
76, 79
81, 84
86, 89
91, 94
96, 99, 100
Ground.
7, 8, 14, 18,
19, 21, 26,
28, 31, 33,
36, 38, 41,
43, 46, 54,
55, 64, 65
9
GND
C1B
GND
Supply
This pin must be connected to system ground. Minimize the
ground path impedance for optimal performance.
O
LVCMOS CKIN1 Invalid Indicator.
This pin performs the CK1_BAD function if CK1_BAD_PIN = 1
and is tristated if CK1_BAD_PIN = 0. Active polarity is con-
trolled by CK_BAD_POL.
0 = No alarm on CKIN1.
1 = Alarm on CKIN1.
10
11
12
C2B
O
LVCMOS CKIN2 Invalid Indicator.
This pin performs the CK2_BAD function if CK2_BAD_PIN = 1
and is tristated if CK2_BAD_PIN = 0. Active polarity is con-
trolled by CK_BAD_POL.
0 = No alarm on CKIN2.
1 = Alarm on CKIN2.
C3B
O
LVCMOS CKIN3 Invalid Indicator.
This pin performs the CK3_BAD function if CK3_BAD_PIN = 1
and is tristated if CK3_BAD_PIN = 0. Active polarity is con-
trolled by CK_BAD_POL.
0 = No alarm on CKIN3.
1 = Alarm on CKIN3.
INT_ALM
O
LVCMOS Interrupt/Alarm Output Indicator.
This pin functions as a maskable interrupt output with active
polarity controlled by the INT_POL register bit. The INT output
function can be turned off by setting INT_PIN = 0. If the ALR-
MOUT function is desired instead on this pin, set
ALRMOUT_PIN = 1 and INT_PIN = 0.
0 = ALRMOUT not active.
1 = ALRMOUT active.
The active polarity is controlled by CK_BAD_POL. If no function
is selected, the pin tristates.
Note: Internal register names are indicated by underlined italics, e.g., INT_PIN. See Si5369 Register Map.
74
Rev. 1.0
Si5369
Table 10. Si5369 Pin Descriptions (Continued)
Pin #
13
57
Pin Name
CS0_C3A
CS1_C4A
I/O Signal Level
Description
I/O
LVCMOS Input Clock Select/CKIN3 or CKIN4 Active Clock Indicator.
Input: If manual clock selection is chosen, and if
CKSEL_PIN = 1, the CKSEL pins control clock selection and
the CKSEL_REG bits are ignored.
CS[1:0]
00
Active Input Clock
CKIN1
01
CKIN2
10
CKIN3
11
CKIN4
If CKSEL_PIN = 0, the CKSEL_REG register bits control this
function and these inputs tristate. If configured as inputs, these
pins must not float.
Output: If auto clock selection is enabled, then they serve as
the CKIN_n active clock indicator.
0 = CKIN3 (CKIN4) is not the active input clock
1 = CKIN3 (CKIN4) is currently the active input to the PLL
The CKn_ACTV_REG bit always reflects the active clock status
for CKIN_n. If CKn_ACTV_PIN = 1, this status will also be
reflected on the CnA pin with active polarity controlled by the
CK_ACTV_POL bit. If CKn_ACTV_PIN = 0, this output tristates.
ANALOG External Crystal or Reference Clock.
External crystal should be connected to these pins to use inter-
nal oscillator based reference. Refer to Family Reference Man-
ual for interfacing to an external reference. External reference
must be from a high-quality clock source (TCXO, OCXO). Fre-
quency of crystal or external clock is set by the RATE pins.
16
17
XA
XB
I
29
30
CKIN4+
CKIN4–
I
I
MULTI
Clock Input 4.
Differential clock input. This input can also be driven with a sin-
gle-ended signal. CKIN4 serves as the frame sync input associ-
ated with the CKIN2 clock when CK_CONFIG_REG = 1.
External Crystal or Reference Clock Rate.
Three level inputs that select the type and rate of external crys-
tal or reference clock to be applied to the XA/XB port. Refer to
the Family Reference Manual for settings. These pins have both
a weak pull-up and a weak pull-down; they default to M.
Clock Input 2.
Differential input clock. This input can also be driven with a sin-
gle-ended signal.
Clock Input 3.
Differential clock input. This input can also be driven with a sin-
gle-ended signal. CKIN3 serves as the frame sync input associ-
ated with the CKIN1 clock when CK_CONFIG_REG = 1.
Clock Input 1.
Differential clock input. This input can also be driven with a sin-
gle-ended signal.
32
42
RATE0
RATE1
3-Level
34
35
CKIN2+
CKIN2–
I
I
MULTI
MULTI
39
40
CKIN3+
CKIN3–
44
45
CKIN1+
CKIN1–
I
MULTI
Note: Internal register names are indicated by underlined italics, e.g., INT_PIN. See Si5369 Register Map.
Rev. 1.0
75
Si5369
Table 10. Si5369 Pin Descriptions (Continued)
Pin #
Pin Name
I/O Signal Level
Description
49
LOL
O
LVCMOS PLL Loss of Lock Indicator.
This pin functions as the active high PLL loss of lock indicator if
the LOL_PIN register bit is set to one.
0 = PLL locked.
1 = PLL unlocked.
If LOL_PIN = 0, this pin will tristate.
Active polarity is controlled by the LOL_POL bit. The PLL lock
status will always be reflected in the LOL_INT read only register
bit.
58
59
C1A
C2A
O
O
LVCMOS CKIN1 Active Clock Indicator.
This pin serves as the CKIN1 active clock indicator. The
CK1_ACTV_REG bit always reflects the active clock status for
CKIN1. If CK1_ACTV_PIN = 1, this status will also be reflected
on the C1A pin with active polarity controlled by the CK_ACT-
V_POL bit. If CK1_ACTV_PIN = 0, this output tristates.
LVCMOS CKIN2 Active Clock Indicator.
This pin serves as the CKIN2 active clock indicator. The
CK2_ACTV_REG bit always reflects the active clock status for
CKIN_2. If CK2_ACTV_PIN = 1, this status will also be reflected
on the C2A pin with active polarity controlled by the CK_ACT-
V_POL bit. If CK2_ACTV_PIN = 0, this output tristates.
60
61
SCL
I
LVCMOS Serial Clock.
This pin functions as the serial port clock input for both SPI and
2
I C modes.
This pin has a weak pull-down.
SDA_SDO
I/O
LVCMOS Serial Data.
2
In I C microprocessor control mode (CMODE = 0), this pin func-
tions as the bidirectional serial data port. In SPI microprocessor
control mode (CMODE = 1), this pin functions as the serial data
output.
68
69
A0
A1
I
I
I
LVCMOS Serial Port Address.
2
In I C microprocessor control mode (CMODE = 0), these pins
function as hardware controlled address bits. The I C address
is 1101 [A2] [A1] [A0]. In SPI microprocessor control mode
(CMODE = 1), these pins are ignored.
This pin has a weak pull-down.
2
70
71
A2_SS
SDI
LVCMOS Serial Port Address/Slave Select.
2
In I C microprocessor control mode (CMODE = 0), this pin func-
tions as a hardware controlled address bit [A2].
In SPI microprocessor control mode (CMODE = 1), this pin
functions as the slave select input.
This pin has a weak pull-down.
LVCMOS Serial Data In.
In SPI microprocessor control mode (CMODE = 1), this pin
functions as the serial data input.
2
In I C microprocessor control mode (CMODE = 0), this pin is
ignored.
This pin has a weak pull-down.
Note: Internal register names are indicated by underlined italics, e.g., INT_PIN. See Si5369 Register Map.
76
Rev. 1.0
Si5369
Table 10. Si5369 Pin Descriptions (Continued)
Pin #
77
78
Pin Name
CKOUT3+
CKOUT3–
I/O Signal Level
Description
O
O
O
MULTI
MULTI
MULTI
Clock Output 3.
Differential clock output. Output signal format is selected by
SFOUT3_REG register bits. Output is differential for LVPECL,
LVDS, and CML compatible modes. For CMOS format, both
output pins drive identical single-ended clock outputs.
Clock Output 1.
Differential clock output. Output signal format is selected by
SFOUT1_REG register bits. Output is differential for LVPECL,
LVDS, and CML compatible modes. For CMOS format, both
output pins drive identical single-ended clock outputs.
Frame Sync Output.
Differential frame sync output or fifth high-speed clock output.
Output signal format is selected by SFOUT_FSYNC_REG reg-
ister bits. Output is differential for LVPECL, LVDS, and CML
compatible modes. For CMOS format, both output pins drive
identical single-ended clock outputs. Duty cycle and active
polarity are controlled by FSYNC_PW and FSYNC_POL bits,
respectively. Detailed operations and timing characteristics for
these pins may be found in the Any-Frequency Precision Clock
Family Reference Manual.
82
83
CKOUT1–
CKOUT1+
87
88
FS_OUT–
FS_OUT+
90
CMODE
I
O
LVCMOS Control Mode.
2
Selects I C or SPI control mode for the device.
2
0 = I C Control Mode.
1 = SPI Control Mode.
This pin must be tied high or low.
92
93
CKOUT2+
CKOUT2–
MULTI
MULTI
Supply
Clock Output 2.
Differential clock output. Output signal format is selected by
SFOUT2_REG register bits. Output is differential for LVPECL,
LVDS, and CML compatible modes. For CMOS format, both
output pins drive identical single-ended clock outputs.
Clock Output 4.
Differential clock output. Output signal format is selected by
SFOUT4_REG register bits. Output is differential for LVPECL,
LVDS, and CML compatible modes. For CMOS format, both
output pins drive identical single-ended clock outputs.
Ground Pad.
97
98
CKOUT4–
CKOUT4+
O
GND PAD
GND PAD
GND
The ground pad must provide a low thermal and electrical
impedance to a ground plane.
Note: Internal register names are indicated by underlined italics, e.g., INT_PIN. See Si5369 Register Map.
Rev. 1.0
77
Si5369
7. Ordering Guide
Ordering Part
Number
Output Clock
Frequency Range
Package
ROHS6, Temperature Range
Pb-Free
Si5369A-C-GQ
2 kHz–945 MHz
970–1134 MHz
1.213–1.417 GHz
100-Pin 14 x 14 mm TQFP
Yes
–40 to 85 °C
Si5369B-C-GQ
Si5369C-C-GQ
Si5369D-C-GQ
2 kHz–808 MHz
2 kHz–346 MHz
2 kHz–243 MHz
100-Pin 14 x 14 mm TQFP
100-Pin 14 x 14 mm TQFP
100-Pin 14 x 14 mm TQFP
Yes
Yes
Yes
–40 to 85 °C
–40 to 85 °C
–40 to 85 °C
Note: Add an R at the end of the device to denote tape and reel options (for example, Si5369D-C-GQ).
78
Rev. 1.0
Si5369
8. Package Outline: 100-Pin TQFP
Figure 9 illustrates the package details for the Si5369. Table 11 lists the values for the dimensions shown in the
illustration.
Figure 9. 100-Pin Thin Quad Flat Package (TQFP)
Table 11. 100-Pin Package Diagram Dimensions
Dimension
Min
—
Nom
—
Max
1.20
0.15
1.05
0.27
0.20
Dimension
Min
Nom
Max
A
E
E1
E2
L
16.00 BSC.
A1
0.05
0.95
0.17
0.09
—
14.00 BSC.
A2
1.00
3.85
0.45
—
4.00
0.60
—
4.15
0.75
0.20
0.20
0.08
0.08
7º
b
0.22
c
D
—
aaa
bbb
ccc
ddd
16.00 BSC.
14.00 BSC.
4.00
—
—
D1
—
—
D2
3.85
4.15
—
—
e
0.50 BSC.
0º
3.5º
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This package outline conforms to JEDEC MS-026, variant AED-HD.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
Rev. 1.0
79
Si5369
9. Recommended PCB Layout
Figure 10. PCB Land Pattern Diagram
80
Rev. 1.0
Si5369
Table 12. PCB Land Pattern Dimensions
Dimension
MIN
MAX
e
E
0.50 BSC.
15.40 REF.
15.40 REF.
D
E2
D2
GE
GD
X
3.90
3.90
13.90
13.90
—
4.10
4.10
—
—
0.30
Y
1.50 REF.
0.15 REF
ZE
ZD
R1
R2
—
—
16.90
16.90
—
1.00
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on IPC-7351 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition
(LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
Solder Mask Design
5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder
mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Stencil Design
6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be
used to assure good solder paste release.
7. The stencil thickness should be 0.125 mm (5 mils).
8. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.
9. A 4 x 4 array of 0.80 mm square openings on 1.05 mm pitch should be used for the center
ground pad.
Card Assembly
10. A No-Clean, Type-3 solder paste is recommended.
11. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for
Small Body Components.
Rev. 1.0
81
Si5369
10. Top Marking
Mark Method:
Logo Size:
Laser
9.2 x 3.1 mm
Center-Justified
Font Size:
3.0 Point (1.07 mm)
Right-Justified
Line 1 Marking:
Line 2 Marking:
Device Part Number
Si5369x-C-GQ
X = Speed Grade
See "7. Ordering Guide" on page 78.
YY = Year
WW = Workweek
Assigned by the Assembly Supplier.
Corresponds to the year and work-
week of the mold date.
R = Die Revision
TTTTT = Mfg Code
Manufacturing Code
“e3” Pb-Free Symbol
Line 3 Marking:
Circle = 1.8 mm Diameter
Center-Justified
Country of Origin
ISO Code Abbreviation
82
Rev. 1.0
Si5369
DOCUMENT CHANGE LIST
Revision 0.1 to Revision 0.4
Updated Table 3, “AC Specifications,” on page 9.
Added table note.
Revision 0.4 to Revision 1.0
Updated " Functional Block Diagram" on page 2.
Updated specification Tables 2, 4, 5, and 6.
Added maximum lock and settle time specs to
Table 3.
Updated Register 21 description.
Updated "10. Top Marking" on page 82.
Added warning about MEMS oscillators to "3.1.
External Reference" on page 21.
Rev. 1.0
83
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Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
USA
http://www.silabs.com
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