SI5380-D_技术文档

Si5380 Rev D Data Sheet

Ultra-Low Phase Noise, 12-output JESD204B Clock Generator

KEY FEATURES

The Si5380 is a high performance, integer-based (M/N) clock generator for small cell

applications which demand the highest level of integration and phase noise perform-

• DSPLL eliminates external VCXO and

analog loop filter components

ance. Based on Silicon Laboratories’ 4^thgeneration DSPLL^™technology, the Si5380

combines frequency synthesis and jitter attenuation in a highly integrated digital solu-

tion that eliminates the need for external VCXO and loop filter components. A low-cost,

fixed-frequency crystal provides frequency stability for free-run and holdover modes.

This all-digital solution provides superior performance that is highly immune to external

board disturbances such as power supply noise.

• Supports JESD204B clocking: DCLK and

SYSREF

• Ultra-low jitter of 65 fs

• Input frequency range:

• External Crystal: 54 MHz

• Differential: 11.52 MHz to 737.28 MHz

• LVCMOS: 11.52 MHz to 245.76 MHz

Applications:

• Output frequency range:

• Differential: 480 kHz to 1.47456 GHz

• JESD204B clock generation

• LVCMOS: 480 kHz to 245.76 MHz

• Status monitoring

• Remote Radio Units (RRU), Remote Access Networks (RAN), picocells, small cells

• Wireless base stations (3G, GSM, W-CDMA, 4G/LTE, LTE-A)

• Remote Radio Head (RRH), wireless repeaters, wireless backhaul

• Data conversion sampling clocks (ADC, DAC, DDC, DUC)

• Hitless switching

• Si5380: 4 input, 12 output, 64-QFN 9×9 mm

54 MHz XTAL

XA

XB

÷INT

OUT0A

OUT0

OUT1

OUT2

OSC

÷INT

Delay

IN0

IN1

IN2

÷INT

DSPLL

4 Input

Clocks

OUT3

OUT4

÷INT

Device and

System Clocks

OUT5

IN3/FB_IN

OUT6

OUT7

OUT8

OUT9

OUT9A

Status Flags

I2C / SPI

Status Monitor

Control

NVM

Si5380

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Si5380 Rev D Data Sheet

Feature List

1. Feature List

The Si5380-D features are listed below:

• Digital frequency synthesis eliminates external VCXO and an-

alog loop filter components

• Adjustable output-output delay: 68 ps/step, ±128 steps

• Optional Zero Delay mode

• Supports JESD204B clocking: DCLK and SYSREF

• Ultra-low jitter:

• Independent output clock supply pins: 3.3, 2.5, or 1.8 V

• Core voltage:

• 65 fs typ (12 kHz to 20 MHz)

• Input frequency range:

• VDD = 1.8 V ±5%

• VDDA = 3.3 V ±5%

• Differential: 11.52 MHz to 737.28 MHz

• LVCMOS: 11.52 MHz to 245.76 MHz

• Output frequency range:

• Automatic free-run, lock, and holdover modes

• Programmable jitter attenuation bandwidth: 0.1 Hz to 100 Hz

• Hitless input clock switching

• Differential: up to 1.47456 GHz

• LVCMOS: up to 245.76 MHz

• Phase noise floor: –159 dBc/Hz

• Status monitoring (LOS, OOF, LOL)

• Serial interface: I2C or SPI In-circuit programmable with non-

volatile OTP memory

• Spur performance: –103 dBc max (relative to a 122.88 MHz

carrier)

ClockBuilder^TMPro software tool simplifies device configura-

tion

•

• Configurable outputs:

• Si5380: 4 input, 12 output, 64-QFN 9×9 mm

• Temperature range: –40 to +85 °C

• Pb-free, RoHS-6 compliant

• Signal swing: 200 to 3200 mVpp

• Compatible with LVDS, LVPECL

• LVCMOS 3.3, 2.5, or 1.8 V

• Output-output skew using same N-divider: 65 ps (Max)

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Si5380 Rev D Data Sheet

Ordering Guide

2. Ordering Guide

Table 2.1. Ordering Guide

Ordering Part Number

Number of

Outputs

Output Clock

Frequency

Range

Package

RoHS-6, Pb-Free

Temperature

Range

Si5380A-D-GM

12

0.480 MHz to

1464.56 MHz

64-Lead 9x9 mm QFN

Evaluation Board

Yes

–40 to +85 °C

Si5380-D-EVB

Note:

1. Add an “R” at the end of the device to denote tape and reel options.

2. Custom, factory pre-programmed devices are available. Ordering part numbers are assigned by ClockBuilder Pro. Part number

format is: Si5380A-Dxxxxx-GM, where “xxxxx” is a unique numerical sequence representing the pre-programmed configuration.

Figure 2.1. Ordering Part Number Fields

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Si5380 Rev D Data Sheet

Functional Description

3. Functional Description

The Si5380 is a high performance clock generator that is capable of synthesizing up to 10 unique integer related frequencies at any of

the device’s 12 outputs. The output clocks can be generated in free-run mode or synchronized to any one of the four external inputs.

Clock generation is provided by Silicon Laboratories’ 4th generation DSPLL technology which combines frequency synthesis and jitter

attenuation in a highly integrated digital solution that eliminates the need for external VCXO and loop filter components. The Si5380

device is fully configurable using the I2C or SPI serial interface and has in-circuit programmable non-volatile memory.

3.1 Frequency Configuration

The DSPLL provides the synthesis for generating the output clock frequencies which are synchronous to the selected input clock fre-

quency or free-running XTAL. It consists of a phase detector, a programmable digital loop filter, a high-performance ultra-low phase

noise analog 15 GHz VCO, and a user configurable feedback divider. An internal oscillator (OSC) provides the DSPLL with a stable

low-noise clock source for frequency synthesis and for maintaining frequency accuracy in the free-run or holdover modes. The oscillator

simply requires an external, low cost 54 MHz fundamental mode crystal to operate. No other external components are required for fre-

quency generation. A key feature of this DSPLL is that it provides immunity to external noise coupling from power supplies and other

uncontrolled noise sources that normally exist on printed circuit boards.

3.1.1 Si5380 LTE Frequency Configuration

The device’s frequency configuration is fully programmable through the serial interface and can also be stored in non-volatile memory.

The combination of flexible integer dividers and a high frequency VCO allows the device to generate multiple output clock frequencies

for applications that require ultra-low phase noise and spurious performance. At the core of the device are the N dividers which deter-

mine the number of unique frequencies that can be generated from the device. The table below shows a list of some possible output

frequencies for LTE applications. The Si5380’s DSPLL core can generate up to five unique top frequencies. These frequencies are dis-

tributed to the output dividers using a configurable crosspoint mux. The R dividers allow further division for up to 10 unique integer-ratio

related frequencies on the Si5380. The ClockBuilder Pro software utility provides a simple means of automatically calculating the opti-

mum divider values (P, M, N and R) for the frequencies listed in the table below.

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Si5380 Rev D Data Sheet

Functional Description

Table 3.1. Example of Possible LTE Clock Frequencies

F_IN(MHz)¹

LTE Device Clock Frequencies Fout (MHz)²

15.36

19.20

30.72

38.40

61.44

76.80

122.88

153.60

184.32

245.76

307.20

368.64

491.52

614.40

737.28

—

15.36

19.20

30.72

38.40

61.44

76.80

122.88

153.60

184.32

245.76

307.20

368.64

491.52

614.40

737.28

983.04

1228.80

1474.56

—

Note:

1. The Si5380 locks to any one of the frequencies listed in the F_INcolumn and generates LTE device clock frequencies.

2. R output dividers allow other frequencies to be generated. These are useful for applications like JESD204B SYSREF clocks.

3.1.2 Si5380 Configuration for JESD204B Clock Generation

The Si5380 can be used as a high performance, fully integrated JEDEC JESD204B jitter cleaner while eliminating the need for discrete

VCXO and loop filter components. The Si5380 supports JESD204B subclass 0 and subclass 1 clocking by providing both device clocks

(DCLK) and system reference clocks (SYSREF). The 12 clock outputs can be independently configured as device clocks or SYSREF

clocks to drive JESD204B converters, FPGAs, or other logic devices. The Si5380 will clock up to four JESD204B targets using four or

more DCLKs and four SYSREF clocks with adjustable delay.Each DCLK is grouped with a SYSREF clock in this configuration.If SYS-

REF clocking is implemented in external logic, then the Si5380 will clock up to 12 JESD204B targets.Not limited to JESD204B applica-

tions, each of the 12 outputs is individually configurable as a high performance output for traditional clocking applications. An example

of a JESD204B frequency configuration is shown in the figure below. In this case, the N dividers determine the device clock frequency

and the R dividers provide the divided SYSREF clock which is used as the lower frequency frame clock. The N divider path also in-

cludes a configurable delay path (∆t) for controlling deterministic latency. The example shows a configuration where all the device

clocks are controlled by a single delay path (∆t0) while the SYSREF clocks each have their own independent delay paths (∆t1 – ∆t4),

though other combinations are also possible. Delay is programmable in steps of 68 ps in the range of ±128 steps (±8.6 ns). See the

3.5.14 Output Skew Control (Δt₀- Δt₄) section for details on skew control. The SYSREF clock is always periodic and can be controlled

(on/off) without glitches by enabling or disabling its output through register writes.

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Si5380 Rev D Data Sheet

Functional Description

IN_SEL[1:0]

Si5380

IN0

IN0b

IN1

÷P₀

÷P₁

÷P₂

÷P₃

DSPLL

IN1b

PD LPF

IN2

IN2b

IN3/FB_IN

IN3b/FB_INb

÷M

÷5

VDDO0

OUT0A

OUT0Ab

÷R_0A

÷R₀

OUT0

OUT0b

VDDO5

OUT5

OUT5b

÷R₅

÷R₆

÷R₇

÷R₈

VDDO6

OUT6

OUT6b

Device

Clocks

t₀

÷N₀

VDDO7

OUT7

OUT7b

VDDO8

OUT8

OUT8b

OUT9

OUT9b

÷R₉

OUT9A

OUT9Ab

÷R_9A

VDDO9

VDDO1

OUT1

OUT1b

t₁

t₂

t₃

t₄

÷N₁

÷N₂

÷N₃

÷N₄

÷R₁

÷R₂

÷R₃

÷R₄

VDDO2

OUT2

OUT2b

SYSREF

Clocks

VDDO3

OUT3

OUT3b

VDDO4

OUT4

OUT4b

Figure 3.1. Example Divider Configuration for Generating JESD204B Subclass 1 Clocks

3.1.3 DSPLL Loop Bandwidth

The DSPLL loop bandwidth determines the amount of input clock jitter attenuation. Register configurable DSPLL loop bandwidth set-

tings in the range of 0.1 Hz to 100 Hz are available for selection. The DSPLL will always remain stable with less than 0.1 dB of peaking

regardless of the DSPLL loop bandwidth selection.

3.1.4 Fastlock

Selecting a low DSPLL loop bandwidth (e.g., 1 Hz) will generally lengthen the lock acquisition time. The fastlock feature allows setting a

temporary fastlock loop bandwidth that is used during the lock acquisition process. Higher fastlock loop bandwidth settings will enable

the DSPLL to lock faster. Once lock acquisition has completed, the DSPLL’s loop bandwidth will automatically revert to the DSPLL

Loop Bandwidth setting. Fastlock loop bandwidth settings in the range of 100 Hz to 4 kHz are available for selection. The fastlock fea-

ture can be enabled or disabled by register configuration.

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Si5380 Rev D Data Sheet

Functional Description

3.1.5 Modes of Operation

Once initialization is complete, the Si5380 operates in one of four modes: Free-run Mode, Lock Acquisition Mode, Locked Mode, or

Holdover Mode. A state diagram showing the modes of operation is shown in the figure below. The following sections describe each of

these modes in greater detail.

Power-Up

Reset and

Initialization

No valid

input clocks

selected

Free-run

Valid input clock

selected

Lock Acquisition

(Fast Lock)

Phase lock on

selected input

clock is achieved

An input is

qualified and

available for

selection

Locked

Mode

No valid input

clocks available

for selection

Holdover

Mode

Input Clock

Switch

Selected input

clock fails

Yes

No

Other Valid

Clock Inputs

Available?

Yes

Holdover

History

Valid?

No

Figure 3.2. Modes of Operation

3.1.6 Initialization and Reset

When power is applied, the device begins an initialization period where it downloads default register values and configuration data from

NVM and performs other initialization tasks. Communicating with the device through the serial interface is possible once this initializa-

tion period is complete. No clocks will be generated until the initialization is complete. There are two types of resets available. A hard

reset is functionally similar to a device power-up. All registers will be restored to the values stored in NVM and all circuits, including the

serial interface, will be restored to their initial state. A hard reset is initiated using the RSTb pin or by asserting the hard reset bit. A soft

reset bypasses the NVM download. It is simply used to initiate register configuration changes.

3.1.7 Freerun Mode

Once power is applied to the Si5380 and initialization is complete, the device will automatically enter freerun mode. Output clocks will

be generated on the outputs with their configured frequencies. The frequency accuracy of the generated output clocks in freerun mode

is dependent on the frequency accuracy of the external crystal or reference clock on the XA/XB pins. For example, if the crystal fre-

quency is ±100 ppm, then all the output clocks will be generated at their configured frequency ±100 ppm in freerun mode. Any change

or drift of the crystal frequency or external reference on the XA/XB pins will be tracked at the output clock frequencies.

3.1.8 Lock Acquisition

If a valid input clock is selected for synchronization, the DSPLL will automatically start the lock acquisition process. If the fast lock fea-

ture is enabled, the DSPLL will acquire lock using the Fastlock Loop Bandwidth setting and then transition to the DSPLL Loop Band-

width setting when lock acquisition is complete. During lock acquisition the outputs will generate a clock that follows the VCO frequency

change as it pulls-in to the input clock frequency.

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Si5380 Rev D Data Sheet

Functional Description

3.1.9 Locked Mode

Once lock is achieved, the Si5380 will generate output clocks that are both frequency and phase locked to the input clock. The DSPLL

will provide jitter attenuation of the input clock using the selected DSPLL loop bandwidth. At this point, any XTAL frequency drift inside

of the loop bandwidth will not affect the output frequencies. When lock is achieved, the LOLb pin will output a logic high level. The LOL

status bit and LOLb status pin will also indicate that the DSPLL is locked. See the 3.4.6 LOL Detection section for more details on LOLb

detection time.

3.1.10 Holdover Mode

The DSPLL will automatically enter holdover mode when the selected input clock becomes invalid and no other valid input clocks are

available for selection. The DSPLL uses an averaged input clock frequency as its final holdover frequency to minimize the disturbance

of the output clock phase and frequency when an input clock suddenly fails. The holdover circuit stores up to 120 seconds of historical

frequency data while the DSPLL is locked to a valid clock input. The final averaged holdover frequency value is calculated from a pro-

grammable window within the stored historical frequency data. Both the window size and the delay are programmable as shown in the

figure below. The window size determines the amount of holdover frequency averaging. The delay value allows ignoring frequency data

that may be corrupt just before the input clock failure.

Figure 3.3. Programmable Holdover Window

Clock Failure

and Entry into

Holdover

Historical Frequency Data Collected

time

Programmable historical data window

Programmable delay

used to determine the final holdover value

120s

0s

30ms, 60ms, 1s,10s, 30s, 60s

1s,10s, 30s, 60s

When entering holdover, the DSPLL will pull the output clock frequencies referred to the calculated averaged holdover frequency. While

in holdover, the output frequency drift is entirely dependent on the external crystal or external reference clock connected to the XA/XB

pins. If a new clock input becomes valid, the DSPLL will automatically exit the holdover mode and re-acquire lock to the new input

clock. This process involves pulling the output clock frequencies to achieve frequency and phase lock with the new input clock. This

pull-in process is glitchless and its rate is controlled by the DSPLL bandwidth and the Fastlock bandwidth. These options are register

programmable.

The DSPLL output frequency when exiting holdover can be ramped (recommend). Just before the exit is initiated, the difference be-

tween the current holdover frequency and the new desired frequency is measured. Using the calculated difference and a user-selecta-

ble ramp rate, the output is linearly ramped to the new frequency. The ramp rate can be 0.2 ppm/s, 40,000 ppm/s, or any of about 40

values in between. The DSPLL loop BW does not limit or affect ramp rate selections (and vice versa). CBPro defaults to ramped exit

from holdover. The same ramp rate settings are used for both exit from holdover and ramped input switching. For more information on

ramped input switching, see 3.3.5 Ramped Input Switching.

Note: If ramped holdover exit is not selected, the holdover exit is governed either by (1) the DSPLL loop BW or (2) a user-selectable

holdover exit BW.

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Si5380 Rev D Data Sheet

Functional Description

3.2 External Reference (XA/XB)

An external crystal (XTAL) is used in combination with the internal oscillator (OSC) to produce an ultra-low phase noise reference clock

for the DSPLL and for providing a stable reference for the free-run and holdover modes. A simplified diagram is shown in the figure

below. The Si5380 includes internal XTAL loading capacitors which eliminates the need for external capacitors and also has the benefit

of reduced noise coupling from external sources. Refer to the Table 5.12 Crystal Specifications on page 34 for crystal specifications.

A crystal frequency of 54 MHz is required, with a total accuracy of ±100 ppm* recommended for best performance. The Si5380 includes

built-in XTAL load capacitors (C_L) of 8 pF, which are switched out of the circuit when using an external XO. The Si5380 Reference

Manual provides additional information on PCB layout recommendations for the crystal to ensure optimum jitter performance. To ach-

ieve optimal jitter performance and minimize BOM cost, a crystal is recommended on the XA/XB reference input. A clock (e.g., XO) may

be used in lieu of the crystal, but it may result in higher output jitter. See the Si5380 Reference Manual for more information. Selection

between the external XTAL or REFCLK is controlled by register configuration. The internal crystal loading capacitors (C_L) are disabled

in this mode. It is important to note that when using the REFCLK option the phase noise of the outputs is directly affected by the phase

noise of the external XO reference. Refer to the Table 5.3 Input Clock Specifications on page 24 for REFCLK requirements when

using the REFCLK mode.

Note: Including initial frequency tolerance and frequency variation over the full operating temperature range, voltage range, load condi-

tions, and aging.

54MHz

XO

54MHz

XO

54MHz

XTAL

100

XA

XB

XA

XB

XA

XB

2xC_L

2xCL

2xC_L

OSC

P_REF

÷

P_REF

÷

Si5380

Crystal Resonator Connection

Differential XO Connection

Single-Ended XO Connection

Figure 3.4. XAXB Crystal Resonator and External Reference Clock Connection Options

3.3 Inputs (IN0, IN1, IN2, IN3/FB_IN)

Four clock inputs are available to synchronize the DSPLL. The inputs are compatible with both single-ended and differential signals.

Input selection can be manual (pin or register controlled) or automatic with definable priorities.

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Si5380 Rev D Data Sheet

Functional Description

3.3.1 Input Configuration and Terminations

Each of the inputs can be configured as differential or single-ended LVCMOS. The recommended input termination schemes are shown

in the figure below. Standard 50% duty cycle signals must be ac-coupled, while low duty cycle Pulsed CMOS signals can be DC-cou-

pled. Unused inputs can be disabled and left unconnected when not in use.

Standard AC-coupled Differential LVDS

Si5380

50

Standard

INx

100

3.3 V, 2.5 V

LVDS or

CML

INxb

50

Pulsed CMOS

Standard AC-coupled Differential LVPECL

Si5380

50

Standard

INx

100

INxb

50

3.3 V, 2.5 V

LVPECL

Pulsed CMOS

Standard AC-coupled Single-ended

Si5380

50

Standard

INx

3.3 V, 2.5 V, 1.8 V

LVCMOS

INxb

Pulsed CMOS

Pulsed CMOS DC-coupled Single-ended

Si5380

R1

Standard

INx

50

R2

INxb

3.3 V, 2.5 V, 1.8 V

LVCMOS

Pulsed CMOS

Resistor values for

f_{IN_PULSED}< 1 MHz

VDD R1 (Ohm) R2 (Ohm)

1.8V

2.5V

3.3V

324

511

634

665

475

365

Figure 3.5. Termination of Differential and LVCMOS Input Signals

3.3.2 Manual Input Selection (IN0, IN1, IN2, IN3/FB_IN)

Input clock selection can be made manually using the IN_SEL[1:0] pins or through a register. A register bit determines input selection

as pin selectable or register selectable. The IN_SEL pins are selected by default. If there is no clock signal on the selected input, the

device will automatically enter free-run or holdover mode.

* NOTE: When the zero delay mode is enabled, IN3 becomes the feedback input (FB_IN) and is not available for selection as a clock

input.

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Si5380 Rev D Data Sheet

Functional Description

Table 3.2. Manual Input Selection Using IN_SEL[1:0] Pins

IN_SEL[1:0]

Selected Input

0

1

0

1

0

1

IN0

IN1

IN2

IN3^*

3.3.3 Automatic Input Switching (IN0, IN1, IN2, IN3/FB_IN)

An automatic input selection state machine is available in addition to the manual switching option. In automatic mode, the selection

criteria is based on reference qualification, input priority, and the revertive option. Only references which are valid can be selected by

the automatic state machine. If there are no valid references available, the DSPLL will enter the holdover mode. With revertive switch-

ing enabled, the highest priority input with a valid reference is always selected. If an input with a higher priority becomes valid, then an

automatic switchover to that input will be initiated. With non-revertive switching, the active input will always remain selected while it is

valid. If it becomes invalid, an automatic switchover to a valid input with the highest priority will be initiated.

3.3.4 Hitless Input Switching

Hitless switching is a feature that prevents a phase transient from propagating to the output when switching between two frequency

locked clock inputs that have a fixed phase difference between them. A hitless switch can only occur when the two input frequencies

are frequency locked meaning that they have to be exactly at the same frequency, or have an integer frequency relationship to each

other. When this feature is enabled, the DSPLL simply absorbs the phase difference between the two input clocks during an input

switch. When disabled (normal switching), the phase difference between the two inputs is propagated to the output at a rate determined

by the DSPLL loop bandwidth.

3.3.5 Ramped Input Switching

When switching between two plesiochronous input clocks (i.e., the frequencies are "almost the same" but not quite), ramped input

switching should be enabled to ensure a smooth transition between the two inputs. Ramped input switching avoids frequency transients

and overshoot when switching between frequencies and so is the default switching mode in CBPro. The feature should be turned off

when switching between input clocks that are always frequency locked (i.e., are always the same exact frequency). The same ramp

rate settings are used for both holdover exit and clock switching. For more information on ramped exit from holdover, see 3.1.10 Hold-

over Mode.

3.3.6 Glitchless Input Switching

The DSPLL has the ability of switching between two input clocks that are up to 40 ppm apart in frequency. The DSPLL will pull-in to the

new frequency using the DSPLL loop bandwidth or using the Fastlock loop bandwidth if it is enabled. The loss of lock (LOL) indicator

will be asserted while the DSPLL is pulling-in to the new clock frequency. There will be no output runt pulses generated at the output.

Glitchless input switching is available regardless of whether the hitless switching feature is enabled or disabled.

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Si5380 Rev D Data Sheet

Functional Description

3.3.7 Zero Delay Mode

A zero delay mode is available for applications that require fixed and consistent minimum delay between the selected input and outputs.

The zero delay mode is configured by opening the internal feedback loop through software configuration and closing the loop externally

as shown in the figure below. This helps to cancel out the internal delay introduced by the dividers, the crosspoint, the input, and the

output drivers. Any one of the outputs can be fed back to the IN3/FB_IN pins, although using the output driver that achieves the short-

est trace length will help to minimize the input-to-output delay. The OUT9A and IN3/FB_IN pins are recommended for the external feed-

back connection. The FB_IN input pins must be terminated and ac-coupled when zero delay mode is used. A differential external feed-

back path connection is necessary for best performance. The order of the OUT9A and FB_IN polarities is such that they may be routed

on the device side of the PCB without requiring vias or needing to cross each other.

IN0

IN0b

IN1

Si5380

÷P₀

÷P₁

÷P₂

DSPLL

IN1b

PD

LPF

IN2

IN2b

÷M

÷5

IN3/FB_IN

÷P₃

VDDO0

IN3b/FB_INb

OUT0A

÷R_0A

÷R₀

OUT0Ab

OUT0

OUT0b

t₀

t₁

t₂

t₃

t₄

÷N₀

÷N₁

÷N₂

÷N₃

÷N₄

VDDO2

OUT2

OUT2b

÷R₂

VDDO8

OUT8

OUT8b

÷R₈

OUT9

OUT9b

÷R₉

OUT9A

÷R_9A

OUT9Ab

VDDO9

External Feedback Path

Figure 3.6. Si5380 Zero Delay Mode Set-up

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Si5380 Rev D Data Sheet

Functional Description

3.4 Fault Monitoring

All four input clocks (IN0, IN1, IN2, IN3/FB_IN) are monitored for loss of signal (LOS) and out-of-frequency (OOF) as shown in the fig-

ure below. The reference at the XA/XB pins is also monitored for LOS since it provides a critical reference clock for the DSPLL. The

DSPLL also has a Loss Of Lock (LOL) indicator, which is asserted when the DSPLL has lost synchronization with the selected input

clock.

XA XB

Si5380

OSC

LOS

XAXB

IN0

Precision

Fast

LOS

OOF

÷P₀

÷P₁

÷P₂

÷P₃

IN0b

DSPLL

IN1

Precision

Fast

LOL

IN1b

PD LPF

Precision

Fast

IN2

Feedback

Clock

IN2b

÷M

÷5

IN3/FB_IN

Precision

Fast

IN3b/FB_INb

Figure 3.7. Si5380 Fault Monitors

3.4.1 Input LOS Detection

The loss of signal monitor measures the period of each input clock cycle to detect phase irregularities or missing clock edges. Each of

the input LOS circuits have their own programmable sensitivity which allows ignoring missing edges or intermittent errors. Loss of signal

sensitivity is configurable using the ClockBuilder Pro utility. The LOS status for each of the monitors is accessible by reading a status

register. The live LOS register always displays the current LOS state and a sticky register always stays asserted until cleared. An option

to disable any of the LOS monitors is also available.

Sticky

Monitor

LOS

en

Live

Figure 3.8. LOS Status Indicators

3.4.2 XA/XB LOS Detection

An LOS monitor is available to ensure that the external crystal or reference clock is valid. By default, the output clocks are disabled

when XAXB LOS is detected. This feature can be disabled such that the device will continue to produce output clocks when XAXB LOS

is detected. See the 3.5.11 Output Disable During XAXB_LOS section for details.

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Si5380 Rev D Data Sheet

Functional Description

3.4.3 OOF Detection

Each input clock is monitored for frequency accuracy with respect to a OOF reference which it considers as its “0_ppm” reference. This

OOF reference can be selected as either: XAXB, IN0, IN1, IN2 or IN3. IN3 is only available as the OOF reference when not in ZDM.

The final OOF status is determined by the combination of both a precise OOF monitor and a fast OOF monitor as shown in the figure

below. An option to disable either monitor is also available. The live OOF register always displays the current OOF state, and its sticky

register bit stays asserted until cleared.

Sticky

Monitor

Precision

Fast

en

LOS

OOF

Live

Figure 3.9. OOF Status Indicator

3.4.4 Precision OOF Monitor

The Precision OOF monitor circuit measures the frequency of all input clocks to within ±1 ppm accuracy with respect to the frequency at

the XA/XB pins. The OOF monitor considers the frequency at the XA/XB pins as its 1/16 ppm OOF reference. A valid input frequency is

one that remains within the OOF frequency range which is register configurable up to ±500 ppm in steps of 1/16 ppm. A configurable

amount of hysteresis is also available to prevent the OOF status from toggling at the failure boundary. An example is shown in the

figure below. In this case the OOF monitor is configured with a valid frequency range of ±6 ppm and with 2 ppm of hysteresis. An option

to use one of the input pins (IN0–IN3) as the 0 ppm OOF reference instead of the XA/XB pins is available. This option is register config-

urable.

OOF Declared

OOF Cleared

f_IN

Hysteresis

-4 ppm

(Clear)

-6 ppm

(Set)

+4 ppm

(Clear)

+6 ppm

(Set)

0 ppm

OOF

Reference

Figure 3.10. Example of Precise OOF Monitor Assertion and De-assertion Triggers

3.4.5 Fast OOF Monitor

Because the precision OOF monitor needs to provide 1/16 ppm of frequency measurement accuracy, it must measure the monitored

input clock frequencies over a relatively long period of time. This may be too slow to detect an input clock that is quickly ramping in

frequency. An additional level of OOF monitoring called the Fast OOF monitor runs in parallel with the precision OOF monitors to quick-

ly detect a ramping input frequency. The Fast OOF monitor asserts OOF on an input clock frequency that has changed by 1,000 to

16,000 ppm.

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Functional Description

3.4.6 LOL Detection

A loss of lock (LOL) monitor asserts the LOL bit when the DSPLL has lost synchronization with the selected input clock. There is also a

dedicated active-low LOLb pin which reflects the loss of lock condition. The LOL monitor measures the frequency difference between

the input and feedback clocks at the phase detector. There are two LOL frequency monitors, one that sets the LOL indicator (LOL Set)

and another that clears the indicator (LOL Clear). A block diagram of the LOL monitor is shown in the figure below. The live LOL regis-

ter always displays the current LOL state and a sticky register always stays asserted until cleared. The LOLb pin reflects the current

state of the LOL monitor.

LOL Monitor

RS Latch

Sticky

LOL

Clear

Timer

Reset

LOL

Q

Live

LOL

Set

LOLb

DSPLL

f_IN

PD LPF

Feedback

Clock

÷M

÷5

Si5380

Figure 3.11. LOL Status Indicators

Each of the frequency monitors have adjustable sensitivity which is register configurable from 0.1 ppm to 10,000 ppm. Having two sep-

arate frequency monitors allows for hysteresis to help prevent chattering of LOL status. An example configuration where LOCK is indi-

cated when there is less than 0.1 ppm frequency difference at the inputs of the phase detector and LOL is indicated when there is more

than 1 ppm frequency difference is shown in the figure below.

Clear LOL

Threshold

Set LOL

Threshold

Lock Acquisition

LOL

Hysteresis

Lost Lock

LOCKED

0

0.1

1

10,000

Phase Detector Frequency Difference (ppm)

Figure 3.12. LOL Set and Clear Thresholds

An optional timer is available to delay clearing of the LOL indicator to allow additional time for the DSPLL to completely phase lock to

the input clock. The timer is also useful to prevent the LOL indicator from toggling or chattering as the DSPLL completes lock acquisi-

tion. The configurable delay value depends on frequency configuration and loop bandwidth of the DSPLL and is automatically calcula-

ted using the ClockBuilder Pro utility.

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Si5380 Rev D Data Sheet

Functional Description

3.4.7 Interrupt Pin INTRb

An interrupt pin INTRb indicates a change in state of the status indicators shown in the figure below. All of the status indicators are

maskable to prevent assertion of the interrupt pin. The state of the INTRb pin is reset by clearing the status register that caused the

interrupt. The sticky version of the fault monitors is used for this function to ensure that the fault condition is still available when re-

sponding to the interrupt.

Si5380

LOS_FLG 0x0012[0]

IN0

OOF_FLG 0x0012[4]

LOS_FLG 0x0012[1]

IN1

OOF_FLG 0x0012[5]

LOS_FLG 0x0012[2]

IN2

INTRb

OOF_FLG 0x0012[6]

LOS_FLG 0x0012[3]

IN3

OOF_FLG 0x0012[7]

LOL_FLG 0x0013[1]

HOLD_FLG 0x0013[5]

PLL

CAL_FLG 0x0014[5]

SYSINCAL_FLG 0x0011[0]

LOSXAXB_FLG 0x0011[1]

LOSREF_FLG 0x0011[2]

Device

XAXB_ERR_FLG 0x0011[3]

SMBUS_TIMEOUT_FLG 0x0011[5]

Figure 3.13. Interrupt Triggers and Masks

3.5 Outputs

The Si5380 supports 12 differential output drivers which can be independently configured as differential or LVCMOS.

3.5.1 Output Crosspoint

The output crosspoint allows any of the N dividers to connect to any of the clock outputs.

3.5.2 Output Signal Format

The differential output amplitude and common mode voltage are both fully programmable covering a wide variety of signal formats in-

cluding LVPECL, LVDS, HCSL, and CML. In addition to supporting differential signals, any of the outputs can be configured as

LVCMOS (3.3 V, 2.5 V, or 1.8 V) drivers providing up to 24 single-ended outputs, or any combination of differential and single-ended

outputs.

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Functional Description

3.5.3 Output Terminations

The output drivers support both ac-coupled and dc-coupled terminations as shown in the following figure.

AC-coupled LVDS/LVPECL

DC-coupled LVDS

V

_DDO= 3.3 V, 2.5 V, 1.8 V

V

_DDO= 3.3 V, 2.5 V

50

OUTx

100

OUTxb

100

OUTxb

Internally

self-biased

Si5380

AC-coupled LVPECL / CML

AC-coupled HCSL

VDD_RX

VDD – 1.3 V

V_DDO= 3.3 V, 2.5 V, 1.8 V

V

_DDO= 3.3 V, 2.5 V

R1

R2

50

OUTx

50

OUTx

Standard

HCSL

Receiver

OUTxb

Si5380

R2

For V_CM= 0.35 V

VDD_RX

R1

R2

442 Ω

56.2 Ω

59 Ω

3.3 V

2.5 V

1.8 V

332 Ω

243 Ω

63.4 Ω

Figure 3.14. Supported Output Terminations

3.5.4 Programmable Common Mode Voltage For Differential Outputs

The common mode voltage (V_CM) for the differential modes is programmable in 100 mV increments from 0.7 V to 2.3 V depending on

the voltage available at the output’s VDDO pin. Setting the common mode voltage is useful when dc-coupling the output drivers.

3.5.5 LVCMOS Output Terminations

LVCMOS outputs are dc-coupled with source-side series termination as shown in the figure below.

DC-coupled LVCMOS

3.3 V, 2.5 V, 1.8 V

LVCMOS

V

_DDO= 3.3V, 2.5V, 1.8V

50

Rs

OUTx

OUTxb

Figure 3.15. LVCMOS Output Terminations

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Si5380 Rev D Data Sheet

Functional Description

3.5.6 LVCMOS Output Impedance and Drive Strength Selection

Each LVCMOS driver has a configurable output impedance to accommodate different trace impedances and drive strengths. A source

termination resistor is recommended to help match the selected output impedance to the trace impedance. There are three programma-

ble output impedance selections for each VDDO options as shown in the table below.

Table 3.3. Typical Output Impedance (Z_S)

VDDO

CMOS_DRIVE_Selection

OUTx_CMOS_DRV = 1

OUTx_CMOS_DRV = 2

OUTx_CMOS_DRV = 3

3.3 V

2.5 V

1.8 V

38 Ω

43 Ω

—

30 Ω

35 Ω

46 Ω

22 Ω

24 Ω

31 Ω

3.5.7 LVCMOS Output Signal Swing

The signal swing (VOL/VOH) of the LVCMOS output drivers is set by the voltage on the VDDO pins. Each output driver has its own

VDDO pin allowing a unique output voltage swing for each of the LVCMOS drivers. OUT0 and OUT0A share the same VDDO pin.

OUT9 and OUT9A also share the VDDO pin. All other outputs have their own individual VDDO pins.

3.5.8 LVCMOS Output Polarity

When a driver is configured as an LVCMOS output it generates a clock signal on both pins (OUTx and OUTxb). By default the clock on

the OUTxb pin is generated with the same polarity (in phase) with the clock on the OUTx pin. The polarity of these clocks is configura-

ble enabling complimentary clock generation and/or inverted polarity with respect to other output drivers.

3.5.9 Output Enable/Disable

The OEb pin provides a convenient method of disabling or enabling all of the output drivers at the same time. When the OEb pin is held

high all outputs will be disabled. When held low, the outputs will all be enabled. Outputs in the enabled state can still be individually

disabled through register control.

3.5.10 Output Disable During LOL

By default, a DSPLL that is out of lock will generate either free-running clocks or generate clocks in holdover mode. There is an option

to disable the outputs when a DSPLL is LOL. This option can be useful to force a downstream PLL into holdover.

3.5.11 Output Disable During XAXB_LOS

The internal oscillator circuit (OSC) in combination with the external crystal (XTAL) provides a critical function for the operation of the

DSPLLs. In the event of a crystal failure, the device will assert an XAXB_LOS alarm. By default, all outputs will be disabled during

assertion of the XAXB_LOS alarm. There is an option to leave the outputs enabled during an XAXB_LOS alarm, but the frequency

accuracy and stability will be indeterminate during this fault condition.The internal oscillator circuit (OSC) in combination with the exter-

nal crystal (XTAL) provides a critical function for the operation of the DSPLLs. In the event of a crystal failure, the device will assert an

XAXB_LOS alarm. By default, all outputs will be disabled during assertion of the XAXB_LOS alarm. There is an option to leave the

outputs enabled during an XAXB_LOS alarm, but the frequency accuracy and stability will be indeterminate during this fault condition.

3.5.12 Output Driver State When Disabled

The disabled state of an output driver is configurable as either disable low or disable high.

3.5.13 Synchronous Enable/Disable Feature

The output drivers provide a selectable synchronous enable/disable feature. Output drivers with synchronous disable active will wait

until a clock period has completed before the driver is disabled or enabled. This prevents unwanted shortened pulses from occurring

when enabling or disabling an output. When this feature is turned off, the output clock will disable immediately without waiting for the

clock period to complete.

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Functional Description

3.5.14 Output Skew Control (Δt₀- Δt₄)

The Si5380 uses independent dividers (N0 - N4) to generate up to 5 unique frequencies to its 12 outputs through a crosspoint switch. A

delay path (Δt0 - Δt4) associated with each of these dividers is available for applications that need a specific output skew configuration.

This is useful for compensating PCB trace delay differences or for applications that require quadrature clock generation. The resolution

of the phase adjustment is approximately 68 ps per step up to 128 steps of added phase delay (+8.6 ns late), or 128 steps of negative

delay (–8.6 ns early). Phase adjustments are register configurable. An example of generating two frequencies with unique configurable

path delays is shown in the following figure.

VDDO0

OUT0A

OUT0Ab

÷R_0A

OUT0

OUT0b

÷R₀

t₀

t₁

t₂

t₃

t₄

÷N₀

÷N₁

÷N₂

÷N₃

÷N₄

VDDO1

OUT1

÷R₁

÷R₂

÷R₃

÷R₄

÷R₅

÷R₆

÷R₇

÷R₈

OUT1b

VDDO2

OUT2

OUT2b

VDDO3

OUT3

OUT3b

VDDO4

OUT4

OUT4b

VDDO5

OUT5

OUT5b

VDDO6

OUT6

OUT6b

VDDO7

OUT7

OUT7b

VDDO8

OUT8

OUT8b

OUT9

OUT9b

÷R₉

OUT9A

OUT9Ab

÷R_9A

VDDO9

Figure 3.16. Example of Independently Configurable Path Delays

All phase delay values are restored to their default values after power-up, power-on reset, or hardware reset using the RSTb pin. Phase

delay default values can be written to NVM allowing a custom phase offset configuration at power-up or after power-on reset, or after a

hardware reset using the RSTb pin.

3.5.15 Output Divider (R) Synchronization

All the output R dividers are reset to a known state during the power-up initialization period. This ensures consistent and repeatable

phase alignment across all output drivers. Resetting the device using the RSTb pin or asserting the reset bit will have the same result.

Asserting the sync register bit provides another method of realigning the R dividers without resetting the device.

3.6 Power Management

Unused inputs and output drivers can be powered down when unused. Consult the Si5380 Reference Manual and ClockBuilder Pro

configuration utility for details.

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Si5380 Rev D Data Sheet

Functional Description

3.6.1 Power Down Pin (PDNb)

A power down pin is provided to force the device in a low power mode. The device’s configuration will be maintained but no output

clocks will be generated. Most of the internal blocks will be shut down but device communication via the serial interface will still be

available. When the PDNb pin is pulled low the outputs will shut down without glitching (the clock’s complete period will be generated

before shutting down). When PDNb is released the device will start generating clocks without glitches. The device will generate free-

running clocks until the DSPLL has acquired lock to the selected input clock source.

3.7 In-Circuit Programming

The Si5380 is fully configurable using the serial interface (I2C or SPI). At power-up, the device downloads its default register values

from internal non-volatile memory (NVM). Application specific default configurations can be written into NVM allowing the device to gen-

erate specific clock frequencies at power-up. Writing default values to NVM is in-circuit programmable with normal operating power sup-

ply voltages applied to its VDD and VDDA pins. The NVM is writable two times. Once a new configuration has been written to NVM, the

old configuration is no longer accessible. Refer to the Si5380 Reference Manual for a detailed procedure for writing registers to NVM.

3.8 Serial Interface

Configuration and operation of the Si5380 is controlled by reading and writing registers using the I2C or SPI interface. The I2C_SEL pin

selects I2C or SPI operation. The Si5380 supports communication with a 3.3 V or 1.8 V host by setting the IO_VDD_SEL configuration

bit. The SPI mode supports 4-wire or 3-wire by setting the SPI_3WIRE configuration bit. See the Si5380 Reference Manual for details.

3.9 Custom Factory Preprogrammed Devices

For applications where a serial interface is not available for programming the device, custom pre-programmed parts can be ordered

with a specific configuration written into NVM. A factory pre-programmed device will generate clocks at power-up. Custom, factory-pre-

programmed devices are available. Use the ClockBuilder Pro custom part number wizard (www.silabs.com/clockbuilderpro) to quickly

and easily request and generate a custom part number for your configuration.

In less than three minutes, you will be able to generate a custom part number with a detailed data sheet addendum matching your

design’s configuration. Once you receive the confirmation email with the data sheet addendum, simply place an order with your local

Silicon Labs sales representative. Samples of your pre-programmed device will ship to you typically within two weeks.

3.10 Enabling Features and/or Configuration Settings Not Available in ClockBuilder Pro for Factory Pre-programmed Devices

As with essentially all software utilities, ClockBuilder Pro is continuously updated and enhanced. By registering at www.silabs.com and

opting in for updates to software, you will be notified whenever changes are made and what the impact of those changes are. This

update process will ultimately enable ClockBuilder Pro users to access all features and register setting values documented in this data

sheet and the Si5380 Reference Manual .

However, if you must enable or access a feature or register setting value so that the device starts up with this feature or a register

setting, but the feature or register setting is NOT yet available in CBPro, you must contact a Silicon Labs applications engineer for as-

sistance. Examples of this type of feature or custom setting are the customizable output amplitude and common voltages for the clock

outputs. After careful review of your project file and custom requirements, all Silicon Labs applications engineer will email back your

CBPro project file with your specific features and register settings enabled, using what is referred to as the manual "settings override"

feature of CBPro. "Override" settings to match your request(s) will be listed in your design report file. Examples of setting "overrides" in

a CBPro design report are shown below:

Table 3.4. Setting Overrides

Location

0x0535[0]

0128[6:4]

Name

Type

No NVM

User

Target

N/A

Dec Value

Hex Value

0x1

FORCE_HOLD

OUT6_AMPL

1

5

OPN and EVB

0x5

Once you receive the updated design file, simply open it in CBPro. After you create a custom OPN, the device will begin operation after

startup with the values in the NVM file, including the Silicon Labs-supplied override settings.

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Si5380 Rev D Data Sheet

Functional Description

Place sample

Start

order

Do I need a

pre-programmed device

with a feature or setting

which is unavailable in

ClockBuilder Pro?

Generate

Custom OPN

in CBPro

Configure device

using CBPro

No

Yes

Contact Silicon Labs

Technical Support

to submit & review

your

Yes

non-standard

configuration

request & CBPro

project file

Receive

updated CBPro

project file

from

Silicon Labs

with “Settings

Override”

Does the updated

CBPro Project file

match your

Load project file

into CBPro and test

requirements?

Figure 3.17. Flowchart to Order Custom Parts with Features not Available in CBPro

Note: Contact Silicon Labs Technical Support at www.silabs.com/support/Pages/default.aspx.

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Si5380 Rev D Data Sheet

Register Map

4. Register Map

This document provides a brief list of available registers. For a complete list of registers and settings, please refer to the Si5380 Refer-

ence Manual .

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Si5380 Rev D Data Sheet

Electrical Specifications

5. Electrical Specifications

Table 5.1. Recommended Operating Conditions ¹

Parameter

Ambient Temperature

Symbol

T_A

Min

–40

—

Typ

25

Max

Unit

°C

V

85

Maximum Junction Temperature

Core Supply Voltage

T_JMAX

V_DD

V_DDA

V_DDO

—

125

1.71

3.14

2.37

1.71

1.80

3.30

2.50

1.80

1.89

3.47

2.62

1.89

V

Output Driver Supply Voltage

V

Note:

1. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical val-

ues apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted.

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Si5380 Rev D Data Sheet

Electrical Specifications

Table 5.2. DC Characteristics

Test Condition

Parameter

Symbol

I_DD

Min

—

Typ

190

125

36

Max

310

135

41

Unit

mA

Core Supply Current ^1,2

I_DDA

—

Output Buffer Supply Current ^{2, 5}

LVPECL Output ³

@ 1474.56 MHz

LVPECL Output ³

@ 153.6 MHz

I_DDO

—

22

25

26

29

mA

mW

LVDS Output ³

@ 1474.56 MHz

LVDS Output ³

15

18

@ 153.6 MHz

3.3 V LVCMOS Output ⁴

@ 153.6 MHz

22

30

2.5 V LVCMOS Output ⁴

@ 153.6 MHz

18

23

1.8 V LVCMOS Output ⁴

@ 153.6 MHz

12

16

Total Power Dissipation ^{1, 2}

P_d

Typical Outputs

1300

1600

Notes:

1. Si5380 test configuration: 3 × 3.3 V LVPECL outputs enabled at 122.88 MHz, 2 × 3.3 V LVPECL outputs enabled at 491.52 MHz,

1 × 3.3 V LVPECL output enabled at 983.04 MHz. Excludes power in termination resistors.

2. Detailed power consumption for any configuration can be estimated using ClockBuilder Pro when an evaluation board (EVB) is

not available. All EVBs support detailed current measurements for any configuration.

3. Differential outputs terminated into an ac-coupled 100 Ω load.

4. LVCMOS outputs measured into a 5-inch 50 Ω PCB trace with 5 pF load. The LVCMOS outputs were set to

OUTx_CMOS_DRV=3, which is the strongest driver setting. Refer to the Si5380 Reference Manual for more details on register

settings.

5. VDDO0 supplies power to both OUT0 and OUT0A buffers. Similarly, VDDO9 supplies power to both OUT9 and OUT9A buffers.

LVCMOS Output Test Configuration

Differential Output Test Configuration

Trace length 5

inches

I_DDO

0.1 uF

56 Ω

0.1 uF

56 Ω

499 Ω

4.7 pF

50

I_DDO

50 Ω Scope Input

50

OUT

100

OUT

OUTb

50

499 Ω

4.7 pF

0.1 uF

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Si5380 Rev D Data Sheet

Electrical Specifications

Table 5.3. Input Clock Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Standard Input Buffer with Differential or Single-Ended/LVCMOS—AC-coupled (IN0, IN1, IN2, IN3/FB_IN)

Input Frequency Range

Voltage Swing¹

f_{IN_DIFF}

f_{IN_SE}

Differential

11.52

—

737.28

245.76

MHz

All Single-ended Signals

(including LVCMOS)

Differential AC-coupled

F_IN< 245.76 MHz

V_IN

100

225

—

1800

mVpp_se

Differential AC-coupled

245.76 MHz < F_IN

737.28 MHz

<

Single-Ended AC-coupled

F_IN< 245.76 MHz

100

400

—

3600

—

mVpp_se

V/µs

Slew Rate ^{2, 3}

Duty Cycle

SR

DC

C_IN

R_IN

40

—

0.3

16

60

—

%

pF

kΩ

Capacitance

Input Resistance

Pulsed CMOS Input Buffer—DC-coupled (IN0, IN1, IN2, IN3/FB_IN) ⁴

Input Frequency

f_{IN_PULSED_CM}

11.52

—

245.76

MHz

OS

Input Voltage Thresholds⁴

V_IL

V_IH

SR

–0.2

0.8

—

0.4

—

V

Slew Rate ^{2, 3}

400

—

V/µs

Duty Cycle

DC

PW

R_IN

Clock Input

Pulse Input

40

1.6

—

8

60

—

%

ns

kΩ

Minimum Pulse Width

Input Resistance

REFCLK (applied to XA/XB)

REFCLK Frequency ⁵

f_{IN_REF}

Frequency required for op-

timum performance

—

54

—

MHz

Total Frequency Tolerance ⁶

Input Voltage Swing

f_RANGE

V_{IN_SE}

V_{IN_DIFF}

SR

–100

365

400

—

+100

2000

2500

—

ppm

mVpp_se

mVpp_diff

V/µs

Slew Rate ^{2 , 3}

Imposed for best phase

noise performance

Input Duty Cycle

DC

40

—

60

%

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Si5380 Rev D Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Notes:

1. Voltage swing is specified as single-ended mVpp.

OUTx

Vcm

Vpp_se

Vpp_diff = 2*Vpp_se

Vcm

OUTxb

2. Imposed for phase noise performance.

3. Rise and fall times can be estimated using the following simplified equation: tr/tf_80-20= ((0.8 – 0.2) * V_{IN_Vpp_se}) / SR.

4. Pulsed CMOS mode is intended primarily for single-end LVCMOS input clocks < 1 MHz, which must be dc-coupled, having a duty

cycle significantly less than 50%. A common application example is a low frequency video frame sync pulse. Since the input

thresholds (VIL, VIH) of the input buffer are non-standard (0.40 and 0.80 V, respectively), refer to the input attenuator circuit for

dc-coupled Pulsed LVCMOS in the in the Si5380 Reference Manual . Otherwise, for standard LVCMOS input clocks, use the

"AC-coupled Single-Ended" mode as shown in Figure 3.14 Supported Output Terminations on page 16.

5. The REFCLK frequency for the Si5380 is fixed at 54 MHz. Contact Silicon Labs technical support for more information.

6. Includes initial tolerance, drift after reflow, change over temperature (–40 °C to +85 °C), V_DDvariation, load pulling, and aging.

Table 5.4. Serial and Control Input Pin Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Si5380 Serial and Control Input Pins (I2C_SEL, IN_SEL[1:0], RSTb, OEb, SYNCb, PDNb, A1/SDO, SDA/SDIO, SCLK, A0/CSb)

Input Voltage Thresholds

V_IL

V_IH

—

0.3xV_DDIO

—

1

V

0.7 x

V_DDIO

1

Input Capacitance

Input Resistance

Minimum Pulse Width

Note:

C_IN

I_L

—

2

—

pF

kΩ

ns

—

20

—

PW

RSTb, SYNCb, PDNb

100

1. V_DDIOis determined by the IO_VDD_SEL bit. It is selectable as V_DDAor V_DD. See the Si5380 Reference Manual for more details

on the register settings.

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Si5380 Rev D Data Sheet

Electrical Specifications

Table 5.5. Differential Clock Output Specifications

Parameter

Output Frequency

Symbol

f_OUT

Test Condition

Min

0.480

48

Typ

—

Max

1474.56

52

Unit

MHz

%

Duty Cycle

DC

f ≤ 400 MHz

f > 400 MHz

—

45

—

55

%

Output-Output Skew

T_SK

Outputs at 737.28 MHz

connected to the same

"N-divider"

—

65

ps

Outputs at 737.28 MHz

connected to different "N-di-

viders"

—

90

ps

OUT-OUTb Skew

T_{SK_OUT}

Measured from the positive

to negative output pins

—

0

50

ps

Output Voltage Amplitude ¹

V_OUT

V_DDO

=

LVDS

350

430

510

mVpp_se

3.3 V or

2.5 V or

1.8 V

V_DDO= 3.3 V

or 2.5 V

LVPECL

640

750

900

Common Mode Voltage¹

V_CM

V_DDO

=

LVDS

1.10

1.90

1.2

2.0

1.3

2.1

V

LVPECL

3.3 V

V_DDO

=

LVPECL

LVDS

1.1

0.8

—

1.2

1.3

1.00

150

2.5 V

V_DDO

=

sub-LVDS

0.9

1.8 V

Rise and Fall Times (20% to

80%)

t_R/t_F

100

ps

Differential Output Impedance

Power Supply Noise Rejection ²

Z_O

—

100

–101

–96

–99

–97

–72

—

Ω

PSRR

10 kHz sinusoidal noise

100 kHz sinusoidal noise

500 kHz sinusoidal noise

1 MHz sinusoidal noise

dBc

dB

Output-Output Crosstalk³

XTALK

Measured spur from adja-

cent output

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Si5380 Rev D Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Notes:

1. Output amplitude and common mode voltage are programmable through register settings and can be stored in NVM. Each output

driver can be programmed independently. The maximum LVDS single-ended amplitude can be up to 110 mV higher than the TIA/

EIA-644 maximum. Refer to the Si5380 Reference Manual for recommended output register settings. Not all combinations of volt-

age amplitude and common mode voltages settings are possible.

2. Measured for 153.6 MHz carrier frequency. 100 mVpp of sinewave noise added to VDDO when programmed at 3.3 V.

3. Measured across two adjacent outputs, both in LVDS mode, with the victim running at 155.52 MHz and the aggressor at 156.25

MHz. These output frequencies are generated using non-production engineering modes only for test. Refer to application note,

"AN862: Optimizing Si534x Jitter Performance in Next Generation Internet Infrastructure Systems", for guidance on crosstalk opti-

mization. Note that all active outputs must be terminated when measuring crosstalk

Table 5.6. LVCMOS Clock Output Specifications

Parameter

Output Frequency

Duty Cycle

Symbol

Test Condition

Min

Typ

—

Max

245.76

52

Unit

MHz

%

0.480

DC

f_OUT< 100 MHz

100 MHz < f_OUT< 245.76 MHz

Outputs at 153.6 MHz

48

—

45

—

55

Output-to-Output Skew

T_SK

30

140

ps

V

V_DDO= 3.3 V

OUTx_CMOS_DRV=1

OUTx_CMOS_DRV=2

OUTx_CMOS_DRV=3

I_{OH =}–10 mA

V

_DDOx 0.85

—

I_{OH =}–12 mA

I_{OH =}–17 mA

V_DDO= 2.5 V

V_DDOx 0.85

Output Voltage High ^{1, 2, 3}

V_OH

OUTx_CMOS_DRV=1

OUTx_CMOS_DRV=2

OUTx_CMOS_DRV=3

I_{OH =}–6 mA

I_{OH =}–8 mA

I_{OH =}–11 mA

—

V

V_DDO= 1.8 V

V_DDOx 0.85

OUTx_CMOS_DRV=2

OUTx_CMOS_DRV=3

I_{OH =}–4 mA

I_{OH =}–5 mA

—

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Si5380 Rev D Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

V_DDO= 3.3 V

OUTx_CMOS_DRV=1

I_{OL =}10 mA

I_{OL =}12 mA

I_{OL =}17 mA

—

V_DDOx 0.15

V

OUTx_CMOS_DRV=2

OUTx_CMOS_DRV=3

—

V_DDO= 2.5 V

Output Voltage Low ^{1, 2, 3}

V_OL

OUTx_CMOS_DRV=1

OUTx_CMOS_DRV=2

OUTx_CMOS_DRV=3

I_{OL =}6 mA

I_{OL =}8 mA

I_{OL =}11 mA

—

V_DDOx 0.15

V

—

V_DDO= 1.8 V

OUTx_CMOS_DRV=2

OUTx_CMOS_DRV=3

I_{OL =}4 mA

I_{OL =}5 mA

—

V_DDOx 0.15

V

—

LVCMOS Rise and Fall

Times ³

tr/tf

V_DDO= 3.3 V

400

450

550

600

750

ps

V_DDO= 2.5 V

V_DDO= 1.8 V

(20% to 80%)

Notes:

1. Driver strength is a register programmable setting and stored in NVM. Options are OUTx_CMOS_DRV = 1, 2, 3. Refer to the

Si5380 Reference Manual for recommended output register settings.

2. I_OL/I_OHis measured at V_OL/V_OHas shown in the DC test configuration

3. A 5 pF capacitive load is assumed. The LVCMOS outputs were set to OUTx_CMOS_DRV = 3.

AC Output Test Configuration

DC Test Configuration

Trace length 5 inches

0.1 uF

499 Ω

4.7 pF

I_DDO

50

I_OL/I_OH

50 Ω Scope Input

OUT

56 Ω

0.1 uF

Zs

OUTb

V_OL/V_OH

499 Ω

4.7 pF

56 Ω

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Si5380 Rev D Data Sheet

Electrical Specifications

Table 5.7. Output Serial and Status Pin Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Si5380 Output Serial and Status Pins (LOLb, INTRb, SDA/SDIO², A1/SDO)

Output Voltage ^{1, 2}

V_OH

I_OH= –2 mA

I_OL= 2 mA

V_DDIO

0.85

x

—

V

V_OL

—

V_DDIO

0.15

x

Notes:

1. V_DDIOis determined by the IO_VDD_SEL bit. It is selectable as V_DDAor V_DD. See the Si5380 Reference Manual for more details

on the register settings.

2. The V_OHspecification does not apply to the open-drain SDA/SDIO output when the serial interface is in I2C mode or is unused,

with I2C_SEL pulled high internally. V_OLremains valid in all cases.

Table 5.8. Performance Characteristics

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

PLL Bandwidth Programming

Range ¹

f_BW

Bandwidth is register

programmable

0.1

—

4000

Hz

Initial Start-Up Time

t_START

Time from power-up to

when the device gener-

ates free-running clocks

—

370

280

450

300

ms

PLL Lock Time²

t_ACQ

Fastlock enabled

F_IN= 19.2 MHz

POR to Serial Interface Ready ³

Output Delay Adjustment

t_RDY

t_{DELAY_int}

t_RANGE

J_PK

—

68

8.6

—

15

—

ms

ps

f_VCO= 14.7456 GHz

±128 / f_VCO

—

ns

Jitter Peaking

Measured with a frequen-

cy plan running a 24.576

MHz input, 24.576 MHz

output, and a Loop Band-

width of 4 Hz

0.1

dB

Jitter Tolerance

J_TOL

Compliant with G.8262

Options 1 and 2 Carrier

Frequency = 2.103125

GHz; Jitter Modulation

Frequency = 10 Hz

—

3180

—

UI pk-pk

Maximum Phase Transient Dur-

ing a Hitless Switch

t_SWITCH

Only valid for a single au-

tomatic switch between

two input clocks at same

frequency

—

2.0

1.3

20

ns

Only valid for a single

manual switch between

two input clocks at same

frequency

Pull-in Range

ω_P

–20

ppm

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Si5380 Rev D Data Sheet

Electrical Specifications

Parameter

Symbol

t_IODELAY

t_ZDELAY

J_GEN

Test Condition

Note 5

Min

—

Typ

—

Max

1.8

—

Unit

ns

Input-to-Output Delay Variation

Note 6

—

110

65

ps

RMS Phase Jitter ⁴

12 kHz to 20 MHz

—

80

fs rms

(measured @ 983.04

MHz)

Phase Noise Performance ⁴

PN

10Hz

100 Hz

—

–72

–98

—

dBc/Hz

dBc

(122.88 MHz Carrier

Frequency)

1 kHz

–126

–140

–148

–154

–165

–103

–95

10 kHz

100 kHz

1 MHz

10 MHz

Spur Performance ⁴(122.88

MHz Carrier Frequency)

SPUR

Up to 1 MHz offset

From 1 MHz to 30 MHz

offset

dBc

Notes:

1. Actual loop bandwidth might be lower; refer to ClockBuilder Pro for actual value on your frequency plan.

2. Lock Time can vary significantly depending on several parameters, such as bandwidths, LOL thresholds, etc. For this case, lock

time was measured with nominal and fastlock bandwidths both set to 100 Hz, LOL set/clear thresholds of 3/0.3 ppm respectively,

using IN0 as clock reference by removing the reference and enabling it again, then measuring the delta time between the first

rising edge of the clock reference and the LOL indicator de-assertion.

3. Measured as time from valid V_DD/V_DDArails (both >90% of settled voltage) to when the serial interface is ready to respond to

commands.

4. Jitter generation test conditions: f_IN= 30.72 MHz, 3.3V LVPECL, DSPLL LBW = 100 Hz. Jitter integrated from 12 kHz to 20 MHz

offset. Does not include jitter from PLL input reference.

5. Measured between a common 2 MHz input and 2 MHz output with different N-dividers on the same unit and a loop bandwidth of

4 kHz. These output frequencies are generated using non-production engineering modes only for test.

6. Delay between reference and feedback input both clocks at 10 MHz and same slew rate. Ref clock rise time must be <200 ps.

These output frequencies are generated using non-production engineering modes only for test.

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Si5380 Rev D Data Sheet

Electrical Specifications

Table 5.9. I²C Timing Specifications (SCL, SDA)

Parameter

Symbol

Test Condition

Standard Mode

100 kbps

Fast Mode

400 kbps

Min

Unit

Min

—

Max

100

35

Max

400

35

SCL Clock Frequency

SMBus Timeout

f_SCL

—

kHz

ms

When Timeout is Ena-

bled

25

Hold Time (Repeated)

START Condition

t_HD:STA

4.0

—

0.6

—

µs

Low Period of the SCL Clock

t_LOW

t_HIGH

4.7

4.0

—

1.3

0.6

—

µs

HIGH Period of the SCL

Clock

Set-up Time for a Repeated

START Condition

t_SU:STA

4.7

—

0.6

—

µs

Data Hold Time

t_HD:DAT

t_SU:DAT

t_r

100

250

—

100

20

—

ns

Data Set-up Time

Rise Time of Both SDA and

SCL Signals

1000

300

Fall Time of Both SDA and

SCL Signals

t_f

—

300

—

300

—

ns

µs

Set-up Time for STOP Con-

dition

t_SU:STO

4.0

4.7

0.6

1.3

Bus Free Time between a

t_BUF

—

STOP and START Condition

Data Valid Time

t_VD:DAT

t_VD:ACK

—

3.45

—

0.9

µs

Data Valid Acknowledge

Time

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Si5380 Rev D Data Sheet

Electrical Specifications

Figure 5.1. I²C Serial Prot Timing Standard and Fast Modes

Table 5.10. SPI Timing Specifications (4-Wire)

Parameter

Symbol

f_SPI

Min

—

40

50

—

5

Typ

—

Max

20

60

—

Unit

MHz

%

SCLK Frequency

SCLK Duty Cycle

SCLK Period

T_DC

T_C

ns

Delay Time, SCLK Fall to SDO Active

Delay Time, SCLK Fall to SDO

Delay Time, CSb Rise to SDO Tri-State

Setup Time, CSb to SCLK

T_D1

18

15

—

ns

T_D2

ns

T_D3

ns

T_SU1

T_H1

T_SU2

T_H2

ns

Hold Time, SCLK Fall to CSb

5

—

ns

Setup Time, SDI to SCLK Rise

Hold Time, SDI to SCLK Rise

5

—

ns

5

—

ns

Delay Time Between Chip Selects (CSb)

T_CS

2

—

T_c

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Si5380 Rev D Data Sheet

Electrical Specifications

T_SU1

T_D1

T_C

SCLK

CSb

T_H1

T_SU2

T_H2

T_CS

SDI

T_D2

T_D3

SDO

Figure 5.2. 4-Wire SPI Serial Interface Timing

Table 5.11. SPI Timing Specifications (3-Wire)

Parameter

Symbol

f_SPI

Min

—

40

50

—

5

Typ

Max

20

60

—

Unit

MHz

%

SCLK Frequency

SCLK Duty Cycle

SCLK Period

—

T_DC

T_C

ns

Delay Time, SCLK Fall to SDIO Turn-on

Delay Time, SCLK Fall to SDIO Next-bit

Delay Time, CSb Rise to SDIO Tri-State

Setup Time, CSb to SCLK

T_D1

20

15

—

ns

T_D2

ns

T_D3

ns

T_SU1

T_H1

T_SU2

T_H2

ns

Hold Time, SCLK Fall to CSb

5

—

ns

Setup Time, SDI to SCLK Rise

5

—

ns

Hold Time, SDI to SCLK Rise

5

—

ns

Delay Time Between Chip Selects (CSb)

T_CS

2

—

T_c

T_SU1

T_C

SCLK

T_H1

T_D1

T_D2

CSb

T_SU2

T_H2

T_CS

SDIO

T_D3

Figure 5.3. 3-Wire SPI Serial Interface Timing

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Si5380 Rev D Data Sheet

Electrical Specifications

Table 5.12. Crystal Specifications

Parameter

Crystal Frequency ¹

Symbol

Test Condition

Min

Typ

Max

Unit

f_XTAL

—

–100

—

54

—

MHz

Total Frequency Tolerance ²

Load Capacitance

f_RANGE

C_L

r_ESR

C_O

—

8

+100

—

ppm

pF

Equivalent Series Resistance

Shunt Capacitance

Refer to the Family Reference Manual to determine ESR and shunt capacitance.

Crystal Drive Level

d_L

The crystal resonator

must be able to tolerate

350 µW of drive level

—

350

µW

Notes:

1. See the Si5380 Reference Manual for a list of qualified 54 MHz crystals. The Si5380 is designed to work with crystals that meet

these specifications.

2. Includes initial tolerance, drift after reflow, change over temperature (–40 °C to +85 °C), V_DDvariation, load pulling, and aging.

Table 5.13. Thermal Characteristics ¹

Parameter

Symbol

Test Condition

Value

Unit

Si5380–64QFN

Thermal Resistance

Junction to Ambient

Ɵ_JA

Still Air

22

°C/W

Air Flow 1 m/s

Air Flow 2 m/s

19.4

18.3

9.5

Thermal Resistance

Junction to Case

Thermal Resistance

Junction to Board

Thermal Resistance

Junction to Board

Thermal Resistance

Junction to Top Center

Note:

Ɵ_JC

Ɵ_JB

Ψ_JB

Ψ_JT

9.4

9.3

0.2

1. Based on PCB Dimension: 3x4.5”, PCB Thickness: 1.6 mm, PCB Land/Via: 36, Number of Cu Layers: 4.

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Si5380 Rev D Data Sheet

Electrical Specifications

Table 5.14. Absolute Maximum Ratings ^{1, 2, 3, 4}

Parameter

DC Supply Voltage

Symbol

V_DD

Test Condition

Value

Unit

V

–0.5 to 3.8

–0.85 to 3.8

–0.5 to 3.8

V_DDA

V_DDO

V

5

Input Voltage Range

V_I1

IN0-IN3/FB_IN

IN_SEL[1:0],

V

V_I2

RSTb, PDNb,OEb, SYNCb,

I2C_SEL, SCLK,

A0/CSb, A1/SDO,

SDA/SDIO

V_I3

LU

XA/XB

–0.5 to 2.7

V

Latch-up Tolerance

JESD78 Compliant

ESD Tolerance

HBM

T_STG

T_JCT

T_PEAK

100 pF, 1.5 kΩ

2.0

–55 to 150

125

kV

°C

Storage Temperature Range

Max Junction Temperature in Operation

Soldering Temperature (Pb-free profile) ⁴

260

Soldering Temperature Time at T_PEAK(Pb-

free profile) ⁴

T_P

20 to 40

sec

Notes:

1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to

the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for ex-

tended periods may affect device reliability.

2. 64-QFN is RoHS-6 compliant.

3. For MSL rating and additional packaging information, go to http://www.silabs.com/support/quality/pages/RoHSInformation.aspx.

4. The device is compliant with JEDEC J-STD-020.

5. The minimum voltage at these pins can be as low as -1.0 V when an AC input signal is applied. See Table 5.3 Input Clock Speci-

fications on page 24 spec for Single-ended AC-coupled f_IN< 245.76 MHz.

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Si5380 Rev D Data Sheet

Typical Application Diagrams

6. Typical Application Diagrams

IEEE

1588

GPS

N

Rx

ADC

LNA

0

90

CPRI

Stratum 3/

3E DPLL

ASIC

Tx

PA

N

DAC

0

90

OCXO

RF

Synth

Recovered Clock

30.72MHz x N

Base Band Unit

LTE

Sampling

Clocks

RF

Synth

Remote Radio

Head

Figure 6.1. LTE Base Station Remote Radio Head

IEEE

1588

JESD

204B

GPS

Rx

A/D

LNA

0

90

JESD

204B

A/D

CPRI

Stratum 3/

3E DPLL

Tx

ASIC

JESD

204B

ASIC

PA

D/A

0

90

JESD

204B

OCXO

D/A

RF

Synth

Base Band Unit

RF

Synth

DCLK

SYSREF

DCLK

SYSREF

DCLK

SYSREF

Remote Radio

Head

Recovered Clock

30.72MHz x N

Figure 6.2. LTE Base Station Using JESD204B Data Converters

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Si5380 Rev D Data Sheet

Detailed Block Diagram

7. Detailed Block Diagram

54MHz

XTAL

Si5380

XA

XB

IN_SEL

OSC

÷R_0A

OUT0A

÷P₀

÷P₁

÷P₂

IN0

IN1

IN2

÷R₀

÷R₁

÷R₂

÷R₃

÷R₄

OUT0

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

OUT7

DSPLL

IN3/

FB_IN

÷P₃

t₀

÷N₀

I2C_SEL

SDA/SDI

A1/SDO

SCLK

t₁

÷N₁

I²C/

SPI

÷R₅

÷R₆

÷R₇

÷N₂

÷N₃

t²

A0/CSb

NVM

t³

t₄

÷N₄

÷R₈

÷R₉

OUT8

OUT9

INTRb

LOLb

Status Monitor

÷R_9A

OUT9A

SYNCb

OEb

PDNb

RSTb

Figure 7.1. Si5380 Block Diagram

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Si5380 Rev D Data Sheet

Typical Operating Characteristics (Phase Noise & Jitter)

8. Typical Operating Characteristics (Phase Noise & Jitter)

Figure 8.1. Input = 61.44 MHz; Output = 983.04 MHz, 3.3 V LVPECL

Figure 8.2. Input = 61.44 MHz; Output = 1,474.56 MHz, 3.3 V LVPECL

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Si5380 Rev D Data Sheet

Typical Operating Characteristics (Phase Noise & Jitter)

Figure 8.3. Input = 61.44 MHz; Output = 245.76 MHz, 3.3 V LVPECL

Figure 8.4. Input = 61.44 MHz; Output = 122.88 MHz, 3.3 V LVPECL

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Si5380 Rev D Data Sheet

Pin Description

9. Pin Description

48 SYNCb

1

2

IN1

IN1b

47

LOLb

46

3

VDD

IN_SEL0

IN_SEL1

PDNb

RSTb

X1

45

4

OUT6

44

5

OUT6b

43

6

VDDO6

42

7

OUT5

41

40

39

38

37

36

35

34

33

8

OUT5b

VDDO5

I2C_SEL

OUT4

XA

GND

Pad

9

XB

10

11

12

13

14

15

16

X2

OEb

OUT4b

VDDO4

OUT3

INTRb

VDDA

IN2

OUT3b

VDDO3

IN2b

SCLK

Figure 9.1. Si5380 64-QFN Top View

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Si5380 Rev D Data Sheet

Pin Description

Table 9.1. Pin Descriptions

Pin Type¹

Pin Name

Pin Number

Function

XA

XB

8

9

I

Crystal Input. Input pin for external crystal (XTAL). Alterna-

tively these pins can be driven with an external reference

clock (REFCLK). An internal register bit selects XTAL or

REFCLK mode. Default is XTAL mode. Single-ended inputs

must be connected to the XA pin, with the XB pin appropri-

ately terminated.

X1

X2

7

I

XTAL Shield. Connect these pins directly to the crystal

ground pins. Both the X1/X2 pins and Crystal ground pins

should be separated from the PCB ground plane. Refer to

the Reference Manual for layout guidelines.

10

IN0

IN0b

63

64

1

I

Clock Inputs. These pins accept an input clock for syn-

chronizing the device. They support both differential and

single-ended clock signals. Refer to 3.3.1 Input Configura-

tion and Terminations for input termination options. These

pins are high-impedance and must be terminated externally,

when being used. The negative side of the differential input

must be ac-grounded when accepting a single-ended clock.

Unused inputs may be left unconnected.

IN1

IN1b

2

IN2

14

15

61

62

IN2b

IN3/FB_IN

IN3b/FB_INb

Clock Input 3/External Feedback Input.

By default, these pins are used as the 4^thclock input (IN3/

IN3b). They can also be used as the external feedback in-

put (FB_IN/FB_INb) for the optional zero delay mode. See

section 5.3.6 for details on the optional zero delay mode.

Outputs

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Si5380 Rev D Data Sheet

Pin Description

Pin Type¹

Pin Name

Pin Number

Function

OUT0A

OUT0Ab

OUT0

21

20

24

23

28

27

31

30

35

34

38

37

42

41

45

44

51

50

54

53

56

55

59

58

O

Output Clocks. These output clocks support programma-

ble signal amplitude and common mode voltage. Desired

output signal format is configurable using register control.

Termination recommendations are provided in

3.5.5 LVCMOS Output Terminations. Unused outputs

should be left unconnected.

OUT0b

OUT1

OUT1b

OUT2

OUT2b

OUT3

OUT3b

OUT4

OUT4b

OUT5

OUT5b

OUT6

OUT6b

OUT7

OUT7b

OUT8

OUT8b

OUT9

OUT9b

OUT9A

OUT9Ab

Serial Interface

I2C_SEL

I2C Select. This pin selects the serial interface mode as I²C

(I2C_SEL = 1) or SPI (I2C_SEL = 0). This pin is internally

pulled high.

39

18

I

SDA/SDIO

I/O

Serial Data Interface. This is the bidirectional data pin

(SDA) for the I²C mode, the bidirectional data pin (SDIO) in

the 3-wire SPI mode, or the input data pin (SDI) in 4-wire

SPI mode. When in I²C mode or unused, this pin must be

pulled-up using an external resistor of >= 1 kΩ. No pull-up

resistor is needed when in SPI mode.

Address Select 1/Serial Data Output. In I²C mode this pin

functions as the A1 address input pin. In 4-wire SPI mode,

this is the serial data output (SDO) pin. This pin should be

externally pulled up or down when unused.

A1/SDO

SCLK

17

16

I/O

I

Serial Clock Input. This pin functions as the serial clock in-

put for both I²C and SPI modes. When in I²C mode or un-

used, this pin must be pulled-up using an external resistor

of >= 1 kΩ. No pull-up resistor is needed when in SPI mode.

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Rev. 1.0 | 42

Si5380 Rev D Data Sheet

Pin Description

Pin Type¹

Pin Name

Pin Number

Function

A0/CSb

19

I

Address Select 0/Chip Select. This pin functions as the

hardware controlled address A0 in I²C mode. In SPI mode,

this pin functions as the chip select input (active low). This

pin is internally pulled-up.

Control/Status

Interrupt. ²This pin is asserted low when a change in de-

vice status has occurred. This pin must be pulled-up exter-

nally using a resistor of >= 1 kΩ. It should be left unconnec-

ted when not in use.

INTRb

12

O

Power Down. ²The device enters into a low power mode

when this pin is pulled low. This pin is internally pulled-up. It

can be left unconnected when not in use.

PDNb

RSTb

5

6

I

Device Reset. ²Active low input that performs power-on re-

set (POR) of the device. Resets all internal logic to a known

state and forces the device registers to their default values.

Clock outputs are disabled during reset. This pin is internal-

ly pulled-up.

Output Enable. ²This pin disables all outputs when held

high. This pin is internally pulled low and can be left uncon-

nected when not in use.

OEb

11

47

I

Loss Of Lock. ²This output pin indicates when the DSPLL

is locked (high) or out-of-lock (low). When in use, this pin

must be pulled-up using an external resistor of >= 1 kΩ. It

can be left unconnected when not in use.

LOLb

O

Output Clock Synchronization. ²An active low signal on

this pin resets the output dividers for the purpose of re-

aligning the output clocks. This pin is internally pulled-up

and can be left unconnected when not in use.

SYNCb

48

I

Input Reference Select. ²The IN_SEL[1:0] pins are used

in manual pin controlled mode to select the active clock in-

put as shown in Table 3.2 Table 6.2 on page 10. These pins

are internally pulled-down and may be left unconnected

when unused.

IN_SEL0

IN_SEL1

3

4

I

RSVD

Power

VDD

25

Reserved. Leave disconnected.

32

46

60

13

P

Core Supply Voltage. The device operates from a 1.8 V

supply. A 1 µF bypass capacitor should be placed very

close to each pin.

VDD

VDDA

Core Supply Voltage 3.3 V. This core supply pin requires a

3.3 V power source. A 1 µF bypass capacitor should be

placed very close to this pin.

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Rev. 1.0 | 43

Si5380 Rev D Data Sheet

Pin Description

Pin Type¹

Pin Name

Pin Number

Function

VDDO0

VDDO1

VDDO2

VDDO3

VDDO4

VDDO5

VDDO6

VDDO7

VDDO8

VDDO9

GND PAD

22

26

29

33

36

40

43

49

52

57

P

Output Clock Supply Voltage. Supply voltage (3.3 V, 2.5

V, 1.8 V) for OUTx, OUTxb Outputs. Note that VDDO0

supplies power to OUT0 and OUT0A; VDDO9 supplies

power to OUT9 and OUT9A. Leave VDDO pins of unused

output drivers unconnected. An alternative option is to con-

nect the VDDO pin to a power supply and disable the output

driver to minimize current consumption. A 1 µF bypass ca-

pacitor should be placed very close to each connected

VDDO pin.

Ground Pad. This pad provides connection to ground and

must be connected for proper operation.

Note:

1. I = Input, O = Output, P = Power

2. The IO_VDD_SEL control bit (0x0943 bit 0) selects 3.3 V or 1.8 V operation.

3. All status pins except I2C and SPI are push-pull.

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Rev. 1.0 | 44

Si5380 Rev D Data Sheet

Package Outline

10. Package Outline

Figure 10.1. Si5380 9x9 mm 64-QFN Package Diagram

Table 10.1. Package Diagram Dimensions

Dimension

MIN

0.80

0.00

0.18

NOM

0.85

MAX

0.90

0.05

0.30

A

A1

0.02

b

0.25

D

9.00 BSC

5.20

D2

5.10

5.30

e

0.50 BSC

9.00 BSC

5.20

E

E2

5.10

0.30

—

5.30

0.50

0.15

0.10

0.08

0.10

L

0.40

aaa

—

bbb

—

ccc

—

ddd

—

Note:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

3. This drawing conforms to the JEDEC Solid State Outline MO-220.

4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.

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Rev. 1.0 | 45

Si5380 Rev D Data Sheet

PCB Land Pattern

11. PCB Land Pattern

Figure 11.1. 9x9 mm 64-QFN Land Pattern

Table 11.1. PCB Land Pattern Dimensions

Dimension

Max

8.90

0.50

0.30

0.85

5.30

C1

C2

E

X1

Y1

X2

Y2

Notes:

General

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. This Land Pattern Design is based on the IPC-7351 guidelines.

3. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition is calculated based on a fabrication

Allowance of 0.05 mm.

Solder Mask Design

1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 μm

minimum, all the way around the pad.

Stencil Design

1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.

2. The stencil thickness should be 0.125 mm (5 mils).

3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.

4. A 3x3 array of 1.25 mm square openings on 1.80 mm pitch should be used for the center ground pad.

Card Assembly

1. A No-Clean, Type-3 solder paste is recommended.

2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.

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Rev. 1.0 | 46

Si5380 Rev D Data Sheet

Top Marking

12. Top Marking

Si5380A-

Rxxxxx-GM

YYWWTTTTTT

e4

TW

64-QFN

Figure 12.1. Si5380 Top Marking

Table 12.1. Top Marking Explanation

Line

Characters

Description

1

Si5380A-

Base part number for Ultra Low Phase Noise, 12-output JESD204B Clock Generator:

Si5380A: 12-output clock generator; 64-QFN

– = Dash character.

2

Rxxxxx-GM

R = Product revision. (See Ordering Guide for current ordering revision).

xxxxx = Customer specific NVM sequence number. Optional NVM code assigned for

custom, factory pre-programmed devices.

Characters are not included for standard, factory default configured devices. See Or-

dering Guide for more information.

-GM = Package (QFN) type and temperature range (–40 to +85 °C).

3

YYWWTTTTTT

YYWW = Characters correspond to the year (YY) and work week (WW) of package

assembly.

TTTTTT = Manufacturing trace code.

Pin 1 indicator; left-justified

4

Circle w/ 1.6 mm diameter

e4

Pb-free symbol; Center-Justified

TW

TW = Taiwan; Country of Origin (ISO Abbreviation)

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Rev. 1.0 | 47

Si5380 Rev D Data Sheet

Device Errata

13. Device Errata

Log in or register at www.silabs.com to access the device errata document.

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Rev. 1.0 | 48

Si5380 Rev D Data Sheet

Document Change List

14. Document Change List

14.1 Revision 1.0

July 19, 2016

• Initial release.

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Rev. 1.0 | 49

Table of Contents

1. Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

3. Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

3.1 Frequency Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 3

3.1.1 Si5380 LTE Frequency Configuration . . . . . . . . . . . . . . . . . . . . . 3

3.1.2 Si5380 Configuration for JESD204B Clock Generation . . . . . . . . . . . . . . . 4

3.1.3 DSPLL Loop Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3.1.4 Fastlock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3.1.5 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3.1.6 Initialization and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3.1.7 Freerun Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3.1.8 Lock Acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3.1.9 Locked Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.1.10 Holdover Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.2 External Reference (XA/XB) . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.3 Inputs (IN0, IN1, IN2, IN3/FB_IN) . . . . . . . . . . . . . . . . . . . . . . . 8

3.3.1 Input Configuration and Terminations . . . . . . . . . . . . . . . . . . . . . 9

3.3.2 Manual Input Selection (IN0, IN1, IN2, IN3/FB_IN) . . . . . . . . . . . . . . . . . 9

3.3.3 Automatic Input Switching (IN0, IN1, IN2, IN3/FB_IN) . . . . . . . . . . . . . . . .10

3.3.4 Hitless Input Switching . . . . . . . . . . . . . . . . . . . . . . . . . .10

3.3.5 Ramped Input Switching. . . . . . . . . . . . . . . . . . . . . . . . . .10

3.3.6 Glitchless Input Switching . . . . . . . . . . . . . . . . . . . . . . . . .10

3.3.7 Zero Delay Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

3.4 Fault Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

3.4.1 Input LOS Detection . . . . . . . . . . . . . . . . . . . . . . . . . . .12

3.4.2 XA/XB LOS Detection . . . . . . . . . . . . . . . . . . . . . . . . . .12

3.4.3 OOF Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

3.4.4 Precision OOF Monitor . . . . . . . . . . . . . . . . . . . . . . . . . .13

3.4.5 Fast OOF Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

3.4.6 LOL Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

3.4.7 Interrupt Pin INTRb . . . . . . . . . . . . . . . . . . . . . . . . . . .15

3.5 Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

3.5.1 Output Crosspoint . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

3.5.2 Output Signal Format. . . . . . . . . . . . . . . . . . . . . . . . . . .15

3.5.3 Output Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . .16

3.5.4 Programmable Common Mode Voltage For Differential Outputs . . . . . . . . . . . .16

3.5.5 LVCMOS Output Terminations . . . . . . . . . . . . . . . . . . . . . . .16

3.5.6 LVCMOS Output Impedance and Drive Strength Selection . . . . . . . . . . . . . .17

3.5.7 LVCMOS Output Signal Swing . . . . . . . . . . . . . . . . . . . . . . .17

3.5.8 LVCMOS Output Polarity . . . . . . . . . . . . . . . . . . . . . . . . .17

3.5.9 Output Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . .17

3.5.10 Output Disable During LOL . . . . . . . . . . . . . . . . . . . . . . . .17

3.5.11 Output Disable During XAXB_LOS. . . . . . . . . . . . . . . . . . . . . .17

3.5.12 Output Driver State When Disabled . . . . . . . . . . . . . . . . . . . . .17

Table of Contents 50

3.5.13 Synchronous Enable/Disable Feature . . . . . . . . . . . . . . . . . . . . .17

3.5.14 Output Skew Control (Δt - Δt ) . . . . . . . . . . . . . . . . . . . . . . .18

0

4

3.5.15 Output Divider (R) Synchronization. . . . . . . . . . . . . . . . . . . . . .18

3.6 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

3.6.1 Power Down Pin (PDNb) . . . . . . . . . . . . . . . . . . . . . . . . .19

3.7 In-Circuit Programming. . . . . . . . . . . . . . . . . . . . . . . . . . .19

3.8 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

3.9 Custom Factory Preprogrammed Devices . . . . . . . . . . . . . . . . . . . .19

3.10 Enabling Features and/or Configuration Settings Not Available in ClockBuilder Pro for Factory Pre-

programmed Devices

. . . . . . . . . . . . . . . . . . . . . . . . . . 1.9

4. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6. Typical Application Diagrams . . . . . . . . . . . . . . . . . . . . . . . . 36

7. Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 37

8. Typical Operating Characteristics (Phase Noise & Jitter) . . . . . . . . . . . . . . 38

9. Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

10. Package Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

11. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

12. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

13. Device Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

14. Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . 49

14.1 Revision 1.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Table of Contents 51

ClockBuilder Pro

One-click access to Timing tools,

documentation, software, source

code libraries & more. Available for

Windows and iOS (CBGo only).

www.silabs.com/CBPro

Timing Portfolio

www.silabs.com/timing

SW/HW

www.silabs.com/CBPro

Quality

www.silabs.com/quality

Support and Community

community.silabs.com

Disclaimer

Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using

or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and

"Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories reserves the right to

make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the

included information. Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply or express copyright licenses

granted hereunder to design or fabricate any integrated circuits. The products are not designed or authorized to be used within any Life Support System without the specific written consent

of Silicon Laboratories. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant

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型号：	SI5380-D
厂家：	SILICON
描述：	Ultra-Low Phase Noise, 12-output JESD204B Clock Generator
文件：	总53页 (文件大小：1431K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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