SI5380-EVB [SILICON]
Ultra-Low Phase Noise, 12-output JESD204B Clock Generator;型号: | SI5380-EVB |
厂家: | SILICON |
描述: | Ultra-Low Phase Noise, 12-output JESD204B Clock Generator |
文件: | 总50页 (文件大小:1109K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Ultra-Low Phase Noise, 12-output JESD204B
Clock Generator
Si5380 Data Sheet
The Si5380 is a high performance, integer-based (M/N) clock generator for small cell ap-
plications which demand the highest level of integration and phase noise performance.
KEY FEATURES
Based on Silicon Laboratories’ 4th generation DSPLL technology, the Si5380 combines
• Digital frequency synthesis eliminates
frequency synthesis and jitter attenuation in a highly integrated digital solution that elimi-
external VCXO and analog loop filter
nates the need for external VCXO and loop filter components. A low cost, fixed-frequen-
components
cy crystal provides frequency stability for free-run and holdover modes. This all-digital
• Supports JESD204B clocking: DCLK and
SYSREF
solution provides superior performance that is highly immune to external board distur-
bances such as power supply noise.
• Input frequency range:
Applications
• Differential: 10 MHz – 750 MHz
• LVCMOS: 10 MHz – 250 MHz
• JESD204B clock generation
• Output frequency range:
• Differential: 480 kHz – 1.47456 GHz
• Remote Radio Units (RRU), Remote Access Networks (RAN), picocells, small cells
• Wireless base stations (3G, GSM, W-CDMA, 4G/LTE, LTE-A)
• Remote Radio Head (RRH), wireless repeaters, wireless backhaul
• Data conversion sampling clocks (ADC, DAC, DDC, DUC)
• LVCMOS: 480 kHz – 250 MHz
54MHz
XTAL
XA
Si5380
XB
IN_SEL
OSC
÷R0A
÷R0
÷R1
÷R2
÷R3
÷R4
÷R5
÷R6
÷R7
OUT0A
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
IN0
IN1
IN2
÷P0
÷P1
÷P2
÷P3
DSPLL
IN3/
FB_IN
t0
t1
÷N0
÷N1
÷N2
÷N3
I2C_SEL
SDA/SDI
A1/SDO
SCLK
I2C/
SPI
t2
t3
t4
A0/CSb
NVM
OUT7
OUT8
OUT9
OUT9A
÷N4
÷R8
÷R9
INTRb
LOLb
Status
Monitor
÷R9A
SYNCb
OEb
PDNb RSTb
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Si5380 Data Sheet
Feature List
1. Feature List
The Si5380 highlighted features are listed below.
• Digital frequency synthesis eliminates external VCXO and an-
alog loop filter components
• Optional Zero Delay mode
• Independent output supply pins: 3.3, 2.5, or 1.8 V
• Core voltage:
• Supports JESD204B clocking: DCLK and SYSREF
• Input frequency range:
• VDD = 1.8 V ±5%
• Differential: 10 MHz – 750 MHz
• LVCMOS: 10 MHz – 250 MHz
• Output frequency range:
• VDDA = 3.3 V ±5%
• Automatic free-run, lock, and holdover modes
• Digitally selectable loop bandwidth: 0.1 Hz to 4 kHz
• Hitless input clock switching
• Differential: up to 1.47456 GHz
• LVCMOS: up to 250 MHz
• Status monitoring (LOS, OOF, LOL)
• Excellent jitter performance:
• 70 fs typ (12 kHz – 20 MHz)
• Phase noise floor: –159 dBc/Hz
• Serial interface: I2C or SPI In-circuit programmable with non-
volatile OTP memory
ClockBuilderTM Pro software tool simplifies device configura-
tion
•
• Spur performance: –103 dBc max (relative to a 122.88 MHz
carrier)
• 4 input, 12 output, 64QFN
• Configurable outputs:
• Temperature range: –40 to +85 °C
• Pb-free, RoHS-6 compliant
• Signal swing: 200 to 3200 mVpp
• Compatible with LVDS, LVPECL
• LVCMOS 3.3, 2.5, or 1.8 V
• Output-output skew: 20 ps (typical, same N-divider)
• Adjustable output-output delay: 68 ps/step, ±128 steps
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Si5380 Data Sheet
Ordering Guide
2. Ordering Guide
Table 2.1. Ordering Guide
Ordering Part Number
Number of
Outputs
Output Clock
Frequency
Range
Package
RoHS-6, Pb-Free
Temperature
Range
Si5380A-B-GM
12
480 kHz—
1.47456 GHz
64-Lead 9x9 mm
QFN
Yes
–40 to +85 °C
Si5380-EVB
Evaluation Board
Note:
1. Add an “R” at the end of the device to denote tape and reel options.
2. Custom, factory pre-programmed devices are available. Ordering part numbers are assigned by ClockBuilder Pro. Part number
format is: Si5380A-Bxxxxx-GM, where “xxxxx” is a unique numerical sequence representing the pre-programmed configuration.
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Si5380 Data Sheet
Functional Description
3. Functional Description
The Si5380 is a high performance clock generator that is capable of synthesizing up to 10 unique integer related frequencies at any of
the device’s 12 outputs. The output clocks can be generated in free-run mode or synchronized to any one of the four external inputs.
Clock generation is provided by Silicon Laboratories’ 4th generation DSPLL technology which combines frequency synthesis and jitter
attenuation in a highly integrated digital solution that eliminates the need for external VCXO and loop filter components. The Si5380
device is fully configurable using the I2C or SPI serial interface and has in-circuit programmable non-volatile memory.
3.1 Frequency Configuration
The DSPLL provides the synthesis for generating the output clock frequencies which are synchronous to the selected input clock fre-
quency or free-running XTAL. It consists of a phase detector, a programmable digital loop filter, a high-performance ultra-low phase
noise analog 15 GHz VCO, and a user configurable feedback divider. An internal oscillator (OSC) provides the DSPLL with a stable
low-noise clock source for frequency synthesis and for maintaining frequency accuracy in the free-run or holdover modes. The oscillator
simply requires an external, low cost 54 MHz fundamental mode crystal to operate. No other external components are required for fre-
quency generation. A key feature of this DSPLL is that it provides immunity to external noise coupling from power supplies and other
uncontrolled noise sources that normally exist on printed circuit boards.
3.1.1 Si5380 LTE Frequency Configuration
The device’s frequency configuration is fully programmable through the serial interface and can also be stored in non-volatile memory.
The combination of flexible integer dividers and a high frequency VCO allows the device to generate multiple output clock frequencies
for applications that require ultra-low phase noise and spurious performance. At the core of the device are the N dividers which deter-
mine the number of unique frequencies that can be generated from the device. The table below shows a list of possible output frequen-
cies for LTE applications. The Si5380’s DSPLL core can generate up to five unique frequencies. These frequencies are distributed to
the output dividers using a configurable crosspoint mux. The R dividers allow further division for up to 10 unique integer-ratio related
frequencies on the Si5380. The ClockBuilder Pro software utility provides a simple means of automatically calculating the optimum di-
vider values (P, M, N and R) for the frequencies listed in the table below.
Table 3.1. Example of Possible LTE Clock Frequencies
Fin (MHz)1
15.36
19.20
30.72
38.40
61.44
76.80
122.88
153.60
184.32
245.76
307.20
368.64
491.52
614.40
737.28
—
LTE Device Clock Frequencies Fout (MHz)2
15.36
19.20
30.72
38.40
61.44
76.80
122.88
153.60
184.32
245.76
307.20
368.64
491.52
614.40
737.28
983.04
1228.80
1474.56
—
—
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Si5380 Data Sheet
Functional Description
Fin (MHz)1
LTE Device Clock Frequencies Fout (MHz)2
Note:
1. The Si5380 locks to any one of the frequencies listed in the Fin column and generates LTE device clock frequencies.
2. R output dividers allow other frequencies to be generated. These are useful for applications like JESD204B SYSREF clocks.
3.1.2 Si5380 Configuration for JESD204B Clock Generation
The Si5380 can be used as a high performance, fully integrated JEDEC JESD204B jitter cleaner while eliminating the need for discrete
VCXO and loop filter components. The Si5380 supports JESD204B subclass 0 and subclass 1 clocking by providing both device clocks
(DCLK) and system reference clocks (SYSREF). The 12 clock outputs can be independently configured as device clocks or SYSREF
clocks to drive JESD204B converters, FPGAs, or other logic devices. The Si5380 will clock up to four JESD204B targets using four or
more DCLKs and four SYSREF clocks with adjustable delay.Each DCLK is grouped with a SYSREF clock in this configuration.If SYS-
REF clocking is implemented in external logic, then the Si5380 will clock up to 12 JESD204B targets.Not limited to JESD204B applica-
tions, each of the 12 outputs is individually configurable as a high performance output for traditional clocking applications. An example
of a JESD204B frequency configuration is shown in the figure below. In this case, the N dividers determine the device clock frequency
and the R dividers provide the divided SYSREF clock which is used as the lower frequency frame clock. The N divider path also in-
cludes a configurable delay path (∆t) for controlling deterministic latency. The example shows a configuration where all the device
clocks are controlled by a single delay path (∆t0) while the SYSREF clocks each have their own independent delay paths (∆t1 – ∆t4),
though other combinations are also possible. Delay is programmable in steps of 68 ps in the range of ±128 steps (±8.6 ns). See the
3.5.15 Output Skew Control (Δt0 - Δt4) section for details on skew control. The SYSREF clock is always periodic and can be controlled
(on/off) without glitches by enabling or disabling its output through register writes.
IN_SEL[1:0]
Si5380
IN0
÷P0
IN0b
IN1
DSPLL
÷P1
IN1b
PD LPF
IN2
÷P2
IN2b
IN3/FB_IN
÷M
÷5
÷P3
IN3b/FB_INb
VDDO0
OUT0A
OUT0Ab
÷R0A
÷R0
OUT0
OUT0b
VDDO5
OUT5
OUT5b
÷R5
÷R6
÷R7
÷R8
VDDO6
OUT6
OUT6b
Device
Clocks
t0
÷N0
VDDO7
OUT7
OUT7b
VDDO8
OUT8
OUT8b
OUT9
OUT9b
÷R9
OUT9A
OUT9Ab
÷R9A
VDDO9
VDDO1
OUT1
OUT1b
t1
÷N1
÷N2
÷N3
÷N4
÷R1
÷R2
÷R3
÷R4
VDDO2
OUT2
OUT2b
SYSREF
Clocks
t2
t3
t4
VDDO3
OUT3
OUT3b
VDDO4
OUT4
OUT4b
Figure 3.1. Example Divider Configuration for Generating JESD204B Subclass 1 Clocks
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Si5380 Data Sheet
Functional Description
3.1.3 DSPLL Loop Bandwidth
The DSPLL loop bandwidth determines the amount of input clock jitter attenuation. Register configurable DSPLL loop bandwidth set-
tings in the range of 0.1 Hz to 100 Hz are available for selection. The DSPLL will always remain stable with less than 0.1 dB of peaking
regardless of the DSPLL loop bandwidth selection.
3.1.4 Fastlock Feature
Selecting a low DSPLL loop bandwidth (e.g., 1 Hz) will generally lengthen the lock acquisition time. The fastlock feature allows setting a
temporary fastlock loop bandwidth that is used during the lock acquisition process. Higher fastlock loop bandwidth settings will enable
the DSPLL to lock faster. Once lock acquisition has completed, the DSPLL’s loop bandwidth will automatically revert to the DSPLL
Loop Bandwidth setting. Fastlock loop bandwidth settings in the range of 100 Hz to 4 kHz are available for selection. The fastlock fea-
ture can be enabled or disabled by register configuration.
3.1.5 Modes of Operation
Once initialization is complete, the Si5380 operates in one of four modes: Free-run Mode, Lock Acquisition Mode, Locked Mode, or
Holdover Mode. A state diagram showing the modes of operation is shown in the figure below. The following sections describe each of
these modes in greater detail.
Power-Up
Reset and
Initialization
No valid
input clocks
selected
Free-run
Valid input clock
selected
An input is qualified
and available for
selection
Lock Acquisition
(Fast Lock)
Phase lock on
selected input
clock is achieved
Holdover
Mode
No
Selected input
clock fails
Is holdover
history valid?
Locked
Mode
Figure 3.2. Modes of Operation
3.1.6 Initialization and Reset
When power is applied, the device begins an initialization period where it downloads default register values and configuration data from
NVM and performs other initialization tasks. Communicating with the device through the serial interface is possible once this initializa-
tion period is complete. No clocks will be generated until the initialization is complete. There are two types of resets available. A hard
reset is functionally similar to a device power-up. All registers will be restored to the values stored in NVM and all circuits, including the
serial interface, will be restored to their initial state. A hard reset is initiated using the RSTb pin or by asserting the hard reset bit. A soft
reset bypasses the NVM download. It is simply used to initiate register configuration changes.
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Si5380 Data Sheet
Functional Description
3.1.7 Freerun Mode
Once power is applied to the Si5380 and initialization is complete, the device will automatically enter freerun mode. Output clocks will
be generated on the outputs with their configured frequencies. The frequency accuracy of the generated output clocks in freerun mode
is dependent on the frequency accuracy of the external crystal or reference clock on the XA/XB pins. For example, if the crystal
frequency is ±100 ppm, then all the output clocks will be generated at their configured frequency ±100 ppm in freerun mode. Any
change or drift of the crystal frequency or external reference on the XA/XB pins will be tracked at the output clock frequencies.
3.1.8 Lock Acquisition
If a valid input clock is selected for synchronization, the DSPLL will automatically start the lock acquisition process. If the fast lock fea-
ture is enabled, the DSPLL will acquire lock using the Fastlock Loop Bandwidth setting and then transition to the DSPLL Loop Band-
width setting when lock acquisition is complete. During lock acquisition the outputs will generate a clock that follows the VCO frequency
change as it pulls-in to the input clock frequency.
3.1.9 Locked Mode
Once lock is achieved, the Si5380 will generate output clocks that are both frequency and phase locked to the input clock. The DSPLL
will provide jitter attenuation of the input clock using the selected DSPLL loop bandwidth. At this point, any XTAL frequency drift outside
of the loop bandwidth will not affect the output frequencies. When lock is achieved, the LOLb pin will output a logic high level. The LOL
status bit and LOLb status pin will also indicate that the DSPLL is locked. See the 3.4.6 LOL Detection section for more details on LOLb
detection time.
3.1.10 Holdover Mode
The DSPLL will automatically enter holdover mode when the selected input clock becomes invalid and no other valid input clocks are
available for selection. The DSPLL uses an averaged input clock frequency as its final holdover frequency to minimize the disturbance
of the output clock phase and frequency when an input clock suddenly fails. The holdover circuit stores up to 120 seconds of historical
frequency data while the DSPLL is locked to a valid clock input. The final averaged holdover frequency value is calculated from a pro-
grammable window within the stored historical frequency data. Both the window size and the delay are programmable as shown in the
figure below. The window size determines the amount of holdover frequency averaging. The delay value allows ignoring frequency data
that may be corrupt just before the input clock failure.
Figure 3.3. Programmable Holdover Window
Clock Failure
and Entry into
Holdover
Historical Frequency Data Collected
time
Programmable historical data window
Programmable delay
used to determine the final holdover value
120s
0s
30ms, 60ms, 1s,10s, 30s, 60s
1s,10s, 30s, 60s
When entering holdover, the DSPLL will pull the output clock frequencies referred to the calculated averaged holdover frequency. While
in holdover, the output frequency drift is entirely dependent on the external crystal or external reference clock connected to the XA/XB
pins. If a new clock input becomes valid, the DSPLL will automatically exit the holdover mode and re-acquire lock to the new input
clock. This process involves pulling the output clock frequencies to achieve frequency and phase lock with the new input clock. This
pull-in process is glitchless and its rate is controlled by the DSPLL bandwidth and the Fastlock bandwidth. These options are register
programmable.
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Si5380 Data Sheet
Functional Description
3.2 External Reference (XA/XB)
An external crystal (XTAL) is used in combination with the internal oscillator (OSC) to produce an ultra-low phase noise reference clock
for the DSPLL and for providing a stable reference for the free-run and holdover modes. A simplified diagram is shown in the figure
below. The Si5380 includes internal XTAL loading capacitors which eliminates the need for external capacitors and also has the benefit
of reduced noise coupling from external sources. Refer to the Table 5.12 Crystal Specifications on page 32 for crystal specifications.
A crystal frequency of 54 MHz is required, with a total accuracy of ±100 ppm* recommended for best performance. The Si5380 includes
built-in XTAL load capacitors (CL) of 8 pF, which are switched out of the circuit when using an external XO. The Si5380 Reference
Manual provides additional information on PCB layout recommendations for the crystal to ensure optimum jitter performance. The
Si5380 can also accommodate an external reference clock (REFCLK) instead of a crystal. Selection between the external XTAL or
REFCLK is controlled by register configuration. The internal crystal loading capacitors (CL) are disabled in this mode. It is important to
note that when using the REFCLK option the close-in phase noise of the outputs is directly affected by the phase noise of the external
XO reference. Refer to the Table 5.3 Input Clock Specifications on page 23 for REFCLK requirements when using this mode.
Note: Including initial frequency tolerance and frequency variation over the full operating temperature range, voltage range, load condi-
tions, and aging.
Differential Connection
Single-ended XO Connection
X1
nc
X1
nc
X2
nc
X2
nc
0.1 uf
Note: 2.0 Vpp_se max
2xCL
2xCL
0.1 uf
XA
XA
0.1 uf
OSC
OSC
XB
XO with Clipped Sine
Wave Output
XB
0.1 uf
2xCL
2xCL
Si5380
Si5380
0.1 uf
Note: 2.5 Vpp diff max
Crystal Connection
Single-ended Connection
X1
nc
X2
nc
Note: 2.0 Vpp_se max
X1
2xCL
CMOS/XO
Output
2xCL
XA
0.1 uf
XA
R1
XTAL
OSC
OSC
R2
0.1 uf
XB
0.1 uf
XB
X2
2xCL
2xCL
Si5380
Si5380
Figure 3.4. XAXB Crystal Resonator and External Reference Clock Connection Options
3.3 Inputs (IN0, IN1, IN2, IN3/FB_IN)
Four clock inputs are available to synchronize the DSPLL. The inputs are compatible with both single-ended and differential signals.
Input selection can be manual (pin or register controlled) or automatic with definable priorities.
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Si5380 Data Sheet
Functional Description
3.3.1 Input Configuration and Terminations
Each of the inputs can be configured as differential or single-ended LVCMOS. The recommended input termination schemes are shown
in the figure below. Standard 50% duty cycle signals must be ac-coupled, while low duty cycle Pulsed CMOS signals can be DC-cou-
pled. Unused inputs can be disabled and left unconnected when not in use.
Standard AC-coupled Differential LVDS
Si5380
50
Standard
INx
100
3.3 V, 2.5 V
LVDS or
CML
INxb
50
Pulsed CMOS
Standard AC-coupled Differential LVPECL
Si5380
50
Standard
INx
100
INxb
50
3.3 V, 2.5 V
LVPECL
Pulsed CMOS
Standard AC-coupled Single-ended
Si5380
50
Standard
INx
3.3 V, 2.5 V, 1.8 V
LVCMOS
INxb
Pulsed CMOS
Pulsed CMOS DC-coupled Single-ended
Si5380
R1
Standard
INx
50
R2
INxb
3.3 V, 2.5 V, 1.8 V
LVCMOS
Pulsed CMOS
Resistor values for
fIN_PULSED < 1 MHz
VDD
1.8V
2.5V
3.3V
R1 (Ω)
549
680
R2 (Ω)
442
324
750
243
Figure 3.5. Termination of Differential and LVCMOS Input Signals
3.3.2 Manual Input Selection (IN0, IN1, IN2, IN3/FB_IN)
Input clock selection can be made manually using the IN_SEL[1:0] pins or through a register. A register bit determines input selection
as pin selectable or register selectable. The IN_SEL pins are selected by default. If there is no clock signal on the selected input, the
device will automatically enter free-run or holdover mode. When the zero delay mode is enabled, IN3 becomes the feedback input
(FB_IN) and is not available for selection as a clock input.
Table 3.2. Manual Input Selection Using IN_SEL[1:0] Pins
IN_SEL[1:0]
Selected Input
Zero Delay Mode Disabled
Zero Delay Mode Enabled
0
0
1
1
0
1
0
1
IN0
IN1
IN2
IN3
IN0
IN1
IN2
Reserved
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Si5380 Data Sheet
Functional Description
3.3.3 Automatic Input Switching (IN0, IN1, IN2, IN3/FB_IN)
An automatic input selection state machine is available in addition to the manual switching option. In automatic mode, the selection
criteria is based on reference qualification, input priority, and the revertive option. Only references which are valid can be selected by
the automatic state machine. If there are no valid references available, the DSPLL will enter the holdover mode. With revertive switch-
ing enabled, the highest priority input with a valid reference is always selected. If an input with a higher priority becomes valid, then an
automatic switchover to that input will be initiated. With non-revertive switching, the active input will always remain selected while it is
valid. If it becomes invalid, an automatic switchover to a valid input with the highest priority will be initiated.
3.3.4 Hitless Input Switching
Hitless switching is a feature that prevents a phase transient from propagating to the output when switching between two frequency
locked clock inputs that have a fixed phase difference between them. A hitless switch can only occur when the two input frequencies
are frequency locked meaning that they have to be exactly at the same frequency, or have an integer frequency relationship to each
other. When this feature is enabled, the DSPLL simply absorbs the phase difference between the two input clocks during an input
switch. When disabled (normal switching), the phase difference between the two inputs is propagated to the output at a rate determined
by the DSPLL loop bandwidth.
3.3.5 Glitchless Input Switching
The DSPLL has the ability of switching between two input clocks that are up to 200 ppm apart in frequency. The DSPLL will pull-in to
the new frequency using the DSPLL loop bandwidth or using the Fastlock loop bandwidth if it is enabled. The loss of lock (LOL) indica-
tor will be asserted while the DSPLL is pulling-in to the new clock frequency. There will be no output runt pulses generated at the out-
put. Glitchless input switching is available regardless of whether the hitless switching feature is enabled or disabled.
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Si5380 Data Sheet
Functional Description
3.3.6 Zero Delay Mode
A zero delay mode is available for applications that require fixed and consistent minimum delay between the selected input and outputs.
The zero delay mode is configured by opening the internal feedback loop through software configuration and closing the loop externally
as shown in the figure below. This helps to cancel out the internal delay introduced by the dividers, the crosspoint, the input, and the
output drivers. Any one of the outputs can be fed back to the IN3/FB_IN pins, although using the output driver that achieves the short-
est trace length will help to minimize the input-to-output delay. The OUT9A and IN3/FB_IN pins are recommended for the external feed-
back connection. The FB_IN input pins must be terminated and ac-coupled when zero delay mode is used. A differential external feed-
back path connection is necessary for best performance. The order of the OUT9A and FB_IN polarities is such that they may be routed
on the device side of the PCB without requiring vias or needing to cross each other.
IN0
IN0b
IN1
Si5380
÷P0
÷P1
÷P2
DSPLL
IN1b
PD
LPF
IN2
IN2b
÷M
÷5
IN3/FB_IN
÷P3
VDDO0
IN3b/FB_INb
OUT0A
÷R0A
÷R0
OUT0Ab
OUT0
OUT0b
t0
t1
t2
t3
t4
÷N0
÷N1
÷N2
÷N3
÷N4
VDDO2
OUT2
OUT2b
÷R2
VDDO8
OUT8
OUT8b
÷R8
OUT9
OUT9b
÷R9
OUT9A
÷R9A
OUT9Ab
VDDO9
External Feedback Path
Figure 3.6. Si5380 Zero Delay Mode Set-up
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Si5380 Data Sheet
Functional Description
3.4 Fault Monitoring
All four input clocks (IN0, IN1, IN2, IN3/FB_IN) are monitored for loss of signal (LOS) and out-of-frequency (OOF) as shown in the fig-
ure below. The reference at the XA/XB pins is also monitored for LOS since it provides a critical reference clock for the DSPLL. The
DSPLL also has a Loss Of Lock (LOL) indicator, which is asserted when the DSPLL has lost synchronization with the selected input
clock.
XA XB
Si5380
OSC
LOS
XAXB
IN0
Precision
Fast
LOS
LOS
LOS
LOS
OOF
OOF
OOF
OOF
÷P0
÷P1
÷P2
÷P3
IN0b
DSPLL
IN1
Precision
Fast
LOL
IN1b
PD LPF
Precision
Fast
IN2
Feedback
Clock
IN2b
÷M
÷5
IN3/FB_IN
Precision
Fast
IN3b/FB_INb
Figure 3.7. Si5380 Fault Monitors
3.4.1 Input LOS Detection
The loss of signal monitor measures the period of each input clock cycle to detect phase irregularities or missing clock edges. Each of
the input LOS circuits have their own programmable sensitivity which allows ignoring missing edges or intermittent errors. Loss of signal
sensitivity is configurable using the ClockBuilder Pro utility. The LOS status for each of the monitors is accessible by reading a status
register. The live LOS register always displays the current LOS state and a sticky register always stays asserted until cleared. An option
to disable any of the LOS monitors is also available.
Sticky
Monitor
LOS
LOS
en
Live
Figure 3.8. LOS Status Indicators
3.4.2 XA/XB LOS Detection
An LOS monitor is available to ensure that the external crystal or reference clock is valid. By default, the output clocks are disabled
when XAXB LOS is detected. This feature can be disabled such that the device will continue to produce output clocks when XAXB LOS
is detected. See the 3.5.15 Output Skew Control (Δt0 - Δt4) section for details.
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Si5380 Data Sheet
Functional Description
3.4.3 OOF Detection
Each input clock is monitored for frequency accuracy with respect to a OOF reference which it considers as its “0_ppm” reference. This
OOF reference can be selected as either: XAXB, IN0, IN1, IN2 or IN3. IN3 is only available as the OOF reference when not in ZDM.
The final OOF status is determined by the combination of both a precise OOF monitor and a fast OOF monitor as shown in the figure
below. An option to disable either monitor is also available. The live OOF register always displays the current OOF state, and its sticky
register bit stays asserted until cleared.
Sticky
Monitor
Precision
Fast
en
en
OOF
OOF
Live
Figure 3.9. OOF Status Indicator
3.4.4 Precision OOF Monitor
The Precision OOF monitor circuit measures the frequency of all input clocks to within ±1 ppm accuracy with respect to the frequency at
the XA/XB pins. The OOF monitor considers the frequency at the XA/XB pins as its 0 ppm OOF reference. A valid input frequency is
one that remains within the OOF frequency range which is register configurable from ±2 ppm to ±500 ppm in steps of 2 ppm. A configu-
rable amount of hysteresis is also available to prevent the OOF status from toggling at the failure boundary. An example is shown in the
figure below. In this case the OOF monitor is configured with a valid frequency range of ±6 ppm and with 2 ppm of hysteresis. An option
to use one of the input pins (IN0–IN3) as the 0 ppm OOF reference instead of the XA/XB pins is available. This option is register config-
urable.
OOF Declared
OOF Cleared
fIN
Hysteresis
Hysteresis
-4 ppm
(Clear)
-6 ppm
(Set)
+4 ppm
(Clear)
+6 ppm
(Set)
0 ppm
OOF
Reference
Figure 3.10. Example of Precise OOF Monitor Assertion and De-assertion Triggers
3.4.5 Fast OOF Monitor
Because the precision OOF monitor needs to provide 1 ppm of frequency measurement accuracy, it must measure the monitored input
clock frequencies over a relatively long period of time. This may be too slow to detect an input clock that is quickly ramping in frequen-
cy. An additional level of OOF monitoring called the Fast OOF monitor runs in parallel with the precision OOF monitors to quickly detect
a ramping input frequency. The Fast OOF monitor asserts OOF on an input clock frequency that has changed by 1,000 to 16,000 ppm.
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Si5380 Data Sheet
Functional Description
3.4.6 LOL Detection
A loss of lock (LOL) monitor asserts the LOL bit when the DSPLL has lost synchronization with the selected input clock. There is also a
dedicated active-low LOLb pin which reflects the loss of lock condition. The LOL monitor measures the frequency difference between
the input and feedback clocks at the phase detector. There are two LOL frequency monitors, one that sets the LOL indicator (LOL Set)
and another that clears the indicator (LOL Clear). A block diagram of the LOL monitor is shown in the figure below. The live LOL regis-
ter always displays the current LOL state and a sticky register always stays asserted until cleared. The LOLb pin reflects the current
state of the LOL monitor.
LOL Monitor
RS Latch
Sticky
LOL
Clear
Timer
Reset
LOL
LOL
Q
Live
LOL
Set
Set
LOLb
DSPLL
LOL
fIN
PD LPF
Feedback
Clock
÷M
÷5
Si5380
Figure 3.11. LOL Status Indicators
Each of the frequency monitors have adjustable sensitivity which is register configurable from 0.1 ppm to 10000 ppm. Having two sepa-
rate frequency monitors allows for hysteresis to help prevent chattering of LOL status. An example configuration where LOCK is indica-
ted when there is less than 0.2 ppm frequency difference at the inputs of the phase detector and LOL is indicated when there is more
than 2 ppm frequency difference is shown in the figure below.
Clear LOL
Threshold
Set LOL
Threshold
Lock Acquisition
LOL
Hysteresis
Lost Lock
LOCKED
0
0.2
2
20000
Phase Detector Frequency Difference (ppm)
Figure 3.12. LOL Set and Clear Thresholds
An optional timer is available to delay clearing of the LOL indicator to allow additional time for the DSPLL to completely phase lock to
the input clock. The timer is also useful to prevent the LOL indicator from toggling or chattering as the DSPLL completes lock acquisi-
tion. The configurable delay value depends on frequency configuration and loop bandwidth of the DSPLL and is automatically calcula-
ted using the ClockBuilder Pro utility.
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Si5380 Data Sheet
Functional Description
3.4.7 Interrupt Pin INTRb
An interrupt pin INTRb indicates a change in state of the status indicators shown in the figure below. Any of the status indicators are
maskable to prevent assertion of the interrupt pin. The state of the INTRb pin is reset by clearing the status register that caused the
interrupt. The sticky version of the fault monitors is used for this function to ensure that the fault condition is still available when re-
sponding to the interrupt.
LOS_INTR_MSK[3-0]
LOS_FLG[3-0]
OOF_INTR_MSK[3-0]
OOF_FLG[3-0]
LOL_INTR_MSK
LOL_FLG
INTRb
HOLD_INTR_MSK
HOLD_FLG
CAL_INTR_MSK
CAL_FLG
SYSINCAL_INTR_MSK
SYSINCAL_FLG
LOSXAXB_INTR_MSK
LOSXAXB_FLG
LOSREF_INTR_MSK
LOSREF_FLG
XAXB_ERR_INTR_MSK
XAXB_ERR_FLG
SMB_TMOUT_INTR_MSK
SMBUS_TIMEOUT_FLG
Figure 3.13. Interrupt Triggers and Masks
3.5 Outputs
The Si5380 supports 12 differential output drivers which can be independently configured as differential or LVCMOS.
3.5.1 Output Crosspoint
The output crosspoint allows any of the N dividers to connect to any of the clock outputs.
3.5.2 Output Signal Format
The differential output amplitude and common mode voltage are both fully programmable covering a wide variety of signal formats in-
cluding LVPECL, LVDS, HCSL, and CML. In addition to supporting differential signals, any of the outputs can be configured as
LVCMOS (3.3 V, 2.5 V, or 1.8 V) drivers providing up to 24 single-ended outputs, or any combination of differential and single-ended
outputs.
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Si5380 Data Sheet
Functional Description
3.5.3 Output Terminations
The output drivers support both ac-coupled and dc-coupled terminations as shown in the following figure.
AC-coupled LVDS/LVPECL
DC-coupled LVDS
V
DDO = 3.3 V, 2.5 V, 1.8 V
V
DDO = 3.3 V, 2.5 V
50
50
50
50
OUTx
OUTx
100
OUTxb
100
OUTxb
Internally
self-biased
Si5380
Si5380
AC-coupled LVPECL / CML
DC-coupled LVCMOS
3.3 V, 2.5 V, 1.8 V
LVCMOS
VDD – 1.3 V
V
DDO = 3.3 V, 2.5 V, 1.8 V
V
DDO = 3.3 V, 2.5 V
50
50
50
50
Rs
Rs
OUTx
50
50
OUTx
OUTxb
OUTxb
Si5380
Si5380
AC-coupled HCSL
VDDRX
V
DDO = 3.3 V, 2.5 V, 1.8 V
R1
R1
R2
OUTx
OUTxb
50
50
Standard
HCSL
Receiver
Si5380
R2
For VCM = 0.35 V
VDDRX
R1
R2
442 Ω
56.2 Ω
59 Ω
3.3 V
2.5 V
1.8 V
332 Ω
243 Ω
63.4 Ω
Figure 3.14. Supported Output Terminations
3.5.4 Differential Output Modes
There are two selectable differential output modes: Normal and Low Power. Each output can support a unique mode.
• Differential Normal Mode: When an output driver is configured in normal amplitude mode, its output amplitude is selectable as one
of 8 settings ranging from 130 mVpp_se to 920 mVpp_se in increments of 100 mV. The output impedance in the normal mode is
100 Ω differential. Any of the ac-coupled terminations shown in Figure 3.14 Supported Output Terminations on page 15 are suppor-
ted in this mode.
• Differential Low Power Mode: When an output driver is configured in low power mode, its output amplitude is configurable as one
of 8 settings ranging from 200 mVpp_se to 1600 mVpp_se in increments of 200 mV. The output driver is in high impedance mode
and supports standard 50 Ω PCB traces. Any of the ac-coupling terminations shown in Figure 3.14 Supported Output Terminations
on page 15 are supported in this mode.
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Si5380 Data Sheet
Functional Description
3.5.5 Programmable Common Mode Voltage for Differential Outputs
The common mode voltage (VCM) for the differential normal and low power modes is programmable in 100 mV increments from 0.7 V
to 2.3 V depending on the voltage available at the output’s VDDO pin. Setting the common mode voltage is useful when dc-coupling the
output drivers.
3.5.6 LVCMOS Output Terminations
LVCMOS outputs are dc-coupled with source-side series termination as shown in the figure below.
DC-coupled LVCMOS
3.3 V, 2.5 V, 1.8 V
LVCMOS
V
DDO = 3.3V, 2.5V, 1.8V
50
50
Rs
Rs
OUTx
OUTxb
Figure 3.15. LVCMOS Output Terminations
3.5.7 LVCMOS Output Impedance and Drive Strength Selection
Each LVCMOS driver has a configurable output impedance to accommodate different trace impedances and drive strengths. A source
termination resistor is recommended to help match the selected output impedance to the trace impedance. There are three programma-
ble output impedance selections for each VDDO options as shown in the table below.
Table 3.3. LVCMOS Output Impedance and Drive Strength Selections
VDDO
OUTx_CMOS_DRV
Source Impedance (Zs)
Drive Strength (Iol/Ioh)
3.3 V
0x01
0x02
0x03*
0x01
0x02
0x03*
0x03*
38 Ω
30 Ω
22 Ω
43 Ω
35 Ω
24 Ω
31 Ω
10 mA
12 mA
17 mA
6 mA
2.5 V
1.8 V
8 mA
11 mA
5 mA
Note: Use of the lowest impedance setting is recommended for all supply voltages for best edge rates.
3.5.8 LVCMOS Output Signal Swing
The signal swing (VOL/VOH) of the LVCMOS output drivers is set by the voltage on the VDDO pins. Each output driver has its own
VDDO pin allowing a unique output voltage swing for each of the LVCMOS drivers. OUT0 and OUT0A share the same VDDO pin.
OUT9 and OUT9A also share the VDDO pin. All other outputs have their own individual VDDO pins. Each output driver automatically
detects the voltage on the VDDO pin to properly determine the correct output voltage.
3.5.9 LVCMOS Output Polarity
When a driver is configured as an LVCMOS output it generates a clock signal on both pins (OUTx and OUTxb). By default the clock on
the OUTxb pin is generated with the same polarity (in phase) with the clock on the OUTx pin. The polarity of these clocks is configura-
ble enabling complimentary clock generation and/or inverted polarity with respect to other output drivers.
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Si5380 Data Sheet
Functional Description
3.5.10 Output Enable/Disable
The OEb pin provides a convenient method of disabling or enabling all of the output drivers at the same time. When the OEb pin is held
high all outputs will be disabled. When held low, the outputs will all be enabled. Outputs in the enabled state can still be individually
disabled through register control.
3.5.11 Output Disable During LOL
By default, a DSPLL that is out of lock will generate either free-running clocks or generate clocks in holdover mode. There is an option
to disable the outputs when a DSPLL is LOL. This option can be useful to force a downstream PLL into holdover.
3.5.12 Output Disable During XAXB_LOS
The internal oscillator circuit (OSC) in combination with the external crystal (XTAL) provides a critical function for the operation of the
DSPLLs. In the event of a crystal failure, the device will assert an XAXB_LOS alarm. By default, all outputs will be disabled during
assertion of the XAXB_LOS alarm. There is an option to leave the outputs enabled during an XAXB_LOS alarm, but the frequency
accuracy and stability will be indeterminate during this fault condition.The internal oscillator circuit (OSC) in combination with the exter-
nal crystal (XTAL) provides a critical function for the operation of the DSPLLs. In the event of a crystal failure, the device will assert an
XAXB_LOS alarm. By default, all outputs will be disabled during assertion of the XAXB_LOS alarm. There is an option to leave the
outputs enabled during an XAXB_LOS alarm, but the frequency accuracy and stability will be indeterminate during this fault condition.
3.5.13 Output Driver State When Disabled
The disabled state of an output driver is configurable as either disable low or disable high.
3.5.14 Synchronous Enable/Disable Feature
The output drivers provide a selectable synchronous enable/disable feature. Output drivers with this feature active will wait until a clock
period has completed before the driver is disabled or enabled. This prevents unwanted runt pulses from occurring when enabling or
disabling an output. When this feature is turned off, the output clock will disable immediately without waiting for the period to complete.
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Si5380 Data Sheet
Functional Description
3.5.15 Output Skew Control (Δt0 - Δt4)
The Si5380 uses independent dividers (N0 - N4) to generate up to 5 unique frequencies to its 12 outputs through a crosspoint switch. A
delay path (Dt0 - Dt4) associated with each of these dividers is available for applications that need a specific output skew configuration.
This is useful for compensating PCB trace delay differences or for applications that require quadrature clock generation. The resolution
of the phase adjustment is approximately 68 ps per step up to 128 steps of added phase delay (+8.6 ns late), or 128 steps of negative
delay (–8.6 ns early). Phase adjustments are register configurable. An example of generating two frequencies with unique configurable
path delays is shown in the following figure.
VDDO0
OUT0A
OUT0Ab
÷R0A
OUT0
OUT0b
÷R0
t0
t1
t2
t3
t4
÷N0
÷N1
÷N2
÷N3
÷N4
VDDO1
OUT1
÷R1
÷R2
÷R3
÷R4
÷R5
÷R6
÷R7
÷R8
OUT1b
VDDO2
OUT2
OUT2b
VDDO3
OUT3
OUT3b
VDDO4
OUT4
OUT4b
VDDO5
OUT5
OUT5b
VDDO6
OUT6
OUT6b
VDDO7
OUT7
OUT7b
VDDO8
OUT8
OUT8b
OUT9
OUT9b
÷R9
OUT9A
OUT9Ab
÷R9A
VDDO9
Figure 3.16. Example of Independently Configurable Path Delays
All phase delay values are restored to their default values after power-up, power-on reset, or hardware reset using the RSTb pin. Phase
delay default values can be written to NVM allowing a custom phase offset configuration at power-up or after power-on reset, or after a
hardware reset using the RSTb pin.
3.5.16 Output Divider (R) Synchronization
All the output R dividers are reset to a known state during the power-up initialization period. This ensures consistent and repeatable
phase alignment across all output drivers. Resetting the device using the RSTb pin or asserting the reset bit will have the same result.
Asserting the sync register bit provides another method of realigning the R dividers without resetting the device.
3.6 Power Management
Unused inputs and output drivers can be powered down when unused. Consult the Si5380 Reference Manual and ClockBuilder Pro
configuration utility for details.
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Si5380 Data Sheet
Functional Description
3.6.1 Power Down Pin (PDNb)
A power down pin is provided to force the device in a low power mode. The device’s configuration will be maintained but no output
clocks will be generated. Most of the internal blocks will be shut down but device communication via the serial interface will still be
available. When the PDNb pin is pulled low the outputs will shut down without glitching (the clock’s complete period will be generated
before shutting down). When PDNb is released the device will start generating clocks without glitches. The device will generate free-
running clocks until the DSPLL has acquired lock to the selected input clock source.
3.7 In-Circuit Programming
The Si5380 is fully configurable using the serial interface (I2C or SPI). At power-up, the device downloads its default register values
from internal non-volatile memory (NVM). Application specific default configurations can be written into NVM allowing the device to gen-
erate specific clock frequencies at power-up. Writing default values to NVM is in-circuit programmable with normal operating power sup-
ply voltages applied to its VDD and VDDA pins. The NVM is writable two times. Once a new configuration has been written to NVM, the
old configuration is no longer accessible. Refer to the Si5380 Reference Manual for a detailed procedure for writing registers to NVM.
3.8 Serial Interface
Configuration and operation of the Si5380 is controlled by reading and writing registers using the I2C or SPI interface. The I2C_SEL pin
selects I2C or SPI operation. The Si5380 supports communication with a 3.3 V or 1.8 V host by setting the IO_VDD_SEL configuration
bit. The SPI mode supports 4-wire or 3-wire by setting the SPI_3WIRE configuration bit. See the Si5380 Reference Manual for details.
3.9 Custom Factory Preprogrammed Devices
For applications where a serial interface is not available for programming the device, custom pre-programmed parts can be ordered
with a specific configuration written into NVM. A factory pre-programmed device will generate clocks at power-up. Custom, factory-pre-
programmed devices are available. Use the ClockBuilder Pro custom part number wizard (www.silabs.com/clockbuilderpro) to quickly
and easily request and generate a custom part number for your configuration.
In less than three minutes, you will be able to generate a custom part number with a detailed data sheet addendum matching your
design’s configuration. Once you receive the confirmation email with the data sheet addendum, simply place an order with your local
Silicon Labs sales representative. Samples of your pre-programmed device will ship to you typically within two weeks.
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Si5380 Data Sheet
Functional Description
3.10 How to Enable Features and/or Configuration Settings Not Available in ClockBuilder Pro for Factory Pre-programmed
Devices
As with essentially all software utilities, ClockBuilder Pro is continuously updated and enhanced. By registering at www.silabs.com and
opting in for updates to software, you will be notified whenever changes are made and what the impact of those changes are. This
update process will ultimately enable ClockBuilder Pro users to access all features and register setting values documented in this data
sheet and the Si5380 Reference Manual .
However, if you must enable or access a feature or register setting value so that the device starts up with this feature or a register
setting, but the feature or register setting is NOT yet available in CBPro, you must contact a Silicon Labs applications engineer for as-
sistance. Examples of this type of feature or custom setting are the customizable output amplitude and common voltages for the clock
outputs. After careful review of your project file and custom requirements, all Silicon Labs applications engineer will email back your
CBPro project file with your specific features and register settings enabled, using what is referred to as the manual "settings override"
feature of CBPro. "Override" settings to match your request(s) will be listed in your design report file. Examples of setting "overrides" in
a CBPro design report are shown below:
Table 3.4. Setting Overrides
Location
Customer Name Engineering
Name
Type
Target
Dec Value
Hex Value
0x1
0x0435[0]
0x0B48[0:4]
FORCE_HOLD_ OLA_HO_FORC No NVM
PLLA
N/A
1
0
E
OOF_DIV_CLK_ OOF_DIV_CLK_ User
DIS DIS
OPN and EVB
0x00
Once you receive the updated design file, simply open it in CBPro. After you create a custom OPN, the device will begin operation after
startup with the values in the NVM file, including the Silicon Labs-supplied override settings.
Place sample
Start
order
Do I need a
pre-programmed device
with a feature or setting
which is unavailable in
ClockBuilder Pro?
Generate
Custom OPN
in CBPro
Configure device
using CBPro
No
Yes
Contact Silicon Labs
Technical Support
to submit & review
your
Yes
non-standard
configuration
request & CBPro
project file
Receive
updated CBPro
project file
from
Silicon Labs
with “Settings
Override”
Does the updated
CBPro Project file
match your
Load project file
into CBPro and test
requirements?
Figure 3.17. Flowchart to Order Custom Parts with Features not Available in CBPro
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Rev. 0.96 | 20
Si5380 Data Sheet
Register Map
4. Register Map
This document provides a brief list of available registers. For a complete list of registers and settings, please refer to the Si5380 Refer-
ence Manual .
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Rev. 0.96 | 21
Si5380 Data Sheet
Electrical Specifications
5. Electrical Specifications
Table 5.1. Recommended Operating Conditions1
Parameter
Symbol
TA
Test Condition
Min
–40
—
Typ
25
Max
85
Unit
°C
°C
V
Ambient Temperature
Maximum Junction Temperature
Core Supply Voltage
TJMAX
VDD
VDDA
VDDO
—
125
1.89
3.47
3.47
2.62
1.89
1.71
3.14
3.14
2.38
1.71
1.80
3.30
3.30
2.50
1.80
V
Output Driver Supply Voltage
V
V
V
Note:
1. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical val-
ues apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted.
Table 5.2. DC Characteristics
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Core Supply Current1, 5
See Note 1
IDD
—
170
265
mA
IDDA
IDDO
—
—
125
28
135
34
mA
mA
Output Buffer Supply Current2, 5
LVPECL Output3
@ 1474.56 MHz
LVPECL Output3
@ 153.6 MHz
—
—
—
—
—
—
—
21
17
25
23
mA
mA
mA
mA
mA
mA
mW
LVDS Output3
@ 1474.56 MHz
LVDS Output3
15
17
@ 153.6 MHz
3.3 V LVCMOS Output 4
@ 153.6 MHz
21
25
2.5 V LVCMOS Output 4
@ 153.6 MHz
16
18
1.8 V LVCMOS Output 4
@ 153.6 MHz
12
13
Total Power Dissipation1,2
Typical Outputs1
Pd
1250
1450
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Si5380 Data Sheet
Electrical Specifications
Parameter
Note:
Symbol
Test Condition
Min
Typ
Max
Unit
1. Si5380 test configuration 1: 4 x 3.3 V LVPECL outputs enabled @122.88 MHz, 2 x 3.3 V LVDS outputs enabled @122.88 MHz,
one input enabled, locked to 30.72 MHz. Excludes power in termination resistors.
2. Detailed power consumption for any configuration can be estimated using ClockBuilder Pro when an evaluation board (EVB) is
not available. All EVBs support detailed current measurements for any configuration.
3. Differential outputs terminated into an ac-coupled 100 Ω load.
4. LVCMOS outputs measured into a 6-inch 50 Ω PCB trace with 5 pF load. The LVCMOS outputs were set to
OUTx_CMOS_DRV=3, which is the strongest driver setting. Refer to the Si5380 Reference Manual for more details on register
settings.
5. VDDO0 supplies power to both OUT0 and OUT0A buffers. Similarly, VDDO9 supplies power to both OUT9 and OUT9A buffers.
LVCMOS Output Test Configuration
Differential Output Test Configuration
Trace length 5
inches
IDDO
0.1 uF
0.1 mF
499 Ω
4.7 pF
50
IDDO
50 Ω Scope Input
50 Ω Scope Input
50
50
OUT
100
OUT
OUTb
56 Ω
0.1 mF
56 Ω
OUTb
50
499 Ω
4.7 pF
0.1 uF
Table 5.3. Input Clock Specifications
Test Condition
Parameter
Symbol
Min
Typ
Max
Unit
Standard Differential or Single-Ended/LVCMOS—AC-coupled (IN0/IN0, IN1/IN1, IN2/IN2, IN3/IN3, FB_IN/FB_IN)
Input Frequency Range
Input Voltage Amplitude
fIN_DIFF
fIN_SE
VIN
Differential
Single-ended/LVCMOS
FIN < 400 MHz
10
10
—
—
—
750
250
MHz
MHz
100
3600
mVpp_se,
mVpp_dif
400 MHz < FIN < 750 MHz
225
400
—
—
3600
—
mVpp_se,
mVpp_dif
Slew Rate1 , 2
Duty Cycle
SR
V/µs
DC
CIN
40
—
—
2
60
—
%
Capacitance
pF
Pulsed CMOS—DC-coupled (IN0, IN1, IN2, IN3/FB_IN) 3
Input Frequency
fIN_CMOS
VIL
10
—
—
—
—
250
0.33
—
MHz
V
Input Voltage Thresholds
–0.2
0.49
400
VIH
V
Slew Rate1 , 2
SR
—
V/µs
Duty Cycle
DC
PW
RIN
Clock Input
Pulse Input
40
1.6
—
—
—
8
60
—
—
%
ns
kΩ
Minimum Pulse Width
Input Resistance
REFCLK (applied to XA/XB)
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Si5380 Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
REFCLK4
fIN_REF
LTE
—
54
—
MHz
Total Frequency Tolerance5
Input Voltage Swing
frange
VIN_SE
VIN_DIFF
SR
–100
365
365
400
—
—
—
—
+100
2000
2500
—
ppm
mVpp_se
mVpp_diff
V/µs
Slew Rate1 , 2
Imposed for phase noise perform-
ance
Input Duty Cycle
DC
40
—
60
%
Note:
1. Imposed for phase noise performance.
2. Rise and fall times can be estimated using the following simplified equation: tr/tf80-20 = ((0.8 – 0.2) * VIN_Vpp_se) / SR.
3. This mode is intended primarily for single-ended LVCMOS input clocks < 1 MHz, which must be dc-coupled, having a duty cycle
significantly less than 50%. A typical application example is a low frequency video frame sync pulse. Since the input thresholds
(VIL, VIH) of the input buffer are non-standard, refer to the input attenuator circuit for dc-coupled Pulsed LVCMOS in the in the
Si5380 Reference Manual . Otherwise, for standard LVCMOS input clocks, use the "AC-coupled Single-Ended" mode as shown
in Figure 6.14.
4. The REFCLK frequency for the Si5380 is fixed at 54 MHz. Contact the applications group for more information.
5. Includes initial tolerance, drift after reflow, change over temperature (–40 °C to +85 °C), VDD variation, load pulling, and aging.
Table 5.4. Control Input Pin Specifications1
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Si5380 Control Input Pins (I2C_SEL, IN_SEL[1:0], RSTb, OEb, SYNCb, PDNb, A1/SDO, SDA/SDIO, SCLK, A0/CSb)
Input Voltage Thresholds
VIL
VIH
—
—
—
0.3xVDDIO
—
*
V
V
0.7 x
VDDIO
*
Input Capacitance
Input Resistance
Minimum Pulse Width
Note:
CIN
IL
—
—
2
—
—
—
pF
kΩ
ns
20
—
PW
RSTb, SYNCb, PDNb
100
1. VDDIO is determined by the IO_VDD_SEL bit. It is selectable as VDDA or VDD. See the Si5380 Reference Manual for more details
on the register settings.
Table 5.5. Differential Clock Output Specifications
Parameter
Symbol
fOUT
Test Condition
Min
0.48
48
Typ
—
Max
1474.56
52
Unit
MHz
%
Output Frequency
Duty Cycle
DC
f < 400 MHz
400 MHz < f < 800 MHz
f >800 MHz
—
45
—
55
%
40
—
60
%
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Si5380 Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Differential Outputs
Same N-divider
Min
Typ
Max
Unit
Output-Output Skew
TSK
—
20
50
ps
Differential Outputs
Different N-dividers
—
—
20
0
100
100
ps
ps
OUT-OUTb Skew
TSK_OUT
Measured from the positive to
negative output pins
Output Voltage Ampli- Normal Mode
tude1
VOUT
VDDO
=
LVDS
340
530
470
810
550
950
mVpp_se
LVPECL
3.3 V or
2.5 V or
1.8 V
Low Power Mode
VOUT
VDDO
=
LVDS
300
530
420
820
530
mVpp_se
3.3 V or
2.5 V or
1.8 V
VDDO = 3.3 V
or 2.5 V
LVPECL
1060
Common Mode Volt-
age1, 2
Normal or Low Power Modes
VCM
VDDO
=
LVDS
1.10
1.90
1.25
2.05
1.30
2.10
V
LVPECL
3.3 V
VDDO
=
LVPECL
LVDS
1.15
1.25
1.30
2.5 V
VDDO
=
LVDS
0.87
0.93
0.98
1.8 V
Rise and Fall Times
(20% to 80%)
tR/tF
Normal Mode
—
—
—
—
170
300
100
Hi-Z
240
430
—
ps
Ω
Low Power Mode
Normal Power Mode
Low Power Mode
Differential Output Im-
pedance3
ZO
—
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Si5380 Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Normal Mode
Min
Typ
Max
Unit
Power Supply Noise
Rejection4
PSRR
10 kHz sinusoidal noise
100 kHz sinusoidal noise
500 kHz sinusoidal noise
1 MHz sinusoidal noise
Low Power Mode
—
—
—
—
-93
-93
-84
-79
—
—
—
—
dBc
10 kHz sinusoidal noise
100 kHz sinusoidal noise
500 kHz sinusoidal noise
1 MHz sinusoidal noise
—
—
—
—
—
-98
-95
-84
-76
-75
—
—
—
—
—
dB
dB
Output-Output Cross-
talk
XTALK
Measured spur from adjacent
output
Note:
1. Normal mode and low power mode amplitude and common mode voltage are programmable through register settings and can be
stored in NVM. Each output driver can be programmed independently. The typical normal mode (or low power mode) LVDS maxi-
mum is 100 mV (or 80 mV) higher than the TIA/EIA-644 maximum. Refer to the Si5380 Reference Manual for more details on
register settings.
2. Not all combinations of voltage amplitude and common mode voltages settings are possible. See the Si5380 Reference Manual
for more information.
3. Driver output impedance depends on selected output mode (Normal, Low Power).
4. Measured for 122.88 MHz carrier frequency. Sinewave noise added to VDDO (1.8 V = 50 mVpp, 2.5 V/3.3 V = 100 mVpp) and
noise spur amplitude measured.
5. Measured across two adjacent outputs, both in LVDS mode, with the victim running at 76.8 MHz and the aggressor at 92.08 MHz.
Refer to application note, "AN862: Optimizing Si534x Jitter Performance in Next Generation Internet Infrastructure Systems", for
guidance on crosstalk optimization. Note that all active outputs must be terminated when measuring crosstalk
Table 5.6. LVCMOS Clock Output Specifications
Parameter
Symbol
Test Condition
Min
0.48
47
Typ
—
Max
250
53
Unit
MHz
%
Output Frequency
Duty Cycle
DC
fOUT < 100 MHz
—
100 MHz < fOUT < 250 MHz
44
—
55
Output-to-Output Skew
TSK
—
—
100
ps
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Si5380 Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Output Voltage High1, 2, 3
VOH
VDDO = 3.3 V
IOH = –10 mA
OUTx_CMOS_DRV=1
VDDO
0.75
x
x
x
—
—
—
—
—
—
V
OUTx_CMOS_DRV=2
OUTx_CMOS_DRV=3
IOH = –12 mA
IOH = –17 mA
VDDO = 2.5 V
OUTx_CMOS_DRV=1
OUTx_CMOS_DRV=2
OUTx_CMOS_DRV=3
IOH = –6 mA
IOH = –8 mA
IOH = –11 mA
VDDO
0.75
—
—
—
—
—
—
V
VDDO = 1.8 V
OUTx_CMOS_DRV=2
OUTx_CMOS_DRV=3
IOH = –4 mA
IOH = –5 mA
VDDO
0.75
—
—
—
—
V
V
Output Voltage Low1, 2, 3
VOL
VDDO = 3.3 V
OUTx_CMOS_DRV=1
OUTx_CMOS_DRV=2
OUTx_CMOS_DRV=3
IOL = 10 mA
IOL = 12 mA
IOL = 17 mA
—
—
—
—
—
—
VDDO
0.15
x
x
x
VDDO = 2.5 V
OUTx_CMOS_DRV=1
OUTx_CMOS_DRV=2
OUTx_CMOS_DRV=3
IOL = 6 mA
IOL = 8 mA
IOL = 11 mA
—
—
—
—
—
—
VDDO
0.15
V
V
VDDO = 1.8 V
OUTx_CMOS_DRV=2
OUTx_CMOS_DRV=3
IOL = 4 mA
IOL = 5 mA
—
—
—
—
—
—
VDDO
0.15
—
LVCMOS Rise and Fall
Times2
tr/tf
VDDO = 3.3 V
420
475
525
550
625
705
ps
ps
ps
VDDO = 2.5 V
VDDO = 1.8 V
(20% to 80%)
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Si5380 Data Sheet
Electrical Specifications
Parameter
Note:
Symbol
Test Condition
Min
Typ
Max
Unit
1. Driver strength is a register programmable setting and stored in NVM. Options are OUTx_CMOS_DRV = 1, 2, 3. Refer to the
Si5380 Reference Manual for more details on register settings.
2. IOL/IOH is measured at VOL/VOH as shown in the DC test configuration
3. A 5 pF capacitive load is assumed. The LVCMOS outputs were set to OUTx_CMOS_DRV = 3.
AC Output Test Configuration
DC Test Configuration
Trace length 5 inches
0.1 mF
499 Ω
4.7 pF
IDDO
50
50
IOL/IOH
50 Ω Scope Input
50 Ω Scope Input
OUT
56 Ω
0.1 mF
Zs
OUTb
VOL/VOH
499 Ω
4.7 pF
56 Ω
Table 5.7. Output Status Pin Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Si5380 Status Output Pins (LOLb, INTRb)
Output Voltage
VDDIO1 x
0.75
VOH
IOH = –2 mA
IOL = 2 mA
—
—
—
V
V
VDDIO1 x
0.15
VOL
—
Note:
1. VDDIO is determined by the IO_VDD_SEL bit. It is selectable as VDDA or VDD. See the Si5380 Reference Manual for more details
on the register settings.
Table 5.8. Performance Characteristics
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
PLL Loop Bandwidth Programming
Range3
fBW
Loop bandwidth is register
programmable
0.1
40
100
Hz
Initial Start-Up Time
tSTART
Time from power-up or de-as-
sertion of PDNb to when the
device generates free-running
clocks.
—
30
45
ms
Fastlock enabled4
tDELAY= 1/fVCO
PLL Lock Time
tACQ
—
—
—
—
—
500
67.8
±8.6
—
600
—
ms
ps
2
Output Delay Adjustment
tDELAY
2
+/-128 / fVCO
—
ns
tRANGE
POR to Serial Interface Ready1
Jitter Peaking
tRDY
JPK
15
ms
dB
When locked, any loop band-
width
—
0.1
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Si5380 Data Sheet
Electrical Specifications
Parameter
Symbol
tSWITCH
ΩP
Test Condition
Min
—
—
1
Typ
—
Max
2.8
—
Unit
ns
Maximum Phase Transient
Pull-in Range
Automatic Hitless Switch
500
2
ppm
ns
Input-to-Output Delay Variation
tIODELAY
tZDELAY
JGEN
In Regular Mode
—
In Zero Delay Mode2
LVPECL Output
@ 1474.56 MHz
LVPECL Output
@ 122.88 MHz
10Hz
—
110
—
ps
RMS Jitter Generation5
—
0.070
0.080
ps RMS
—
0.080
0.125
ps RMS
Phase Noise Performance5
PN
—
—
—
—
—
—
—
—
—
–71
–98
—
—
—
—
—
—
—
—
—
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc
100 Hz
(122.88 MHz Carrier Frequency)
1 kHz
–123
–136
–144
–154
–165
–103
–95
10 kHz
100 kHz
1 MHz
10 MHz
Spur Performance 5(122.88 MHz Carri-
er Frequency)
SPUR
Up to 1 MHz offset
From 1 MHz to 30 MHz offset
dBc
Note:
1. Measured as time from valid VDD/VDDA rails (both >90% of settled voltage) to when the serial interface is ready to respond to
commands.
2. Measured from the INx input to the feedback input, with both clocks running at 15.36 MHz and having the same slew rate. The
rise time of the reference input should not exceed 200 ps in order to guarantee this specification.
3. Actual loop bandwidth might be lower; refer to ClockBuilder Pro for actual value on your frequency plan.
4. Lock Time can vary significantly depending on several parameters, such as bandwidths, LOL thresholds, etc. For this case, lock
time was measured with nominal and fastlock bandwidths both set to 100 Hz, LOL set/clear thresholds of 3/0.3 ppm respectively,
using IN0 as clock reference by removing the reference and enabling it again, then measuring the delta time between the first
rising edge of the clock reference and the LOL indicator de-assertion.
5. Jitter generation test conditions: fIN = 30.72 MHz, fOUT = 122.88 MHz LVPECL, DSPLL LBW = 100 Hz. Does not include jitter
from PLL input reference.
Table 5.9. I2C Timing Specifications (SCL,SDA)
Parameter
Symbol
Test Condition
Min
Max
Min
Fast Mode
400 kbps
Max
Unit
Standard Mode
100 kbps
SCL Clock Frequency
SMBus Timeout
fSCL
—
0
100
0
400
35
kHz
ms
µs
When Timeout is Enabled
25
4.0
35
—
25
Hold Time (Repeated)
START Condition
tHD:STA
0.6
—
Low Period of the SCL
Clock
tLOW
4.7
—
1.3
—
µs
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Si5380 Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Max
Min
Max
Unit
HIGH Period of the SCL
Clock
tHIGH
4.0
—
0.6
—
µs
Set-up Time for a Repea-
ted START Condition
tSU:STA
4.7
—
0.6
—
µs
Data Hold Time
tHD:DAT
tSU:DAT
tr
100
250
—
—
—
100
100
20
—
—
ns
ns
ns
Data Set-up Time
Rise Time of Both SDA
and SCL Signals
1000
300
Fall Time of Both SDA and
SCL Signals
tf
—
300
—
—
300
—
ns
µs
µs
Set-up Time for STOP
Condition
tSU:STO
4.0
4.7
0.6
1.3
Bus Free Time between a
STOP and START Condi-
tion
tBUF
—
—
Data Valid Time
tVD:DAT
tVD:ACK
—
—
3.45
3.45
—
—
0.9
0.9
µs
µs
Data Valid Acknowledge
Time
Figure 5.1. I2C Serial Prot Timing Standard and Fast Modes
Table 5.10. SPI Timing Specifications (4-Wire)
Parameter
Symbol
fSPI
Min
—
Typ
—
Max
20
Unit
MHz
%
SCLK Frequency
SCLK Duty Cycle
TDC
40
—
60
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Si5380 Data Sheet
Electrical Specifications
Parameter
Symbol
Tr/Tf
TC
Min
—
Typ
—
Max
10
Unit
ns
SCLK Rise and Fall Time
SCLK Period
50
—
—
—
ns
Delay Time, SCLK Fall to SDO
Active
TD1
—
12.5
ns
Delay Time, SCLK Fall to SDO
TD2
TD3
—
—
—
—
12.5
12.5
ns
ns
Delay Time, CSb Rise to SDO
Tri-State
Setup Time, CSb to SCLK
TSU1
TH1
TSU2
TH2
25
25
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
Tc
Hold Time, SCLK Fall to CSb
Setup Time, SDI to SCLK Rise
Hold Time, SDI to SCLK Rise
12.5
12.5
1.9
Delay Time Between Chip Selects
(CSb)
TCS
TSU1
TD1
TC
SCLK
TH1
CSb
TSU2
TH2
TCS
SDI
TD2
TD3
SDO
Figure 5.2. 4-Wire SPI Serial Interface Timing
Table 5.11. SPI Timing Specifications (3-Wire)
Parameter
Symbol
fSPI
Min
—
Typ
Max
20
Unit
MHz
%
SCLK Frequency
—
—
—
—
—
—
—
—
—
SCLK Duty Cycle
TDC
Tr/Tf
TC
40
—
60
SCLK Rise and Fall Time
SCLK Period
10
ns
50
—
—
ns
Delay Time, SCLK Fall to SDIO Turn-on
Delay Time, SCLK Fall to SDIO Next-bit
Delay Time, CSb Rise to SDIO Tri-State
Setup Time, CSb to SCLK
Hold Time, SCLK Fall to CSb
TD1
12.5
12.5
12.5
—
ns
TD2
—
ns
TD3
—
ns
TSU1
TH1
25
25
ns
—
ns
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Si5380 Data Sheet
Electrical Specifications
Parameter
Symbol
TSU2
TH2
Min
12.5
12.5
1.9
Typ
—
Max
—
Unit
ns
Setup Time, SDI to SCLK Rise
Hold Time, SDI to SCLK Rise
Delay Time Between Chip Selects (CSb)
—
—
ns
TCS
—
—
Tc
TSU1
TC
SCLK
TH1
TD1
TD2
CSb
TSU2
TH2
TCS
SDIO
TD3
Figure 5.3. 3-Wire SPI Serial Interface Timing
Table 5.12. Crystal Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Crystal Frequency1
fXTAL
fRANGE
CL
—
–100
—
54
—
MHz
Total Frequency Tolerance2
Load Capacitance
—
8
+100
—
ppm
pF
Crystal Output Capacitance
Equivalent Series Resistance
Crystal Drive Level
CO
—
—
—
—
2
pF
rESR
dL
—
23
Ω
The crystal resonator must be
able to tolerate 200 µW of drive
level
—
200
µW
Note:
1. Refer to the Si5380 Reference Manual for qualified crystals. The Si5380 is designed to operate with crystals that meet the specifi-
cations in the Table 5.14 Absolute Maximum Ratings1,2,3, 4 on page 33. See the Si5380 Reference Manual for a list of qualified
54 MHz crystals.
2. Includes initial tolerance, drift after reflow, change over temperature (–40 °C to +85 °C), VDD variation, load pulling, and aging.
Table 5.13. Thermal Characteristics1
Parameter
Symbol
Test Condition
Value
Unit
Si5380—64QFN
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Si5380 Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Still Air
Value
22
Unit
Thermal Resistance Junction to
Ambient
ƟJA
°C/W
Air Flow 1 m/s
Air Flow 2 m/s
19.4
18.3
9.5
Thermal Resistance Junction to
Case
ƟJC
ƟJB
ΨJB
ΨJT
Thermal Resistance Junction to
Board
9.4
9.3
0.2
Thermal Resistance Junction to
Board
Thermal Resistance Junction to
Top Center
Note:
1. Based on PCB Dimension: 3x4.5”, PCB Thickness: 1.6 mm, PCB Land/Via: 36, Number of Cu Layers: 4.
Table 5.14. Absolute Maximum Ratings1,2,3, 4
Parameter
Symbol
VDD
Test Condition
Value
Unit
V
DC Supply Voltage
–0.5 to 3.8
–0.5 to 3.8
–0.5 to 3.8
–0.85 to 3.8
–0.5 to 3.8
VDDA
VDDO
VI1
V
V
Input Voltage Range
IN0-IN3/FB_IN
IN_SEL[1:0],
V
VI2
RSTb, PDNb,OEb, SYNCb,
I2C_SEL, SCLK,
A0/CSb, A1/SDO,
SDA/SDIO
VI3
LU
XA/XB
–0.5 to 2.7
JESD78 Compliant
2.0
V
Latch-up Tolerance
ESD Tolerance
HBM
TSTG
TJCT
TPEAK
100 pF, 1.5 kΩ
kV
°C
°C
°C
Storage Temperature Range
Junction Temperature
–55 to 150
–55 to 150
260
Soldering Temperature (Pb-free
profile)4
Soldering Temperature Time at
TPEAK (Pb-free profile)4
TP
20 to 40
sec
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Si5380 Data Sheet
Electrical Specifications
Parameter
Note:
Symbol
Test Condition
Value
Unit
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to
the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for ex-
tended periods may affect device reliability.
2. 64-QFN is RoHS-6 compliant.
3. For MSL rating and additional packaging information, go to http://www.silabs.com/support/quality/pages/RoHSInformation.aspx.
4. The device is compliant with JEDEC J-STD-020.
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Si5380 Data Sheet
Typical Application Diagrams
6. Typical Application Diagrams
IEEE
1588
GPS
N
N
Rx
ADC
ADC
LNA
0
90
CPRI
Stratum 3/
3E DPLL
ASIC
ASIC
Tx
PA
N
N
DAC
DAC
0
90
OCXO
RF
Synth
Recovered Clock
30.72MHz x N
Base Band Unit
LTE
Sampling
Clocks
RF
Synth
Remote Radio
Head
Figure 6.1. LTE Base Station Remote Radio Head
IEEE
1588
JESD
204B
GPS
Rx
A/D
LNA
0
90
JESD
204B
A/D
CPRI
Stratum 3/
3E DPLL
Tx
ASIC
JESD
204B
ASIC
PA
D/A
0
90
JESD
204B
OCXO
D/A
RF
Synth
Base Band Unit
RF
Synth
DCLK
SYSREF
DCLK
SYSREF
DCLK
SYSREF
Remote Radio
Head
Recovered Clock
30.72MHz x N
Figure 6.2. LTE Base Station Using JESD204B Data Converters
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Si5380 Data Sheet
Detailed Block Diagram
7. Detailed Block Diagram
54MHz
XTAL
Si5380
XA
XB
IN_SEL
OSC
÷R0A
OUT0A
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
÷P0
÷P1
÷P2
IN0
IN1
IN2
÷R0
÷R1
÷R2
÷R3
÷R4
DSPLL
IN3/
FB_IN
÷P3
t0
÷N0
I2C_SEL
SDA/SDI
A1/SDO
SCLK
t1
÷N1
I2C/
SPI
÷R5
÷R6
÷R7
÷N2
÷N3
t2
A0/CSb
NVM
t3
t4
÷N4
÷R8
÷R9
OUT8
OUT9
INTRb
LOLb
Status Monitor
÷R9A
OUT9A
SYNCb
OEb
PDNb
RSTb
Figure 7.1. Si5380 Block Diagram
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Si5380 Data Sheet
Typical Operating Characteristics (Phase Noise & Jitter)
8. Typical Operating Characteristics (Phase Noise & Jitter)
Figure 8.1. Typical Phase Noise and Jitter—1,474.56 MHz
Figure 8.2. Typical Phase Noise and Jitter—245.76 MHz
Figure 8.3. Typical Phase Noise and Jitter—122.88 MHz
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Si5380 Data Sheet
Pin Description
9. Pin Description
48 SYNCb
1
2
IN1
IN1b
47
LOLb
46
3
VDD
IN_SEL0
IN_SEL1
PDNb
RSTb
X1
45
4
OUT6
44
5
OUT6b
43
6
VDDO6
42
7
OUT5
41
40
39
38
37
36
35
34
33
8
OUT5b
VDDO5
I2C_SEL
OUT4
XA
GND
Pad
9
XB
10
11
12
13
14
15
16
X2
OEb
OUT4b
VDDO4
OUT3
INTRb
VDDA
IN2
OUT3b
VDDO3
IN2b
SCLK
Figure 9.1. Si5380 64-QFN Top View
Table 9.1. Pin Descriptions
Pin Type1
Pin Name
Pin Number
Function
XA
XB
8
9
I
I
Crystal Input. Input pin for external crystal
(XTAL). Alternatively these pins can be driven with
an external reference clock (REFCLK). An internal
register bit selects XTAL or REFCLK mode. De-
fault is XTAL mode. Single-ended inputs must be
connected to the XA pin, with the XB pin appropri-
ately terminated.
X1
X2
7
I
I
XTAL Shield. Connect these pins directly to the
crystal ground pins. Both the X1/X2 pins and Crys-
tal ground pins should be separated from the PCB
ground plane. Refer to the Reference Manual for
layout guidelines.
10
IN0
IN0b
IN1
63
64
1
I
I
I
I
I
I
Clock Inputs. These pins accept an input clock
for synchronizing the device. They support both
differential and single-ended clock signals. Refer
to section 3.3.1 Input Configuration and Termina-
tions for input termination options. These pins are
high-impedance and must be terminated external-
ly, when being used. The negative side of the dif-
ferential input must be ac-grounded when accept-
ing a single-ended clock. Unused inputs may be
left unconnected.
IN1b
IN2
2
14
15
IN2b
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Si5380 Data Sheet
Pin Description
Pin Type1
Pin Name
Pin Number
Function
IN3/FB_IN
61
62
I
I
Clock Input 3/External Feedback Input.
IN3b/FB_INb
By default, these pins are used as the 4th clock in-
put (IN3/IN3b). They can also be used as the ex-
ternal feedback input (FB_IN/FB_INb) for the op-
tional zero delay mode. See section 5.3.6 for de-
tails on the optional zero delay mode.
Outputs
OUT0A
OUT0Ab
OUT0
21
20
24
23
28
27
31
30
35
34
38
37
42
41
45
44
51
50
54
53
56
55
59
58
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Output Clocks. These output clocks support pro-
grammable signal amplitude and common mode
voltage. Desired output signal format is configura-
ble using register control. Termination recommen-
dations are provided in the sections, 3.5.4 Differ-
ential Output Modes and 3.5.6 LVCMOS Output
Terminations. Unused outputs should be left un-
connected.
OUT0b
OUT1
OUT1b
OUT2
OUT2b
OUT3
OUT3b
OUT4
OUT4b
OUT5
OUT5b
OUT6
OUT6b
OUT7
OUT7b
OUT8
OUT8b
OUT9
OUT9b
OUT9A
OUT9Ab
Serial Interface
I2C_SEL
39
I
I2C Select. This pin selects the serial interface
mode as I2C (I2C_SEL = 1) or SPI (I2C_SEL = 0).
This pin is internally pulled high.
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Si5380 Data Sheet
Pin Description
Pin Type1
Pin Name
Pin Number
Function
SDA/SDIO
18
I/O
Serial Data Interface. This is the bidirectional da-
ta pin (SDA) for the I2C mode, the bidirectional da-
ta pin (SDIO) in the 3-wire SPI mode, or the input
data pin (SDI) in 4-wire SPI mode. When in I2C
mode or unused, this pin must be pulled-up using
an external resistor of at least 1 kΩ. No pull-up re-
sistor is needed when in SPI mode. This pin is 3.3
V tolerant.
Address Select 1/Serial Data Output. In I2C
mode this pin functions as the A1 address input
pin. In 4-wire SPI mode, this is the serial data out-
put (SDO) pin. This pin is 3.3 V tolerant. This pin
must be pulled-up externally when unused.
A1/SDO
SCLK
17
16
I/O
I
Serial Clock Input. This pin functions as the seri-
al clock input for both I2C and SPI modes. When
in I2C mode or unused, this pin must be pulled-up
using an external resistor of at least 1 kΩ. No pull-
up resistor is needed when in SPI mode. This pin
is 3.3 V tolerant.
A0/CSb
19
12
I
Address Select 0/Chip Select. This pin functions
as the hardware controlled address A0 in I2C
mode. In SPI mode, this pin functions as the chip
select input (active low). This pin is internally
pulled-up. This pin is 3.3 V tolerant.
Control/Status
Interrupt. 2 This pin is asserted low when a
change in device status has occurred. This pin
must be pulled-up externally using a resistor of at
least 1 kΩ. It should be left unconnected when not
in use.
INTRb
O
Power Down. 2 The device enters into a low pow-
er mode when this pin is pulled low. This pin is in-
ternally pulled-up. This pin is 3.3 V tolerant. It can
be left unconnected when not in use.
PDNb
RSTb
5
6
I
I
Device Reset. 2 Active low input that performs
power-on reset (POR) of the device. Resets all in-
ternal logic to a known state and forces the device
registers to their default values. Clock outputs are
disabled during reset. This pin is internally pulled-
up. This pin is 3.3 V tolerant.
Output Enable. 2 This pin disables all outputs
when held high. This pin is internally pulled low
and can be left unconnected when not in use. This
pin is 3.3 V tolerant.
OEb
11
47
I
Loss Of Lock. 2 This output pin indicates when
the DSPLL is locked (high) or out-of-lock (low).
When in use, this pin must be pulled-up using an
external resistor of at least 1 kΩ. It can be left un-
connected when not in use.
LOLb
O
Output Clock Synchronization. 2 An active low
signal on this pin resets the output dividers for the
purpose of re-aligning the output clocks. This pin
is internally pulled-up and can be left unconnected
when not in use.
SYNCb
48
I
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Si5380 Data Sheet
Pin Description
Pin Type1
Pin Name
Pin Number
Function
Input Reference Select. 2 The IN_SEL[1:0] pins
are used in manual pin controlled mode to select
the active clock input as shown in Table 3.2 Table
6.2 on page 8. These pins are internally pulled-
down and may be left unconnected when unused.
IN_SEL0
IN_SEL1
3
4
I
I
RSVD
25
Reserved. Leave disconnected.
Power
VDD
VDD
32
46
60
13
P
P
P
P
Core Supply Voltage. The device operates from
a 1.8 V supply. A 1 uF bypass capacitor should be
placed very close to each pin.
VDD
VDDA
Core Supply Voltage 3.3 V. This core supply pin
requires a 3.3 V power source. A 1 uF bypass ca-
pacitor should be placed very close to this pin.
VDDO0
VDDO1
VDDO2
VDDO3
VDDO4
VDDO5
VDDO6
VDDO7
VDDO8
VDDO9
GND PAD
22
26
29
33
36
40
43
49
52
57
P
P
P
P
P
P
P
P
P
P
P
Output Clock Supply Voltage. Supply voltage
(3.3 V, 2.5 V, 1.8 V) for OUTx, OUTxb Outputs.
Note that VDDO0 supplies power to OUT0 and
OUT0A; VDDO9 supplies power to OUT9 and
OUT9A. Leave VDDO pins of unused output driv-
ers unconnected. An alternative option is to con-
nect the VDDO pin to a power supply and disable
the output driver to minimize current consumption.
A 1 µF bypass capacitor should be placed very
close to each connected VDDO pin.
Ground Pad. This pad provides connection to
ground and must be connected for proper opera-
tion.
Note:
1. I = Input, O = Output, P = Power
2. The IO_VDD_SEL control bit (0x0943 bit 0) selects 3.3 V or 1.8 V operation.
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Rev. 0.96 | 41
Si5380 Data Sheet
Package Outline
10. Package Outline
Figure 10.1. Si5380 9x9 mm 64-QFN Package Diagram
Table 10.1. Package Diagram Dimensions
NOM
Dimension
MIN
MAX
0.90
0.05
0.30
A
0.80
0.00
0.18
0.85
0.02
0.25
A1
b
D
9.00 BSC
D2
e
5.10
5.20
5.30
0.50 BSC
9.00 BSC
E
E2
L
5.10
0.30
—
5.20
0.40
—
5.30
0.50
0.10
0.10
0.08
0.10
aaa
bbb
ccc
ddd
Note:
—
—
—
—
—
—
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-220.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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Rev. 0.96 | 42
Si5380 Data Sheet
PCB Land Pattern
11. PCB Land Pattern
Figure 11.1. 9x9 mm 64-QFN Land Pattern
Table 11.1. PCB Land Pattern Dimensions
Dimension
Max
8.90
8.90
0.50
0.30
0.85
5.30
5.30
C1
C2
E
X1
Y1
X2
Y2
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Si5380 Data Sheet
PCB Land Pattern
Dimension
Max
General
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
3. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition is calculated based on a fabrication
Allowance of 0.05 mm.
Solder Mask Design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 μm
minimum, all the way around the pad.
Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
4. A 3x3 array of 1.25 mm square openings on 1.80 mm pitch should be used for the center ground pad.
Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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Rev. 0.96 | 44
Si5380 Data Sheet
Top Marking
12. Top Marking
Si5380A-
Rxxxxx-GM
YYWWTTTTTT
e4
TW
64-QFN
Figure 12.1. Si5380 Top Marking
Table 12.1. Top Marking Explanation
Description
Line
Characters
Line 1
Si5380A-
Base part number for Ultra Low Phase Noise, 12-output JESD204B Clock Gen-
erator:
Si5380A: 12-output clock generator in 64-QFN package.
– = Dash character.
Line 2
Rxxxxx-GM
R = Product revision. (See Ordering Guide for current ordering revision).
xxxxx = Customer specific NVM sequence number. Optional NVM code as-
signed for custom, factory pre-programmed devices.
Characters are not included for standard, factory default configured devices.
See Ordering Guide for more information.
-GM = Package (QFN) type and temperature range (–40 to +85 °C).
Line 3
Line 4
YYWWTTTTTT
YYWW = Characters correspond to the year (YY) and work week (WW) of
package assembly.
TTTTTT = Manufacturing trace code.
Circle w/ 1.6 mm diame- Pin 1 indicator; left-justified
ter
e4
Pb-free symbol; Center-Justified
TW
TW = Taiwan; Country of Origin (ISO Abbreviation)
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Rev. 0.96 | 45
Si5380 Data Sheet
Device Errata
13. Device Errata
Please log in or register at www.silabs.com to access the device errata document.
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Rev. 0.96 | 46
Table of Contents
1. Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3. Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.1 Frequency Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.1.1 Si5380 LTE Frequency Configuration . . . . . . . . . . . . . . . . . . . . . 3
3.1.2 Si5380 Configuration for JESD204B Clock Generation . . . . . . . . . . . . . . . 4
3.1.3 DSPLL Loop Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1.4 Fastlock Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1.5 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1.6 Initialization and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1.7 Freerun Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1.8 Lock Acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1.9 Locked Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1.10 Holdover Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.2 External Reference (XA/XB) . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.3 Inputs (IN0, IN1, IN2, IN3/FB_IN) . . . . . . . . . . . . . . . . . . . . . . . 7
3.3.1 Input Configuration and Terminations . . . . . . . . . . . . . . . . . . . . . 8
3.3.2 Manual Input Selection (IN0, IN1, IN2, IN3/FB_IN) . . . . . . . . . . . . . . . . . 8
3.3.3 Automatic Input Switching (IN0, IN1, IN2, IN3/FB_IN) . . . . . . . . . . . . . . . . 9
3.3.4 Hitless Input Switching . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3.5 Glitchless Input Switching . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3.6 Zero Delay Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.4 Fault Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.4.1 Input LOS Detection . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.4.2 XA/XB LOS Detection . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.4.3 OOF Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.4.4 Precision OOF Monitor . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.4.5 Fast OOF Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.4.6 LOL Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.4.7 Interrupt Pin INTRb . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3.5 Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3.5.1 Output Crosspoint . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3.5.2 Output Signal Format. . . . . . . . . . . . . . . . . . . . . . . . . . .14
3.5.3 Output Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.5.4 Differential Output Modes . . . . . . . . . . . . . . . . . . . . . . . . .15
3.5.5 Programmable Common Mode Voltage for Differential Outputs. . . . . . . . . . . . .16
3.5.6 LVCMOS Output Terminations . . . . . . . . . . . . . . . . . . . . . . .16
3.5.7 LVCMOS Output Impedance and Drive Strength Selection . . . . . . . . . . . . . .16
3.5.8 LVCMOS Output Signal Swing . . . . . . . . . . . . . . . . . . . . . . .16
3.5.9 LVCMOS Output Polarity . . . . . . . . . . . . . . . . . . . . . . . . .16
3.5.10 Output Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . .17
3.5.11 Output Disable During LOL . . . . . . . . . . . . . . . . . . . . . . . .17
3.5.12 Output Disable During XAXB_LOS. . . . . . . . . . . . . . . . . . . . . .17
3.5.13 Output Driver State When Disabled . . . . . . . . . . . . . . . . . . . . .17
3.5.14 Synchronous Enable/Disable Feature . . . . . . . . . . . . . . . . . . . . .17
Table of Contents 47
3.5.15 Output Skew Control (Δt - Δt ) . . . . . . . . . . . . . . . . . . . . . . .18
0
4
3.5.16 Output Divider (R) Synchronization. . . . . . . . . . . . . . . . . . . . . .18
3.6 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
3.6.1 Power Down Pin (PDNb) . . . . . . . . . . . . . . . . . . . . . . . . .19
3.7 In-Circuit Programming. . . . . . . . . . . . . . . . . . . . . . . . . . .19
3.8 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
3.9 Custom Factory Preprogrammed Devices . . . . . . . . . . . . . . . . . . . .19
3.10 How to Enable Features and/or Configuration Settings Not Available in ClockBuilder Pro for Factory
Pre-programmed Devices . . . . . . . . . . . . . . . . . . . . . . . . . .20
4. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6. Typical Application Diagrams . . . . . . . . . . . . . . . . . . . . . . . . 35
7. Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 36
8. Typical Operating Characteristics (Phase Noise & Jitter) . . . . . . . . . . . . . . 37
9. Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
10. Package Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
11. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
12. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
13. Device Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table of Contents 48
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