SI8655BD-B-IS [SILICON]

Analog Circuit, 1 Func, CMOS, PDSO16, SOIC-16;
SI8655BD-B-IS
型号: SI8655BD-B-IS
厂家: SILICON    SILICON
描述:

Analog Circuit, 1 Func, CMOS, PDSO16, SOIC-16

光电二极管
文件: 总42页 (文件大小:974K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
Si8650/51/52/55 Data Sheet  
Low Power Five-Channel Digital Isolator  
KEY FEATURES  
Silicon Lab's family of ultra-low-power digital isolators are CMOS devices offering sub-  
stantial data rate, propagation delay, power, size, reliability, and external BOM advan-  
tages over legacy isolation technologies. The operating parameters of these products  
remain stable across wide temperature ranges and throughout device service life for  
ease of design and highly uniform performance. All device versions have Schmitt trigger  
inputs for high noise immunity and only require VDD bypass capacitors.  
• High-speed operation  
• DC to 150 Mbps  
• No start-up initialization required  
• Wide Operating Supply Voltage  
• 2.5–5.5 V  
• Up to 5000 V  
isolation  
RMS  
Data rates up to 150 Mbps are supported, and all devices achieve propagation delays of  
less than 10 ns. Enable inputs provide a single point control for enabling and disabling  
output drive. Ordering options include a choice of isolation ratings (1.0, 2.5, 3.75 and 5  
kV) and a selectable fail-safe operating mode to control the default output state during  
power loss. All products >1 kVRMS are safety certified by UL, CSA, VDE, and CQC, and  
products in wide-body packages support reinforced insulation withstanding up to 5  
• 60-year life at rated working voltage  
• High electromagnetic immunity  
• Ultra low power (typical)  
• 5 V Operation  
• 1.6 mA per channel at 1 Mbps  
kVRMS  
.
• 5.5 mA per channel at 100 Mbps  
• 2.5 V Operation  
• 1.5 mA per channel at 1 Mbps  
Automotive Grade is available for certain part numbers. These products are built using  
automotive-specific flows at all steps in the manufacturing process to ensure the robust-  
ness and low defectivity required for automotive applications.  
• 3.5 mA per channel at 100 Mbps  
• Tri-state outputs with ENABLE  
• Schmitt trigger inputs  
Automotive Applications  
Industrial Applications  
• On-board chargers  
• Industrial automation systems  
• Selectable fail-safe mode  
• Default high or low output (ordering  
option)  
• Battery management systems  
• Medical electronics  
• Charging stations  
• Isolated switch mode supplies  
• Traction inverters  
• Precise timing (typical)  
• 10 ns propagation delay  
• Isolated ADC, DAC  
• Hybrid Electric Vehicles  
• Motor control  
• 1.5 ns pulse width distortion  
• 0.5 ns channel-channel skew  
• 2 ns propagation delay skew  
• 5 ns minimum pulse width  
• Transient Immunity 50 kV/µs  
• AEC-Q100 qualification  
• Battery Electric Vehicles  
• Power inverters  
• Communication systems  
Safety Regulatory Approvals  
• UL 1577 recognized  
• Up to 5000 VRMS for 1 minute  
• CSA component notice 5A approval  
• Wide temperature range  
• –40 to 125 °C  
• IEC 60950-1, 62368-1, 60601-1 (re-  
inforced insulation)  
• RoHS-compliant packages  
• SOIC-16 wide body  
• VDE certification conformity  
• VDE 0884-10  
• SOIC-16 narrow body  
• QSOP-16  
• EN60950-1 (reinforced insulation)  
• CQC certification approval  
• GB4943.1  
• Automotive-grade OPNs available  
• AIAG compliant PPAP documentation  
support  
• IMDS and CAMDS listing support  
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Rev. 2.01  
Si8650/51/52/55 Data Sheet  
Ordering Guide  
1. Ordering Guide  
Table 1.1. Ordering Guide for Valid OPNs1, 2, 3  
Ordering Part  
Number (OPN)  
Number of Number of  
Inputs Inputs  
VDD1 Side VDD2 Side  
Max Data  
Rate  
(Mbps)  
Default  
Output  
State  
Isolation rating  
(kV)  
Temp (°C)  
Package  
QSOP-16 Packages  
Si8650BB-B-IU  
Si8650EB-B-IU  
Si8651BB-B-IU  
Si8651EB-B-IU  
Si8652BB-B-IU  
Si8652EB-B-IU  
Si8655BA-B-IU  
Si8655BA-C-IU  
SOIC-16 Packages  
Si8650BB-B-IS1  
Si8650BD-B-IS  
Si8650EC-B-IS1  
Si8650ED-B-IS  
Si8651BB-B-IS1  
Si8651BC-B-IS1  
Si8651BD-B-IS  
Si8651EC-B-IS1  
Si8651ED-B-IS  
Si8652BB-B-IS1  
Si8652BC-B-IS1  
Si8652BD-B-IS  
Si8652EC-B-IS1  
Si8652ED-B-IS  
Si8655BA-B-IS  
Si8655BB-B-IS1  
Si8655BD-B-IS  
Notes:  
5
5
4
4
3
3
5
5
0
0
1
1
2
2
0
0
150  
150  
150  
150  
150  
150  
150  
150  
Low  
High  
Low  
High  
Low  
High  
Low  
Low  
2.5  
2.5  
2.5  
2.5  
2.5  
2.5  
1.0  
1.0  
–40 to 125 °C  
–40 to 125 °C  
–40 to 125 °C  
-40 to 125˚C  
-40 to 125˚C  
-40 to 125˚C  
–40 to 125 °C  
–40 to 125 °C  
QSOP-16  
QSOP-16  
QSOP-16  
QSOP-16  
QSOP-16  
QSOP-16  
QSOP-16  
QSOP-16  
5
5
5
5
4
4
4
4
4
3
3
3
3
3
5
5
5
0
0
0
0
1
1
1
1
1
2
2
2
2
2
0
0
0
150  
150  
150  
150  
150  
150  
150  
150  
150  
150  
150  
150  
150  
150  
150  
150  
150  
Low  
Low  
High  
High  
Low  
Low  
Low  
High  
High  
Low  
Low  
Low  
High  
High  
Low  
Low  
Low  
2.5  
5.0  
–40 to 125 °C  
–40 to 125 °C  
–40 to 125 °C  
–40 to 125 °C  
–40 to 125 °C  
–40 to 125 °C  
–40 to 125 °C  
–40 to 125 °C  
–40 to 125 °C  
–40 to 125 °C  
–40 to 125 °C  
–40 to 125 °C  
–40 to 125 °C  
–40 to 125 °C  
–40 to 125 °C  
–40 to 125 °C  
–40 to 125 °C  
NB SOIC-16  
WB SOIC-16  
NB SOIC-16  
WB SOIC-16  
NB SOIC-16  
NB SOIC-16  
WB SOIC-16  
NB SOIC-16  
WB SOIC-16  
NB SOIC-16  
NB SOIC-16  
WB SOIC-16  
NB SOIC-16  
WB SOIC-16  
WB SOIC-16  
NB SOIC-16  
WB SOIC-16  
3.75  
5.0  
2.5  
3.75  
5.0  
3.75  
5.0  
2.5  
3.75  
5.0  
3.75  
5.0  
1.0  
2.5  
5.0  
1. All packages are RoHS-compliant with peak reflow temperatures of 260 °C according to the JEDEC industry standard classifica-  
tions and peak solder temperatures.  
2. “Si” and “SI” are used interchangeably.  
3. An "R" at the end of the part number denotes tape and reel packaging option.  
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Rev. 2.01 | 2  
 
 
 
 
Si8650/51/52/55 Data Sheet  
Ordering Guide  
Automotive Grade OPNs  
Automotive-grade devices are built using automotive-specific flows at all steps in the manufacturing process to ensure robustness and  
low defectivity. These devices are supported with AIAG-compliant Production Part Approval Process (PPAP) documentation, and fea-  
ture International Material Data System (IMDS) and China Automotive Material Data System (CAMDS) listing. Qualifications are compli-  
ant with AEC-Q100, and a zero-defect methodology is maintained throughout definition, design, evaluation, qualification, and mass pro-  
duction steps.  
Table 1.2. Ordering Guide for Automotive Grade OPNs1, 2, 4, 5  
Ordering Part  
Number (OPN)  
Number of Number of  
Inputs Inputs  
VDD1 Side VDD2 Side  
Max Data  
Rate  
(Mbps)  
Default  
Output  
State  
Isolation rating  
(kV)  
Temp (°C)  
Package  
QSOP-16 Packages  
Si8655BA-AU  
SOIC-16 Packages  
Si8651BB-AS1  
Si8651BD-AS  
Si8652BD-AS  
Si8655BA-AS  
Note:  
5
0
150  
Low  
1.0  
–40 to 125 °C  
QSOP-16  
4
4
3
5
1
1
2
0
150  
150  
150  
150  
Low  
Low  
Low  
Low  
2.5  
5.0  
5.0  
1.0  
–40 to 125 °C  
–40 to 125 °C  
–40 to 125 °C  
–40 to 125 °C  
NB SOIC-16  
WB SOIC-16  
WB SOIC-16  
WB SOIC-16  
1. All packages are RoHS-compliant with peak reflow temperatures of 260 °C according to the JEDEC industry standard classifica-  
tions.  
2. “Si” and “SI” are used interchangeably.  
3. An "R" at the end of the part number denotes tape and reel packaging option.  
4. Automotive-Grade devices (with an "–A" suffix) are identical in construction materials, topside marking, and electrical parameters  
to their Industrial-Grade (with a "–I" suffix) version counterparts. Automotive-Grade products are produced utilizing full automotive  
process flows and additional statistical process controls throughout the manufacturing flow. The Automotive-Grade part number is  
included on shipping labels.  
5. Additional Ordering Part Numbers may be available in Automotive-Grade. Please contact your local Silicon Labs sales represen-  
tative for further information.  
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Rev. 2.01 | 3  
 
Table of Contents  
1. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2  
2. Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 5  
2.1 Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5  
2.2 Eye Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
3. Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
3.1 Device Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
3.2 Undervoltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
3.3 Layout Recommendations. . . . . . . . . . . . . . . . . . . . . . . . . . 9  
3.3.1 Supply Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
3.3.2 Output Pin Termination. . . . . . . . . . . . . . . . . . . . . . . . . 9  
3.4 Fail-Safe Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
3.5 Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . .10  
4. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26  
5.1 Si8650/51/52 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . .26  
5.2 Si8655 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . .27  
6. Package Outline (16-Pin Wide Body SOIC)  
7. Land Pattern (16-Pin Wide-Body SOIC). . . . . . . . . . . . . . . . . . . . . 30  
8. Package Outline (16-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . .31  
. . . . . . . . . . . . . . . . . . . 28  
9. Land Pattern (16-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . . 33  
10. Package Outline (16-Pin QSOP) . . . . . . . . . . . . . . . . . . . . . . . 34  
11. Land Pattern (16-Pin QSOP)  
. . . . . . . . . . . . . . . . . . . . . . . . 36  
12. Top Marking (16-Pin Wide Body SOIC)  
13. Top Marking (16-Pin Narrow Body SOIC)  
. . . . . . . . . . . . . . . . . . . . 37  
. . . . . . . . . . . . . . . . . . .38  
14. Top Marking (16-Pin QSOP)  
. . . . . . . . . . . . . . . . . . . . . . . . 39  
15. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40  
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Rev. 2.01 | 4  
Si8650/51/52/55 Data Sheet  
Functional Description  
2. Functional Description  
2.1 Theory of Operation  
The operation of an Si865x channel is analogous to that of an opto coupler, except an RF carrier is modulated instead of light. This  
simple architecture provides a robust isolated data path and requires no special considerations or initialization at start-up. A simplified  
block diagram for a single Si865x channel is shown in the figure below.  
Transmitter  
Receiver  
RF  
OSCILLATOR  
Semiconductor-  
Based Isolation  
Barrier  
MODULATOR  
DEMODULATOR  
A
B
Figure 2.1. Simplified Channel Diagram  
A channel consists of an RF Transmitter and RF Receiver separated by a semiconductor-based isolation barrier. Referring to the  
Transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying. The Receiver contains a demodulator that  
decodes the input state according to its RF energy content and applies the result to output B via the output driver. This RF on/off keying  
scheme is superior to pulse code schemes as it provides best-in-class noise immunity, low power consumption, and better immunity to  
magnetic fields. See the figure below for more details.  
Input Signal  
Modulation Signal  
Output Signal  
Figure 2.2. Modulation Scheme  
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Si8650/51/52/55 Data Sheet  
Functional Description  
2.2 Eye Diagram  
The figure below illustrates an eye-diagram taken on an Si8650. For the data source, the test used an Anritsu (MP1763C) Pulse Pattern  
Generator set to 1000 ns/div. The output of the generator's clock and data from an Si8650 were captured on an oscilloscope. The re-  
sults illustrate that data integrity was maintained even at the high data rate of 150 Mbps. The results also show that 2 ns pulse width  
distortion and 350 ps peak jitter were exhibited.  
Figure 2.3. Eye Diagram  
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Si8650/51/52/55 Data Sheet  
Device Operation  
3. Device Operation  
Device behavior during start-up, normal operation, and shutdown is shown in Figure 3.1 Device Behavior during Normal Operation on  
page 9, where UVLO+ and UVLO- are the positive-going and negative-going thresholds respectively. Refer to the table below to  
determine outputs when power supply (VDD) is not present. Additionally, refer to the table on the following page for logic conditions  
when enable pins are used.  
Table 3.1. Si865x Logic Operation  
VI Input 1,2  
EN Input  
1,2,3,4  
VDDI State  
VDDO State  
VO Output 1,2  
Comments  
1,5,6  
1,5,6  
H
L
H or NC  
H or NC  
L
P
P
P
P
P
P
H
L
Enabled, normal operation.  
X 7  
X 7  
Hi-Z 8  
L 9  
Disabled.  
H or NC  
UP  
P
Upon transition of VDDI from unpowered to pow-  
ered, VO returns to the same state as VI in less  
than 1 μs.  
H 9  
X 7  
X 7  
Hi-Z 8  
L
UP  
P
P
Disabled.  
X 7  
UP  
Undetermined Upon transition of VDDO from unpowered to pow-  
ered, VO returns to the same state as VI within 1  
μs, if EN is in either the H or NC state. Upon tran-  
sition of VDDO from unpowered to powered, VO  
returns to Hi-Z within 1 μs if EN is L.  
Notes:  
1. VDDI and VDDO are the input and output power supplies. VI and VO are the respective input and output terminals. EN is the  
enable control input located on the same output side.  
2. X = not applicable; H = Logic High; L = Logic Low; Hi-Z = High Impedance.  
3. It is recommended that the enable inputs be connected to an external logic high or low level when the Si865x is operating in noisy  
environments.  
4. No Connect (NC) replaces EN1 on Si8650. No Connects are not internally connected and can be left floating, tied to VDD, or tied  
to GND.  
5. “Powered” state (P) is defined as 2.5 V < VDD < 5.5 V.  
6. “Unpowered” state (UP) is defined as VDD = 0 V.  
7. Note that an I/O can power the die for a given side through an internal diode if its source has adequate current.  
8. When using the enable pin (EN) function, the output pin state is driven into a high-impedance state when the EN pin is disabled  
(EN = 0).  
9. See 1. Ordering Guide for details. This is the selectable fail-safe operating mode (ordering option). Some devices have default  
output state = H, and some have default output state = L, depending on the ordering part number (OPN). For default high devi-  
ces, the data channels have pull-ups on inputs/outputs. For default low devices, the data channels have pull-downs on inputs/  
outputs.  
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Si8650/51/52/55 Data Sheet  
Device Operation  
Table 3.2. Enable Input Truth 1  
EN1 1,2  
EN2 1,2  
P/N  
Operation  
Outputs B1, B2, B3, B4, B5 are enabled and follow input state.  
Si8650  
H
L
Outputs B1, B2, B3, B4, B5 are disabled and Logic Low or in high impedance state. 3  
Output A5 enabled and follow input state.  
Si8651  
Si8652  
Si8655  
H
L
X
X
Output A5 disabled and in high impedance state. 3  
X
X
H
L
Outputs B1, B2, B3, B4 are enabled and follow input state.  
Outputs B1, B2, B3, B4 are disabled and in high impedance state. 3  
Outputs A4 and A5 are enabled and follow input state.  
H
L
X
X
Outputs A4 and A5 are disabled and in high impedance state. 3  
Outputs B1, B2, B3 are enabled and follow input state.  
X
X
H
L
Outputs B1, B2, B3 are disabled and in high impedance state. 3  
Outputs B1, B2, B3, B4, B5 are enabled and follow input state.  
Notes:  
1. Enable inputs EN1 and EN2 can be used for multiplexing, for clock sync, or other output control. These inputs are internally  
pulled-up to local VDD by a 2 μA current source allowing them to be connected to an external logic level (high or low) or left  
floating. To minimize noise coupling, do not connect circuit traces to EN1 or EN2 if they are left floating. If EN1, EN2 are unused,  
it is recommended they be connected to an external logic level, especially if the Si865x is operating in a noisy environment.  
2. X = not applicable; H = Logic High; L = Logic Low.  
3. When using the enable pin (EN) function, the output pin state is driven into a high-impedance state when the EN pin is disabled  
(EN = 0).  
3.1 Device Startup  
Outputs are held low during powerup until VDD is above the UVLO threshold for time period tSTART. Following this, the outputs follow  
the states of inputs.  
3.2 Undervoltage Lockout  
Undervoltage Lockout (UVLO) is provided to prevent erroneous operation during device startup and shutdown or when VDD is below its  
specified operating circuits range. Both Side A and Side B each have their own undervoltage lockout monitors. Each side can enter or  
exit UVLO independently. For example, Side A unconditionally enters UVLO when VDD1 falls below VDD1(UVLO–) and exits UVLO when  
VDD1 rises above VDD1(UVLO+). Side B operates the same as Side A with respect to its VDD2 supply.  
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Si8650/51/52/55 Data Sheet  
Device Operation  
UVLO+  
UVLO-  
VDD1  
UVLO+  
UVLO-  
VDD2  
INPUT  
tPHL  
tPLH  
tSD  
tSTART  
tSTART  
tSTART  
OUTPUT  
Figure 3.1. Device Behavior during Normal Operation  
3.3 Layout Recommendations  
To ensure safety in the end user application, high voltage circuits (i.e., circuits with >30 VAC) must be physically separated from the  
safety extra-low voltage circuits (SELV is a circuit with <30 VAC) by a certain distance (creepage/clearance). If a component, such as a  
digital isolator, straddles this isolation barrier, it must meet those creepage/clearance requirements and also provide a sufficiently large  
high-voltage breakdown protection rating (commonly referred to as working voltage protection). Table 4.5 Regulatory Information 1 on  
page 21 and Table 4.6 Insulation and Safety-Related Specifications on page 22 detail the working voltage and creepage/clearance  
capabilities of the Si86xx. These tables also detail the component standards (UL1577, IEC60747, CSA 5A), which are readily accepted  
by certification bodies to provide proof for end-system specifications requirements. Refer to the end-system specification (61010-1,  
60950-1, 60601-1, etc.) requirements before starting any design that uses a digital isolator.  
3.3.1 Supply Bypass  
The Si865x family requires a 0.1 μF bypass capacitor between VDD1 and GND1 and VDD2 and GND2. The capacitor should be placed  
as close as possible to the package. To enhance the robustness of a design, the user may also include resistors (50–300 Ω ) in series  
with the inputs and outputs if the system is excessively noisy.  
3.3.2 Output Pin Termination  
The nominal output impedance of an isolator driver channel is approximately 50 Ω, ±40%, which is a combination of the value of the on-  
chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will  
be a factor, output pins should be appropriately terminated with controlled impedance PCB traces.  
3.4 Fail-Safe Operating Mode  
Si86xx devices feature a selectable (by ordering option) mode whereby the default output state (when the input supply is unpowered)  
can either be a logic high or logic low when the output supply is powered. See Table 3.1 Si865x Logic Operation on page 7 and  
1. Ordering Guide for more information.  
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Si8650/51/52/55 Data Sheet  
Device Operation  
3.5 Typical Performance Characteristics  
The typical performance characteristics depicted in the following diagrams are for information purposes only. Refer to Table 4.2 Electri-  
cal Characteristics on page 12 through Table 4.4 Electrical Characteristics on page 18 for actual specification limits.  
Figure 3.2. Si8650/55 Typical VDD1 Supply Current vs. Data  
Rate 5, 3.3, and 2.5 V Operation  
Figure 3.3. Si8650/55 Typical VDD2 Supply Current vs. Data  
Rate 5, 3.3, and 2.5 V Operation (15 pF Load)  
Figure 3.4. Si8651 Typical VDD1 Supply Current  
vs. Data Rate 5, 3.3, and 2.5 V Operation  
(15 pF Load)  
Figure 3.5. Si8651 Typical VDD2 Supply Current vs. Data Rate  
5, 3.3, and 2.5 V Operation  
(15 pF Load)  
Figure 3.7. Si8652 Typical VDD2 Supply Current vs. Data Rate  
5, 3.3, and 2.5 V Operation  
Figure 3.6. Si8652 Typical VDD1 Supply Current vs. Data Rate  
5, 3.3, and 2.5 V Operation  
(15 pF Load)  
(15 pF Load)  
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Si8650/51/52/55 Data Sheet  
Device Operation  
Figure 3.8. Propagation Delay  
vs. Temperature  
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Si8650/51/52/55 Data Sheet  
Electrical Specifications  
4. Electrical Specifications  
Table 4.1. Recommended Operating Conditions  
Parameter  
Symbol  
TJ  
Min  
Typ  
Max  
150  
125  
5.5  
Unit  
°C  
°C  
V
Junction Operating Temperature  
Ambient Operating Temperature 1  
TA  
–40  
25  
VDD1  
VDD2  
2.375  
2.375  
Supply Voltage  
5.5  
V
Note:  
1. The maximum ambient temperature is dependent on data frequency, output loading, number of operating channels, and supply  
voltage.  
Table 4.2. Electrical Characteristics  
(VDD1 = 5 V±10%, VDD2 = 5 V±10%, TA = –40 to 125 °C)  
Parameter  
Symbol  
VDDUV+  
VDDUV–  
VDDHYS  
Test Condition  
VDD1, VDD2 rising  
VDD1, VDD2 falling  
Min  
1.95  
1.88  
50  
Typ  
2.24  
2.16  
70  
Max  
2.375  
2.325  
95  
Unit  
V
VDD Undervoltage Threshold  
VDD Undervoltage Threshold  
V
VDD Undervoltage  
Hysteresis  
mV  
Positive-Going Input Threshold  
VT+  
VT–  
All inputs rising  
All inputs falling  
1.4  
1.0  
1.67  
1.23  
1.9  
1.4  
V
V
Negative-Going  
Input Threshold  
Input Hysteresis  
VHYS  
VIH  
VIL  
0.38  
0.44  
0.50  
V
V
High Level Input Voltage  
Low Level input voltage  
High Level Output Voltage  
Low Level Output Voltage  
Input Leakage Current  
2.0  
0.8  
V
VOH  
VOL  
IL  
loh = –4 mA  
lol = 4 mA  
VDD1,VDD2 – 0.4  
4.8  
0.2  
V
0.4  
±10  
V
μA  
Ω
Output Impedance 1  
ZO  
50  
Enable Input High Current  
Enable Input Low Current  
IENH  
IENL  
VENx = VIH  
VENx = VIL  
2.0  
2.0  
μA  
μA  
DC Supply Current (All Inputs 0 V or at Supply)  
Si8650Bx, Ex, Si8655Bx  
VDD1  
VI = 0(Bx), 1(Ex)  
VI = 0(Bx), 1(Ex)  
VI = 1(Bx), 0(Ex)  
VI = 1(Bx), 0(Ex)  
1.1  
3.1  
7.0  
3.3  
1.8  
4.7  
9.8  
5.0  
mA  
VDD2  
VDD1  
VDD2  
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Si8650/51/52/55 Data Sheet  
Electrical Specifications  
Parameter  
Si8651Bx, Ex  
Symbol  
Test Condition  
Min  
Typ  
Max  
Unit  
VDD1  
VDD2  
VDD1  
VDD2  
VI = 0(Bx), 1(Ex)  
VI = 0(Bx), 1(Ex)  
VI = 1(Bx), 0(Ex)  
VI = 1(Bx), 0(Ex)  
1.5  
2.7  
6.6  
4.0  
2.4  
4.1  
9.2  
6.0  
mA  
Si8652Bx, Ex  
VDD1  
VI = 0(Bx), 1(Ex)  
VI = 0(Bx), 1(Ex)  
VI = 1(Bx), 0(Ex)  
VI = 1(Bx), 0(Ex)  
2.0  
2.4  
5.6  
5.0  
3.0  
3.6  
7.8  
7.5  
mA  
VDD2  
VDD1  
VDD2  
1 Mbps Supply Current (All Inputs = 500 kHz Square Wave, CI = 15 pF on All Outputs)  
Si8650Bx, Ex, Si8655Bx  
VDD1  
4.1  
3.7  
5.7  
5.2  
mA  
mA  
mA  
VDD2  
Si8651Bx, Ex  
VDD1  
4.2  
3.8  
5.8  
5.3  
VDD2  
Si8652Bx, Ex  
VDD1  
4.0  
4.0  
5.6  
5.6  
VDD2  
10 Mbps Supply Current (All Inputs = 5 MHz Square Wave, CI = 15 pF on All Outputs)  
Si8650Bx, Ex, Si8655Bx  
VDD1  
4.1  
5.2  
5.7  
7.2  
mA  
mA  
mA  
VDD2  
Si8651Bx, Ex  
VDD1  
4.4  
4.9  
6.2  
6.9  
VDD2  
Si8652Bx, Ex  
VDD1  
4.6  
4.9  
6.4  
6.8  
VDD2  
100 Mbps Supply Current (All Inputs = 50 MHz Square Wave, CI = 15 pF on All Outputs)  
Si8650Bx, Ex, Si8655Bx  
VDD1  
4.1  
5.7  
mA  
22.1  
28.7  
VDD2  
Si8651Bx, Ex  
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Si8650/51/52/55 Data Sheet  
Electrical Specifications  
Parameter  
Symbol  
Test Condition  
Min  
Typ  
8.0  
Max  
10.8  
24  
Unit  
VDD1  
VDD2  
mA  
18.4  
Si8652Bx, Ex  
VDD1  
11.7  
15  
15.2  
19.5  
mA  
VDD2  
Timing Characteristics  
Si865xBx, Ex  
Maximum Data Rate  
Minimum Pulse Width  
Propagation Delay  
0
150  
5.0  
13  
Mbps  
ns  
tPHL, tPLH See Figure 4.2 Propagation  
Delay Timing on page 15  
5.0  
8.0  
ns  
Pulse Width Distortion  
PWD  
See Figure 4.2 Propagation  
Delay Timing on page 15  
0.2  
4.5  
ns  
|tPLH – tPHL  
|
Propagation Delay Skew 2  
Channel-Channel Skew  
All Models  
tPSK(P-P)  
tPSK  
2.0  
0.4  
4.5  
2.5  
ns  
ns  
Output Rise Time  
tr  
CL = 15 pF  
2.5  
2.5  
4.0  
4.0  
ns  
ns  
See Figure 4.2 Propagation  
Delay Timing on page 15  
Output Fall Time  
tf  
CL = 15 pF  
See Figure 4.2 Propagation  
Delay Timing on page 15  
Peak eye diagram jitter  
tJIT(PK)  
CMTI  
See Figure 2.3 Eye Diagram  
on page 6  
350  
50  
ps  
Common Mode  
VI = VDD or 0 V  
35  
kV/μs  
Transient Immunity  
VCM = 1500 V (see Figure  
4.3 Common Mode Transi-  
ent Immunity Test Circuit on  
page 15)  
Enable to Data Valid  
ten1  
ten2  
tSU  
See Figure 4.1 ENABLE  
Timing Diagram on page  
15  
6.0  
8.0  
15  
11  
12  
40  
ns  
ns  
μs  
Enable to Data Tri-State  
See Figure 4.1 ENABLE  
Timing Diagram on page  
15  
Start-up Time 3  
Notes:  
1. The nominal output impedance of an isolator driver channel is approximately 50 Ω, ±40%, which is a combination of the value of  
the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission  
line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces.  
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same  
supply voltages, load, and ambient temperature.  
3. Start-up time is the time period from the application of power to valid data at the output.  
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Si8650/51/52/55 Data Sheet  
Electrical Specifications  
ENABLE  
OUTPUTS  
ten1  
ten2  
Figure 4.1. ENABLE Timing Diagram  
1.4 V  
Typical  
Input  
tPLH  
tPHL  
90%  
10%  
90%  
10%  
1.4 V  
Typical  
Output  
tr  
tf  
Figure 4.2. Propagation Delay Timing  
3 to 5 V  
Supply  
Si86xx  
VDD1  
VDD2  
Input  
Signal  
Switch  
INPUT  
OUTPUT  
3 to 5 V  
Isolated  
Supply  
Oscilloscope  
GND1  
GND2  
Isolated  
Ground  
High Voltage  
Differential  
Probe  
Output  
Input  
Vcm Surge  
Output  
High Voltage  
Surge Generator  
Figure 4.3. Common Mode Transient Immunity Test Circuit  
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Si8650/51/52/55 Data Sheet  
Electrical Specifications  
Table 4.3. Electrical Characteristics  
(VDD1 = 3.3 V±10%, VDD2 = 3.3 V±10%, TA = –40 to 125 °C)  
Parameter  
Symbol  
VDDUV+  
VDDUV–  
VDDHYS  
Test Condition  
VDD1, VDD2 rising  
VDD1, VDD2 falling  
Min  
1.95  
1.88  
50  
Typ  
2.24  
2.16  
70  
Max  
2.375  
2.325  
95  
Unit  
V
VDD Undervoltage Threshold  
VDD Undervoltage Threshold  
V
VDD Undervoltage  
Hysteresis  
mV  
Positive-Going Input Threshold  
Negative-Going Input Threshold  
Input Hysteresis  
VT+  
VT–  
VHYS  
VIH  
All inputs rising  
All inputs falling  
1.4  
1.67  
1.23  
0.44  
1.9  
1.4  
0.50  
V
V
1.0  
0.38  
V
High Level Input Voltage  
Low Level Input Voltage  
High Level Output Voltage  
Low Level Output Voltage  
Input Leakage Current  
2.0  
V
VIL  
0.8  
V
VOH  
VOL  
IL  
loh = –4 mA  
lol = 4 mA  
VDD1,VDD2 – 0.4  
3.1  
0.2  
V
0.4  
±10  
V
μA  
Ω
Output Impedance 1  
ZO  
50  
Enable Input High Current  
Enable Input Low Current  
IENH  
IENL  
VENx = VIH  
VENx = VIL  
2.0  
2.0  
μA  
μA  
DC Supply Current (all Inputs 0 V or at Supply)  
Si8650Bx, Ex, Si8655Bx  
VDD1  
VI = 0(Bx), 1(Ex)  
VI = 0(Bx), 1(Ex)  
VI = 1(Bx), 0(Ex)  
VI = 1(Bx), 0(Ex)  
1.1  
3.1  
7.0  
3.3  
1.8  
4.7  
9.8  
5.0  
mA  
mA  
mA  
VDD2  
VDD1  
VDD2  
Si8651Bx, Ex  
VDD1  
VI = 0(Bx), 1(Ex)  
VI = 0(Bx), 1(Ex)  
VI = 1(Bx), 0(Ex)  
VI = 1(Bx), 0(Ex)  
1.5  
2.7  
6.6  
4.0  
2.4  
4.1  
9.2  
6.0  
VDD2  
VDD1  
VDD2  
Si8652Bx, Ex  
VDD1  
VI = 0(Bx), 1(Ex)  
VI = 0(Bx), 1(Ex)  
VI = 1(Bx), 0(Ex)  
VI = 1(Bx), 0(Ex)  
2.0  
2.4  
5.6  
5.0  
3.0  
3.6  
7.8  
7.5  
VDD2  
VDD1  
VDD2  
1 Mbps Supply Current (All Inputs = 500 kHz Square Wave, CI = 15 pF on All Outputs)  
Si8650Bx, Ex, Si8655Bx  
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Si8650/51/52/55 Data Sheet  
Electrical Specifications  
Parameter  
Symbol  
Test Condition  
Min  
Typ  
4.1  
3.7  
Max  
5.7  
Unit  
VDD1  
VDD2  
mA  
5.2  
Si8651Bx, Ex  
VDD1  
4.2  
3.8  
5.8  
5.3  
mA  
mA  
VDD2  
Si8652Bx, Ex  
VDD1  
4.0  
4.0  
5.6  
5.6  
VDD2  
10 Mbps Supply Current (All Inputs = 5 MHz Square Wave, CI = 15 pF on All Outputs)  
Si8650Bx, Ex, Si8655Bx  
VDD1  
4.1  
4.4  
5.7  
6.1  
mA  
mA  
mA  
VDD2  
Si8651Bx, Ex  
VDD1  
4.3  
4.3  
6.0  
6.0  
VDD2  
Si8652Bx, Ex  
VDD1  
4.3  
4.4  
6.0  
6.1  
VDD2  
100 Mbps Supply Current (All Inputs = 50 MHz Square Wave, CI = 15 pF on All Outputs)  
Si8650Bx, Ex, Si8655Bx  
VDD1  
VDD2  
4.1  
5.7  
mA  
mA  
mA  
15.5  
20.1  
Si8651Bx, Ex  
VDD1  
6.6  
8.9  
13.2  
17.1  
VDD2  
Si8652Bx, Ex  
VDD1  
8.9  
11.6  
14.4  
11.1  
VDD2  
Timing Characteristics  
Si865xBx, Ex  
Maximum Data Rate  
Minimum Pulse Width  
Propagation Delay  
0
150  
5.0  
13  
Mbps  
ns  
tPHL, tPLH See Figure 4.2 Propagation  
Delay Timing on page 15  
5.0  
8.0  
ns  
Pulse Width Distortion  
PWD  
See Figure 4.2 Propagation  
Delay Timing on page 15  
0.2  
4.5  
ns  
|tPLH – tPHL  
|
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Si8650/51/52/55 Data Sheet  
Electrical Specifications  
Parameter  
Symbol  
Test Condition  
Min  
Typ  
Max  
Unit  
Propagation Delay Skew 2  
Channel-Channel Skew  
All Models  
tPSK(P-P)  
2.0  
4.5  
ns  
tPSK  
0.4  
2.5  
ns  
Output Rise Time  
tr  
CL = 15 pF  
2.5  
4.0  
ns  
See Figure 4.2 Propagation  
Delay Timing on page 15  
Output Fall Time  
tf  
CL = 15 pF  
2.5  
4.0  
ns  
(See Figure 4.2 Propagation  
Delay Timing on page 15)  
Peak eye diagram jitter  
tJIT(PK)  
CMTI  
See Figure 2.3 Eye Diagram  
on page 6  
350  
50  
ps  
Common Mode  
VI = VDD or 0 V  
35  
kV/μs  
Transient Immunity  
VCM = 1500 V  
(See Figure 4.3 Common  
Mode Transient Immunity  
Test Circuit on page 15)  
Enable to Data Valid  
ten1  
ten2  
tSU  
See Figure 4.1 ENABLE  
Timing Diagram on page 15  
6.0  
8.0  
15  
11  
12  
40  
ns  
ns  
μs  
Enable to Data Tri-State  
See Figure 4.1 ENABLE  
Timing Diagram on page 15  
Start-Up Time 3  
Notes:  
1. The nominal output impedance of an isolator driver channel is approximately 50 Ω, ±40%, which is a combination of the value of  
the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission  
line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces.  
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same  
supply voltages, load, and ambient temperature.  
3. Start-up time is the time period from the application of power to valid data at the output.  
Table 4.4. Electrical Characteristics  
(VDD1 = 2.5 V ±5%, VDD2 = 2.5 V ±5%, TA = –40 to 125 °C)  
Parameter  
Symbol  
VDDUV+  
VDDUV–  
VDDHYS  
VT+  
Test Condition  
VDD1, VDD2 rising  
VDD1, VDD2 falling  
Min  
Typ  
2.24  
2.16  
70  
Max  
2.375  
2.325  
95  
Unit  
V
VDD Undervoltage Threshold  
VDD Undervoltage Threshold  
VDD Undervoltage Hysteresis  
Positive-Going Input Threshold  
Negative-Going Input Threshold  
Input Hysteresis  
1.95  
1.88  
V
50  
mV  
V
All inputs rising  
All inputs falling  
1.4  
1.67  
1.23  
0.44  
1.9  
VT–  
1.0  
1.4  
V
VHYS  
0.38  
0.50  
V
High Level Input Voltage  
Low Level Input Voltage  
VIH  
2.0  
V
VIL  
0.8  
V
High Level Output Voltage  
VOH  
loh = –4 mA  
VDD1,VDD2 – 0.4  
2.3  
V
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Si8650/51/52/55 Data Sheet  
Electrical Specifications  
Parameter  
Low Level Output Voltage  
Input Leakage Current  
Symbol  
VOL  
IL  
Test Condition  
Min  
Typ  
0.2  
Max  
0.4  
±10  
Unit  
V
lol = 4 mA  
μA  
Ω
Output Impedance 1  
ZO  
50  
Enable Input High Current  
Enable Input Low Current  
IENH  
IENL  
VENx = VIH  
VENx = VIL  
2.0  
2.0  
μA  
μA  
DC Supply Current (All Inputs 0 V or at Supply)  
Si8650Bx, Ex, Si8655Bx  
VDD1  
VI = 0(Bx), 1(Ex)  
VI = 0(Bx), 1(Ex)  
VI = 1(Bx), 0(Ex)  
VI = 1(Bx), 0(Ex)  
1.1  
3.1  
7.0  
3.3  
1.8  
4.7  
9.8  
5.0  
mA  
mA  
mA  
VDD2  
VDD1  
VDD2  
Si8651Bx, Ex  
VDD1  
VI = 0(Bx), 1(Ex)  
VI = 0(Bx), 1(Ex)  
VI = 1(Bx), 0(Ex)  
VI = 1(Bx), 0(Ex)  
1.5  
2.7  
6.6  
4.0  
2.4  
4.1  
9.2  
6.0  
VDD2  
VDD1  
VDD2  
Si8652Bx, Ex  
VDD1  
VI = 0(Bx), 1(Ex)  
VI = 0(Bx), 1(Ex)  
VI = 1(Bx), 0(Ex)  
VI = 1(Bx), 0(Ex)  
2.0  
2.4  
5.6  
5.0  
3.0  
3.6  
7.8  
7.5  
VDD2  
VDD1  
VDD2  
1 Mbps Supply Current (All Inputs = 500 kHz Square Wave, CI = 15 pF on All Outputs)  
Si8650Bx, Ex, Si8655Bx  
VDD1  
4.1  
3.7  
5.7  
5.2  
mA  
mA  
mA  
VDD2  
Si8651Bx, Ex  
VDD1  
4.2  
3.8  
5.8  
5.3  
VDD2  
Si8652Bx, Ex  
VDD1  
4.0  
4.0  
5.6  
5.6  
VDD2  
10 Mbps Supply Current (All Inputs = 5 MHz Square Wave, CI = 15 pF on All Outputs)  
Si8650Bx, Ex, Si8655Bx  
VDD1  
4.1  
4.0  
5.7  
5.6  
mA  
VDD2  
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Si8650/51/52/55 Data Sheet  
Electrical Specifications  
Parameter  
Si8651Bx, Ex  
VDD1  
Symbol  
Test Condition  
Min  
Typ  
Max  
Unit  
4.2  
4.0  
5.9  
5.6  
mA  
VDD2  
Si8652Bx, Ex  
VDD1  
4.1  
4.2  
5.8  
5.9  
mA  
VDD2  
100 Mbps Supply Current (All Inputs = 50 MHz Square Wave, CI = 15 pF on All Outputs)  
Si8650Bx, Ex, Si8655Bx  
VDD1  
VDD2  
4.1  
5.7  
mA  
mA  
mA  
12.5  
16.2  
Si8651Bx, Ex  
VDD1  
6.0  
8.1  
14  
10.8  
VDD2  
Si8652Bx, Ex  
VDD1  
7.6  
9.3  
9.9  
12.0  
VDD2  
Timing Characteristics  
Si865xBx, Ex  
Maximum Data Rate  
Minimum Pulse Width  
Propagation Delay  
0
150  
5.0  
14  
Mbps  
ns  
tPHL, tPLH See Figure 4.2 Propagation  
Delay Timing on page 15  
5.0  
8.0  
ns  
Pulse Width Distortion  
PWD  
See Figure 4.2 Propagation  
Delay Timing on page 15  
0.2  
5.0  
ns  
|tPLH - tPHL  
|
Propagation Delay Skew 2  
Channel-Channel Skew  
All Models  
tPSK(P-P)  
tPSK  
2.0  
0.4  
5.0  
2.5  
ns  
ns  
Output Rise Time  
tr  
CL = 15 pF  
2.5  
2.5  
4.0  
4.0  
ns  
ns  
ps  
See Figure 4.2 Propagation  
Delay Timing on page 15  
Output Fall Time  
tf  
CL = 15 pF  
See Figure 4.2 Propagation  
Delay Timing on page 15  
Peak Eye Diagram Jitter  
tJIT(PK)  
See Figure 2.3 Eye Diagram  
on page 6  
350  
silabs.com | Building a more connected world.  
Rev. 2.01 | 20  
Si8650/51/52/55 Data Sheet  
Electrical Specifications  
Parameter  
Symbol  
Test Condition  
Min  
Typ  
Max  
Unit  
Common Mode Transient Immunity  
CMTI  
VI = VDD or 0 V  
35  
50  
kV/μs  
VCM = 1500 V (See Figure  
4.3 Common Mode Transi-  
ent Immunity Test Circuit on  
page 15)  
Enable to Data Valid  
ten1  
ten2  
tSU  
See Figure 4.1 ENABLE  
Timing Diagram on page 15  
6.0  
8.0  
15  
11  
12  
40  
ns  
ns  
μs  
Enable to Data Tri-State  
See Figure 4.1 ENABLE  
Timing Diagram on page 15  
Startup Time 3  
Notes:  
1. The nominal output impedance of an isolator driver channel is approximately 50 Ω, ±40%, which is a combination of the value of  
the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission  
line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces.  
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same  
supply voltages, load, and ambient temperature.  
3. Start-up time is the time period from the application of power to valid data at the output.  
Table 4.5. Regulatory Information 1  
CSA  
The Si865x is certified under CSA Component Acceptance Notice 5A. For more details, see Master Contract Number 232873.  
60950-1, 62368-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage.  
60601-1: Up to 250 VRMS working voltage and 2 MOPP (Means of Patient Protection).  
VDE  
The Si865x is certified according to VDE 0884-10. For more details, see certificate 40018443.  
0884-10: Up to 1200 Vpeak for basic insulation working voltage.  
60950-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage.  
UL  
The Si865x is certified under UL1577 component recognition program. For more details, see File E257455.  
Rated up to 5000 VRMS isolation voltage for basic protection.  
CQC  
The Si865x is certified under GB4943.1-2011. For more details, see certificates CQC13001096110 and CQC13001096239.  
Rated up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage.  
Note:  
1. Regulatory Certifications apply to 2.5 kVRMS rated devices which are production tested to 3.0 kVRMS for 1 sec. Regulatory Certifi-  
cations apply to 3.75 kVRMS rated devices which are production tested to 4.5 kVRMS for 1 sec. Regulatory Certifications apply to  
5.0 kVRMS rated devices which are production tested to 6.0 kVRMS for 1 sec.  
For more information, see 1. Ordering Guide.  
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Si8650/51/52/55 Data Sheet  
Electrical Specifications  
Table 4.6. Insulation and Safety-Related Specifications  
Parameter  
Symbol  
Test Condition  
Value  
NB SOIC-16  
4.9  
Unit  
WB SOIC-16  
QSOP-16  
Nominal External Air Gap (Clearance)1  
CLR  
CPG  
DTI  
8.0  
3.6  
3.6  
mm  
mm  
mm  
Nominal External Tracking (Creepage) 1  
Minimum Internal Gap  
(Internal Clearance)  
8.0  
4.01  
0.014  
0.014  
0.014  
Tracking Resistance  
CTI or PTI  
ED  
IEC60112  
f = 1 MHz  
600  
600  
600  
VRMS  
mm  
Ω
Erosion Depth  
0.019  
0.019  
0.031  
Resistance (Input-Output)2  
Capacitance (Input-Output)2  
1012  
2.0  
1012  
2.0  
1012  
2.0  
RIO  
CIO  
CI  
pF  
pF  
Input Capacitance3  
4.0  
4.0  
4.0  
Note:  
1. The values in this table correspond to the nominal creepage and clearance values. VDE certifies the clearance and creepage  
limits as 4.7 mm minimum for the NB SOIC-16 package and QSOP-16 packages and 8.5 mm minimum for the WB SOIC-16  
package. UL does not impose a clearance and creepage minimum for component-level certifications. CSA certifies the clearance  
and creepage of the WB SOIC-16 package with designation "IS2" as 8 mm minimum. CSA certifies the clearance and creepage  
limits as 3.9 mm minimum for the NB SOIC 16, 3.6 mm minimum for the QSOP-16, and 7.6 mm minimum for the WB SOIC-16  
package with package designation "IS" as listed in the data sheet.  
2. To determine resistance and capacitance, the Si86xx is converted into a 2-terminal device. Pins 1–8 are shorted together to form  
the first termina and pins 9–16 are shorted together to form the second terminal. The parameters are then measured between  
these two terminals.  
3. Measured from input pin to ground.  
Table 4.7. IEC 60664-1 Ratings  
Parameter  
Test Conditions  
Specification  
WB SOIC-16  
NB SOIC-16  
QSOP-16  
Basic Isolation Group  
Material Group  
I
I
I
Installation Classification  
Rated Mains Voltages < 150  
VRMS  
I-IV  
I-IV  
I-IV  
Rated Mains Voltages < 300  
VRMS  
I-IV  
I-III  
I-III  
I-III  
I-II  
I-II  
I-III  
I-II  
I-II  
Rated Mains Voltages < 400  
VRMS  
Rated Mains Voltages < 600  
VRMS  
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Si8650/51/52/55 Data Sheet  
Electrical Specifications  
Table 4.8. VDE 0884-10 Insulation Characteristics for Si86xxxx1  
Characteristic  
WB SOIC-16 NB SOIC-16 QSOP-16  
Parameter  
Symbol  
Test Condition  
Unit  
Maximum Working Insulation  
Voltage  
VIORM  
1200  
630  
630  
Vpeak  
Method b1  
(VIORM x 1.875 = VPR, 100%  
Production Test, tm = 1 sec,  
Partial Discharge < 5 pC)  
t = 60 sec  
VPR  
Input to Output Test Voltage  
2250  
6000  
1182  
6000  
1182  
6000  
Vpeak  
VIOTM  
Transient Overvoltage  
Surge Voltage  
Vpeak  
Vpeak  
Tested per IEC 60065 with surge  
voltage of 1.2 µs/50 µs  
VIOSM  
Si865xxB/C/D tested with 4000 V  
3077  
2
3077  
2
3077  
2
Pollution Degree  
(DIN VDE 0110, Table 1)  
Insulation Resistance at TS, VIO  
= 500 V  
>109  
>109  
>109  
RS  
Ω
Note:  
1. Maintenance of the safety data is ensured by protective circuits. The Si86xxxx provides a climate classification of 40/125/21.  
Table 4.9. VDE 0884-10 Safety Limiting Values1  
Max  
WB SOIC-16 NB SOIC-16 QSOP-16  
Parameter  
Symbol  
Test Condition  
Unit  
TS  
Case Temperature  
150  
220  
415  
150  
215  
415  
150  
215  
415  
°C  
θJA = 100 °C/W (WB SOIC-16)  
105 °C/W (NB SOIC-16, QSOP-16)  
VI = 5.5 V, TJ = 150 °C, TA = 25 °C  
Safety Input, Output, or Supply  
Current  
IS  
mA  
Device Power Dissipation2  
PD  
mW  
Note:  
1. Maximum value allowed in the event of a failure; also see the thermal derating curve in Figure 4.4 (WB SOIC-16) Thermal Derat-  
ing Curve, Dependence of Safety Limiting Values with Case Temperature per VDE 0884-10 on page 24 and Figure 4.5 (NB  
SOIC-16, QSOP-16) Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per VDE 0884-10  
on page 24.  
2. The Si86xx is tested with VDD1 = VDD2 = 5.5 V; TJ = 150 ºC; CL = 15 pF, input a 150 Mbps 50% duty cycle square wave.  
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Si8650/51/52/55 Data Sheet  
Electrical Specifications  
Table 4.10. Thermal Characteristics  
Parameter  
Symbol  
WB SOIC-16  
NB SOIC-16/QSOP-16  
Unit  
IC Junction-to-Air Thermal Resistance  
θJA  
100  
105  
°C/W  
500  
450  
VDD1, VDD2 = 2.70 V  
VDD1, VDD2 = 3.6 V  
400  
300  
200  
100  
0
370  
220  
VDD1, VDD2 = 5.5 V  
0
50  
100  
150  
200  
Temperature (ºC)  
Figure 4.4. (WB SOIC-16) Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per VDE  
0884-10  
500  
430  
VDD1, VDD2 = 2.70 V  
400  
360  
VDD1, VDD2 = 3.6 V  
300  
215  
200  
VDD1, VDD2 = 5.5 V  
100  
0
0
50  
100  
150  
200  
Temperature (ºC)  
Figure 4.5. (NB SOIC-16, QSOP-16) Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature  
per VDE 0884-10  
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Si8650/51/52/55 Data Sheet  
Electrical Specifications  
Table 4.11. Absolute Maximum Ratings 1  
Parameter  
Storage Temperature 2  
Symbol  
Min  
Max  
Unit  
TSTG  
–65  
–40  
150  
125  
°C  
Ambient Temperature Under Bias  
Junction Temperature  
Supply Voltage  
TA  
°C  
°C  
V
TJ  
150  
VDD1, VDD2  
–0.5  
–0.5  
–0.5  
7.0  
Input Voltage  
VI  
VO  
IO  
VDD + 0.5  
VDD + 0.5  
10  
V
Output Voltage  
V
Output Current Drive Channel  
mA  
(All devices unless otherwise stated)  
Output Current Drive Channel  
(All Si865xxA-x-xx devices)  
IO  
22  
mA  
Latchup Immunity 3  
100  
V/ns  
Lead Solder Temperature (10 s)  
260  
°C  
Maximum Isolation (Input to Output) (1 sec)  
NB SOIC-16, QSOP-16  
4500  
VRMS  
Maximum Isolation (Input to Output) (1 sec)  
WB SOIC-16  
6500  
VRMS  
Notes:  
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to  
conditions as specified in the operational sections of this data sheet.  
2. VDE certifies storage temperature from –40 to 150 °C.  
3. Latchup immunity specification is for slew rate applied across GND1 and GND2.  
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Si8650/51/52/55 Data Sheet  
Pin Descriptions  
5. Pin Descriptions  
5.1 Si8650/51/52 Pin Descriptions  
VDD1  
VDD1  
A1  
VDD1  
VDD2  
B1  
VDD2  
B1  
VDD2  
RF  
XMITR  
RF  
RCVR  
RF  
XMITR  
RF  
RCVR  
RF  
XMITR  
RF  
RCVR  
B1  
A1  
A2  
A1  
A2  
I
s
o
l
a
t
i
o
n
I
s
o
l
a
t
i
o
n
I
RF  
XMITR  
RF  
RCVR  
RF  
XMITR  
RF  
RCVR  
RF  
XMITR  
RF  
RCVR  
B2  
A2  
B2  
s
o
l
a
t
i
o
n
B2  
RF  
XMITR  
RF  
RCVR  
RF  
XMITR  
RF  
RCVR  
RF  
XMITR  
RF  
RCVR  
B3  
A3  
B3  
A3  
A4  
A5  
B3  
A3  
A4  
RF  
XMITR  
RF  
RCVR  
RF  
XMITR  
RF  
RCVR  
RF  
RCVR  
RF  
A4  
B4  
B4  
B4  
XMITR  
RF  
XMITR  
RF  
RCVR  
RF  
RCVR  
RF  
XMITR  
RF  
RCVR  
RF  
XMITR  
A5  
B5  
A5  
B5  
B5  
EN2/NC  
GND2  
EN2  
GND2  
EN2  
GND2  
NC  
EN1  
GND1  
EN1  
GND1  
GND1  
Si8650  
Si8651  
Si8652  
Figure 5.1. Si8650/51/52 Pinout  
Table 5.1. Si8650/51/52 Pin Descriptions  
Type  
Name  
SOIC-16 Pin#  
Description  
VDD1  
A1  
1
2
3
4
5
6
7
Supply  
Side 1 power supply.  
Side 1 digital input.  
Side 1 digital input.  
Side 1 digital input.  
Digital Input  
Digital Input  
Digital Input  
Digital I/O  
A2  
A3  
A4  
Side 1 digital input or output.  
Side 1 digital input or output.  
A5  
Digital I/O  
EN1/NC1  
GND1  
GND2  
EN2  
B5  
Digital Input  
Side 1 active high enable. NC on Si8650.  
8
Ground  
Ground  
Side 1 ground.  
9
Side 2 ground.  
10  
11  
12  
13  
14  
15  
16  
Digital Input  
Digital I/O  
Digital I/O  
Digital Output  
Digital Output  
Digital Output  
Supply  
Side 2 active high enable.  
Side 2 digital input or output.  
Side 2 digital input or output.  
Side 2 digital output.  
Side 2 digital output.  
Side 2 digital output.  
Side 2 power supply.  
B4  
B3  
B2  
B1  
VDD2  
Note:  
1. No Connect. These pins are not internally connected. They can be left floating, tied to VDD or tied to GND.  
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Si8650/51/52/55 Data Sheet  
Pin Descriptions  
5.2 Si8655 Pin Descriptions  
VDD1  
VDD2  
GND2  
B1  
GND1  
A1  
I
s
o
l
RF  
XMITR  
RF  
RCVR  
RF  
XMITR  
RF  
RCVR  
A2  
B2  
a
t
i
o
n
RF  
XMITR  
RF  
RCVR  
A3  
A4  
B3  
RF  
XMITR  
RF  
RCVR  
B4  
RF  
XMITR  
RF  
RCVR  
A5  
B5  
GND2  
GND1  
Si8655  
Figure 5.2. Si8655 Pinout  
Table 5.2. Si8655 Pin Descriptions  
Type  
Name  
VDD1  
SOIC-16 Pin#  
Description  
1
Supply  
Ground  
Side 1 power supply.  
Side 1 ground.  
21  
3
GND1  
A1  
A2  
Digital Input  
Digital Input  
Digital Input  
Digital Input  
Digital Input  
Ground  
Side 1 digital input.  
Side 1 digital input.  
Side 1 digital input.  
Side 1 digital input.  
Side 1 digital input.  
Side 1 ground.  
4
A3  
5
A4  
6
A5  
7
81  
GND1  
91  
10  
11  
12  
13  
14  
GND2  
Ground  
Side 2 ground.  
B5  
B4  
Digital Output  
Digital Output  
Digital Output  
Digital Output  
Digital Output  
Ground  
Side 2 digital output.  
Side 2 digital output.  
Side 2 digital output.  
Side 2 digital output.  
Side 2 digital output.  
Side 2 ground.  
B3  
B2  
B1  
151  
16  
GND2  
VDD2  
Supply  
Side 2 power supply.  
Note:  
1. For narrow-body devices, Pin 2 and Pin 8 GND must be externally connected to respective ground. Pin 9 and Pin 15 must also be  
connected to external ground.  
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Si8650/51/52/55 Data Sheet  
Package Outline (16-Pin Wide Body SOIC)  
6. Package Outline (16-Pin Wide Body SOIC)  
The figure below illustrates the package details for the Si86xx digital isolator in a 16-pin wide-body SOIC package. The table below lists  
the values for the dimensions shown in the illustration.  
Figure 6.1. 16-Pin Wide Body SOIC  
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Si8650/51/52/55 Data Sheet  
Package Outline (16-Pin Wide Body SOIC)  
Table 6.1. 16-Pin Wide Body SOIC Package Diagram Dimensions  
Dimension  
Min  
Max  
2.65  
0.30  
A
A1  
A2  
b
0.10  
2.05  
0.31  
0.20  
0.51  
0.33  
c
D
10.30 BSC  
10.30 BSC  
7.50 BSC  
1.27 BSC  
E
E1  
e
L
0.40  
0.25  
0°  
1.27  
0.75  
8°  
h
θ
aaa  
bbb  
ccc  
ddd  
eee  
fff  
0.10  
0.33  
0.10  
0.25  
0.10  
0.20  
Notes:  
1. All dimensions shown are in millimeters (mm) unless otherwise noted.  
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.  
3. This drawing conforms to JEDEC Outline MS-013, Variation AA.  
4. Recommended reflow profile per JEDEC J-STD-020 specification for small body, lead-free components.  
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Si8650/51/52/55 Data Sheet  
Land Pattern (16-Pin Wide-Body SOIC)  
7. Land Pattern (16-Pin Wide-Body SOIC)  
The figure below illustrates the recommended land pattern details for the Si86xx in a 16-pin wide-body SOIC package. The table below  
lists the values for the dimensions shown in the illustration.  
Figure 7.1. 16-Pin Wide Body SOIC PCB Land Pattern  
Table 7.1. 16-Pin Wide Body SOIC Land Pattern Dimensions  
Dimension  
Feature  
Pad Column Spacing  
Pad Row Pitch  
Pad Width  
(mm)  
9.40  
1.27  
0.60  
1.90  
C1  
E
X1  
Y1  
Pad Length  
Notes:  
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P1032X265-16AN for Density Level B (Median Land Protru-  
sion).  
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed.  
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Si8650/51/52/55 Data Sheet  
Package Outline (16-Pin Narrow Body SOIC)  
8. Package Outline (16-Pin Narrow Body SOIC)  
The figure below illustrates the package details for the Si86xx in a 16-pin narrow-body SOIC package. The table below lists the values  
for the dimensions shown in the illustration.  
Figure 8.1. 16-Pin Narrow Body SOIC  
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Si8650/51/52/55 Data Sheet  
Package Outline (16-Pin Narrow Body SOIC)  
Table 8.1. 16-Pin Narrow Body SOIC Package Diagram Dimensions  
Dimension  
Min  
Max  
1.75  
0.25  
A
A1  
A2  
b
0.10  
1.25  
0.31  
0.17  
0.51  
0.25  
c
D
9.90 BSC  
6.00 BSC  
3.90 BSC  
1.27 BSC  
E
E1  
e
L
0.40  
1.27  
L2  
h
0.25 BSC  
0.25  
0°  
0.50  
8°  
θ
aaa  
bbb  
ccc  
ddd  
0.10  
0.20  
0.10  
0.25  
Notes:  
1. All dimensions shown are in millimeters (mm) unless otherwise noted.  
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.  
3. This drawing conforms to the JEDEC Solid State Outline MS-012, Variation AC.  
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.  
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Si8650/51/52/55 Data Sheet  
Land Pattern (16-Pin Narrow Body SOIC)  
9. Land Pattern (16-Pin Narrow Body SOIC)  
The figure below illustrates the recommended land pattern details for the Si86xx in a 16-pin narrow-body SOIC package. The table  
below lists the values for the dimensions shown in the illustration.  
Figure 9.1. 16-Pin Narrow Body SOIC PCB Land Pattern  
Table 9.1. 16-Pin Narrow Body SOIC Land Pattern Dimensions  
Dimension  
Feature  
Pad Column Spacing  
Pad Row Pitch  
Pad Width  
(mm)  
5.40  
1.27  
0.60  
1.55  
C1  
E
X1  
Y1  
Pad Length  
Notes:  
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X165-16N for Density Level B (Median Land Protrusion).  
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed.  
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Si8650/51/52/55 Data Sheet  
Package Outline (16-Pin QSOP)  
10. Package Outline (16-Pin QSOP)  
The figure below illustrates the package details for the Si86xx in a 16-pin QSOP package. The table below lists the values for the di-  
mensions shown in the illustration.  
Figure 10.1. 16-Pin QSOP Package  
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Si8650/51/52/55 Data Sheet  
Package Outline (16-Pin QSOP)  
Table 10.1. 16-Pin QSOP Package Diagram Dimensions  
Dimension  
Min  
Max  
1.75  
0.25  
A
A1  
A2  
b
0.10  
1.25  
0.20  
0.30  
0.25  
c
0.17  
D
4.89 BSC  
6.00 BSC  
3.90 BSC  
0.635 BSC  
0.40  
E
E1  
e
L
1.27  
L2  
h
0.25 BSC  
0.25  
0.50  
8°  
θ
0°  
aaa  
bbb  
ccc  
ddd  
0.10  
0.20  
0.10  
0.25  
Notes:  
1. All dimensions shown are in millimeters (mm) unless otherwise noted.  
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.  
3. This drawing conforms to the JEDEC Solid State Outline MO-137, Variation AB.  
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.  
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Si8650/51/52/55 Data Sheet  
Land Pattern (16-Pin QSOP)  
11. Land Pattern (16-Pin QSOP)  
The figure below illustrates the recommended land pattern details for the Si86xx in a 16-pin QSOP package. The table below lists the  
values for the dimensions shown in the illustration.  
Figure 11.1. 16-Pin QSOP PCB Land Pattern  
Table 11.1. 16-Pin QSOP Land Pattern Dimensions  
Dimension  
Feature  
Pad Column Spacing  
Pad Row Pitch  
Pad Width  
(mm)  
5.40  
C1  
E
0.635  
0.40  
X1  
Y1  
Pad Length  
1.55  
Notes:  
1. This Land Pattern Design is based on IPC-7351 pattern SOP63P602X173-16N for Density Level B (Median Land Protrusion).  
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed.  
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Si8650/51/52/55 Data Sheet  
Top Marking (16-Pin Wide Body SOIC)  
12. Top Marking (16-Pin Wide Body SOIC)  
Si86XYSV  
YYWWRTTTTT  
e4  
TW  
Figure 12.1. 16-Pin Wide Body SOIC Top Marking  
Table 12.1. 16-Pin Wide Body SOIC Top Marking Explanation  
Si86 = Isolator product series  
XY = Channel Configuration  
X = # of data channels (5)  
Y = # of reverse channels (2, 1, 0) 1  
Base Part Number  
Line 1 Marking: Ordering Options  
(See 1. Ordering Guide for more information).  
S = Speed Grade (max data rate) and operating mode:  
A = 1 Mbps (default output = low)  
B = 150 Mbps (default output = low)  
D = 1 Mbps (default output = high)  
E = 150 Mbps (default output = high)  
V = Insulation rating  
A = 1 kV; B = 2.5 kV; C = 3.75 kV; D = 5.0 kV  
YY = Year  
Assigned by assembly subcontractor. Corresponds to the year  
and work week of the mold date.  
WW = Workweek  
Line 2 Marking:  
Manufacturing code from assembly house  
“R” indicates revision  
RTTTTT = Mfg Code  
Circle = 1.7 mm Diameter  
“e4” Pb-free symbol  
Line 3 Marking: (Center-Justified)  
Country of Origin ISO Code Abbreviation  
TW = Taiwan as shown, TH = Thailand  
Note:  
1. Si8655 has 0 reverse channels.  
1
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Si8650/51/52/55 Data Sheet  
Top Marking (16-Pin Narrow Body SOIC)  
13. Top Marking (16-Pin Narrow Body SOIC)  
Si86XYSV  
YYWWRTTTTT  
e3  
Figure 13.1. 16-Pin Narrow Body SOIC Top Marking  
Table 13.1. 16-Pin Narrow Body SOIC Top Marking Explanation  
Si86 = Isolator product series  
XY = Channel Configuration  
X = # of data channels (5)  
Y = # of reverse channels (2, 1, 0) 1  
S = Speed Grade (max data rate) and operating mode:  
Base Part Number  
Line 1 Marking:  
A = 1 Mbps (default output = low)  
B = 150 Mbps (default output = low)  
D = 1 Mbps (default output = high)  
E = 150 Mbps (default output = high)  
V = Insulation rating  
Ordering Options  
(See 1. Ordering Guide for more information).  
A = 1 kV; B = 2.5 kV; C = 3.75 kV  
“e3” Pb-Free Symbol  
Circle = 1.2 mm Diameter  
YY = Year  
Assigned by the assembly subcontractor. Corresponds to the  
year and work week of the mold date.  
Line 2 Marking: WW = Work Week  
Manufacturing code from assembly house.  
“R” indicates revision.  
RTTTTT = Mfg Code  
Note:  
1. Si8655 has 0 reverse channels.  
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Rev. 2.01 | 38  
 
 
Si8650/51/52/55 Data Sheet  
Top Marking (16-Pin QSOP)  
14. Top Marking (16-Pin QSOP)  
Figure 14.1. 16-Pin QSOP Top Marking  
Table 14.1. 16-Pin QSOP Top Marking Explanation  
86 = Isolator product series  
XY = Channel Configuration  
X = # of data channels (5)  
Y = # of reverse channels (2, 1, 0) 1  
Base Part Number  
S = Speed Grade (max data rate) and operating mode:  
A = 1 Mbps (default output = low)  
B = 150 Mbps (default output = low)  
D = 1 Mbps (default output = high)  
E = 150 Mbps (default output = high)  
V = Insulation rating.  
Line 1 Marking: Ordering Options  
(See 1. Ordering Guide for more information).  
A = 1 kV; B = 2.5 kV; C = 3.75 kV  
Manufacturing code from assembly house.  
“R” indicates revision.  
Line 2 Marking: RTTTTT = Mfg Code  
YY = Year  
Line 3 Marking:  
Assigned by the Assembly House. Corresponds to the year and  
work week of the mold date.  
WW = Work Week  
Note:  
1. Si8655 has 0 reverse channels.  
silabs.com | Building a more connected world.  
Rev. 2.01 | 39  
 
 
Si8650/51/52/55 Data Sheet  
Revision History  
15. Revision History  
Revision 2.01  
January 2018  
• Added new table to Ordering Guide for Automotive-Grade OPN options.  
Revision 2.0  
October 18, 2017  
• Added new OPNs in Ordering Guide for IU (QSOP) and IS2 (8 mm creepage WB SOIC) package options.  
• Added 62368-1 references throughout.  
• Removed 61010-1 references throughout.  
Revision 1.9  
November 30, 2016  
• Updated data sheet format.  
Added note to Table 1.1 Ordering Guide for Valid OPNs1, 2, 3 on page 2 for denoting tape and reel marking.  
Revision 1.8  
June 18, 2015  
Updated Table 4.5 Regulatory Information 1 on page 21.  
• Added CQC certificate numbers.  
• Updated 1. Ordering Guide.  
• Removed references to moisture sensitivity levels.  
• Removed former note 2.  
Revision 1.7  
September 25, 2013  
• Added Figure 4.3 Common Mode Transient Immunity Test Circuit on page 15.  
• Added references to CQC throughout.  
• Added references to 2.5 kVRMS devices throughout.  
• Updated 1. Ordering Guide.  
• Updated 12. Top Marking (16-Pin Wide Body SOIC).  
• Updated 14. Top Marking (16-Pin QSOP).  
Revision 1.6  
June 26, 2012  
Added junction temperature spec to Table 4.11 Absolute Maximum Ratings 1 on page 25.  
• Updated 3.3.1 Supply Bypass.  
• Removed former Section 3.3.2. Pin Connections.  
• Updated table notes in 5.1 Si8650/51/52 Pin Descriptions.  
• Removed Rev A devices from 1. Ordering Guide.  
• Updated 6. Package Outline (16-Pin Wide Body SOIC).  
• Added revision description to Top Markings.  
Revision 1.5  
March 20, 2012  
• Updated 1. Ordering Guide to include MSL2A.  
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Si8650/51/52/55 Data Sheet  
Revision History  
Revision 1.4  
February 15, 2012  
Updated Table 1.1 Ordering Guide for Valid OPNs1, 2, 3 on page 2.  
• Updated Note 1 with MSL2A.  
Revision 1.3  
November 11, 2011  
• Added Output Current Drive Channel specification for Si865xxA-x-xx devices.  
• Added Latchup Immunity specification.  
Revision 1.2  
September 14, 2011  
• Updated High Level Output Voltage VOH to 3.1 V in Table 4.3 Electrical Characteristics on page 16.  
• Updated High Level Output Voltage VOH to 2.3 V in Table 4.4 Electrical Characteristics on page 18.  
Revision 1.1  
July 14, 2011  
• Reordered spec tables to conform to new convention.  
• Removed "pending" throughout document.  
Revision 1.0  
March 31, 2011  
• Added chip graphics on the front page.  
Moved Table 4.1 Recommended Operating Conditions on page 12 and Table 4.11 Absolute Maximum Ratings 1 on page 25.  
• Updated 4. Electrical Specifications.  
Moved Table 3.1 Si865x Logic Operation on page 7 and Table 3.2 Enable Input Truth 1 on page 8.  
• Moved 3.5 Typical Performance Characteristics.  
• Updated 5.1 Si8650/51/52 Pin Descriptions.  
• Updated 5.2 Si8655 Pin Descriptions.  
• Updated 1. Ordering Guide.  
Revision 0.2  
September 15, 2010  
• Deleted Sections 4.3.4 and 4.3.5.  
• Updated 1. Ordering Guide.  
Updated Table 1.1 Ordering Guide for Valid OPNs1, 2, 3 on page 2.  
• Added 3.4 Fail-Safe Operating Mode.  
Revision 0.1  
June 30, 2010  
• Initial release.  
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Rev. 2.01 | 41  
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intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical"  
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