SL28442AZC-2T_技术文档

SL28442-2

Clock Generator for Intel^®Alviso Chipset

• 96 /100 MHz Spreadable differential clock.

• 33 MHz PCI clock

Features

• Compliant to Intel^®CK410M

• Supports Intel Pentium-M CPU

• Selectable CPU frequencies

• Differential CPU clock pairs

• 100 MHz differential SRC clocks

• 96 MHz differential dot clock

• 48 MHz USB clocks

• Low-voltage frequency select input

• I²C support with readback capabilities

• Ideal Lexmark Spread Spectrum profile for maximum

electromagnetic interference (EMI) reduction

• 3.3V power supply

• 56-pin TSSOP package

CPU

SRC DOT96

x1

PCI

x 6

REF SSCG USB_48

x 2 x 1 x 1

• SRC clocks independently stoppable through

CLKREQ#[A:B]

x2 / x3 x5/6/7

Block Diagram

Pin Configuration

VDD_REF

XIN

14.318MHz

Crystal

PCI2/SEL_CLKREQ**

PCI_STP#*

CPU_STP#*

FS_C_TEST_SE/REF0

1

2

3

4

5

6

7

8

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

VDD_REF

VSS_REF

PCI3

PCI4

PCI5

VSS_PCI

VDD_PCI

ITP_EN/PCIF0

REF

XOUT

PLL Reference

Divider

IREF

VDD_CPU

CPUT

PCI_STP#

PLL1

CPU

REF1

VSSA2

XIN

XOUT

VDDA2

SDATA

SCLK

VSS_CPU

CPUT0

CPUC0

VDD_CPU

CPUT1

CPUC1

IREF

CPUC

CPU_STP#

CLKREQ[A:B]#

FS_[C:A]

VDD_CPU

CPUT_ITP/SRCT7

CPUC_ITP/SRCC7

**96_100_SEL/PCIF1

9

VDD_SRC

SRCT[1:5]

CPUC[1:5]

VDD_PCI

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

*VTTPWRGD#/PD

VDD_48

FS_A/48M_0

VSS_48

DOT96T

PCI

VDD_PCI

PCIF

DOT96C

FS_B/TESTMODE

96_100_SSCT

96_100_SSCC

VDD_48MHz

96_100_SSCT

96_100_SSCC

PLL2

96MSS

Divider

SRCT1

SRCC1

VDD_SRC

SRCT2

SRCC2

VSSA

VDDA

CPU2T_ITP/SRCT7

CPU2C_ITP/SRCC7

VDD_SRC_ITP

SRCT6/CLKREQA#*

SRCC6/CLKREQB#*

SRCT5

VDD_48MHz

DOT96T

DOT96C

PLL3

FIXED

SRCT3

VDD_48

USB

SRCC3

SRCT4_SATA

SRCC4_SATA

VDD_SRC

VTTPWR_GD#/PD

SRCC5

VSS_SRC

56 pin TSSOP

I2C

Logic

SDATA

SCLK

* Internal pull-up

** Internal pull-down

Rev 1.2, July 3 , 2007

Page 1 of 21

2200 Laurelwood Road, Santa Clara, CA 95054

Tel:(408) 855-0555 Fax:(408) 855-0550

www.SpectraLinear.com

SL28442-2

Pin Definitions

Pin No.

Name

VDD_REF

VSS_REF

Type

Description

1

PWR 3.3V power supply for output

GND Ground for outputs.

2

33,32

CLKREQA#/SRCT6, I/O, PU 3.3V LVTTL input for enabling assigned SRC clock (active low) /100MHz

CLKREQB#/SRCC6

Serial Reference Clock.

Selectable through CLKREQA# defaults to enable/disable SRCT/C4,

CLKREQB# defaults to enable/disable SRCT/C5. Assignment can be changed

via SMBUS register Byte 8.

7

VDD_PCI

VSS_PCI

PCI

PWR 3.3V power supply for outputs.

GND Ground for outputs.

O, SE 33-MHz clock

6

3,4,5

8

ITP_EN/PCIF0

I/O, SE 3.3V LVTTL input to enable SRC7 or CPU2_ITP/33MHz clock output.

(sampled on the VTT_PWRGD# assertion).

1 = CPU2_ITP, 0 = SRC7

9

PCIF1/96_100_SEL

VTT_PWRGD#/PD

I/O, 33-MHz clock/3.3V-tolerant input for 96_100M frequency selection

PD,SE (sampled on the VTT_PWRGD# assertion).

1 = 100 MHz, 0 = 96 MHz

10

I, PU 3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A,

FS_B, FS_C and ITP_EN, 96MSS_SRC_SEL inputs, SEL_CLKREQ. After

VTT_PWRGD# (active LOW) assertion, this pin becomes a real-time input for

asserting power down (active HIGH).

11

12

VDD_48

PWR 3.3V power supply for outputs.

FS_A/48_M0

I/O 3.3V-tolerant input for CPU frequency selection/fixed 48-MHz clock output.

Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.

13

VSS_48

GND Ground for outputs.

14,15

16

DOT96T, DOT96C

FS_B/TEST_MODE

O, DIF Fixed 96-MHz clock output.

I

3.3V-tolerant input for CPU frequency selection. Selects Ref/N or Tri-state

when in test mode

0 = Tri-state, 1 = Ref/N

Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.

17,18

96_100_SSC

O,DIF Differential 96-/100-MHz SS clock for flat-panel display

O, DIF 100-MHz Differential serial reference clocks.

19,20,22,23, SRCT/C

24,25,30,31

21,28

34

VDD_SRC

PWR 3.3V power supply for outputs.

VDD_SRC_ITP

PWR 3.3V power supply for outputs.

26,27

SRC4_SATAT,

SRC4_SATAC

O, DIF Differential serial reference clock. Recommended output for SATA.

29

VSS_SRC

GND Ground for outputs.

36,35

CPUT2_ITP/SRCT7, O, DIF Selectable differential CPU or SRC clock output.

CPUC2_ITP/SRCC7

ITP_EN = 0 @ VTT_PWRGD# assertion = SRC7

ITP_EN = 1 @ VTT_PWRGD# assertion = CPU2

37

38

39

VDDA

VSSA

IREF

PWR 3.3V power supply for PLL.

GND Ground for PLL.

I

A precision resistor is attached to this pin, which is connected to the internal

current reference.

42

VDD_CPU

PWR 3.3V power supply for outputs.

O, DIF Differential CPU clock outputs.

GND Ground for outputs.

40, 41,43,44 CPUT/C

45

46

47

48

VSS_CPU

SCLK

I

SMBus-compatible SCLOCK.

SMBus-compatible SDATA.

SDATA

VDDA2

I/O

PWR 3.3V power supply for PLL2

Rev 1.2,July 3 , 2007

Page 2 of 21

SL28442-2

Pin Definitions (continued)

Pin No.

Name

Type

Description

49

50

51

52

53

XOUT

XIN

O, SE 14.318-MHz crystal output.

I

14.318-MHz crystal input.

VSSA2

REF1

GND Ground for PLL2.

O

Fixed 14.318 MHz clock output.

FS_C_TEST_SEL/

REF0

I/O

3.3V-tolerant input for CPU frequency selection/fixed 14.318 clock output.

Selects test mode if pulled to greater than 1.8V when VTT_PWRGD# is asserted

LOW.

Refer to DC Electrical Specifications table for V_{IL_FS},V_{IH_FS}specifications.

54

55

56

CPU_STP#

PCI_STP#

I, PU 3.3V LVTTL input for CPU_STP# active low.

I, PU 3.3V LVTTL input for PCI_STP# active low.

PCI2/SEL_CLKREQ I/O, PD 3.3V-tolerant input for CLKREQ pin selection/fixed 33-MHz clock output.

(sampled on the VTT_PWRGD# assertion).

1 = pins 32,33 function as clk request pins, 0 = pins 32,33 function as SRC outputs.

Table 1. Frequency Select Table FS_A, FS_B and FS_C

FS_C

FS_B

FS_A

CPU

SRC

PCIF/PCI

33 MHz

REF0

DOT96

96 MHz

USB

1

0

1

0

100 MHz

14.318 MHz

48 MHz

66.6667 MHz

83.3333 MHz

71.4286 MHz

initialize to their default setting upon power-up, and therefore

use of this interface is optional. Clock device register changes

are normally made upon system initialization, if any are

required. The interface cannot be used during system

operation for power management functions.

Frequency Select Pins (FS_A, FS_B, and FS_C)

Host clock frequency selection is achieved by applying the

appropriate logic levels to FS_A, FS_B, FS_C inputs prior to

VTT_PWRGD# assertion (as seen by the clock synthesizer).

Upon VTT_PWRGD# being sampled LOW by the clock chip

(indicating processor VTT voltage is stable), the clock chip

samples the FS_A, FS_B, and FS_C input values. For all logic

levels of FS_A, FS_B, and FS_C, VTT_PWRGD# employs a

Data Protocol

The clock driver serial protocol accepts byte write, byte read,

block write, and block read operations from the controller. For

block write/read operation, the bytes must be accessed in

sequential order from lowest to highest byte (most significant

bit first) with the ability to stop after any complete byte has

been transferred. For byte write and byte read operations, the

system controller can access individually indexed bytes. The

offset of the indexed byte is encoded in the command code,

as described in Table 2.

one-shot functionality in that once

a valid LOW on

VTT_PWRGD# has been sampled, all further VTT_PWRGD#,

FS_A, FS_B, and FS_C transitions will be ignored, except in

test mode.

Serial Data Interface

To enhance the flexibility and function of the clock synthesizer,

a two-signal serial interface is provided. Through the Serial

Data Interface, various device functions, such as individual

clock output buffers, can be individually enabled or disabled.

The registers associated with the Serial Data Interface

The block write and block read protocol is outlined in Table 3

while Table 4 outlines the corresponding byte write and byte

read protocol. The slave receiver address is 11010010 (D2h).

Table 2. Command Code Definition

Bit

Description

7

0 = Block read or block write operation, 1 = Byte read or byte write operation

(6:0) Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'

Table 3. Block Read and Block Write Protocol

Block Write Protocol

Description

Block Read Protocol

Description

Bit

1

Bit

1

Start

Slave address – 7 bits

Start

Slave address – 7 bits

8:2

Rev 1.2,July 3 , 2007

Page 3 of 21

SL28442-2

Table 3. Block Read and Block Write Protocol (continued)

Block Write Protocol

Block Read Protocol

Description

Bit

9

Description

Bit

9

Write

10

Acknowledge from slave

Command Code – 8 bits

Acknowledge from slave

Byte Count – 8 bits

10

Acknowledge from slave

Command Code – 8 bits

Acknowledge from slave

Repeat start

18:11

19

18:11

19

27:20

28

20

Acknowledge from slave

Data byte 1 – 8 bits

27:21

28

Slave address – 7 bits

Read = 1

36:29

37

Acknowledge from slave

Data byte 2 – 8 bits

29

Acknowledge from slave

Byte Count from slave – 8 bits

Acknowledge

45:38

46

37:30

38

Acknowledge from slave

Data Byte /Slave Acknowledges

Data Byte N – 8 bits

Acknowledge from slave

Stop

....

46:39

47

Data byte 1 from slave – 8 bits

Acknowledge

....

55:48

56

Data byte 2 from slave – 8 bits

Acknowledge

....

Data bytes from slave / Acknowledge

Data Byte N from slave – 8 bits

NOT Acknowledge

....

Stop

Table 4. Byte Read and Byte Write Protocol

Byte Write Protocol

Byte Read Protocol

Description

Bit

1

Description

Bit

1

Start

8:2

9

Slave address – 7 bits

Write

8:2

9

Slave address – 7 bits

Write

10

Acknowledge from slave

Command Code – 8 bits

Acknowledge from slave

Data byte – 8 bits

Acknowledge from slave

Stop

10

Acknowledge from slave

Command Code – 8 bits

Acknowledge from slave

Repeated start

18:11

19

18:11

19

27:20

28

20

27:21

28

Slave address – 7 bits

Read

29

Acknowledge from slave

Data from slave – 8 bits

NOT Acknowledge

Stop

37:30

38

39

Control Registers

Byte 0: Control Register 0

Bit

@Pup

Name

Description

7

1

CPUT2_ITP/SRCT7

CPUC2_ITP/SRCC7

CPU[T/C]2_ITP/SRC[T/C]7 Output Enable

0 = Disable (Tri-state), 1 = Enable

6

1

SRC[T/C]6

SRC[T/C]6 Output Enable

0 = Disable (Tri-state), 1 = Enable

Rev 1.2,July 3 , 2007

Page 4 of 21

SL28442-2

Byte 0: Control Register 0 (continued)

Bit

@Pup

Name

Description

5

1

SRC[T/C]5

SRC[T/C]5 Output Enable

0 = Disable (Tri-state), 1 = Enable

4

3

2

1

0

1

SRC[T/C]4

SRC[T/C]3

SRC[T/C]2

SRC[T/C]1

RESERVED

SRC[T/C]4 Output Enable

0 = Disable (Tri-state), 1 = Enable

SRC[T/C]3 Output Enable

0 = Disable (Tri-state), 1 = Enable

SRC[T/C]2 Output Enable

0 = Disable (Tri-state), 1 = Enable

SRC[T/C]1 Output Enable

0 = Disable (Tri-state), 1 = Enable

RESERVED

Byte 1: Control Register 1

Bit

@Pup

Name

Description

7

1

PCIF0

PCIF0 Output Enable

0 = Disabled, 1 = Enabled

6

5

4

3

2

1

0

1

0

DOT_96T/C

USB_48

REF0

DOT_96 MHz Output Enable

0 = Disable (Tri-state), 1 = Enabled

USB_48 MHz Output Enable

0 = Disabled, 1 = Enabled

REF0 Output Enable

0 = Disabled, 1 = Enabled

REF1

REF1 Output Enable

0 = Disabled, 1 = Enabled

CPU[T/C]1

CPU[T/C]0

CPU

CPU[T/C]1 Output Enable

0 = Disable (Tri-state), 1 = Enabled

CPU[T/C]0 Output Enable

0 = Disable (Tri-state), 1 = Enabled

PLL1 (CPU PLL) Spread Spectrum Enable

0 = Spread off, 1 = Spread on

Byte 2: Control Register 2

Bit

@Pup

Name

Description

7

1

PCI5

PCI5 Output Enable

0 = Disabled, 1 = Enabled

6

5

4

1

PCI4

PCI3

PCI2

PCI4 Output Enable

0 = Disabled, 1 = Enabled

PCI3 Output Enable

0 = Disabled, 1 = Enabled

PCI2 Output Enable

0 = Disabled, 1 = Enabled

3

2

1

0

1

Reserved

PCIF1

Reserved, Set = 1

PCIF1 Output Enable

0 = Disabled, 1 = Enabled

Byte 3: Control Register 3

Bit

@Pup

Name

Description

7

0

SRC7

Allow control of SRC[T/C]7 with assertion of PCI_STP# or SW PCI_STP#

0 = Free running, 1 = Stopped with PCI_STP#

6

0

SRC6

Allow control of SRC[T/C]6 with assertion of PCI_STP# or SW PCI_STP#

0 = Free running, 1 = Stopped with PCI_STP#

Rev 1.2,July 3 , 2007

Page 5 of 21

SL28442-2

Byte 3: Control Register 3 (continued)

Bit

@Pup

Name

Description

5

0

SRC5

Allow control of SRC[T/C]5 with assertion of PCI_STP# or SW PCI_STP#

0 = Free running, 1 = Stopped with PCI_STP#

4

3

2

1

0

SRC4

SRC3

Allow control of SRC[T/C]4 with assertion of PCI_STP# or SW PCI_STP#

0 = Free running, 1 = Stopped with PCI_STP#

Allow control of SRC[T/C]3 with assertion of PCI_STP# or SW PCI_STP#

0 = Free running, 1 = Stopped with PCI_STP#

SRC2

Allow control of SRC[T/C]2 with assertion of PCI_STP# or SW PCI_STP#

0 = Free running, 1 = Stopped with PCI_STP#

SRC1

Allow control of SRC[T/C]1 with assertion of PCI_STP# or SW PCI_STP#

0 = Free running, 1 = Stopped with PCI_STP#

RESERVED

Byte 4: Control Register 4

Bit

@Pup

Name

Description

7

0

96_100_SSC

96_100_SSC Drive Mode

0 = Driven in PWRDWN, 1 = Tri-state

6

0

DOT96T/C

DOT_PWRDWN Drive Mode

0 = Driven in PWRDWN, 1 = Tri-state

5

4

0

RESERVED

PCIF1

RESERVED

Allow control of PCIF1 with assertion of SW and HW PCI_STP#

0 = Free running, 1 = Stopped with PCI_STP#

3

2

1

0

1

PCIF0

Allow control of PCIF0 with assertion of SW and HW PCI_STP#

0 = Free running, 1 = Stopped with PCI_STP#

CPU[T/C]2

CPU[T/C]1

CPU[T/C]0

Allow control of CPU[T/C]2 with assertion of CPU_STP#

0 = Free running, 1 = Stopped with CPU_STP#

Allow control of CPU[T/C]1 with assertion of CPU_STP#

0 = Free running, 1 = Stopped with CPU_STP#

Allow control of CPU[T/C]0 with assertion of CPU_STP#

0 = Free running, 1 = Stopped with CPU_STP#

Byte 5: Control Register 5

Bit

@Pup

Name

Description

7

0

SRC[T/C]

SRC[T/C] Stop Drive Mode

0 = Driven when PCI_STP# asserted,1 = Tri-state when PCI_STP#

asserted

6

5

4

0

CPU[T/C]2

CPU[T/C]1

CPU[T/C]0

CPU[T/C]2 Stop Drive Mode

0 = Driven when CPU_STP# asserted,1 = Tri-state when CPU_STP#

asserted

CPU[T/C]1 Stop Drive Mode

0 = Driven when CPU_STP# asserted,1 = Tri-state when CPU_STP#

asserted

CPU[T/C]0 Stop Drive Mode

0 = Driven when CPU_STP# asserted,1 = Tri-state when CPU_STP#

asserted

3

2

1

0

SRC[T/C][7:1]

CPU[T/C]2

CPU[T/C]1

CPU[T/C]0

SRC[T/C] PWRDWN Drive Mode

0 = Driven when PD asserted,1 = Tri-state when PD asserted

CPU[T/C]2 PWRDWN Drive Mode

0 = Driven when PD asserted,1 = Tri-state when PD asserted

CPU[T/C]1 PWRDWN Drive Mode

0 = Driven when PD asserted,1 = Tri-state when PD asserted

CPU[T/C]0 PWRDWN Drive Mode

0 = Driven when PD asserted,1 = Tri-state when PD asserted

Rev 1.2,July 3 , 2007

Page 6 of 21

SL28442-2

Byte 6: Control Register 6

Bit

@Pup

Name

Description

7

0

TEST_SEL

REF/N or Tri-state Select

0 = Tri-state, 1 = REF/N Clock

6

0

TEST_MODE

Test Clock Mode Entry Control

0 = Normal operation, 1 = REF/N or Tri-state mode,

5

4

0

1

RESERVED

REF

RESERVED

REF Output Drive Strength

0 = Low, 1 = High

3

1

PCI, PCIF and SRC clock SW PCI_STP Function

outputs except those set 0=SW PCI_STP assert, 1= SW PCI_STP deassert

to free running

When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will

be stopped in a synchronous manner with no short pulses.

When this bit is set to 1, all STOPPED PCI, PCIF and SRC outputs will

resume in a synchronous manner with no short pulses.

2

1

0

HW

FS_C

FS_B

FS_A

FS_C Reflects the value of the FS_C pin sampled on power up

0 = FS_C was low during VTT_PWRGD# assertion

FS_B Reflects the value of the FS_B pin sampled on power up

0 = FS_B was low during VTT_PWRGD# assertion

FS_A Reflects the value of the FS_A pin sampled on power up

0 = FS_A was low during VTT_PWRGD# assertion

Byte 7: Vendor ID

Bit @Pup

Name

Description

Revision Code Bit 3

Revision Code Bit 2

Revision Code Bit 1

Revision Code Bit 0

Vendor ID Bit 3

7

6

5

4

3

2

1

0

1

0

Revision Code Bit 3

Revision Code Bit 2

Revision Code Bit 1

Revision Code Bit 0

Vendor ID Bit 3

Vendor ID Bit 2

Vendor ID Bit 1

Vendor ID Bit 0

Byte 8: Control Register 8

Bit

@Pup

Name

Description

7

6

5

4

0

CLKREQ#B

SRC[T/C]7CLKREQ#B control

1 = SRC[T/C]7 stoppable by CLKREQ#B pin

0 = SRC[T/C]7 not controlled by CLKREQ#B pin

1

0

CLKREQ#B

SRC[T/C]5 CLKREQ#B control

1 = SRC[T/C]5 stoppable by CLKREQ#B pin

0 = SRC[T/C]5 not controlled by CLKREQ#B pin

SRC[T/C]3 CLKREQ#B control

1 = SRC[T/C]3 stoppable by CLKREQ#B pin

0 = SRC[T/C]3 not controlled by CLKREQ#B pin

SRC[T/C]1 CLKREQ#B control

1 = SRC[T/C]1 stoppable by CLKREQ#B pin

0 = SRC[T/C]1 not controlled by CLKREQ#B pin

3

2

0

1

RESERVED

CLKREQ#A

RESERVED

SRC[T/C]4 CLKREQ#A control

1 = SRC[T/C]4 stoppable by CLKREQ#A pin

0 = SRC[T/C]4 not controlled by CLKREQ#A pin

1

0

CLKREQ#A

SRC[T/C]2 CLKREQ#A control

1 = SRC[T/C]2 stoppable by CLKREQ#A pin

0 = SRC[T/C]2 not controlled by CLKREQ#A pin

Rev 1.2,July 3 , 2007

Page 7 of 21

SL28442-2

Byte 8: Control Register 8 (continued)

Bit

@Pup

Name

Description

0

RESERVED

Byte 9: Control Register 9

Bit

@Pup

Name

S3

7

6

5

4

0

96_100_SSC Spread Spectrum Selection table:

S[3:0] SS%

S2

‘0000’ = –0.8%(Default value)

‘0001’ = –1.0%

‘0010’ = –1.25%

‘0011’ = –1.5%

S1

S0

‘0100’ = –1.75%

‘0101’ = –2.0%

‘0110’ = –2.5%

‘0111’ = –0.5%

‘1000’ = ±0.25%

‘1001’ = ±0.4%

‘1010’ = ±0.5%

‘1011’ = ±0.6%

‘1100’ = ±0.8%

‘1101’ = ±1.0%

‘1110’ = ±1.25%

‘1111’ = ±1.5%

3

2

1

0

1

0

96_100 SEL

96_100 Enable

96_100 SS Enable

96_100 SW HW

Software select 96_100_SSC output frequency, 0 = 96 MHz, 1 = 100 MHz.

96_100_SSC Enable, 0 = Disable, 1 = Enable.

96_100_SSC Spread spectrum enable. 0 = Disable, 1 = Enable.

Select output frequency of 96_100_SSC via software or hardware

0 = Hardware, 1 = Software.

Byte 10: Control Register 10

Bit

@Pup

Name

Description

7

6

0

RESERVED

CLKREQ#B

RESERVED

SRC[T/C]4 CLKREQ#B control

1 = SRC[T/C]4 stoppable by CLKREQ#B pin

0 = SRC[T/C]4not controlled by CLKREQ#B pin

5

0

CLKREQ#B

SRC[T/C]2 CLKREQ#B control

1 = SRC[T/C]2 stoppable by CLKREQ#B pin

0 = SRC[T/C]2 not controlled by CLKREQ#B pin

4

3

0

RESERVED

CLKREQ#A

RESERVED

SRC[T/C]7CLKREQ#A control

1 = SRC[T/C]7 stoppable by CLKREQ#A pin

0 = SRC[T/C]7 not controlled by CLKREQ#A pin

2

1

0

CLKREQ#A

SRC[T/C]5 CLKREQ#A control

1 = SRC[T/C]5 stoppable by CLKREQ#A pin

0 = SRC[T/C]5 not controlled by CLKREQ#A pin

SRC[T/C]3 CLKREQ#A control

1 = SRC[T/C]3 stoppable by CLKREQ#A pin

0 = SRC[T/C]3 not controlled by CLKREQ#A pin

SRC[T/C]1 CLKREQ#A control

1 = SRC[T/C]1 stoppable by CLKREQ#A pin

0 = SRC[T/C]1 not controlled by CLKREQ#A pin

Rev 1.2,July 3 , 2007

Page 8 of 21

SL28442-2

Table 5. Crystal Recommendations

Frequency

Drive

(max.)

Shunt Cap Motional

Tolerance

(max.)

Stability

(max.)

Aging

(max.)

(Fund)

Cut

Loading Load Cap

(max.)

14.31818 MHz

AT

Parallel 20 pF

0.1 mW

5 pF

0.016 pF

35 ppm

30 ppm

5 ppm

.

The SL28442-2 requires a Parallel Resonance Crystal. Substi-

tuting a series resonance crystal will cause the SL28442-2 to

operate at the wrong frequency and violate the ppm specifi-

cation. For most applications there is a 300-ppm frequency

shift between series and parallel crystals due to incorrect

loading.

Clock Chip

Ci2

Ci1

3 to 6p

Crystal Loading

Crystal loading plays a critical role in achieving low ppm perfor-

mance. To realize low ppm performance, the total capacitance

the crystal will see must be considered to calculate the appro-

priate capacitive loading (CL).

X2

X1

Cs2

Cs1

Trace

2.8pF

Figure 1 shows a typical crystal configuration using the two

trim capacitors. An important clarification for the following

discussion is that the trim capacitors are in series with the

crystal not parallel. It’s a common misconception that load

capacitors are in parallel with the crystal and should be

approximately equal to the load capacitance of the crystal.

This is not true.

XTAL

Ce1

Ce2

Trim

33pF

Figure 2. Crystal Loading Example

As mentioned previously, the capacitance on each side of the

crystal is in series with the crystal. This mean the total capac-

itance on each side of the crystal must be twice the specified

load capacitance (CL). While the capacitance on each side of

the crystal is in series with the crystal, trim capacitors

(Ce1,Ce2) should be calculated to provide equal capacitance

loading on both sides.

Use the following formulas to calculate the trim capacitor

values for Ce1 and Ce2.

Figure 1. Crystal Capacitive Clarification

Load Capacitance (each side)

Calculating Load Capacitors

Ce = 2 * CL – (Cs + Ci)

In addition to the standard external trim capacitors, trace

capacitance and pin capacitance must also be considered to

correctly calculate crystal loading. As mentioned previously,

the capacitance on each side of the crystal is in series with the

crystal. This means the total capacitance on each side of the

crystal must be twice the specified crystal load capacitance

(CL). While the capacitance on each side of the crystal is in

series with the crystal, trim capacitors (Ce1,Ce2) should be

calculated to provide equal capacitive loading on both sides.

Total Capacitance (as seen by the crystal)

1

CLe

=

1

(

)

+

Ce2 + Cs2 + Ci2

Ce1 + Cs1 + Ci1

CL....................................................Crystal load capacitance

CLe......................................... Actual loading seen by crystal

using standard value trim capacitors

Ce..................................................... External trim capacitors

Cs..............................................Stray capacitance (terraced)

Ci ...........................................................Internal capacitance

(lead frame, bond wires etc.)

Rev 1.2,July 3 , 2007

Page 9 of 21

SL28442-2

CLK_REQ[0:1]# Description

VTT_PWRGD# has been sampled LOW by the clock chip, the

pin assumes PD functionality. The PD pin is an asynchronous

active HIGH input used to shut off all clocks cleanly prior to

shutting off power to the device. This signal is synchronized

internal to the device prior to powering down the clock synthe-

sizer. PD is also an asynchronous input for powering up the

system. When PD is asserted high, all clocks need to be driven

to a low value and held prior to turning off the VCOs and the

crystal oscillator.

The CLKREQ#[A:B] signals are active LOW inputs used for

clean enabling and disabling selected SRC outputs. The

outputs controlled by CLKREQ#[A:B] are determined by the

settings in register byte 8. The CLKREQ# signal is a

debounced signal in that its state must remain unchanged

during two consecutive rising edges of SRCC to be recognized

as a valid assertion or deassertion. (The assertion and

deassertion of this signal is absolutely asynchronous.)

PD (Power-down)—Assertion

CLK_REQ[A:B]# Assertion (CLKREQ# -> LOW)

When PD is sampled HIGH by two consecutive rising edges

of CPUC, all single-ended outputs will be held LOW on their

next HIGH-to-LOW transition and differential clocks must held

HIGH or tri-stated (depending on the state of the control

register drive mode bit) on the next diff clock# HIGH-to-LOW

transition within 4 clock periods. When the SMBus PD drive

mode bit corresponding to the differential (CPU, SRC, and

DOT) clock output of interest is programmed to ‘0’, the clock

output are held with “Diff clock” pin driven HIGH at 2 x Iref, and

“Diff clock#” tri-state. If the control register PD drive mode bit

corresponding to the output of interest is programmed to “1”,

then both the “Diff clock” and the “Diff clock#” are tri-state. Note

Figure 4 shows CPUT = 133 MHz and PD drive mode = ‘1’ for

all differential outputs. This diagram and description is appli-

cable to valid CPU frequencies 100, 133, 166, 200, 266, 333,

and 400 MHz. In the event that PD mode is desired as the

initial power-on state, PD must be asserted HIGH in less than

10 µs after asserting Vtt_PwrGd#.

All differential outputs that were stopped are to resume normal

operation in a glitch-free manner. The maximum latency from

the assertion to active outputs is between 2–6 SRC clock

periods (2 clocks are shown) with all SRC outputs resuming

simultaneously. All stopped SRC outputs must be driven high

within 10 ns of CLKREQ#[1:0] de-assertion to a voltage

greater than 200 mV.

CLK_REQ[A:B]# Deassertion (CLKREQ# -> HIGH)

The impact of deasserting the CLKREQ#[A:B] pins is all SRC

outputs that are set in the control registers to stoppable via

deassertion of CLKREQ#[A:B] are to be stopped after their

next transition. The final state of all stopped DIF signals is

LOW, both SRCT clock and SRCC clock outputs will not be

driven.

PD (Power-down) Clarification

The VTT_PWRGD# /PD pin is a dual-function pin. During

initial power-up, the pin functions as VTT_PWRGD#. Once

CLKREQ#X

SRCT(free running)

SRCC(free running)

SRCT(stoppable)

Figure 3. CLK_REQ#[A:B] Deassertion/Assertion Waveform

PD

CPUT, 133MHz

CPUC, 133MHz

SRCT 100MHz

SRCC 100MHz

USB, 48MHz

DOT96T

DOT96C

PCI, 33 MHz

REF

Figure 4. Power-down Assertion Timing Waveform

Rev 1.2,July 3 , 2007

Page 10 of 21

SL28442-2

PD Deassertion

When the CPU_STP# pin is asserted, all CPU outputs that are

set with the SMBus configuration to be stoppable via assertion

of CPU_STP# will be stopped within two–six CPU clock

periods after being sampled by two rising edges of the internal

CPUC clock. The final states of the stopped CPU signals are

CPUT = HIGH and CPUC = LOW. There is no change to the

output drive current values during the stopped state. The

CPUT is driven HIGH with a current value equal to 6 x (Iref),

and the CPUC signal will be tri-stated.

The power-up latency is less than 1.8 ms. This is the time from

the deassertion of the PD pin or the ramping of the power

supply until the time that stable clocks are output from the

clock chip. All differential outputs stopped in a three-state

condition resulting from power down will be driven high in less

than 300 µs of PD deassertion to a voltage greater than 200

mV. After the clock chip’s internal PLL is powered up and

locked, all outputs will be enabled within a few clock cycles of

each other. Figure 5 is an example showing the relationship of

clocks coming up.

CPU_STP# Deassertion

The deassertion of the CPU_STP# signal will cause all CPU

outputs that were stopped to resume normal operation in a

synchronous manner. Synchronous manner meaning that no

short or stretched clock pulses will be produce when the clock

resumes. The maximum latency from the deassertion to active

outputs is no more than two CPU clock cycles.

CPU_STP# Assertion

The CPU_STP# signal is an active LOW input used for

synchronous stopping and starting the CPU output clocks

while the rest of the clock generator continues to function.

Tstable

<1.8nS

PD

CPUT, 133MHz

CPUC, 133MHz

SRCT 100MHz

SRCC 100MHz

USB, 48MHz

DOT96T

DOT96C

PCI, 33MHz

Tdrive_PWRDN#

<300µS, >200mV

REF

Figure 5. Power-down Deassertion Timing Waveform

CPU_STP#

CPUT

CPUC

Figure 6. CPU_STP# Assertion Waveform

CPU_STP#

CPUT

CPUC

CPUT Internal

CPUC Internal

Tdrive_CPU_STP#,10nS>200mV

Figure 7. CPU_STP# Deassertion Waveform

Rev 1.2,July 3 , 2007

Page 11 of 21

SL28442-2

1.8mS

CPU_STOP#

PD

CPUT(Free Running

CPUC(Free Running

CPUT(Stoppable)

CPUC(Stoppable)

DOT96T

DOT96C

Figure 8. CPU_STP#= Driven, CPU_PD = Driven, DOT_PD = Driven

1.8mS

CPU_STOP#

PD

CPUT(Free Running)

CPUC(Free Running)

CPUT(Stoppable)

CPUC(Stoppable)

DOT96T

DOT96C

Figure 9. CPU_STP# = Tri-state, CPU_PD = Tri-state, DOT_PD = Tri-state

PCI_STP# Assertion

PCI_STP# Deassertion

The PCI_STP# signal is an active LOW input used for

synchronous stopping and starting the PCI outputs while the

rest of the clock generator continues to function. The set-up

time for capturing PCI_STP# going LOW is 10 ns (t_SU). (See

Figure 10.) The PCIF clocks will not be affected by this pin if

their corresponding control bit in the SMBus register is set to

allow them to be free running.

The deassertion of the PCI_STP# signal will cause all PCI and

stoppable PCIF clocks to resume running in a synchronous

manner within two PCI clock periods after PCI_STP# transi-

tions to a HIGH level.

Tsu

PCI_STP#

PCI_F

PCI

SRC 100MHz

Figure 10. PCI_STP# Assertion Waveform

Rev 1.2,July 3 , 2007

Page 12 of 21

SL28442-2

Tdrive_SRC

Tsu

PCI_STP#

PCI_F

PCI

SRC 100MHz

Figure 11. PCI_STP# Deassertion Waveform

FS_A, FS_B,FS_C

VTT_PWRGD#

PWRGD_VRM

0.2-0.3mS

Delay

Wait for

VTT_PWRGD#

Device is not affected,

VTT_PWRGD# is ignored

Sample Sels

State 2

VDD Clock Gen

Clock State

State 0

Off

State 1

State 3

On

Clock Outputs

Clock VCO

On

Off

Figure 12. VTT_PWRGD# Timing Diagram

S2

S1

VTT_PWRGD# = Low

Delay

Sample

>0.25mS

Inputs straps

VDD_A = 2.0V

Wait for <1.8ms

S0

S3

VDD_A = off

Normal

Operation

Enable Outputs

Power Off

VTT_PWRGD# = toggle

Figure 13. Clock Generator Power-up/Run State Diagram

Rev 1.2,July 3 , 2007

Page 13 of 21

SL28442-2

Absolute Maximum Conditions

Parameter

V_DD

Description

Core Supply Voltage

Condition

Min.

–0.5

Max.

4.6

Unit

V

V_{DD_A}

V_IN

Analog Supply Voltage

4.6

V

Input Voltage

Relative to V_SS

–0.5 V_DD+ 0.5 VDC

T_S

Temperature, Storage

Non-functional

–65

150

85

150

20

60

–

°C

T_A

Temperature, Operating Ambient

Temperature, Junction

Functional

0

–

T_J

Functional

°C

Ø_JC

Dissipation, Junction to Case

Dissipation, Junction to Ambient

ESD Protection (Human Body Model)

Flammability Rating

Mil-STD-883E Method 1012.1

JEDEC (JESD 51)

MIL-STD-883, Method 3015

At 1/8 in.

–

°C/W

V

Ø_JA

–

ESD_HBM

UL-94

MSL

2000

V–0

1

Moisture Sensitivity Level

Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.

DC Electrical Specifications

Parameter

All V_DDs

Description

Condition

Min.

3.135

–

Max.

Unit

V

3.3V Operating Voltage

Input Low Voltage

3.3 ± 5%

3.465

V_ILI2C

V_IHI2C

V_{IL_FS}

V_{IH_FS}

V_{ILFS_C}

V_{IMFS_C}

V_{IHFS_C}

V_IL

SDATA, SCLK

1.0

V

Input High Voltage

2.2

–

V

FS_[A,B] Input Low Voltage

FS_[A,B] Input High Voltage

FS_C Input Low Voltage

FS_C Input Middle Voltage

FS_C Input High Voltage

3.3V Input Low Voltage

3.3V Input High Voltage

Input Low Leakage Current

Input High Leakage Current

3.3V Output Low Voltage

3.3V Output High Voltage

V_SS– 0.3

0.7

0.35

V

V_DD+ 0.5

V

V_SS– 0.3

0.7

0.35

V

1.8

V

1.8

V_DD+ 0.5

V

V_SS– 0.3

2.0

0.8

V

V_IH

V_DD+ 0.3

V

I_IL

Except internal pull-up resistors, 0 < V_IN< V_DD

Except internal pull-down resistors, 0 < V_IN< V_DD

I_OL= 1 mA

–5

5

µA

V

I_IH

–

V_OL

–

0.4

–

V_OH

I_OH= –1 mA

2.4

V

I_OZ

High-impedance Output

Current

–10

10

µA

C_IN

Input Pin Capacitance

Output Pin Capacitance

Pin Inductance

3

5

pF

nH

V

C_OUT

L_IN

3

–

7

V_XIH

Xin High Voltage

0.7V_DD

V_DD

0.3V_DD

400

70

V_XIL

Xin Low Voltage

0

–

V

I_DD3.3V

I_PD3.3V

I_TRI

Dynamic Supply Current

Power-down Supply Current

Tri-state Current

At max. load and freq. per Figure 15

PD asserted, Outputs Driven

PD asserted, Outputs Tri-state

Current in tri-state mode

mA

2

100

Rev 1.2,July 3 , 2007

Page 14 of 21

SL28442-2

AC Electrical Specifications

Parameter

Description

Condition

Min.

Max.

Unit

Crystal

T_DC

XIN Duty Cycle

The device will operate reliably with

input duty cycles up to 30/70 but the

REF clock duty cycle will not be within

specification

47.5

52.5

%

T_PERIOD

T_R/ T_F

T_CCJ

XIN Period

When XIN is driven from an external

clock source

69.841

71.0

10.0

500

ns

ps

XIN Rise and Fall Times

XIN Cycle to Cycle Jitter

Measured between 0.3V_DDand

0.7V_DD

–

As an average over 1-µs duration

CPU at 0.7V

T_DC

CPUT and CPUC Duty Cycle

Measured at crossing point V_OX

45

55

%

T_PERIOD

T_PERIODSS

100-MHz CPUT and CPUC Period

66-MHz CPUT and CPUC Period

83-MHz CPUT and CPUC Period

71-MHz CPUT and CPUC Period

9.997001 10.00300 ns

14.99554 15.00449 ns

11.99640 12.00360 ns

13.9958 14.00419 ns

9.997001 10.05327 ns

100-MHz CPUT and CPUC Period,

SSC

T_PERIODSS

T_PERIODAbs

66-MHz CPUT and CPUC Period, SSC Measured at crossing point V_OX

83-MHz CPUT and CPUC Period, SSC Measured at crossing point V_OX

71-MHz CPUT and CPUC Period, SSC Measured at crossing point V_OX

14.99554 15.07989 ns

11.99640 12.06392 ns

13.9958 14.07457 ns

9.912001 10.08800 ns

100-MHz CPUT and CPUC Absolute Measured at crossing point V_OX

period

T_PERIODAbs

66-MHz CPUT and CPUC Absolute

period

Measured at crossing point V_OX

14.91054 15.08949 ns

11.91140 12.08860 ns

13.9108 14.08919 ns

9.912001 10.13827 ns

14.91054 15.16489 ns

11.91140 12.14892 ns

13.9108 14.15957 ns

T_PERIODAbs

83-MHz CPUT and CPUC Absolute

period

T_PERIODAbs

71-MHz CPUT and CPUC Absolute

period

T_PERIODSSAbs

100-MHz CPUT and CPUC Absolute Measured at crossing point V_OX

period, SSC

66-MHz CPUT and CPUC Absolute

period, SSC

Measured at crossing point V_OX

83-MHz CPUT and CPUC Absolute

period, SSC

71-MHz CPUT and CPUC Absolute

period, SSC

T_CCJ

CPUT/C Cycle to Cycle Jitter

CPU2_ITP Cycle to Cycle Jitter

CPU Long Term Accuracy

Measured at crossing point V_OX

–

85

ps

T_CCJ2

L_ACC

125

300

100

150

700

–

ppm

ps

T_SKEW

T_SKEW2

T_R/ T_F

CPU1 to CPU0 Clock Skew

CPU2_ITP to CPU0 Clock Skew

–

ps

CPUT and CPUC Rise and Fall Time Measured from V_OL= 0.175 to

_OH= 0.525V

175

ps

V

T_RFM

Rise/Fall Matching

Determined as a fraction of

2*(T_R– T_F)/(T_R+ T_F)

–

20

%

∆T_R

Rise Time Variation

Fall Time Variation

Voltage High

–

125

850

ps

∆T_F

V_HIGH

Math averages Figure 15

660

mV

Rev 1.2,July 3 , 2007

Page 15 of 21

SL28442-2

AC Electrical Specifications (continued)

Parameter

V_LOW

Description

Condition

Min.

–150

250

–

Max.

–

Unit

mV

V

Voltage Low

Math averages Figure 15

V_OX

Crossing Point Voltage at 0.7V Swing

Maximum Overshoot Voltage

550

V_OVS

V_HIGH

0.3

+

V_UDS

V_RB

Minimum Undershoot Voltage

Ring Back Voltage

–0.3

–

V

See Figure 15. Measure SE

0.2

SRC at 0.7V

T_DC

SRCT and SRCC Duty Cycle

Measured at crossing point V_OX

45

55

%

T_PERIOD

100-MHz SRCT and SRCC Period

9.997001 10.00300 ns

9.997001 10.05327 ns

T_PERIODSS

100-MHz SRCT and SRCC Period,

SSC

T_PERIODAbs

100-MHz SRCT and SRCC Absolute Measured at crossing point V_OX

Period

9.872001 10.12800 ns

9.872001 10.17827 ns

T_PERIODSSAbs

100-MHz SRCT and SRCC Absolute Measured at crossing point V_OX

Period, SSC

T_SKEW

T_CCJ

Any SRCT/C to SRCT/C Clock Skew Measured at crossing point V_OX

–

250

125

300

700

ps

SRCT/C Cycle to Cycle Jitter

SRCT/C Long Term Accuracy

Measured at crossing point V_OX

L_ACC

–

ppm

ps

T_R/ T_F

SRCT and SRCC Rise and Fall Time Measured from V_OL= 0.175 to

V_OH= 0.525V

175

T_RFM

Rise/Fall Matching

Determined as a fraction of

2*(T_R– T_F)/(T_R+ T_F)

–

20

%

∆T_R

Rise TimeVariation

–

125

850

–

ps

∆T_F

Fall Time Variation

V_HIGH

V_LOW

V_OX

Voltage High

Math averages Figure 15

660

–150

250

–

mV

V

Voltage Low

Crossing Point Voltage at 0.7V Swing

Maximum Overshoot Voltage

550

V_OVS

V_HIGH

0.3

+

V_UDS

V_RB

Minimum Undershoot Voltage

Ring Back Voltage

–0.3

–

V

See Figure 15. Measure SE

0.2

DOT at 0.7V

T_DC

DOT96T and DOT96C Duty Cycle

DOT96T and DOT96C Period

Measured at crossing point V_OX

45

55

%

T_PERIOD

T_PERIODAbs

T_CCJ

10.41354 10.41979 ns

10.16354 10.66979 ns

DOT96T and DOT96C Absolute Period Measured at crossing point V_OX

DOT96T/C Cycle to Cycle Jitter

DOT96T/C Long Term Accuracy

Measured at crossing point V_OX

–

250

100

700

ps

ppm

ps

L_ACC

T_R/ T_F

DOT96T and DOT96C Rise and Fall

Time

Measured from V_OL= 0.175 to

V_OH= 0.525V

175

T_RFM

Rise/Fall Matching

Determined as a fraction of

2*(T_R– T_F)/(T_R+ T_F)

–

20

%

∆T_R

Rise Time Variation

Fall Time Variation

Voltage High

–

125

850

–

ps

∆T_F

V_HIGH

V_LOW

V_OX

Math averages Figure 15

660

–150

250

mV

Voltage Low

Crossing Point Voltage at 0.7V Swing

550

Rev 1.2,July 3 , 2007

Page 16 of 21

SL28442-2

AC Electrical Specifications (continued)

Parameter

V_OVS

Description

Condition

Min.

Max.

Unit

Maximum Overshoot Voltage

–

V_HIGH

0.3

+

V

V_UDS

V_RB

Minimum Undershoot Voltage

Ring Back Voltage

–0.3

–

V

See Figure 15. Measure SE

0.2

96_100SSCG at 0.7V

T_DC

DOT96T and DOT96C Duty Cycle

Measured at crossing point V_OX

45

55

%

T_{PERIOD_100}

T_{PERIODSS_100}

100-MHz SSCG Period

9.997001 10.00300 ns

9.997001 10.05327 ns

9.872001 10.12800 ns

9.872001 10.17827 ns

100-MHz SSCG Period, -0.5% SSC

T_{PERIODAbs_100}100-MHz SSCG Absolute Period

T_{PERIODSSAbs-100}100-MHz SSCG Absolute Period,

-0.5% SSC

T_{PERIOD_96}

T_{PERIODAbs_96}

T_CCJ

96-MHz SSCG Period

Measured at crossing point V_OX

Measured from V_OL= 0.175 to

10.41354 10.41979 ns

10.16354 10.66979 ns

96-MHz SSCG Absolute Period

SSCG Cycle to Cycle Jitter

SSCG Long Term Accuracy

SSCG Rise and Fall Time

–

250

300

700

ps

ppm

ps

L_ACC

T_R/ T_F

175

V_OH= 0.525V

T_RFM

Rise/Fall Matching

Determined as a fraction of

2*(T_R– T_F)/(T_R+ T_F)

–

20

%

∆T_R

Rise Time Variation

–

125

850

–

ps

∆T_F

Fall Time Variation

V_HIGH

V_LOW

V_OX

Voltage High

Math averages Figure 15

660

–150

250

–

mV

V

Voltage Low

Crossing Point Voltage at 0.7V Swing

Maximum Overshoot Voltage

550

V_OVS

V_HIGH

0.3

+

V_UDS

V_RB

Minimum Undershoot Voltage

Ring Back Voltage

–0.3

–

V

See Figure 15. Measure SE

0.2

PCI/PCIF

T_DC

PCI Duty Cycle

Measurement at 1.5V

45

55

%

T_PERIOD

T_PERIODSS

T_PERIODAbs

T_PERIODSSAbs

T_HIGH

Spread Disabled PCIF/PCI Period

29.99100 30.00900 ns

29.9910 30.15980 ns

29.49100 30.50900 ns

29.49100 30.65980 ns

Spread Enabled PCIF/PCI Period, SSC Measurement at 1.5V

Spread Disabled PCIF/PCI Period Measurement at 1.5V

Spread Enabled PCIF/PCI Period, SSC Measurement at 1.5V

PCIF and PCI high time

PCIF and PCI low time

Measurement at 2.4V

Measurement at 0.4V

12.0

1.0

–

ns

T_LOW

–

T_R/ T_F

PCIF/PCI rising and falling Edge Rate Measured between 0.8V and 2.0V

Any PCI clock to Any PCI clock Skew Measurement at 1.5V

4.0

500

V/ns

ps

T_SKEW

T_CCJ

PCIF and PCI Cycle to Cycle Jitter

Measurement at 1.5V

–

ps

USB

T_DC

USB Duty Cycle

USB Period

Measurement at 1.5V

Measurement at 2.4V

Measurement at 0.4V

Measured between 0.8V and 2.0V

45

55

%

T_PERIOD

T_PERIODAbs

T_HIGH

20.83125 20.83542 ns

20.48125 21.18542 ns

USB Absolute Period

USB high time

8.094

7.694

1.0

10.036

9.836

2.0

ns

T_LOW

USB low time

T_R/ T_F

Rising and Falling Edge Rate

V/ns

Rev 1.2,July 3 , 2007

Page 17 of 21

SL28442-2

AC Electrical Specifications (continued)

Parameter

T_CCJ

Description

Cycle to Cycle Jitter

Condition

Min.

Max.

Unit

Measurement at 1.5V

–

350

ps

REF

T_DC

REF Duty Cycle

Measurement at 1.5V

45

55

%

T_PERIOD

T_PERIODAbs

T_R/ T_F

REF Period

Measurement at 1.5V

69.8203

69.8622

ns

REF Absolute Period

REF Rising and Falling Edge Rate

REF Cycle to Cycle Jitter

Measurement at 1.5V

68.82033 70.86224 ns

Measured between 0.8V and 2.0V

Measurement at 1.5V

1.0

–

4.0

V/ns

ps

T_CCJ

1000

ENABLE/DISABLE and SET-UP

T_STABLEClock Stabilization from Power-up

T_SS

–

10.0

0

1.8

–

ms

ns

Stopclock Set-up Time

Stopclock Hold Time

T_SH

–

Test and Measurement Set-up

For PCI Single-ended Signals and Reference

The following diagram shows the single-ended PCI outputs.

Output under Test

tDC

Probe

3.3V

2.4V

30

pF

Load

1.5V

Cap

0.4V

0V

Tr

Tf

Figure 14. Single-Ended PCI Lumped Load Configuration

The following diagram shows the test load configuration for the

differential CPU and SRC outputs.

M e a s u re m e n t

P o in t

2 p F

3 3 Ω

C P U T

S R C T

D O T 9 6 T

4 9 .9 Ω

9 6 _ 1 0 0 S S C T

1 0 0 Ω D iffe re n tia l

M e a s u re m e n t

P o in t

2 p F

C P U C

S R C C

D O T 9 6 C

3 3 Ω

4 9 .9 Ω

9 6 _ 1 0 0 S S C C

IR E F

4 7 5 Ω

Figure 15. 0.7V Differential Clock Load Configuration

Rev 1.2,July 3 , 2007

Page 18 of 21

SL28442-2

3 .3 V s ig n a ls

T _{D C}

-

3 .3 V

2 .4 V

1 .5 V

0 .4 V

0 V

T _R

T _F

Figure 16. Single-ended Output Signals (for AC Parameters Measurement)

While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any cir-

cuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in

normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other applica-

tion requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional

processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any

circuitry or specification without notice.

Rev 1.2, July 3 , 2007

Page 19 of 21

SL28442-2

Ordering Information

Part Number

Lead-free

Package Type

Product Flow

SL28442AZC-2

SL28442AZC-2T

56-pin TSSOP

56-pin TSSOP—Tape and Reel

Commercial, 0° to 85°C

Package Diagrams

56-Lead Thin Shrunk Small Outline Package, Type II (6 mm x 12 mm) Z56

0.249[0.009]

28

1

DIMENSIONS IN MM[INCHES] MIN.

MAX.

7.950[0.313]

8.255[0.325]

REFERENCE JEDEC MO-153

PACKAGE WEIGHT 0.42gms

5.994[0.236]

6.198[0.244]

PART #

Z5624 STANDARD PKG.

ZZ5624 LEAD FREE PKG.

29

56

13.894[0.547]

14.097[0.555]

1.100[0.043]

MAX.

GAUGE PLANE

0.25[0.010]

0.20[0.008]

0.508[0.020]

0.762[0.030]

0.051[0.002]

0.152[0.006]

0.851[0.033]

0.950[0.037]

0.500[0.020]

BSC

0°-8°

0.100[0.003]

0.200[0.008]

0.170[0.006]

0.279[0.011]

SEATING

PLANE

Rev 1.2,July 3 , 2007

Page 20 of 21

SL28442-2

Document History Page

Document Title: SL28442-2 Clock Generator for Intel^®Alviso Chipset

Document Number:

Orig. of

REV.

1.0

ECN NO. Issue Date Change

Description of Change

05/18/2007

06/05/2007

SLI

New data sheet

1.1

Updated AC Electrical Specification table

Modified Ordering Information

1.2

07/03/2007

SLI

Remove Preliminary

Updated AC Electrical Specification table

Update Package Diagrams

Rev 1.2,July 3 , 2007

Page 21 of 21


型号：	SL28442AZC-2T
厂家：	SILICON
描述：	Processor Specific Clock Generator, CMOS, PDSO56, 6 X 12 MM, LEAD FREE, MO-153, TSSOP-56 光电二极管外围集成电路
文件：	总21页 (文件大小：197K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SL28442AZC-2T [SILICON]

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