SL28540ALC_技术文档

SL28540

Low Power Clock Generator for Intel^®Mobile Platform

• 48 MHz USB clocks

Features

• 33 MHz PCI clocks

• Compliant to Intel^®CK540 UMPC clock spec

• Low power push-pull type differential output buffers

• Integrated voltage regulator

• Buffered Reference Clock 14.318 MHz

• Low-voltage frequency select input

• I²C support with readback capabilities

• Integrated series termination resistors on differential

clocks

• Ideal Lexmark Spread Spectrum profile for maximum

electromagnetic interference (EMI) reduction

• Scalable low voltage VDD_IO (3.3V to 1.05V)

• 8-step drive strength control for all single-ended clocks

• Differential CPU clocks with selectable frequency

• 100 MHz Differential SRC clocks

• 56-pin QFN (8x8) package

CPU

SRC

x7

PCI

x6

REF DOT96 USB_48 LCD

x 1 x 1 x 1 x1

x2 / x3

• 96 MHz Differential DOT clock

Block Diagram

Pin Configuration

VDD_REF

Xin

Xout

14.318MHz

Crystal

REF

PLL Reference

VDD_CPU_I/O

CPU_STP#

CPUT[1:0]

CPUC[1:0]

PCI_STP#

CLKREQ#

CPU

SRC

VDD_SRC_I/O

CPU PLL1

SS

FS[C:A]

CPUT2_ITP/SRC8T

CPUC2_ITP/SRC8C

ITP_EN

CKPWRGD/PD#

VDD_SRC_I/O

GCLK_SEL

PCI

SRCT [2,3,4,11,7]

SRCC [2,3,4,11,7]

VDD_PCI

PCI[4:0], PCIF0

VDD_SRC_I/O

PLL3

SS

LCD_100T/SRC1T

LCD_100C/SRC1C

LCD_100

DOT96

VDD_I/O

DOT96T

DOT96C

PLL2

Fixed

VDD_48

USB_48

I2C

Logic

SDATA

SCLK

* internal Pull-up

** internal Pull-down

..................................................... Document #: Page 1 of 25

400 West Cesar Chavez, Austin, TX 78701 1+(512) 416-8500 1+(512) 416-9669

www.silabs.com

SL28540

Pin Definitions

Pin No.

Name

Type

Description

1

2

3

Xout

Xin

O, SE 14.318 MHz Crystal output.

I

14.318 MHz Crystal input.

VDD_REF

PWR 3.3V Power supply for outputs and maintains SMBUS registers during power

down.

4

REF0 / FSC / TEST_SEL

I/O

Fixed 14.318 clock output/3.3V-tolerant input for CPU frequency selection/

Selects test mode if pulled to V_{IHFS_C}when CK_PWRGD is asserted HIGH.

Refer to DC Electrical Specifications table for V_{ILFS_C}, V_{IMFS_C}, V_{IHFS_C}specifica-

tions.

5

6

7

SDATA

I/O

I

SMBus compatible SDATA.

SMBus compatible SCLOCK.

SCLK

PCI0 / CR#_A

I/O, SE 33 MHz Clock/3.3V Clock Request # Input

Mappable via I2C to control either SRC 0 or SRC 2. Default PCI0.

To configure this pin to serve as a Clock Request pin for either SRC pair 2 or pair

0 using the CR#_A_EN bit located in byte 5 bit 7, first disable PCI output (Hi-z) in

byte 2, bit 1.

0 = PCI0 enabled (default)

1= CR#_A enabled.

Byte 5, bit 6 controls whether CR#_A controls SRC0 or SRC2 pair

Byte 5, bit 6:

0 = CR#_A controls SRC0 pair (default)

1= CR#_A controls SRC2 pair

8

9

VDD_PCI

PWR 3.3V power supply for PCI PLL

PCI1 / CR#_B

I/O, SE 33 MHz Clock/3.3V Clock Request # Input

Mappable via I2C to control either SRC 1 or SRC 4. Default PCI1.

To configure this pin to serve as a Clock Request pin for either SRC pair 1 or pair

4 using the CR#_B_EN bit located in byte 5, bit 5, first disable PCI output (Hi-z) in

byte 2, bit 1.

0 = PCI1 enabled (default)

1= CR#_B enabled.

Byte 5, bit 4 controls whether CR#_B controls SRC1 or SRC4 pair

Byte 5, bit 4:

0 = CR#_B controls SRC1 pair (default)

1= CR#_B controls SRC4 pair

10

11

PCI2

PCI3

O, SE 33 MHz Clock output/3.3V-tolerant input for enabling Trusted Mode

O, SE 33 MHz Clock output

11, 12 PCI 4/GCLK_SEL

I/O, SE 33 MHz Clock output/3.3V-tolerant input for selecting clock source on pin 23,

PD

24.

Sampled at CKPWRGD assertion:

0 = SRC1(default), 1 = LCD_100M

Internal weak pull-down to GND

13

PCIF0 / ITP_EN

I/O, SE 33 MHz free running clock output/3.3V LVTTL input to enable SRC8 or

CPU2_ITP (sampled on the CKPWRGD assertion)

1 = CPU2_ITP, 0 = SRC8

14

15

16

VSS_PCI

GND Ground for outputs.

VDD_48

PWR 3.3V power supply for outputs and PLL.

USB_48 / FSA

I/O

Fixed 48 MHz clock output/3.3V-tolerant input for CPU frequency selection

Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.

17

18

19

20

VSS_48

VDD_IO

DOT96T

DOT96C

GND Ground for outputs.

PWR 3.3V-1.05V power supply for outputs

O, DIF Fixed True 96 MHz clock output.

O, DIF Fixed complement 96 MHz clock output.

.....................................................Document #: Page 2 of 25

SL28540

Pin Definitions (continued)

Pin No.

21

Name

Type

Description

VSS_IO

GND Ground for outputs.

PWR 3.3V Power supply for PLL3.

22

VDD_PLL3

23

SRCT1 / LCDT_100

O, DIF True 100 MHz differential serial reference clock output/True 100 MHz LCD

video clock output

24

SRCC1 / LCDC_100

O, DIF Complementary 100 MHz differential serial reference clock output/Comple-

mentary 100 MHz LCD video clock output

25

26

27

28

29

30

VSS_PLL3

VDD_PLL3_IO

SRCT2

GND Ground for PLL3.

PWR 3.3V-1.05V power supply for outputs.

O, DIF True 100 MHz differential serial reference clock output.

O, DIF Complementary 100 MHz differential serial reference clock output.

GND Ground for outputs.

SRCC2

VSS_SRC

SRCT3 / CR#_C

I/O, True 100 MHz differential serial reference clock output /3.3V Clock Request

DIF #_C/D input

Selected via CR#_C_EN/CR#_D_EN bit located in byte 5 bit 3and 1.

The CR#_C_SEL and CR#_D_SEL bits in byte 5 bit 2 and 0 will select which SRC

to stop when asserted

31

SRCC3 / CR#_D

I/O, Complementary 100 MHz differential serial reference clock output/3.3V Clock

DIF Request #_C/D input

Selected via CR#_C_EN/CR#_D_EN bit located in byte 5 bit 3and 1.

The CR#_C_SEL and CR#_D_SEL bits in byte 5 bit 2 and 0 will select which SRC

to stop when asserted

32

33

34

35

36

37

VDD_SRC_IO

SRCT4

PWR 3.3V-1.05V Power supply for outputs.

O, DIF True 100 MHz differential serial reference clocks.

O, DIF Complementary 100 MHz differential serial reference clocks.

O, DIF True 100 MHz differential serial reference clocks.

O, DIF Complementary 100 MHz differential serial reference clocks.

SRCC4

SRCT11

SRCC11

CPU_STOP#

I

3.3V-tolerant input for stopping CPU outputs

During direct clock off to M1 mode transition, a serial load of BSEL data is driven

on CPU_STOP# and sampled on the rising edge of PCI_STOP#. See Figure 12

for more information.

38

PCI_STOP#

I

3.3V-tolerant input for stopping PCI and SRC outputs

During direct clock off to M1 mode transition, a serial load of BSEL data is driven

on CPU_STOP# and sampled on the rising edge of PCI_STOP#. See Figure 12

for more information.

39

40

41

VDD_SRC

PWR 3.3V power supply for SRC PLL.

GND Ground for outputs.

VSS_SRC

SRCC7/ CR#_E

I/O, Complementary 100 MHz differential serial reference clocks/3.3V CR#_E

DIF Input.

Selected via CR#_E_EN/CR#_F_EN bit located in byte 6 bit 7 and 6.

When selected, CR#_E controls SRC6, CR#_F controls SRC8

42

SRCT7/ CR#_F

I/O, True 100 MHz differential serial reference clocks/3.3V CR#_F Input.

DIF Selected via CR#_E_EN/CR#_F_EN bit located in byte 6 bit 7 and 6.

When selected, CR#_E controls SRC6, CR#_F controls SRC8

43

44

VDD_SRC_IO

PWR 3.3V-1.05V Power supply for outputs.

SRCC8 / CPUC2_ITP

O, DIF Selectable complementary differential CPU or SRC clock output.

ITP_EN = 0 @ CK_PWRGD assertion = SRC8

ITP_EN = 1 @ CK_PWRGD assertion = CPU2

45

46

SRCT8 / CPUT2_ITP,

NC

O, DIF Selectable True differential CPU or SRC clock output.

ITP_EN = 0 @ CK_PWRGD assertion = SRC8

ITP_EN = 1 @ CK_PWRGD assertion = CPU2

NC

No connect.

.....................................................Document #: Page 3 of 25

SL28540

Pin Definitions (continued)

Pin No.

47

Name

VDD_CPU_IO

Type

Description

PWR 3.3V-1.05V Power supply for outputs.

48

CPUC1

O, DIF Complementary differential CPU clock outputs.

Note that CPU1 is the iAMT clock and is on in that mode.

49

CPUT1

O, DIF True differential CPU clock outputs.

Note that CPU1 is the iAMT clock and is on in that mode.

50

51

52

53

54

VSS_CPU

GND Ground for outputs.

CPUC0

O, DIF Complement differential CPU clock outputs.

O, DIF True differential CPU clock outputs.

PWR 3.3V Power supply for CPU PLL.

CPUT0

VDD_CPU

CKPWRGD / PWRDWN#

I

3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A,

FS_B, FS_C, GLCK_SEL and ITP_EN.

After CKPWRGD (active HIGH) assertion, this pin becomes a real-time input for

asserting power down (active LOW).

55

56

FSB / TEST_MODE

VSS_REF

I

3.3V-tolerant input for CPU frequency selection / Selects Ref/N or Tri-state

when in test mode.

0 = Tri-state, 1 = Ref/N

Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.

GND Ground for outputs.

Table 1. Frequency Select Pin (FSA, FSB and FSC)

FSC

FSB

FSA

CPU

SRC

PCIF/PCI

33 MHz

REF

DOT96

96 MHz

USB

1

0

1

0

100 MHz

133 MHz

166 MHz

200 MHz

100 MHz

14.318 MHz

48 MHz

Apply the appropriate logic levels to FSA, FSB, and FSC

inputs before CK-PWRGD assertion to achieve host clock

frequency selection. When the clock chip sampled HIGH on

CK-PWRGD and indicates that VTT voltage is stable then

FSA, FSB, and FSC input values are sampled. This process

employs a one-shot functionality and once the CK-PWRGD

sampled a valid HIGH, all other FSA, FSB, FSC, and

CK-PWRGD transitions are ignored except in test mode

system initialization, if any are required. The interface cannot

be used during system operation for power management

functions.

Data Protocol

The clock driver serial protocol accepts byte write, byte read,

block write, and block read operations from the controller. For

block write/read operation, Access the bytes in sequential

order from lowest to highest (most significant bit first) with the

ability to stop after any complete byte is transferred. For byte

write and byte read operations, the system controller can

access individually indexed bytes. The offset of the indexed

byte is encoded in the command code described in Table 2.

Serial Data Interface

To enhance the flexibility and function of the clock synthesizer,

a two-signal serial interface is provided. Through the Serial

Data Interface, various device functions, such as individual

clock output buffers are individually enabled or disabled. The

registers associated with the Serial Data Interface initialize to

their default setting at power-up. The use of this interface is

The block write and block read protocol is outlined in Table 3

while Table 4 outlines byte write and byte read protocol. The

slave receiver address is 11010010 (D2h)

optional. Clock device register changes are normally made at

.

Table 2. Command Code Definition

Bit

Description

7

0 = Block read or block write operation, 1 = Byte read or byte write operation

(6:0) Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'

.....................................................Document #: Page 4 of 25

SL28540

Table 3. Block Read and Block Write Protocol

Block Write Protocol

Block Read Protocol

Description

Bit

1

Description

Bit

1

Start

8:2

9

Slave address–7 bits

Write

8:2

9

Slave address–7 bits

Write

10

Acknowledge from slave

Command Code–8 bits

Acknowledge from slave

Byte Count–8 bits

10

Acknowledge from slave

Command Code–8 bits

Acknowledge from slave

Repeat start

18:11

19

18:11

19

27:20

28

20

Acknowledge from slave

Data byte 1–8 bits

27:21

28

Slave address–7 bits

Read = 1

36:29

37

Acknowledge from slave

Data byte 2–8 bits

29

Acknowledge from slave

Byte Count from slave–8 bits

Acknowledge

45:38

46

37:30

38

Acknowledge from slave

Data Byte /Slave Acknowledges

Data Byte N–8 bits

Acknowledge from slave

Stop

....

46:39

47

Data byte 1 from slave–8 bits

Acknowledge

....

55:48

56

Data byte 2 from slave–8 bits

Acknowledge

....

Data bytes from slave / Acknowledge

Data Byte N from slave–8 bits

NOT Acknowledge

....

Stop

Table 4. Byte Read and Byte Write Protocol

Byte Write Protocol

Byte Read Protocol

Description

Bit

1

Description

Bit

1

Start

8:2

9

Slave address–7 bits

Write

8:2

9

Slave address–7 bits

Write

10

Acknowledge from slave

Command Code–8 bits

Acknowledge from slave

Data byte–8 bits

10

Acknowledge from slave

Command Code–8 bits

Acknowledge from slave

Repeated start

18:11

19

18:11

19

27:20

28

20

Acknowledge from slave

Stop

27:21

28

Slave address–7 bits

Read

29

Acknowledge from slave

Data from slave–8 bits

NOT Acknowledge

Stop

37:30

38

39

.....................................................Document #: Page 5 of 25

SL28540

Control Registers

Byte 0: Control Register 0

Bit

7

@Pup

HW

0

Name

FS_C

Description

CPU Frequency Select Bit, set by HW

6

FS_B

CPU Frequency Select Bit, set by HW

5

FS_A

4

iAMT_EN

Set via SMBus or by combination of PWRDWN, CPU_STP, and PCI_STP

0 = Legacy Mode, 1 = iAMT Enabled

3

2

1

0

1

Reserved

PD_Restore

Save Config. In powerdown

0 = Config. Cleared, 1 = Config. Saved

Byte 1: Control Register 1

Bit

7

@Pup

Name

Description

0

Reserved

6

PLL1_SS_DC

Select for down or center SS

0 = Down spread, 1 = Center spread

5

0

PLL3_SS_DC

Select for down or center SS

0 = Down spread, 1 = Center spread

4

3

2

1

0

1

PLL3_CFB3

PLL3_CFB2

PLL3_CFB1

PLL3_CFB0

Reserved

SeeTable 8: PLL3 / SE configuration table

Reserved

Byte 2: Control Register 2

Bit

@Pup

Name

Description

7

1

REF_OE

Output enable for REF

0 = Output Disabled, 1 = Output Enabled

6

5

4

3

2

1

0

1

USB_OE

PCIF0_OE

PCI4_OE

PCI3_OE

PCI2_OE

PCI1_OE

PCI0_OE

Output enable for USB

0 = Output Disabled, 1 = Output Enabled

Output enable for PCIF0

0 = Output Disabled, 1 = Output Enabled

Output enable for PCI4

0 = Output Disabled, 1 = Output Enabled

Output enable for PCI3

0 = Output Disabled, 1 = Output Enabled

Output enable for PCI2

0 = Output Disabled, 1 = Output Enabled

Output enable for PCI1

0 = Output Disabled, 1 = Output Enabled

Output enable for PCI0

0 = Output Disabled, 1 = Output Enabled

Byte 3: Control Register 3

Bit @Pup

Name

Description

.....................................................Document #: Page 6 of 25

SL28540

Byte 3: Control Register 3

7

1

SRC[T/C]11_OE

Output enable for SRC11

0 = Output Disabled, 1 = Output Enabled

6

5

4

1

Reserved

SRC[T/C]8/CPU2_ITP_OE Output enable for SRC8 or CPU2_ITP

0 = Output Disabled, 1 = Output Enabled

3

1

SRC[T/C]7_OE

Output enable for SRC7

0 = Output Disabled, 1 = Output Enabled

2

1

0

1

Reserved

SRC[T/C]4_OE

Output enable for SRC4

0 = Output Disabled, 1 = Output Enabled

Byte 4: Control Register 4

Bit

@Pup

Name

Description

7

1

SRC[T/C]3_OE

Output enable for SRC3

0 = Output Disabled, 1 = Output Enabled

6

5

4

3

2

1

0

1

SRC[T/C]2_OE

Output enable for SRC2

0 = Output Disabled, 1 = Output Enabled

SRC[T/C]1/LCD_100M[T/C] Output enable for SRC1/LCD_100M

_OE

0 = Output Disabled, 1 = Output Enabled

DOT96[T/C]_OE

Output enable for DOT96

0 = Output Disabled, 1 = Output Enabled

CPU[T/C]1_OE

CPU[T/C]0_OE

PLL1_SS_EN

PLL3_SS_EN

Output enable for CPU1

0 = Output Disabled, 1 = Output Enabled

Output enable for CPU0

0 = Output Disabled, 1 = Output Enabled

Enable PLL1’s spread modulation,

0 = Spread Disabled, 1 = Spread Enabled

Enable PLL3’s spread modulation

0 = Spread Disabled, 1 = Spread Enabled

Byte 5: Control Register 5

Bit

@Pup

Name

Description

7

0

CR#_A_EN

Enable CR#_A (clk req)

0 = Disabled, 1 = Enabled,

6

5

4

3

2

1

0

CR#_A_SEL

CR#_B_EN

CR#_B_SEL

CR#_C_EN

CR#_C_SEL

CR#_D_EN

CR#_D_SEL

Set CR#_A  SRC0 or SRC2

0 = CR#_ASRC0, 1 = CR#_ASRC2

Enable CR#_B(clk req)

0 = Disabled, 1 = Enabled,

Set CR#_B  SRC1 or SRC4

0 = CR#_BSRC1, 1 = CR#_BSRC4

Enable CR#_C (clk req)

0 = Disabled, 1 = Enabled

Set CR#_C  SRC0 or SRC2

0 = CR#_CSRC0, 1 = CR#_CSRC2

Enable CR#_D (clk req)

0 = Disabled, 1 = Enabled

Set CR#_D SRC1 or SRC4

0 = CR#_DSRC1, 1 = CR#_DSRC4

.....................................................Document #: Page 7 of 25

SL28540

Byte 6: Control Register 6

Bit

@Pup

Name

Description

7

0

CR#_E_EN

Enable CR#_E (clk req)  SRC6

0 = Disabled, 1 = Enabled

6

0

CR#_F_EN

Enable CR#_F (clk req)  SRC8

0 = Disabled, 1 = Enabled

5

4

3

2

1

0

Reserved

LCD_100_STP_CTRL

If set, LCD_100 stop with PCI_STOP#

0 = Free running, 1 = PCI_STOP# stoppable

0

SRC_STP_CTRL

If set, SRCs stop with PCI_STOP#

0 = Free running, 1 = PCI_STOP# stoppable

Byte 7: Vendor ID

Bit

7

@Pup

Name

Description

Revision Code Bit 3

Revision Code Bit 2

Revision Code Bit 1

Revision Code Bit 0

Vendor ID Bit 3

0

1

0

Rev Code Bit 3

Rev Code Bit 2

Rev Code Bit 1

Rev Code Bit 0

Vendor ID bit 3

Vendor ID bit 2

Vendor ID bit 1

Vendor ID bit 0

6

5

4

3

2

Vendor ID Bit 2

1

Vendor ID Bit 1

0

Vendor ID Bit 0

Byte 8: Control Register 8

Bit

7

@Pup

Name

Description

1

0

1

0

Device_ID3

Device_ID2

Device_ID1

Device_ID0

0000 = CK505 Yellow Cover Device, 56-pin TSSOP

0001 = CK505 Yellow Cover Device, 64-pin TSSOP

6

0010 = CK505 Yellow Cover Device, 48-pin QFN (Reserved)

0011 = CK505 Yellow Cover Device, 56-pin QFN (Reserved)

0100 = CK505 Yellow Cover Device, 64-pin QFN

0101 = CK505 Yellow Cover Device, 72-pin QFN (Reserved)

0110 = CK505 Yellow Cover Device, 48-pin SSOP (Reserved)

0111 = CK505 Yellow Cover Device, 56-pin SSOP (Reserved)

1000 = Reserved

5

4

1001 = Reserevd

1010 = CK505 Mobile

1011 = Reserved

1100 = Reserved

1101 = Reserved

1110 = Reserved

1111 = Reserved

3

2

1

0

Reserved

Byte 9: Control Register 9

Bit @Pup

Name

Description

.....................................................Document #: Page 8 of 25

SL28540

Byte 9: Control Register 9

7

6

5

0

HW

1

PCIF_0_with PCI_STOP# Allows control of PCIF_0 with assertion of PCI_STOP#

0 = Free running PCIF, 1 = Stopped with PCI_STOP#

TME_STRAP

Trusted mode enable strap status

0 = Normal, 1 = No overclocking

REF drive strength

REF drive strength bit 1 (DSC 1)

0 = Low, 1 = High

See byte 13 for full-range setting

4

3

0

TEST_MODE_SEL

Mode select either REF/N or tri-state

0 = All output tri-state, 1 = All output REF/N

TEST_MODE_ENTRY

Allow entry into test mode

0 = Normal operation, 1 = Enter test mode

2

1

0

1

0

1

12C_VOUT<2>

12C_VOUT<1>

12C_VOUT<0>

I2C_VOUT[2,1,0]

000 = 0.3V

001 = 0.4V

010 = 0.5V

011 = 0.6V

100 = 0.7V

101 = 0.8V (default)

110 = 0.9V

111 = 1.0V

Byte 10: Control Register 10

Bit

@Pup

Name

Description

7

HW

GCLK_SEL latch

Readback of GCLK_SEL latch

0 = SRC1, 1 = LCD_100M

6

0

PLL3_EN

PLL3 power down

0 = Power down, 1 = Power up

When GCLK_SEL=0, this bit is 0. When GCLK_SEL=1, this bit is 1.

5

4

3

2

1

0

1

PLL2_EN

SRC_DIV_EN

PLL2 power down

0 = Power down, 1 = Power up

SRC divider disable

0 = Disabled, 1 = Enabled

PCI_DIV_EN

PCI divider disable

0 = Disabled, 1 = Enabled

CPU_DIV_EN

CPU divider disable

0 = Disabled, 1 = Enabled

CPU1 Stop Enable

CPU0 Stop Enable

Enable CPU_STOP# control of CPU1

0 = Free running, 1= Stoppable

Enable CPU_STOP# control of CPU0

0 = Free running, 1= Stoppable

Byte 11: Control Register 11

Bit

7

@Pup

Name

Description

0

Reserved

6

5

4

3

2

1

.....................................................Document #: Page 9 of 25

SL28540

Byte 11: Control Register 11 (continued)

0

1

CPU[T/C]2

Allow control of CPU2 with assertion of CPU_STOP#

0 = Free running, 1 = Stopped with CPU_STOP#

Byte 12: Byte Count

Bit

7

@Pup

Name

Reserved

BC5

Description

0

1

0

1

Reserved

Byte count

6

5

4

BC4

3

BC3

2

BC2

1

BC1

0

BC0

Byte 13: Control Register 13

Bit

@Pup

Name

Description

7

0

PCI/PCIF drive strength Drive Strength Control table (DSC[2:0])

control bit 2

6

5

4

3

2

1

0

1

0

1

0

PCI/PCIF drive strength

control bit 1

DSC_2

DSC_1

DSC_0

Buffer

Strength

Strongest

PCI/PCIF drive strength

control bit 0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

USB drive strength control

bit 2

USB drive strength control

bit 1

Default PCI

Default REF/USB

USB drive strength control

bit 0

Weakest

REF drive strength control

bit 2

REF drive strength control

bit 0

Byte 14: Control Register 14

Bit

7

@Pup

Name

Description

0

Reserevd

Reserved

6

5

PLL1 spread percentage Select percentage of spread for PLL1

0 = 0.5%, 1=1%

4

3

2

1

0

Reserevd

Reserved

...................................................Document #: Page 10 of 25

SL28540

Byte 14: Control Register 14

Bit

@Pup

Name

Description

0

1

SW_PCI

SW PCI_STP# Function

0 = SW PCI_STP assert, 1 = SW PCI_STP deassert

When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs are

stopped in a synchronous manner with no short pulses.

When this bit is set to 1, all STOPPED PCI, PCIF and SRC outputs are

resumed in a synchronous manner with no short pulses.

Table 5. Crystal Recommendations

Frequency

Drive

(max.)

Shunt Cap Motional

Tolerance

(max.)

Stability

(max.)

Aging

(max.)

(Fund)

Cut

Loading Load Cap

(max.)

14.31818 MHz

AT

Parallel 20 pF

0.1 mW

5 pF

0.016 pF

35 ppm

30 ppm

5 ppm

The SL28540 requires a Parallel Resonance Crystal. Substi-

tuting a series resonance crystal causes the SL28540 to

operate at the wrong frequency and violates the ppm specifi-

cation. For most applications there is a 300-ppm frequency

shift between series and parallel crystals due to incorrect

loading

C lo ck C h ip

C i2

C i1

P in

3 to 6 p

Crystal Loading

Crystal loading plays a critical role in achieving low ppm perfor-

mance. To realize low ppm performance, use the total capac-

itance the crystal sees to calculate the appropriate capacitive

loading (CL).

X 2

X 1

C s2

C s1

T ra ce

2 .8 p F

X T A L

Figure 1 shows a typical crystal configuration using the two

trim capacitors. It is important that the trim capacitors are in

series with the crystal. It is not true that load capacitors are in

parallel with the crystal and are approximately equal to the

load capacitance of the crystal.

C e 1

C e 2

T rim

3 3 p F

Figure 2. Crystal Loading Example

,

Use the following formulas to calculate the trim capacitor

values for Ce1 and Ce2.

Load Capacitance (each side)

Ce = 2 * CL – (Cs + Ci)

Total Capacitance (as seen by the crystal)

1

CLe

=

1

(

)

+

Ce2 + Cs2 + Ci2

Ce1 + Cs1 + Ci1

Figure 1. Crystal Capacitive Clarification

CL....................................................Crystal load capacitance

CLe......................................... Actual loading seen by crystal

using standard value trim capacitors

Calculating Load Capacitors

In addition to the standard external trim capacitors, consider

the trace capacitance and pin capacitance to calculate the

crystal loading correctly. Again, the capacitance on each side

is in series with the crystal. The total capacitance on both side

is twice the specified crystal load capacitance (CL). Trim

capacitors are calculated to provide equal capacitive loading

on both sides.

Ce..................................................... External trim capacitors

Cs..............................................Stray capacitance (terraced)

Ci ...........................................................Internal capacitance

(lead frame, bond wires, etc.)

................................................... Document #: Page 11 of 25

SL28540

PD_RESTORE

PWRDWN# (Power down) Assertion

If a ‘0’ is set for Byte 0 bit 0 then, upon assertion of PWRDWN#

LOW, the SL28540 initiates a full reset. The result of this is that

the clock chip emulates a cold power on start and goes to the

“Latches Open” state. If the PD_RESTORE bit is set to a ‘1’

then the configuration is stored upon PWRDWN# asserted

LOW. Note that if the iAMT bit, Byte 0 bit 3, is set to a ‘1’ then

the PD_RESTORE bit must be ignored. In other words, in Intel

iAMT mode, PWRDWN# reset is not allowed.

When PD is sampled HIGH by two consecutive rising edges

of CPUC, all single-ended outputs will be held LOW on their

next HIGH-to-LOW transition and differential clocks must held

LOW. When PD mode is desired as the initial power on state,

PD must be asserted HIGH in less than 10 s after asserting

CKPWRGD.

PWRDWN# Deassertion

The power up latency is less than 1.8 ms. This is the time from

the deassertion of the PD# pin or the ramping of the power

supply until the time that stable clocks are generated from the

clock chip. All differential outputs stopped in a three-state

condition, resulting from power down are driven high in less

than 300 s of PD# deassertion to a voltage greater than

200 mV. After the clock chip’s internal PLL is powered up and

locked, all outputs are enabled within a few clock cycles of

each clock. Figure 4 is an example showing the relationship of

clocks coming up.

PWRDWN# (Power down) Clarification

The CKPWRGD/PWRDWN# pin is a dual-function pin. During

initial power up, the pin functions as CKPWRGD. Once

CKPWRGD has been sampled HIGH by the clock chip, the pin

assumes PD# functionality. The PD# pin is an asynchronous

active LOW input used to shut off all clocks cleanly before

shutting off power to the device. This signal is synchronized

internally to the device before powering down the clock

synthesizer. PD# is also an asynchronous input for powering

up the system. When PD# is asserted LOW, clocks are driven

to a LOW value and held before turning off the VCOs and the

crystal oscillator.

PD#

CPUT, 133MHz

CPUC, 133MHz

SRCT 100MHz

SRCC 100MHz

USB, 48MHz

DOT96T

DOT96C

PCI, 33 MHz

REF

Figure 3. Power down Assertion Timing Waveform

Ts table

<1.8 ms

PD#

CP UT , 133MHz

CP UC, 133MHz

S RCT 100MHz

S RCC 100MHz

US B , 48MHz

DOT 96T

DOT 96C

P CI, 33MHz

REF

Tdriv e_PW R D N #

<300 s , >200m V

Figure 4. Power down Deassertion Timing Waveform

...................................................Document #: Page 12 of 25

SL28540

Figure 5. CKPWRGD Timing Diagram

...................................................Document #: Page 13 of 25

SL28540

CPU_STP# Assertion

CPU_STP# Deassertion

The CPU_STP# signal is an active LOW input used for

synchronous stopping and starting the CPU output clocks

while the rest of the clock generator continues to function.

When the CPU_STP# pin is asserted, all CPU outputs that are

set with the SMBus configuration to be stoppable are stopped

within two to six CPU clock periods after sampled by two rising

edges of the internal CPUC clock. The final states of the

stopped CPU signals are CPUT = HIGH and CPUC = LOW.

The deassertion of the CPU_STP# signal causes all stopped

CPU outputs to resume normal operation in a synchronous

manner. No short or stretched clock pulses are produced when

the clock resumes. The maximum latency from the

deassertion to active outputs is no more than two CPU clock

cycles.

CPU_STP#

CPUT

CPUC

Figure 6. CPU_STP# Assertion Waveform

CPU_STP#

CPUT

CPUC

CPUT Internal

CPUC Internal

Tdrive_CPU_STP#,10 ns>200 mV

Figure 7. CPU_STP# Deassertion Waveform

1.8 ms

CPU_STOP#

PD#

CPUT(Free Running

CPUC(Free Running

CPUT(Stoppable)

CPUC(Stoppable)

DOT96T

DOT96C

Figure 8. CPU_STP# = Driven, CPU_PD = Driven, DOT_PD = Driven

...................................................Document #: Page 14 of 25

SL28540

.

PCI_STP# Assertion

The PCI_STP# signal is an active LOW input used for

synchronously stopping and starting the PCI outputs while the

rest of the clock generator continues to function. The set-up

time for capturing PCI_STP# going LOW is 10 ns (t_SU). (See

Figure 9.) The PCIF clocks are affected by this pin if their

corresponding control bit in the SMBus register is set to allow

them to be free running.

Tsu

PCI_STP#

PCI_F

PCI

SRC 100MHz

Figure 9. PCI_STP# Assertion Waveform

PCI_STP# Deassertion

.

The deassertion of the PCI_STP# signal causes all PCI and

stoppable PCIF clocks to resume running in a synchronous

manner within two PCI clock periods, after PCI_STP# transi-

tions to a HIGH level.

Tdrive_SRC

Tsu

PCI_STP#

PCI_F

PCI

SRC 100MHz

Figure 10. PCI_STP# Deassertion Waveform

.

Table 6. Output Driver Status during PCI-STOP# and CPU-STOP#

PCI_STOP# Asserted

CPU_STOP# Asserted

Running

SMBus OE Disabled

Single-ended Clocks Stoppable

Non stoppable

Stoppable

Driven low

Running

Differential Clocks

Clock driven high

Clock# driven low

Running

Clock driven high

Clock# driven low

Running

Clock driven Low or 20K

pulldown

Non stoppable

Table 7. Output Driver Status

All Single-ended Clocks

w/o Strap w/ Strap

Low Hi-Z

All Differential Clocks except CPU1

CPU1

Clock

Clock#

Clock

Clock#

Low

Latches Open State

Powerdown

Low or 20K pulldown Low

Low or 20K

pulldown

Low

Hi-Z

Low or 20K pulldown Low

Low or 20K

pulldown

Low

...................................................Document #: Page 15 of 25

SL28540

.

Table 8. PLL3/SE Configuration Table

GCLK_SEL

B1b4

B1b3

B1b2

B1b1

Pin 23 (MHz)

Pin 24 (MHz) Spread (%)

Comment

0

1

0

1

0

1

0

1

0

1

0

1

PLL3 Disabled

100

0.5

1

SRC1 from SRC_Main

LCD_100 from PLL3

1.5

2

Figure 11. Clock Generator Power up/Run State Diagram

...................................................Document #: Page 16 of 25

SL28540

Absolute Maximum Conditions

Parameter

V_DD

Description

Core Supply Voltage

Analog Supply Voltage

IO Supply Voltage

Input Voltage

Condition

Min.

Max.

4.6

3.8

4.6

150

85

Unit

V

V_{DD_A}

V_{DD_IO}

V_IN

V

Relative to V_SS

Non-functional

Functional

–0.5

–65

0

V

T_S

Temperature, Storage

°C

T_A

Temperature, Operating

Ambient

T_J

Temperature, Junction

Functional

–

150

20

60

–

°C

°C/W

V

Ø_JC

Dissipation, Junction to Case Mil-STD-883E Method 1012.1

Dissipation, Junction to Ambient JEDEC (JESD 51)

Ø_JA

–

ESD_HBM

ESD Protection (Human Body MIL-STD-883, Method 3015

Model)

2000

UL-94

MSL

Flammability Rating

At 1/8 in.

V–0

1

Moisture Sensitivity Level

Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.

DC Electrical Specifications

Parameter

VDD core

Description

3.3V Operating Voltage

1.05V Operating Voltage

3.3V Input High Voltage (SE)

3.3V Input Low Voltage (SE)

Input High Voltage

Condition

Min.

3.135

0.9975

2.0

Max.

Unit

V

3.3 ± 5%

3.465

VDD IO

3.3 ± 5%,

1.05V± 5%

3.465

V

1.1025

V

V_IH

V_DD+ 0.3

V

V_IL

V_SS– 0.3

2.2

0.8

V

V_IHI2C

V_ILI2C

V_{IH_FS}

V_{IL_FS}

V_{IHFS_C_TEST}

SDATA, SCLK

–

V

Input Low Voltage

–

1.0

V

FS_[A,B] Input High Voltage

FS_[A,B] Input Low Voltage

FS_C Input High Voltage

0.7

V_DD+ 0.3

V

V_SS– 0.3

2.0

0.35

V

V_DD+ 0.3

V

V_{IMFS_C_NORMAL}FS_C Input Middle Voltage

V_{ILFS_C_NORMAL}FS_C Input Low Voltage

0.7

1.5

0.35

5

V

V_SS– 0.3

–

V

I_IH

Input High Leakage Current

Input Low Leakage Current

3.3V Output High Voltage (SE)

3.3V Output Low Voltage (SE)

High-impedance Output Current

Input Pin Capacitance

Except internal pull-down resistors, 0 < V_IN< V_DD

Except internal pull-up resistors, 0 < V_IN< V_DD

I_OH= –1 mA

A

V

I_IL

–5

–

V_OH

2.4

–

V_OL

I_OL= 1 mA

–

0.4

10

V

I_OZ

–10

A

pF

nH

V

C_IN

1.5

5

C_OUT

L_IN

Output Pin Capacitance

Pin Inductance

6

–

7

V_XIH

V_XIL

Xin High Voltage

0.7V_DD

V_DD

0.3V_DD

100¹

40

Xin Low Voltage

0

–

V

I_DD3.3V

I_{DD_IO}

I_{DD_PWRDWN}

Dynamic Supply Current

Dynamic IO Supply Current

Power down supply current

mA

1

1. All clock outputs are driving test case lump loads

...................................................Document #: Page 17 of 25

SL28540

AC Electrical Specifications

Parameter

Crystal

T_DC

Description

Condition

Min.

Max.

Unit

XIN Duty Cycle

XIN Period

The device operates reliably with input

dutycyclesupto30/70buttheREFclock

duty cycle will not be within specification

47.5

52.5

%

T_PERIOD

When XIN is driven from an external

clock source

69.841

71.0

ns

T_R/T_F

XIN Rise and Fall Times

XIN Cycle to Cycle Jitter

Measured between 0.3V_DDand 0.7V_DD

–

10.0

500

ns

ps

T_CCJ

As an average over 1-s duration

CPU at 0.8V

T_DC

CPUT and CPUC Duty Cycle

Measured at 0V differential at 0.1s

45

55

%

ns

T_PERIOD

T_PERIODSS

T_PERIODAbs

100 MHz CPUT and CPUC Period

133 MHz CPUT and CPUC Period

166 MHz CPUT and CPUC Period

200 MHz CPUT and CPUC Period

9.99900

7.49925

5.99940

4.99950

10.0010

7.50075

6.00060

5.00050

100 MHz CPUT and CPUC Period, SSC Measured at 0V differential at 0.1s

133 MHz CPUT and CPUC Period, SSC Measured at 0V differential at 0.1s

166 MHz CPUT and CPUC Period, SSC Measured at 0V differential at 0.1s

200 MHz CPUT and CPUC Period, SSC Measured at 0V differential at 0.1s

10.02406 10.0261

7.51805

6.01444

5.01203

9.91400

7.51955

6.01564

5.01303

10.0860

100 MHz CPUT and CPUC Absolute

period

Measured at 0V differential at 1 clock

Measured at 0V differential @ 1 clock

T_PERIODAbs

133 MHz CPUT and CPUC Absolute

period

7.41425

5.91440

4.91450

9.93906

7.43305

5.92944

4.92703

7.58575

6.08560

5.08550

10.1362

7.62340

6.11572

5.11060

ns

166 MHz CPUT and CPUC Absolute

period

200 MHz CPUT and CPUC Absolute

period

T_PERIODSSAbs100 MHz CPUT and CPUC Absolute

period, SSC

T_PERIODSSAbs133 MHz CPUT and CPUC Absolute

period, SSC

T_PERIODSSAbs166 MHz CPUT and CPUC Absolute

period, SSC

T_PERIODSSAbs200 MHz CPUT and CPUC Absolute

period, SSC

T_CCJ

CPUT/C Cycle to Cycle Jitter

CPU2_ITP Cycle to Cycle Jitter

Long-term Accuracy

Measured at 0V differential

–

85

125

100

150

8

ps

T_CCJ2

L_ACC

Measured at 0V differential

–

ppm

ps

T_SKEW

T_SKEW2

T_R/T_F

T_RFM

CPU1 to CPU0 Clock Skew

CPU2_ITP to CPU0 Clock Skew

CPU Rising and Falling slew rate

Rise/Fall Matching

Measured at 0V differential

–

Measured at 0V differential

–

ps

Measured differentially from ±150 mV

Measured single-endedly from ±75 mV

2.5

–

V/ns

%

20

V_HIGH

V_LOW

Voltage High

1.15

–

V

Voltage Low

–0.3

300

V

V_OX

Crossing Point Voltage at 0.7V Swing

550

mV

SRC at 0.8V

T_DC

SRCT and SRCC Duty Cycle

100 MHz SRC Period

Measured at 0V differential

45

55

%

T_PERIOD

Measured at 0V differential @ 0.1s

9.99900

10.0010

ns

...................................................Document #: Page 18 of 25

SL28540

AC Electrical Specifications (continued)

Parameter

Description

Condition

Min.

Max.

Unit

T_PERIODSS

100 MHz SRC Period with Spread

enabled

Measured at 0V differential @ 0.1s

10.02406 10.0261

ns

T_PERIODAbs

100 MHz SRC Absolute Period

Measured at 0V differential @ 1 clock

9.8740

10.1260

10.1762

ns

T_PERIODSSAbs100 MHz SRC Absolute Period with

Spread enbled

9.89906

T_CCJ

SRC Cycle to Cycle Jitter

SRC Long Term Accuracy

SRC Rising and Falling slew rate

Rise/Fall Matching

Measured at 0V differential

–

125

100

8

ps

ppm

V/ns

%

L_ACC

Measured at 0V differential

T_R/ T_F

T_RFM

Measured differentially from ±150 mV

Measured single-endedly from ±75 mV

2.5

–

20

V_HIGH

V_LOW

Voltage High

1.15

–

V

Voltage Low

–0.3

300

V

V_OX

Crossing Point Voltage at 0.7V Swing

550

mV

DOT96 at 0.8V

T_DC

DOT96T and DOT96C Duty Cycle

DOT96T and DOT96C Period

Measured at 0V differential

45

55

10.4177

10.6677

250

%

ns

T_PERIOD

T_PERIODAbs

T_CCJ

Measured at 0V differential at 0.1s

10.4156

DOT96T and DOT96C Absolute Period Measured at 0V differential at 0.1s

10.1656

ns

DOT96 Cycle to Cycle Jitter

DOT96 Long Term Accuracy

DOT96 Rising and Falling slew rate

Rise/Fall Matching

Measured at 0V differential at 1 clock

Measured differentially from ±150 mV

Measured single-endedly from ±75 mV

–

ps

L_ACC

100

ppm

V/ns

%

T_R/ T_F

T_RFM

2.5

–

8

20

V_HIGH

V_LOW

Voltage High

1.15

–

V

Voltage Low

–0.3

300

V

V_OX

Crossing Point Voltage at 0.7V Swing

550

mV

LCD_100_SSC at 0.8V

T_DC

LCD_100 Duty Cycle

Measured at 0V differential

45

55

%

ns

T_PERIOD

T_PERIODSS

T_PERIODAbs

LCD_100 Period

Measured at 0V differential at 0.1s

Measured at 0V differential at 1 clock

Measured at 0V differential @ 1 clock

Measured at 0V differential

9.99900

10.0010

LCD_100 Period with -0.5% Spread

LCD_100 Absolute Period

10.02406 10.0261

ns

9.874

10.0860

10.1762

250

100

8

ns

T_PERIODSSAbsLCD_100 Absolute Period, SSC

9.89906

ns

T_CCJ

LCD_100 Cycle to Cycle Jitter

LCD_100 Long Term Accuracy

–

ps

L_ACC

T_R/ T_F

T_RFM

V_HIGH

V_LOW

V_OX

Measured at 0V differential

ppm

V/ns

%

LCD_100 Rising and Falling slew rate Measured differentially from ±150 mV

2.5

–

Rise/Fall Matching

Voltage High

Measured single-endedly from ±75 mV

20

1.15

–

V

Voltage Low

–0.3

300

V

Crossing Point Voltage at 0.7V Swing

550

mV

PCI/PCIF at 3.3V

T_DC

PCI Duty Cycle

Measurement at 1.5V

45

55

%

T_PERIOD

T_PERIODSS

T_PERIODAbs

Spread Disabled PCIF/PCI Period

Spread Enabled PCIF/PCI Period

Spread Disabled PCIF/PCI Period

29.99100 30.00900 ns

29.99100 30.15980 ns

29.49100 30.50900 ns

29.49100 30.65980 ns

T_PERIODSSAbsSpread Enabled PCIF/PCI Period

T_HIGH

T_LOW

Pread enabled PCIF and PCI high time Measurement at 2.0V

Spread enabled PCIF and PCI low time Measurement at 0.8V

12

ns

...................................................Document #: Page 19 of 25

SL28540

AC Electrical Specifications (continued)

Parameter

T_R/ T_F

T_SKEW

T_CCJ

Description

Condition

Min.

1.0

–

Max.

4.0

Unit

V/ns

ps

PCIF/PCI rising and falling Edge Rate Measured between 0.8V and 2.0V

Any PCI clock to Any PCI clock Skew Measurement at 1.5V

1000

500

300

PCIF and PCI Cycle to Cycle Jitter

PCIF/PCI Long Term Accuracy

Measurement at 1.5V

–

ps

L_ACC

–

ppm

48_M at 3.3V

T_DC

Duty Cycle

Measurement at 1.5V

Measurement at 2.0V

Measurement at 0.8V

Measured between 0.8V and 2.0V

Measurement at 1.5V

45

55

%

T_PERIOD

T_PERIODAbs

T_HIGH

Period

20.83125 20.83542 ns

20.48125 21.18542 ns

8.216563 11.15198 ns

Absolute Period

48_M High time

T_LOW

48_M Low time

7.694

1.0

–

9.836

2.0

ns

V/ns

ps

T_R/ T_F

T_CCJ

Rising and Falling Edge Rate

Cycle to Cycle Jitter

48M Long Term Accuracy

350

100

L_ACC

–

ppm

REF

T_DC

REF Duty Cycle

Measurement at 1.5V

Measured between 0.8V and 2.0V

Measurement at 1.5V

45

55

%

T_PERIOD

T_PERIODAbs

T_R/ T_F

T_SKEW

T_CCJ

REF Period

69.82033 69.86224 ns

68.83429 70.86224 ns

REF Absolute Period

REF Rising and Falling Edge Rate

REF Clock to REF Clock

REF Cycle to Cycle Jitter

Long Term Accuracy

1.0

–

4.0

500

V/ns

ps

–

1000

300

ps

L_ACC

–

ppm

ENABLE/DISABLE and SET-UP

T_STABLEClock Stabilization from Power-up

T_SSStopclock Set-up Time

–

1.8

–

ms

ns

10.0

Test and Measurement Set-up

For PCI Single-ended Signals and Reference

The following diagram shows the test load configurations for

the single-ended PCI, USB, and REF output signals.

Measurement

Point

22

L1

L2

50

4 pF

PCI/USB

L1 = 0.5", L2 = 4"

Measurement

Point

50

22

L2

L1

Figure 12. Single-ended PCI and USB Double Load Configuration

...................................................Document #: Page 20 of 25

SL28540

Measurement

Point

4 pF

15

L2

L1

50

Measurement

Point

4 pF

15

L1

L2

REF

50

Measurement

Point

4 pF

L2

50

Figure 13. Single-ended REF Triple Load Configuration

Figure 14. Single-ended Output Signals (for AC Parameters Measurement)

For CPU, SRC, and DOT96 Signals and Reference

This diagram shows the test load configuration for the differential CPU and SRC outputs

Figure 15. 0.7V Differential Load Configuration

...................................................Document #: Page 21 of 25

SL28540

Clock Period (Differential)

Positive Duty Cycle (Differential)

Negative Duty Cycle (Differential)

0.0V

Clck-Clck#

Rise

Edge

Rate

Fall

Edge

Rate

VIH = +150V

0.0V

VIH = +150V

0.0V

VIL = -150V

Clock-Clock#

Figure 16. Differential Measurement for Differential Output Signals (for AC Parameters Measurement)

V_MAX= 1.15V

CLK#

Vcross_MAX= 550mV

Vcross_MIN= 300mV

Vcross_MAX= 550mV

Vcross_MIN= 300mV

CLK

V_MIN= 0.30V

CLK#

Vcross delta = 140mV

CLK#

Vcross median +75mV

Vcross median

Vcross median -75mV

CLK

Figure 17. Single-ended Measurement for Differential Output Signals (for AC Parameters Measurement)

...................................................Document #: Page 22 of 25

SL28540

Ordering Information

Part Number

Lead-free

Package Type

Product Flow

SL28540ALC

56-pin QFN

56-pin QFN, Tape and Reel

Commercial, 0 to 85C

SL28540ALCT

...................................................Document #: Page 23 of 25

SL28540

Package Diagrams

56-Lead QFN 8x 8mm LF56A

TOP VIEW

BOTTOM VIEW

SIDE VIEW

0.08[0.003]

C

1.00[0.039] MAX.

0.80[0.031] MAX.

7.90[0.311]

8.10[0.319]

A

0.05[0.002] MAX.

0.18[0.007]

0.28[0.011]

7.70[0.303]

7.80[0.307]

0.20[0.008] REF.

PIN1 ID

N

0.20[0.008] R.

1

2

1

2

0.45[0.018]

0.80[0.031]

DIA.

E-PAD

(PAD SIZE VARY

BY DEVICE TYPE)

0.30[0.012]

0.50[0.020]

0.24[0.009]

0.60[0.024]

(4X)

0°-12°

0.50[0.020]

6.45[0.254]

6.55[0.258]

C

SEATING

PLANE

51-85215-**

...................................................Document #: Page 24 of 25

SL28540

Document History Page

Document Title: SL28540 Low Power Clock Generator for Intel^®Mobile Platform

Document Number:

Orig. of

REV.

1.0

Issue Date Change

Description of Change

03/19/2007

08/15/2007

SLI

New data sheet

1.1

Updated Features list

Updated DC Electrical Specifications table

Updated AC Electrical Specifications table

Updated ordering information

1.2

09/15/2008

JMA

1. Added iAMT functions

2. Removed TME definition

The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Sil-

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...................................................Document #: Page 25 of 25


型号：	SL28540ALC
厂家：	SILICON
描述：	Clock Generator, 200MHz, CMOS, 8 X 8 MM, LEAD FREE, QFN-56 时钟外围集成电路晶体
文件：	总25页 (文件大小：180K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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