SL28541BZCT [SILICON]
Clock Generator, 400MHz, CMOS, PDSO64, 6 X 17 MM, HALOGEN FREE AND ROHS COMPLIANT, MO-153EF, TSSOP-64;型号: | SL28541BZCT |
厂家: | SILICON |
描述: | Clock Generator, 400MHz, CMOS, PDSO64, 6 X 17 MM, HALOGEN FREE AND ROHS COMPLIANT, MO-153EF, TSSOP-64 时钟 光电二极管 外围集成电路 晶体 |
文件: | 总31页 (文件大小:262K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
SL28541
Clock Generator for Intel®Mobile Chipset
• 33 MHz PCI clocks
Features
• 27 MHz Video clocks
• Intel® CK505 Rev. 1.0 Compliant
• Buffered Reference Clock 14.318 MHz
• Low power push-pull type differential output buffers
• Integrated voltage regulator
• 14.318 MHz Crystal Input or Clock Input
• Low-voltage frequency select input
• I2C support with readback capabilities
• Integrated resistors on differential clocks
• Scalable low voltage VDD_IO (1.05V to 3.3V)
• Ideal Lexmark Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
• 8-step programmable drive strength for single-ended
clocks
• Industrial Temperature -40°C to 85°C
• 3.3V Power supply
• Differential CPU clocks with selectable frequency
• 100 MHz Differential SRC clocks
• 100 MHz Differential LCD clock
• 96 MHz Differential DOT clock
• 48 MHz USB clock
• 64-pin QFN and TSSOP packages
CPU SRC PCI REF DOT96 USB_48 LCD 27M
x2 / x3 x8/12 x6
x 1
x 1
x 1
x1
x2
Block Diagram
........................ DOC #: SP-AP-0063 (Rev. AA) Page 1 of 31
400 West Cesar Chavez, Austin, TX 78701
1+(512) 416-8500 1+(512) 416-9669
www.silabs.com
SL28541
Pin Configurations
1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PCI0/OE#_0/2_A
VDD_PCI
PCI1/OE#_0/2_A
PCI2/TME
SCLK
2
SDATA
3
REF0/FSC/TEST_SEL
VDD_REF
XIN/CLKIN
XOUT
4
5
PCI3
6
PCI4/GCLK_SEL
PCIF0/ITP_EN
VSS_PCI
VDD_48
USB_48/ FSA
VSS_48
7
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VSS_REF
8
FSB/TEST_MODE
CKPWRGD/PD#
VDD_CPU
CPU0
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VSS_REF
XOUT
SRC6
9
SRC#
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
3
XIN/CLKIN
VDD_SRC
PCI_STP#
CPU_STP#
VDD_SRC_IO
SRC10#
4
VDD_IO
CPU#0
VDD_REF
SRC0/DOT96
SRC0#/DOT96#
VSS_IO
VSS_CPU
CPU1
5
REF0/FSC/TEST_SEL
SDATA
6
CPU1#
64 TSSOP
7
SCLK
VDD_PLL3
VDD_CPU_IO
NC
64 QFN
8
PCI0/OE#_0/2_A
VDD_PCI
SRC10
SRC1/LCD100/27M_NSS
SRC1#/LCD100#/27M_SS
VSS_PLL3
SRC8/ CPU2_ITP
SRC8#/ CPU2_ITP#
VDD_SRC_IO
SRC7/OE#_8
SRC7#/OE#_6
VSS_SRC
SRC6
9
SRC11/OE#_10
SRC11#//OE#_9
SRC9#
10
11
12
13
14
15
16
PCI1/OE#_0/2_A
PCI2/TME
VDD_PLL3_IO
SRC2/SATA
SRC2#/SATA#
VSS_SRC
PCI3
SRC9
PCI4/GCLK_SEL
PCIF0/ITP_EN
VSS_PCI
VSS_SRC
SRC4#
SRC3/OE#_0/2_B
SRC3#/OE#_1/4_B
VDD_SRC_IO
SRC4
SRC#
SRC4
VDD_SRC
PCI_STP#
CPU_STP#
VDD_SRC_IO
SRC10#
VDD_48
VDD_SRC_IO
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
SRC4#
VSS_SRC
SRC9
SRC9#
SRC10
SRC11#//OE#_9
SRC11/OE#_10
........................ DOC #: SP-AP-0063 (Rev. AA) Page 2 of 31
SL28541
64 QFN Pin Definitions
Pin No.
Name
VSS_REF
Type
Description
1
2
3
4
GND Ground for outputs.
XOUT
O, SE 14.318MHz Crystal output. (Float XOUT if using CLKIN)
14.318MHz Crystal input or 3.3V, 14.318MHz input clock signal.
XIN/CLKIN
VDD_REF
I
PWR 3.3V Power supply for outputs and also maintains SMBUS registers during
power-down.
5
REF0/FSC/TEST_SEL
I/O
3.3V tolerant input for CPU frequency selection/fixed 14.318MHz clock output.
Selects test mode if pulled to VIHFS_C when CKPWRGD is asserted HIGH. Refer
to DC Electrical Specifications table for VILFS_C, VIMFS_C, VIHFS_C specifications.
6
7
8
SMB_DATA
I/O
I
SMBus compatible SDATA.
SMBus compatible SCLOCK.
SMB_CLK
PCI0/OE#_0/2_A
I/O, SE 3.3V, 33MHz clock/3.3V OE# Input mappable via I2C to control either SRC0 or
SRC2. (Default PCI0, 33MHz clock)
9
VDD_PCI
PWR 3.3V Power supply for PCI PLL.
10
PCI1/OE#_1/4_A
I/O, SE 3.3V, 33MHz clock/3.3V OE# Input mappable via I2C to control either SRC1 or
SRC4. (Default PCI1, 33MHz clock)
11
PCI2/TME
I/O, SE 3.3V tolerance input for overclocking enable pin/3.3V, 33MHz clock.
(Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications)
12
13
PCI3
O, SE, 33 MHz clock.
PCI4 / GCLK_SEL
I/O, SE 33 MHz clock output/3.3V-tolerant input for selecting graphic clock source on pin
13, 14, 17and 18
Sampled on CKPWRGD assertion
GCLK_SEL
Pin13
DOT96T DOT96C SRC1T/LCD_100T SRC1C/LCD_100C
SRCT0 SRCC0 27M_NSS 27M_SS
Pin14
Pin17
Pin 18
0
1
14
PCIF_0/ITP_EN
I/O, SE 3.3V LVTTL input to enable SRC8 or CPU2_ITP/33 MHz clock output. (sampled
on the CK_PWRGD assertion)
1 = CPU2_ITP, 0 = SRC8
15
16
17
VSS_PCI
GND Ground for outputs.
VDD_48
PWR 3.3V Power supply for outputs and PLL.
USB_48/FSA
I/O
3.3V tolerant input for CPU frequency selection/fixed 3.3V, 48MHz clock output.
(Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications)
18
19
20
VSS_48
GND Ground for outputs.
VDD_IO
PWR 0.7V Power supply for outputs.
SRC0/DOT96
O, DIF 100MHz Differential serial reference clocks/Fixed 96MHz clock output.
(Selected via I2C default is SRC0)
21
SRC0#/DOT96#
O, DIF 100MHz Differential serial reference clocks/Fixed 96MHz clock output.
(Selected via I2C default is SRC0)
22
23
24
VSS_IO
GND Ground for PLL2.
VDD_PLL3
PWR 3.3V Power supply for PLL3
SRC1/LCD100/27_NSS O, DIF, True 100 MHz differential serial reference clock output/True 100 MHz LCD video
SE
clock output / Non-spread 27-MHz video clock output.
Selected via GCLK_SEL at CKPWRGD assertion.
25
26
SRC1#/LCD100#27_SS O, DIF, Complementary 100 MHz differential serial reference clock output/Complementary
SE
100 MHz LCD video clock output /Spread 27 MHz video clock output.
Selected via GCLK_SEL at CKPWRGD assertion.
VSS_PLL3
GND Ground for PLL3.
........................ DOC #: SP-AP-0063 (Rev. AA) Page 3 of 31
SL28541
64 QFN Pin Definitions (continued)
Pin No.
27
Name
VDD_PLL3_IO
SRC2/SATA
Type
Description
PWR IO Power supply for PLL3 outputs.
28
O, DIF 100MHz Differential serial reference clocks.
O, DIF 100MHz Differential serial reference clocks.
GND Ground for outputs.
29
SRC2#/SATA#
VSS_SRC
30
31
SRC3/OE#_0/2_B
I/O, 100MHz Differential serial reference clocks / 3.3V OE#_0/2_B, input, mappable via
Dif I2C to control either SRC0 or SRC2. (Default SRC3, 100MHz clock)
32
SRC3#OE#_1/4_B
I/O, 100MHz Differential serial reference clocks / 3.3V OE#_1/4_B input, mappable via
Dif I2C to control either SRC1 or SRC4. (Default SRC3, 100MHz clock)
33
34
35
36
37
38
39
VDD_SRC_IO
SRC4
PWR IO power supply for SRC outputs.
O, DIF 100MHz Differential serial reference clocks.
O, DIF 100MHz Differential serial reference clocks.
GND Ground for outputs.
SRC4#
VSS_SRC
SRC9
O, DIF 100MHz Differential serial reference clocks.
O, DIF 100MHz Differential serial reference clocks.
I/O, 100MHz Differential serial reference clocks/3.3V OE#9 Input controlling SRC9
SRC9#
SRC11#/OE#_9
Dif
I/O, 100MHz Differential serial reference clocks/3.3V OE#10 Input controlling SRC10.
Dif (Default SRC11, 100MHz clock)
(Default SRC11, 100MHz clock)
40
SRC11/OE#_10
41
42
43
44
45
46
47
48
49
50
SRC10
O, DIF 100MHz Differential serial reference clocks.
O, DIF 100MHz Differential serial reference clocks.
PWR IO Power supply for SRC outputs.
SRC10#
VDD_SRC_IO
CPU_STP#
PCI_STP#
VDD_SRC
SRC6#
I
I
3.3V tolerant input for stopping CPU outputs
3.3V tolerant input for stopping PCI and SRC outputs
PWR 3.3V Power supply for SRC PLL.
O, DIF 100MHz Differential serial reference clocks.
O, DIF 100MHz Differential serial reference clocks.
GND Ground for outputs.
SRC6
VSS_SRC
SRC7#/OE#_6
I/O, 100MHz Differential serial reference clocks/3.3V OE#6 Input controlling SRC6.
Dif
I/O, 100MHz Differential serial reference clocks/3.3V OE#8 Input controlling SRC8.
Dif (Default SRC7, 100MHz clock).
(Default SRC7, 100MHz clock).
51
SRC7/OE#_8
52
53
VDD_SRC_IO
PWR 0.7V power supply for SRC outputs.
SRC8#/CPU2#_ITP#
O, DIF Selectable differential CPU or SRC clock output. ITP_EN = 0 at CKPWRGD
assertion = SRC8
ITP_EN = 1 @ CKPWRGD assertion = CPU2
(Note: CPU2 is an iAMT clock in iAMT mode depending on the configuration set in Byte 11
Bit3:2)
54
SRC8/CPU2_ITP
O, DIF Selectable differential CPU or SRC clock output. ITP_EN = 0 at CKPWRGD
assertion = SRC8
ITP_EN = 1 @ CKPWRGD assertion = CPU2
(Note: CPU2 is an iAMT clock in iAMT mode depending on the configuration set in Byte 11
Bit3:2)
55
56
57
NC
NC
No Connect
VDD_CPU_IO
CPU1#
PWR IO Power supply for CPU outputs.
O, DIF Differential CPU clock outputs. (Note: CPU1 is an iAMT clock in iAMT mode depending
on the configuration set in Byte 11 Bit3:2)
58
59
CPU1
O, DIF Differential CPU clock outputs. (Note: CPU1 is an iAMT clock in iAMT mode depending
on the configuration set in Byte 11 Bit3:2)
VSS_CPU
GND Ground for outputs.
........................ DOC #: SP-AP-0063 (Rev. AA) Page 4 of 31
SL28541
64 QFN Pin Definitions (continued)
Pin No.
60
Name
Type
Description
CPU#0
CPU0
O, DIF Differential CPU clock outputs.
O, DIF Differential CPU clock outputs.
PWR 3.3V Power supply for CPU PLL.
61
62
VDD_CPU
63
CKPWRGD/PD#
I
3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A, FS_B,
FS_C, FS_D, SRC5_SEL, and ITP_EN.
After CKPWRGD (active HIGH) assertion, this pin becomes a real-time input for
asserting power down (active LOW).
64
FSB/TEST_MODE
I
3.3V tolerant input for CPU frequency selection.
Selects Ref/N or Tri-state when in test mode
0 = Tri-state, 1 = Ref/N.
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
64 TSSOP Pin Definition
Pin No.
Name
Type
Description
1
PCI0/OE#_0/2_A
I/O, SE 3.3V, 33MHz clock/3.3V OE# Input mappable via I2C to control either SRC0 or
SRC2. (Default PCI0, 33MHz clock)
2
3
VDD_PCI
PWR 3.3V Power supply for PCI PLL.
PCI1/OE#_1/4_A
I/O, SE 3.3V, 33MHz clock/3.3V OE# Input mappable via I2C to control either SRC1 or
SRC4. (Default PCI1, 33MHz clock)
4
PCI2/TME
I/O, SE 3.3V tolerance input for overclocking enable pin/3.3V, 33MHz clock.
(Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications)
5
6
PCI3
O, SE, 33 MHz clock.
PCI4 / GCLK_SEL
I/O, SE 33 MHz clock output/3.3V-tolerant input for selecting graphic clock source on pin
13, 14, 17and 18
Sampled on CKPWRGD assertion
GCLK_SEL
Pin13
DOT96T DOT96C SRC1T/LCD_100T SRC1C/LCD_100C
SRCT0 SRCC0 27M_NSS 27M_SS
Pin14
Pin17
Pin 18
0
1
7
PCIF_0/ITP_EN
I/O, SE 3.3V LVTTL input to enable SRC8 or CPU2_ITP/33 MHz clock output. (sampled
on the CK_PWRGD assertion)
1 = CPU2_ITP, 0 = SRC8
8
VSS_PCI
GND Ground for outputs.
9
VDD_48
PWR 3.3V Power supply for outputs and PLL.
10
USB_48/FSA
I/O
3.3V tolerant input for CPU frequency selection/fixed 3.3V, 48MHz clock output.
(Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications)
11
12
13
VSS_48
GND Ground for outputs.
VDD_IO
PWR 0.7V Power supply for outputs.
SRC0/DOT96
O, DIF 100MHz Differential serial reference clocks/Fixed 96MHz clock output.
(Selected via I2C default is SRC0)
14
SRC0#/DOT96#
O, DIF 100MHz Differential serial reference clocks/Fixed 96MHz clock output.
(Selected via I2C default is SRC0)
15
16
VSS_IO
GND Ground for PLL2.
VDD_PLL3
PWR 3.3V Power supply for PLL3
........................ DOC #: SP-AP-0063 (Rev. AA) Page 5 of 31
SL28541
64 TSSOP Pin Definition (continued)
Pin No.
Name
Type
Description
17
SRC1/LCD100/27_NSS O, DIF, True 100 MHz differential serial reference clock output/True 100 MHz LCD video
SE
clock output / Non-spread 27-MHz video clock output.
Selected via GCLK_SEL at CKPWRGD assertion.
18
SRC1#/LCD100#/27_SS O, DIF, Complementary 100 MHz differential serial reference clock output/Complementary
SE
100 MHz LCD video clock output /Spread 27 MHz video clock output.
Selected via GCLK_SEL at CKPWRGD assertion.
19
20
21
22
23
24
VSS_PLL3
GND Ground for PLL3.
VDD_PLL3_IO
SRC2/SATA
PWR IO Power supply for PLL3 outputs.
O, DIF 100MHz Differential serial reference clocks.
O, DIF 100MHz Differential serial reference clocks.
GND Ground for outputs.
SRC2#/SATA#
VSS_SRC
SRC3/OE#_0/2_B
I/O, 100MHz Differential serial reference clocks / 3.3V OE#_0/2_B, input, mappable via
Dif
I/O, 100MHz Differential serial reference clocks / 3.3V OE#_1/4_B input, mappable via
Dif I2C to control either SRC1 or SRC4. (Default SRC3, 100MHz clock)
I2C to control either SRC0 or SRC2. (Default SRC3, 100MHz clock)
25
SRC3#OE#_1/4_B
26
27
28
29
30
31
32
VDD_SRC_IO
SRC4
PWR IO power supply for SRC outputs.
O, DIF 100MHz Differential serial reference clocks.
O, DIF 100MHz Differential serial reference clocks.
GND Ground for outputs.
SRC4#
VSS_SRC
SRC9
O, DIF 100MHz Differential serial reference clocks.
O, DIF 100MHz Differential serial reference clocks.
I/O, 100MHz Differential serial reference clocks/3.3V OE#9 Input controlling SRC9
SRC9#
SRC11#/OE#_9
Dif
I/O, 100MHz Differential serial reference clocks/3.3V OE#10 Input controlling SRC10.
Dif (Default SRC11, 100MHz clock)
(Default SRC11, 100MHz clock)
33
SRC11/OE#_10
34
35
36
37
38
39
40
41
42
43
SRC10
O, DIF 100MHz Differential serial reference clocks.
O, DIF 100MHz Differential serial reference clocks.
PWR IO Power supply for SRC outputs.
SRC10#
VDD_SRC_IO
CPU_STP#
PCI_STP#
VDD_SRC
SRC6#
I
I
3.3V tolerant input for stopping CPU outputs
3.3V tolerant input for stopping PCI and SRC outputs
PWR 3.3V Power supply for SRC PLL.
O, DIF 100MHz Differential serial reference clocks.
O, DIF 100MHz Differential serial reference clocks.
GND Ground for outputs.
SRC6
VSS_SRC
SRC7#/OE#_6
I/O, 100MHz Differential serial reference clocks/3.3V OE#6 Input controlling SRC6.
Dif
I/O, 100MHz Differential serial reference clocks/3.3V OE#8 Input controlling SRC8.
Dif (Default SRC7, 100MHz clock).
(Default SRC7, 100MHz clock).
44
SRC7/OE#_8
45
46
VDD_SRC_IO
PWR 0.7V power supply for SRC outputs.
SRC8#/CPU2#_ITP#
O, DIF Selectable differential CPU or SRC clock output. ITP_EN = 0 at CKPWRGD
assertion = SRC8
ITP_EN = 1 @ CKPWRGD assertion = CPU2
(Note: CPU2 is an iAMT clock in iAMT mode depending on the configuration set in Byte 11
Bit3:2)
47
SRC8/CPU2_ITP
O, DIF Selectable differential CPU or SRC clock output. ITP_EN = 0 at CKPWRGD
assertion = SRC8
ITP_EN = 1 @ CKPWRGD assertion = CPU2
(Note: CPU2 is an iAMT clock in iAMT mode depending on the configuration set in Byte 11
Bit3:2)
........................ DOC #: SP-AP-0063 (Rev. AA) Page 6 of 31
SL28541
64 TSSOP Pin Definition (continued)
Pin No.
48
Name
Type
Description
NC
NC
No Connect
49
VDD_CPU_IO
CPU1#
PWR IO Power supply for CPU outputs.
50
O, DIF Differential CPU clock outputs. (Note: CPU1 is an iAMT clock in iAMT mode depending
on the configuration set in Byte 11 Bit3:2)
51
CPU1
O, DIF Differential CPU clock outputs. (Note: CPU1 is an iAMT clock in iAMT mode depending
on the configuration set in Byte 11 Bit3:2)
52
53
54
55
56
VSS_CPU
CPU#0
GND Ground for outputs.
O, DIF Differential CPU clock outputs.
O, DIF Differential CPU clock outputs.
PWR 3.3V Power supply for CPU PLL.
CPU0
VDD_CPU
CKPWRGD/PD#
I
3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A, FS_B,
FS_C, FS_D, SRC5_SEL, and ITP_EN.
After CKPWRGD (active HIGH) assertion, this pin becomes a real-time input for
asserting power down (active LOW).
57
FSB/TEST_MODE
I
3.3V tolerant input for CPU frequency selection.
Selects Ref/N or Tri-state when in test mode
0 = Tri-state, 1 = Ref/N.
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
58
59
60
61
VSS_REF
XOUT
GND Ground for outputs.
O, SE 14.318MHz Crystal output. (Float XOUT if using CLKIN)
XIN/CLKIN
VDD_REF
I
14.318MHz Crystal input or 3.3V, 14.318MHz input clock signal.
PWR 3.3V Power supply for outputs and also maintains SMBUS registers during
power-down.
62
REF0/FSC/TEST_SEL
I/O
3.3V tolerant input for CPU frequency selection/fixed 14.318MHz clock output.
Selects test mode if pulled to VIHFS_C when CKPWRGD is asserted HIGH. Refer
to DC Electrical Specifications table for VILFS_C, VIMFS_C, VIHFS_C specifications.
63
64
SMB_DATA
SMB_CLK
I/O
I
SMBus compatible SDATA.
SMBus compatible SCLOCK.
Table 1. Frequency Select Pin (FSA, FSB and FSC)
FSC
0
FSB
0
FSA
0
CPU
SRC
PCIF/PCI
27MHz
REF
DOT96
USB
266 MHz
133 MHz
200 MHz
166 MHz
333 MHz
100 MHz
400 MHz
0
0
1
0
1
0
0
1
1
100 MHz
33 MHz
27 MHz
14.318 MHz
Reserved
96 MHz
48 MHz
1
0
0
1
0
1
1
1
0
1
1
1
Reserved Reserved Reserved Reserved
Reserved Reserved
employs a one-shot functionality and once the CKPWRGD
sampled a valid HIGH, all other FSA, FSB, FSC, and
CKPWRGD transitions are ignored except in test mode.
Frequency Select Pin (FSA, FSB and FSC)
Apply the appropriate logic levels to FSA, FSB, and FSC
inputs before CKPWRGD assertion to achieve host clock
frequency selection. When the clock chip sampled HIGH on
CKPWRGD and indicates that VTT voltage is stable then FSA,
FSB, and FSC input values are sampled. This process
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
........................ DOC #: SP-AP-0063 (Rev. AA) Page 7 of 31
SL28541
clock output buffers are individually enabled or disabled. The
registers associated with the Serial Data Interface initialize to
block write/read operation, access the bytes in sequential
order from lowest to highest (most significant bit first) with the
ability to stop after any complete byte is transferred. For byte
write and byte read operations, the system controller can
access individually indexed bytes. The offset of the indexed
byte is encoded in the command code described in Table 2.
their default setting at power-up. The use of this interface is
optional. Clock device register changes are normally made at
system initialization, if any are required. The interface cannot
be used during system operation for power management
functions.
The block write and block read protocol is outlined in Table 3
while Table 4 outlines byte write and byte read protocol. The
slave receiver address is 11010010 (D2h).
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
.
Table 2. Command Code Definition
Bit
Description
7
0 = Block read or block write operation, 1 = Byte read or byte write operation
(6:0) Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'
Table 3. Block Read and Block Write Protocol
Block Write Protocol
Description
Block Read Protocol
Description
Bit
1
Bit
1
Start
Start
8:2
9
Slave address–7 bits
Write
8:2
9
Slave address–7 bits
Write
10
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
Byte Count–8 bits
10
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
Repeat start
18:11
19
18:11
19
27:20
28
20
Acknowledge from slave
Data byte 1–8 bits
27:21
28
Slave address–7 bits
Read = 1
36:29
37
Acknowledge from slave
Data byte 2–8 bits
29
Acknowledge from slave
Byte Count from slave–8 bits
Acknowledge
45:38
46
37:30
38
Acknowledge from slave
Data Byte /Slave Acknowledges
Data Byte N–8 bits
Acknowledge from slave
Stop
....
46:39
47
Data byte 1 from slave–8 bits
Acknowledge
....
....
55:48
56
Data byte 2 from slave–8 bits
Acknowledge
....
....
Data bytes from slave / Acknowledge
Data Byte N from slave–8 bits
NOT Acknowledge
Stop
....
....
....
Table 4. Byte Read and Byte Write Protocol
Byte Write Protocol
Byte Read Protocol
Description
Bit
1
Description
Bit
1
Start
Start
8:2
9
Slave address–7 bits
Write
8:2
9
Slave address–7 bits
Write
10
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
10
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
18:11
19
18:11
19
........................ DOC #: SP-AP-0063 (Rev. AA) Page 8 of 31
SL28541
Table 4. Byte Read and Byte Write Protocol
27:20
28
Data byte–8 bits
Acknowledge from slave
Stop
20
27:21
28
Repeated start
Slave address–7 bits
Read
29
29
Acknowledge from slave
Data from slave–8 bits
NOT Acknowledge
Stop
37:30
38
39
Control Registers
Byte 0: Control Register 0
Bit
7
@Pup
HW
HW
HW
0
Name
FS_C
Description
CPU Frequency Select Bit, set by HW
CPU Frequency Select Bit, set by HW
CPU Frequency Select Bit, set by HW
6
FS_B
5
FS_A
4
iAMT_EN
Set via SMBus or by combination of PWRDWN, CPU_STP, and PCI_STP
0 = Legacy Mode, 1 = iAMT Enabled
3
2
0
0
Reserved
Reserved
SRC_Main_SEL
Select source for SRC clock
0 = SRC_MAIN = PLL1, PLL3_CFG Table applies
1 = SRC_MAIN = PLL3, PLL3_CFG Table does not apply
1
0
0
1
SATA_SEL
Select source of SATA clock
0 = SATA = SRC_MAIN, 1= SATA = PLL2
PD_Restore
Save configuration when PD# is asserted
0 = Config. cleared, 1 = Config. saved
Byte 1: Control Register 1
Bit
@Pup
Name
Description
7
0
SRC0_SEL
Select for SRC0 or DOT96
0 = SRC0, 1 = DOT96
When GCLK_SEL=0, this bit is 1. When GCLK_SEL=1, this bit is 0
6
5
0
0
PLL1_SS_DC
PLL3_SS_DC
Select for down or center SS
0 = Down spread, 1 = Center spread
Select for down or center SS
0 = Down spread, 1 = Center spread
4
3
2
1
0
0
0
1
0
1
PLL3_CFB3
PLL3_CFB2
PLL3_CFB1
PLL3_CFB0
Reserved
Bit 4:1 only applies when SRC_Main_SEL = 0
SeeTable 8: PLL3 / SE configuration table
Reserved
Byte 2: Control Register 2
Bit
@Pup
Name
Description
7
1
REF
Output enable for REF
0 = Output Disabled, 1 = Output Enabled
6
5
1
1
USB
Output enable for USB
0 = Output Disabled, 1 = Output Enabled
PCIF0
Output enable for PCIF0
0 = Output Disabled, 1 = Output Enabled
........................ DOC #: SP-AP-0063 (Rev. AA) Page 9 of 31
SL28541
Byte 2: Control Register 2 (continued)
Bit
@Pup
Name
Description
4
1
PCI4
Output enable for PCI4
0 = Output Disabled, 1 = Output Enabled
3
2
1
0
1
1
1
1
PCI3
PCI2
PCI1
PCI0
Output enable for PCI3
0 = Output Disabled, 1 = Output Enabled
Output enable for PCI2
0 = Output Disabled, 1 = Output Enabled
Output enable for PCI1
0 = Output Disabled, 1 = Output Enabled
Output enable for PCI0
0 = Output Disabled, 1 = Output Enabled
Byte 3: Control Register 3
Bit
@Pup
Name
Description
7
1
SRC[T/C]11
Output enable for SRC11
0 = Output Disabled, 1 = Output Enabled
6
5
4
3
2
1
1
1
1
1
SRC[T/C]10
SRC[T/C]9
Output enable for SRC10
0 = Output Disabled, 1 = Output Enabled
Output enable for SRC9
0 = Output Disabled, 1 = Output Enabled
SRC[T/C]8/CPU2_ITP
SRC[T/C]7
Output enable for SRC8 or CPU2_ITP
0 = Output Disabled, 1 = Output Enabled
Output enable for SRC7
0 = Output Disabled, 1 = Output Enabled
SRC[T/C]6
Output enable for SRC6
0 = Output Disabled, 1 = Output Enabled
1
0
1
1
Reserved
Reserved
SRC[T/C]4
Output enable for SRC4
0 = Output Disabled, 1 = Output Enabled
Byte 4: Control Register 4
Bit
@Pup
Name
Description
7
1
SRC[T/C]3
Output enable for SRC3
0 = Output Disabled, 1 = Output Enabled
6
5
4
3
2
1
0
1
1
1
1
1
1
1
SRC[T/C]2/SATA
Output enable for SRC2/SATA
0 = Output Disabled, 1 = Output Enabled
SRC[T/C]1/LCD_100M[T/C] Output enable for SRC1/LCD_100M
0 = Output Disabled, 1 = Output Enabled
SRC[T/C]0/DOT96[T/C]
Output enable for SRC0/DOT96
0 = Output Disabled, 1 = Output Enabled
CPU[T/C]1
Output enable for CPU1
0 = Output Disabled, 1 = Output Enabled
CPU[T/C]0
Output enable for CPU0
0 = Output Disabled, 1 = Output Enabled
PLL1_SS_EN
PLL3_SS_EN
Enable PLL1s spread modulation,
0 = Spread Disabled, 1 = Spread Enabled
Enable PLL3s spread modulation
0 = Spread Disabled, 1 = Spread Enabled
...................... DOC #: SP-AP-0063 (Rev. AA) Page 10 of 31
SL28541
Byte 5: Control Register 5
Bit
@Pup
Name
Description
7
0
CR#_A_EN
Enable CR#_A (clk req)
0 = Disabled, 1 = Enabled,
6
5
4
3
2
1
0
0
0
0
0
0
0
0
CR#_A_SEL
CR#_B_EN
CR#_B_SEL
CR#_C_EN
CR#_C_SEL
CR#_D_EN
CR#_D_SEL
Set CR#_A SRC0 or SRC2
0 = CR#_ASRC0, 1 = CR#_ASRC2
Enable CR#_B(clk req)
0 = Disabled, 1 = Enabled,
Set CR#_B SRC1 or SRC4
0 = CR#_BSRC1, 1 = CR#_BSRC4
Enable CR#_C (clk req)
0 = Disabled, 1 = Enabled
Set CR#_C SRC0 or SRC2
0 = CR#_CSRC0, 1 = CR#_CSRC2
Enable CR#_D (clk req)
0 = Disabled, 1 = Enabled
Set CR#_D SRC1 or SRC4
0 = CR#_DSRC1, 1 = CR#_DSRC4
Byte 6: Control Register 6
Bit
@Pup
Name
Description
7
0
CR#_E_EN
Enable CR#_E (clk req) SRC6
0 = Disabled, 1 = Enabled
6
5
4
0
0
0
CR#_F_EN
CR#_G_EN
CR#_H_EN
Enable CR#_F (clk req) SRC8
0 = Disabled, 1 = Enabled
Enable CR#_G (clk req) SRC9
0 = Disabled, 1 = Enabled
Enable CR#_H (clk req) SRC10
0 = Disabled, 1 = Enabled
3
2
1
0
0
0
Reserved
Reserved
Reserved
Reserved
LCD_100_STP_CTRL
If set, LCD_100 stop with PCI_STP#
0 = Free running, 1 = PCI_STP# stoppable
0
0
SRC_STP_CTRL
If set, SRCs stop with PCI_STP#
0 = Free running, 1 = PCI_STP# stoppable
Byte 7: Vendor ID
Bit
7
@Pup
Name
Description
Revision Code Bit 3
Revision Code Bit 2
Revision Code Bit 1
Revision Code Bit 0
Vendor ID Bit 3
0
0
0
1
1
0
0
0
Rev Code Bit 3
Rev Code Bit 2
Rev Code Bit 1
Rev Code Bit 0
Vendor ID bit 3
Vendor ID bit 2
Vendor ID bit 1
Vendor ID bit 0
6
5
4
3
2
Vendor ID Bit 2
1
Vendor ID Bit 1
0
Vendor ID Bit 0
...................... DOC #: SP-AP-0063 (Rev. AA) Page 11 of 31
SL28541
Byte 8: Control Register 8
Bit
7
@Pup
Name
Description
1
0
0
0
Device_ID3
Device_ID2
Device_ID1
Device_ID0
0000 = CK505 Yellow Cover Device, 56-pin TSSOP
0001 = CK505 Yellow Cover Device, 64-pin TSSOP
6
0010 = CK505 Yellow Cover Device, 48-pin QFN (Reserved)
0011 = CK505 Yellow Cover Device, 56-pin QFN (Reserved)
0100 = CK505 Yellow Cover Device, 64-pin QFN
0101 = CK505 Yellow Cover Device, 72-pin QFN (Reserved)
0110 = CK505 Yellow Cover Device, 48-pin SSOP (Reserved)
0111 = CK505 Yellow Cover Device, 48-pin SSOP (Reserved)
1000 = Reserved
5
4
1001 = CY28548
1010 = Reserved
1011 = Reserved
1100 = Reserved
1101 = Reserved
1110 = Reserved
1111 = Reserved
3
2
1
0
0
1
Reserved
Reserved
Reserved
Reserved
27M_NSS_OE
Output enable for 27M_NSS
0 = Output Disabled, 1 = Output Enabled
0
1
27M_SS_OE
Output enable for 27M_SS
0 = Output Disabled, 1 = Output Enabled
Byte 9: Control Register 9
Bit
@Pup
Name
Description
7
0
PCIF_0_with PCI_STP# Allows control of PCIF_0 with assertion of PCI_STP#
0 = Free running PCIF, 1 = Stopped with PCI_STP#
6
5
4
3
HW
1
TME_STRAP
Trusted mode enable strap status
0 = Normal, 1 = No overclocking
REF_DSC1
REF drive strength 1 of 2 (See Byte 17 and 18 for more setting)
0 = Low, 1 = High
0
TEST_MODE_SEL
TEST_MODE_ENTRY
Mode select either REF/N or tri-state
0 = All output tri-state, 1 = All output REF/N
0
Allow entry into test mode
0 = Normal operation, 1 = Enter test mode
2
1
0
1
0
1
I2C_VOUT<2>
I2C_VOUT<1>
I2C_VOUT<0>
Differential Amplitude Configuration
I2C_VOUT[2,1,0]
000 = 0.63V
001 = 0.71V
010 = 0.77V
011 = 082V
100 = 0.86V
101 = 0.90V (default)
110 = 0.93V
111 = unused
Byte 10: Control Register 10
Bit
@Pup
Name
Description
7
HW
GCLK_SEL latch
Readback of GCLK_SEL latch
0 = DOT96/LCD_100, 1 = SRC0/27 MHz
6
1
PLL3_EN
PLL3 power down
0 = Power down, 1 = Power up
...................... DOC #: SP-AP-0063 (Rev. AA) Page 12 of 31
SL28541
Byte 10: Control Register 10 (continued)
Bit
@Pup
Name
Description
5
1
PLL2_EN
PLL2 power down
0 = Power down, 1 = Power up
4
3
2
1
0
1
1
1
1
1
SRC_DIV_EN
PCI_DIV_EN
SRC divider disable
0 = Disabled, 1 = Enabled
PCI divider disable
0 = Disabled, 1 = Enabled
CPU_DIV_EN
CPU divider disable
0 = Disabled, 1 = Enabled
CPU1 Stop Enable
CPU0 Stop Enable
Enable CPU_STP# control of CPU1
0 = Free running, 1= Stoppable
Enable CPU_STP# control of CPU0
0 = Free running, 1= Stoppable
Byte 11: Control Register 11
Bit
7
@Pup
Name
Description
0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
6
5
4
3
2
1
0
Byte 12: Byte Count
Bit
7
@Pup
Name
Reserved
Reserved
BC5
Description
0
0
0
1
0
0
1
1
Reserved
Reserved
6
5
Byte count register for block read operation.
The default value for Byte count is 19.
In order to read beyond Byte 19, the user should change the byte count
limit.to or beyond the byte that is desired to be read.
4
BC4
3
BC3
2
BC2
1
BC1
0
BC0
Byte 13: Control Register 13
Bit
@Pup
Name
Description
7
1
USB_BIT1
USB drive strength 1 of 3(See Byte 17 for more setting)
0 = Low, 1= High
6
5
4
3
1
0
1
1
PCI/ PCIF_BIT1
PLL1_Spread
SATA_SS_EN
CPU[T/C]2
PCI drive strength 1 of 3(See Byte 17 & 18 for more setting)
0 = Low, 1 = High
Select percentage of spread for PLL1
0 = 0.5%, 1=1%
Enable SATA spread modulation,
0 = Spread Disabled, 1 = Spread Enabled
Allow control of CPU2 with assertion of CPU_STP#
0 = Free running, 1 = Stopped with CPU_STP#
...................... DOC #: SP-AP-0063 (Rev. AA) Page 13 of 31
SL28541
Byte 13: Control Register 13 (continued)
Bit
@Pup
Name
Description
2
1
SE1/SE2_BIT_1
SE1 and SE2 Drive Strength Setting 1 of 3 (See Byte 17 and 18 for more setting)
0 = Low, 1= High
1
0
1
1
Reserved
SW_PCI
Reserved
SW PCI_STP# Function
0 = SW PCI_STP assert, 1 = SW PCI_STP deassert
When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs are
stopped in a synchronous manner with no short pulses.
When this bit is set to 1, all STOPPED PCI, PCIF and SRC outputs are
resumed in a synchronous manner with no short pulses.
Byte 14: Control Register 14
Bit
7
@Pup
Name
Description
0
0
0
0
0
0
0
0
CPU_DAF_N7
CPU_DAF_N6
CPU_DAF_N5
CPU_DAF_N4
CPU_DAF_N3
CPU_DAF_N2
CPU_DAF_N1
CPU_DAF_N0
If Prog_CPU_EN is set, the values programmed in CPU_DAF_N[8:0] and
CPU_DAF_M[6:0] are used to determine the CPU output frequency.
6
5
4
3
2
1
0
Byte 15: Control Register 15
Bit
7
@Pup
Name
Description
0
0
0
0
0
0
0
0
CPU_DAF_N8
CPU_DAF_M6
CPU_DAF_M5
CPU_DAF_M4
CPU_DAF_M3
CPU_DAF_M2
CPU_DAF_M1
CPU_DAF_M0
See Byte 14 for description
6
If Prog_CPU_EN is set, the values programmed in CPU_DAF_N[8:0] and
CPU_DAF_M[6:0] are used to determine the CPU output frequency.
5
4
3
2
1
0
Byte 16: Control Register 16
Bit
7
@Pup
Name
Description
PCI-E Dial-A-Frequency® Bit N7
PCI-E Dial-A-Frequency Bit N6
PCI-E Dial-A-Frequency Bit N5
PCI-E Dial-A-Frequency Bit N4
PCI-E Dial-A-Frequency Bit N3
PCI-E Dial-A-Frequency Bit N2
PCI-E Dial-A-Frequency Bit N1
PCI-E Dial-A-Frequency Bit N0
0
0
0
0
0
0
0
0
PCI-E_N7
PCI-E_N6
PCI-E_N5
PCI-E_N4
PCI-E_N3
PCI-E_N2
PCI-E_N1
PCI-E_N0
6
5
4
3
2
1
0
...................... DOC #: SP-AP-0063 (Rev. AA) Page 14 of 31
SL28541
Byte 17: Control Register 17
Bit
@Pup
Name
Description
7
0
SMSW_EN
Enable Smooth Switching
0 = Disabled, 1= Enabled
6
5
4
3
2
1
0
0
0
0
0
0
0
0
SMSW_SEL
SE1/SE2_BIT0
Prog_PCI-E_EN
Prog_CPU_EN
REF_BIT0
Smooth switch select
0 = CPU_PLL, 1 = SRC_PLL
SE1 and SE2 drive strength Setting 2 of 3(see Byte 18 for more setting)
0 = Low, 1= High
Programmable PCI-E frequency enable
0 = Disabled, 1= Enabled
Programmable CPU frequency enable
0 = Disabled, 1= Enabled
REFdrive strength strength Setting 2 of 3(see Byte 18 for more setting)
0 = Low, 1= High
USB_BIT0
USB drive strength strength Setting 2 of 3(see Byte 18 for more setting)
0 = Low, 1= High
PCI/ PCIF_BIT0
PCI drive strength strength Setting 2 of 3(see Byte 18 for more setting)
0 = Low, 1= High
Byte 18: Control Register 18
7
6
5
4
3
2
1
0
0
0
1
0
0
0
0
0
REF_BIT2
RESERVED
RESERVED
RESERVED
USB_BIT2
Drive Strength Control
BIT_2
(Byte18)
1
BIT_0
(Byte 17)
1
Buffer
Strength
Strongest
BIT_1
(Various B ytes)
1
1
0
0
1
1
0
PCI/PCIF_BIT2
SE1/SE2_BIT2
RESERVED
1
1
1
0
0
0
0
1
0
1
0
1
Default
Table 5. Output Driver Status during PCI-STP# and CPU-STP#
PCI_STP# Asserted
CPU_STP# Asserted
Running
SMBus OE Disabled
Single-ended Clocks Stoppable
Non stoppable
Stoppable
Driven low
Driven low
Running
Running
Differential Clocks
Clock driven high
Clock# driven low
Running
Clock driven high
Clock# driven low
Running
Clock driven Low or 20K
pulldown
Non stoppable
Table 6. Output Driver Status
All Differential Clocks except
CPU1
All Single-ended Clocks
w/o Strap w/ Strap
Low Hi-z
CPU1
Clock
Clock#
Clock
Low or 20K pulldown Low
Low or 20K pulldown Low
Running Running
Clock#
Latches Open State
Powerdown
M1
Low or 20K pulldown Low
Low or 20K pulldown Low
Low or 20K pulldown Low
Low
Low
Hi-z
Hi-z
...................... DOC #: SP-AP-0063 (Rev. AA) Page 15 of 31
SL28541
Table 7. PLL3/SE Configuration Table
GCLK_SEL
B1b4
0
B1b3
0
B1b2
0
B1b1
0
Pin 24 (17) MHz Pin 25 (18) MHz Spread (%)
Comment
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
PLL3 Disabled
0
0
0
1
100
100
100
100
0.5
0.5
1
SRC1 from SRC_Main
0
0
1
0
LCD_100 from PLL3
0
0
1
1
100
100
LCD_100 from PLL3
0
1
0
0
100
100
1.5
2
LCD_100 from PLL3
0
1
0
1
100
100
LCD_100 from PLL3
0
1
1
0
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
none
N/A
N/A
N/A
N/A
0.5
0.5
1
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0
1
1
1
N/A
N/A
1
0
0
0
N/A
N/A
1
0
0
1
N/A
N/A
1
0
1
0
N/A
N/A
1
0
1
1
N/A
N/A
1
1
0
0
N/A
N/A
1
1
0
1
N/A
N/A
1
1
1
0
N/A
N/A
1
1
1
1
N/A
N/A
0
0
0
0
N/A
N/A
0
0
0
1
27M_NSS
27M_NSS
27M_NSS
27M_NSS
27M_NSS
N/A
27M_SS
27M_SS
27M_SS
27M_SS
27M_SS
N/A
27M_SS from PLL3
27M_SS from PLL3
27M_SS from PLL3
27M_SS from PLL3
27M_SS from PLL3
0
0
1
0
0
0
1
1
0
1
0
0
1.5
2
0
1
0
1
0
1
1
0
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0
1
1
1
N/A
N/A
1
0
0
0
N/A
N/A
1
0
0
1
N/A
N/A
1
0
1
0
N/A
N/A
1
0
1
1
N/A
N/A
1
1
0
0
N/A
N/A
1
1
0
1
N/A
N/A
control of the N register, the M value is fixed and
documented in Table 1, Frequency Select Table.
Dial-A-Frequency® (CPU and SRC Clocks)
In this mode, the user writes the desired N and M values into
the DAF I2C registers. The user cannot change only the M
value and must change both the M and the N values at the
same time, if they require a change to the M value. The user
may change only the N value.
This feature allows the user to over-clock their system by
slowly stepping up the CPU or SRC frequency. When the
programmable output frequency feature is enabled, the CPU
and SRC frequencies are determined by the following
equation:
Associated Register Bits
Fcpu = G * N/M or Fcpu=G2 * N, where G2 = G / M.
• CPU_DAF Enable – This bit enables CPU DAF mode. By
default, it is not set. When set, the operating frequency is
determined by the values entered into the CPU_DAF_N
register. Note that the CPU_DAF_N and M register must
contain valid values before CPU_DAF is set. Default = 0,
(No DAF).
• “N” and “M” are the values programmed in Programmable
Frequency Select N-Value Register and M-Value Register,
respectively.
• “G” stands for the PLL Gear Constant, which is determined
by the programmed value of FS[E:A]. See Table 1,
Frequency Select Table for the Gear Constant for each
Frequency selection. The PCI Express only allows user
• CPU_DAF_N – There are nine bits (for 512 values) to
linearly change the CPU frequency (limited by VCO range).
...................... DOC #: SP-AP-0063 (Rev. AA) Page 16 of 31
SL28541
Default = 0, (0000). The allowable values for N are detailed
PD_RESTORE
in Table 1, Frequency Select Table.
If a ‘0’ is set for Byte 0 bit 0 then, upon assertion of PD# LOW,
the SL28541 initiates a full reset. The result of this is that the
clock chip emulates a cold power on start and goes to the
“Latches Open” state. If the PD_RESTORE bit is set to a ‘1’
then the configuration is stored upon PD# asserted LOW. Note
that if the iAMT bit, Byte 0 bit 3, is set to a ‘1’ then the
PD_RESTORE bit must be ignored. In other words, in Intel
iAMT mode, PD# reset is not allowed.
• CPU DAF M – There are 7 bits (for 128 values) to linearly
change the CPU frequency (limited by VCO range). Default
= 0, the allowable values for M are detailed in Table 1,
Frequency Select Table
• SRC_DAF Enable – This bit enables SRC DAF mode. By
default, it is not set. When set, the operating frequency is
determined by the values entered into the SRC_DAF_N
register. Note that the SRC_DAF_N register must contain
valid values before SRC_DAF is set. Default = 0, (No DAF).
PD# (Power down) Clarification
The CKPWRGD/PD# pin is a dual-function pin. During initial
power up, the pin functions as CKPWRGD. Once CKPWRGD
has been sampled HIGH by the clock chip, the pin assumes
PD# functionality. The PD# pin is an asynchronous active
LOW input used to shut off all clocks cleanly before shutting
off power to the device. This signal is synchronized internally
to the device before powering down the clock synthesizer. PD#
is also an asynchronous input for powering up the system.
When PD# is asserted LOW, clocks are driven to a LOW value
and held before turning off the VCOs and the crystal oscillator.
• SRC_DAF_N – There are nine bits (for 512 values) to
linearly change the CPU frequency (limited by VCO range).
Default = 0, (0000). The allowable values for N are detailed
in Table 1, Frequency Select Table.
Smooth Switching
The device contains one smooth switch circuit that is shared
by the CPU PLL and SRC PLL. The smooth switch circuit
ensures that when the output frequency changes by
overclocking, the transition from the old frequency to the new
frequency is a slow, smooth transition containing no glitches.
The rate of change of output frequency when using the smooth
switch circuit is less than 1 MHz/0.667 s. The frequency
overshoot and undershoot is less than 2%.
PD# (Power down) Assertion
When PD is sampled HIGH by two consecutive rising edges
of CPUC, all single-ended outputs will be held LOW on their
next HIGH-to-LOW transition and differential clocks must held
LOW. When PD mode is desired as the initial power on state,
PD must be asserted HIGH in less than 10 s after asserting
CKPWRGD.
The Smooth Switch circuit assigns auto or manual. In Auto
mode, clock generator assigns smooth switch automatically
when the PLL does overclocking. For manual mode, assign
the smooth switch circuit to PLL via Smbus. By default the
smooth switch circuit is set to auto mode. PLL can be
over-clocked when it does not have control of the smooth
switch circuit but it is not guaranteed to transition to the new
frequency without large frequency glitches.
PD# Deassertion
The power up latency is less than 1.8 ms. This is the time from
the deassertion of the PD# pin or the ramping of the power
supply until the time that stable clocks are generated from the
clock chip. All differential outputs stopped in a three-state
condition, resulting from power down are driven high in less
than 300 s of PD# deassertion to a voltage greater than
200 mV. After the clock chip’s internal PLL is powered up and
locked, all outputs are enabled within a few clock cycles of
each clock. Figure 2 is an example showing the relationship of
clocks coming up.
Do not enable over-clocking and change the N values of both
PLLs in the same SMBUS block write and use smooth switch
mechanism on spread spectrum on/off.
PD#
CPUT, 133MHz
CPUC, 133MHz
SRCT 100MHz
SRCC 100MHz
USB, 48MHz
DOT96T
DOT96C
PCI, 33 MHz
REF
Figure 1. Power down Assertion Timing Waveform
...................... DOC #: SP-AP-0063 (Rev. AA) Page 17 of 31
SL28541
Ts table
<1.8 ms
PD#
CP UT , 133MHz
CP UC, 133MHz
S RCT 100MHz
S RCC 100MHz
US B , 48MHz
DOT 96T
DOT 96C
P CI, 33MHz
REF
Tdriv e_PW R D N #
<300 s , >200m V
Figure 2. Power down Deassertion Timing Waveform
FS_A, FS_B,FS_C,FS_D
CKPWRGD
PWRGD_VRM
0.2-0.3 ms
Delay
Wait for
VTT_PWRGD#
Device is not affected,
VTT_PWRGD# is ignored
Sample Sels
State 2
VDD Clock Gen
Clock State
State 0
Off
State 1
State 3
On
Clock Outputs
Clock VCO
On
Off
Figure 3. CKPWRGD Timing Diagram
CPU_STP# Assertion
The CPU_STP# signal is an active LOW input used for
synchronous stopping and starting the CPU output clocks
while the rest of the clock generator continues to function.
When the CPU_STP# pin is asserted, all CPU outputs that are
set with the SMBus configuration to be stoppable are stopped
within two to six CPU clock periods after sampled by two rising
edges of the internal CPUC clock. The final states of the
stopped CPU signals are CPUT = HIGH and CPUC = LOW.
CPU_STP# Deassertion
The deassertion of the CPU_STP# signal causes all stopped
CPU outputs to resume normal operation in a synchronous
manner. No short or stretched clock pulses are produced when
the clock resumes. The maximum latency from the
deassertion to active outputs is no more than two CPU clock
cycles.
CPU_STP#
CPUT
CPUC
Figure 4. CPU_STP# Assertion Waveform
...................... DOC #: SP-AP-0063 (Rev. AA) Page 18 of 31
SL28541
CPU_STP#
CPUT
CPUC
CPUT Internal
CPUC Internal
Tdrive_CPU_STP#,10 ns>200 mV
Figure 5. CPU_STP# Deassertion Waveform
PCI_STP# Assertion
The PCI_STP# signal is an active LOW input used for
synchronously stopping and starting the PCI outputs while the
rest of the clock generator continues to function. The set-up
time for capturing PCI_STP# going LOW is 10 ns (tSU). (See
Figure 6.) The PCIF clocks are affected by this pin if their
corresponding control bit in the SMBus register is set to allow
them to be free running.
Tsu
PCI_STP#
PCI_F
PCI
SRC 100MHz
Figure 6. PCI_STP# Assertion Waveform
PCI_STP# Deassertion
.
The deassertion of the PCI_STP# signal causes all PCI and
stoppable PCIF clocks to resume running in a synchronous
manner within two PCI clock periods, after PCI_STP# transi-
tions to a HIGH level.
Tdrive_SRC
Tsu
PCI_STP#
PCI_F
PCI
SRC 100MHz
Figure 7. PCI_STP# Deassertion Waveform
.
.
...................... DOC #: SP-AP-0063 (Rev. AA) Page 19 of 31
SL28541
Figure 8. Clock Generator Power up/Run State Diagram
C l o c k O f f t o M 1
3.3V
Vcc
2.0V
T_delay t
FSC
FSB
FSA
CPU_STP#
PCI_STP#
CKPWRGD/PD#
CK505 SMBUS
CK505 State
Off
Latches Open
M1
Off
Off
BSEL[0..2]
CK505 Core Logic
PLL1
Locked
CPU1
PLL2 & PLL3
All Other Clocks
REF Oscillator
T_delay2
T_delay3
Figure 9. BSEL Serial Latching
...................... DOC #: SP-AP-0063 (Rev. AA) Page 20 of 31
SL28541
Absolute Maximum Conditions
Parameter
VDD_3.3V
VDD_IO
VIN
Description
Supply Voltage
Condition
Min.
Max. Unit
Functional
–
4.6
3.465
4.6
V
V
IO Supply Voltage
Input Voltage
Functional
Relative to VSS
Non-functional
Functional
–0.5
–65
0
VDC
°C
°C
TS
Temperature, Storage
150
85
TA
Commercial Temperature,
Operating Ambient
Industrial Temperature,
Operating Ambient
-40
+85
°C
TJ
Temperature, Junction
Functional
–
–
–
150
20
°C
°C/W
ØJC
ØJA
Dissipation, Junction to Case JEDEC (JESD 51)
Dissipation, Junction to Ambient JEDEC (JESD 51)
60
°C/
W
ESDHBM
ESD Protection (Human Body JEDEC (JESD 22-A114)
Model)
2000
–
V
UL-94
MSL
Flammability Rating
UL (CLASS)
V–0
Moisture Sensitivity Level
1
Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
DC Electrical Specifications
Parameter
VDD core
Description
Condition
Min.
Max.
3.465
VDD + 0.3
0.8
Unit
3.3V Operating Voltage
3.3V Input High Voltage (SE)
3.3V Input Low Voltage (SE)
Input High Voltage
3.3 ± 5%
3.135
V
V
VIH
2.0
VIL
VSS – 0.3
V
VIHI2C
VILI2C
VIH_FS
VIL_FS
VIHFS_C_TEST
SDATA, SCLK
SDATA, SCLK
2.2
–
V
Input Low Voltage
–
1.0
V
FS_[A,B] Input High Voltage
FS_[A,B] Input Low Voltage
FS_C Input High Voltage
0.7
1.5
V
VSS – 0.3
0.35
VDD + 0.3
1.5
V
2
V
VIMFS_C_NORMAL FS_C Input Middle Voltage
VILFS_C_NORMAL FS_C Input Low Voltage
0.7
V
VSS – 0.3
0.35
5
V
IIH
Input High Leakage Current
Input Low Leakage Current
Except internal pull-down resistors, 0 < VIN < VDD
Except internal pull-up resistors, 0 < VIN < VDD
–
–5
2.4
–
A
A
V
IIL
–
VOH
VOL
VDD IO
IOZ
3.3V Output High Voltage (SE) IOH = –1 mA
3.3V Output Low Voltage (SE) IOL = 1 mA
Low Voltage IO Supply Voltage
–
0.4
V
1
3.465
10
V
High-impedance Output
Current
–10
A
CIN
Input Pin Capacitance
Output Pin Capacitance
Pin Inductance
1.5
5
6
pF
pF
nH
V
COUT
LIN
–
0.7VDD
0
7
VXIH
Xin High Voltage
VDD
0.3VDD
1
VXIL
Xin Low Voltage
V
IDDPWRDWN
IDD
Power Down Current
Dynamic Supply Current
mA
mA
–
250
...................... DOC #: SP-AP-0063 (Rev. AA) Page 21 of 31
SL28541
AC Electrical Specifications
Parameter
Crystal
Description
Condition
Min.
Max.
Unit
LACC
Long-term Accuracy
–
300
ppm
Clock Input
TDC
CLKIN Duty Cycle
Measured at VDD/2
47
0.5
–
53
4.0
%
V/ns
ps
TR/TF
CLKIN Rise and Fall Times
CLKIN Cycle to Cycle Jitter
CLKIN Long Term Jitter
Input Low Voltage
Measured between 0.2VDD and 0.8VDD
Measured at VDD/2
TCCJ
250
TLTJ
Measured at VDD/2
–
350
ps
VIL
XIN / CLKIN pin
–
0.8
V
VIH
Input High Voltage
XIN / CLKIN pin
2
VDD+0.3
20
V
IIL
Input LowCurrent
XIN / CLKIN pin, 0 < VIN <0.8
XIN / CLKIN pin, VIN = VDD
–
uA
uA
IIH
Input HighCurrent
–
35
CPU at 0.7V
TDC
45
55
CPU Clock Duty Cycle
Measured at 0V differential at 0.1s
Measured at 0V differential at 0.1s
Measured at 0V differential at 0.1s
Measured at 0V differential at 0.1s
Measured at 0V differential at 0.1s
Measured at 0V differential at 0.1s
Measured at 0V differential at 0.1s
Measured at 0V differential at 0.1s
Measured at 0V differential at 0.1s
Measured at 0V differential at 0.1s
Measured at 0V differential at 0.1s
Measured at 0V differential at 0.1s
Measured at 0V differential at 0.1s
Measured at 0V differential at 0.1s
Measured at 0V differential at 0.1s
Measured at 0V differential at 1 clock
Measured at 0V differential at 1 clock
Measured at 0V differential at 1 clock
Measured at 0V differential at 1 clock
Measured at 0V differential at 1 clock
Measured at 0V differential at 1 clock
Measured at 0V differential at 1 clock
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
9.99900
7.49925
5.99940
4.99950
3.74963
2.99970
2.49975
10.00100
7.50075
6.00060
5.00050
3.75038
3.00030
2.50025
TPERIOD
TPERIOD
TPERIOD
TPERIOD
TPERIOD
TPERIOD
TPERIOD
TPERIODSS
TPERIODSS
TPERIODSS
TPERIODSS
TPERIODSS
TPERIODSS
TPERIODSS
TPERIODAbs
TPERIODAbs
TPERIODAbs
TPERIODAbs
TPERIODAbs
TPERIODAbs
TPERIODAbs
100 MHz CPU Clock Period
133 MHz CPU Clock Period
166 MHz CPU Clock Period
200 MHz CPU Clock Period
266 MHz CPU Clock Period
333 MHz CPU Clock Period
400 MHz CPU Clock Period
10.02406 10.02607
100 MHz CPU Clock Period, SSC
133 MHz CPU Clock Period, SSC
166 MHz CPU Clock Period, SSC
200 MHz CPU Clock Period, SSC
266 MHz CPU Clock Period, SSC
333 MHz CPU Clock Period, SSC
400 MHz CPU Clock Period, SSC
100 MHz CPU Clock Absolute period
133 MHz CPU Clock Absolute period
166 MHz CPU Clock Absolute period
200 MHz CPU Clock Absolute period
266 MHz CPU Clock Absolute period
333 MHz CPU Clock Absolute period
400 MHz CPU Clock Absolute period
7.51804
6.01444
5.01203
3.75902
3.00722
2.50601
9.91400
7.41425
5.91440
4.91450
3.66463
2.91470
2.41475
9.91406
7.51955
6.01564
5.01303
3.75978
3.00782
2.50652
10.0860
7.58575
6.08560
5.08550
3.83538
3.08530
2.58525
10.1362
TPERIODSSAbs 100 MHz CPU Clock Absolute period, Measured at 0V differential at 1 clock
SSC
7.41430
5.91444
4.91453
3.66465
2.91472
7.62340
6.11572
5.11060
3.85420
3.10036
TPERIODSSAbs 133 MHz CPU Clock Absolute period, Measured at 0V differential at 1 clock
SSC
ns
ns
ns
ns
ns
TPERIODSSAbs 166 MHz CPU Clock Absolute period, Measured at 0V differential at 1 clock
SSC
TPERIODSSAbs 200 MHz CPU Clock Absolute period, Measured at 0V differential at 1 clock
SSC
TPERIODSSAbs 266 MHz CPU Clock Absolute period, Measured at 0V differential at 1 clock
SSC
TPERIODSSAbs 333 MHz CPU Clock Absolute period, Measured at 0V differential at 1 clock
SSC
...................... DOC #: SP-AP-0063 (Rev. AA) Page 22 of 31
SL28541
AC Electrical Specifications (continued)
Parameter
Description
Condition
Min.
Max.
Unit
2.41477
2.59780
TPERIODSSAbs 400 MHz CPU Clock Absolute period, Measured at 0V differential at 1 clock
SSC
ns
TCCJ
CPU Cycle to Cycle Jitter
CPU2_ITP Cycle to Cycle Jitter
Long-term Accuracy
Measured at 0V differential
–
–
85
125
100
100
150
8
ps
ps
TCCJ2
Measured at 0V differential
LACC
Measured at 0V differential
–
ppm
ps
TSKEW
TSKEW2
TR / TF
TRFM
CPU0 to CPU1 Clock Skew
CPU2_ITP to CPU0 Clock Skew
CPU Rising/Falling Slew rate
Rise/Fall Matching
Measured at 0V differential
–
Measured at 0V differential
–
ps
Measured differentially from ±150 mV
Measured single-endedly from ±75 mV
2.5
–
V/ns
%
20
VHIGH
Voltage High
1.15
–
V
VLOW
Voltage Low
–0.3
300
V
VOX
Crossing Point Voltage at 0.7V Swing
550
mV
SRC at 0.7V
TDC
SRC Duty Cycle
Measured at 0V differential
45
55
%
ns
ns
ns
ns
ns
9.99900
10.0010
TPERIOD
TPERIODSS
TPERIODAbs
100 MHz SRC Period
Measured at 0V differential at 0.1s
Measured at 0V differential at 0.1s
Measured at 0V differential at 1 clock
Measured at 0V differential at 1 clock
10.02406 10.02607
100 MHz SRC Period, SSC
100 MHz SRC Absolute Period
9.87400
9.87406
–
10.1260
10.1762
3.0
TPERIODSSAbs 100 MHz SRC Absolute Period, SSC
TSKEW(window) Any SRC Clock Skew from the earliest Measured at 0V differential
bank to the latest bank
TCCJ
SRC Cycle to Cycle Jitter
SRC Long Term Accuracy
SRC Rising/Falling Slew Rate
Rise/Fall Matching
Measured at 0V differential
–
–
125
100
8
ps
ppm
V/ns
%
LACC
Measured at 0V differential
TR / TF
TRFM
Measured differentially from ±150 mV
Measured single-endedly from ±75 mV
2.5
–
20
VHIGH
VLOW
Voltage High
1.15
–
V
Voltage Low
–0.3
300
V
VOX
Crossing Point Voltage at 0.7V Swing
550
mV
DOT96 at 0.7V
TDC
DOT96 Duty Cycle
Measured at 0V differential
45
55
10.4177
10.6677
250
100
8
%
ns
10.4156
TPERIOD
TPERIODAbs
TCCJ
DOT96 Period
Measured at 0V differential at 0.1s
Measured at 0V differential at 0.1s
Measured at 0V differential at 1 clock
Measured at 0V differential at 1 clock
Measured differentially from ±150 mV
Measured single-endedly from ±75 mV
10.1656
DOT96 Absolute Period
DOT96 Cycle to Cycle Jitter
DOT96 Long Term Accuracy
DOT96 Rising/Falling Slew Rate
Rise/Fall Matching
ns
–
–
ps
LACC
ppm
V/ns
%
TR / TF
TRFM
2.5
–
20
VHIGH
VLOW
Voltage High
1.15
–
V
Voltage Low
–0.3
300
V
VOX
Crossing Point Voltage at 0.7V Swing
550
mV
LCD_100_SSC at 0.7V
TDC
LCD_100 Duty Cycle
100 MHz LCD_100 Period
Measured at 0V differential
45
55
%
TPERIOD
TPERIODSS
TPERIODAbs
Measured at 0V differential at 0.1s
9.99900
10.0010
ns
100 MHz LCD_100 Period, SSC -0.5% Measured at 0V differential at 0.1s
10.02406 10.02607 ns
9.74900 10.25100 ns
100 MHz LCD_100 Absolute Period
Measured at 0V differential at 1 clock
Measured at 0V differential at 1 clock
TPERIODSSAbs 100 MHz LCD_100 Absolute Period,
SSC
9.74906
10.3012
ns
...................... DOC #: SP-AP-0063 (Rev. AA) Page 23 of 31
SL28541
AC Electrical Specifications (continued)
Parameter
TCCJ
Description
LCD_100 Cycle to Cycle Jitter
LCD_100 Long Term Accuracy
LCD_100 Rising/Falling Slew Rate
Rise/Fall Matching
Condition
Min.
–
Max.
250
100
8
Unit
ps
Measured at 0V differential
LACC
TR / TF
TRFM
VHIGH
VLOW
VOX
Measured at 0V differential
–
ppm
V/ns
%
Measured differentially from ±150 mV
Measured single-endedly from ±75 mV
2.5
–
20
Voltage High
1.15
–
V
Voltage Low
–0.3
300
V
Crossing Point Voltage at 0.7V Swing
550
mV
PCI/PCIF at 3.3V
TDC
PCI Duty Cycle
Measurement at 1.5V
Measurement at 1.5V
Measurement at 1.5V
Measurement at 1.5V
Measurement at 1.5V
45
55
%
ns
ns
ns
ns
29.99700 30.00300
30.08421 30.23459
29.49700 30.50300
29.56617 30.58421
TPERIOD
TPERIODSS
TPERIODAbs
Spread Disabled PCIF/PCI Period
Spread Enabled PCIF/PCI Period
Spread Disabled PCIF/PCI Period
TPERIODSSAbs Spread Enabled PCIF/PCI Period
THIGH
TLOW
THIGH
Spread Enabled PCIF and PCI high time Measurement at 2V
Spread Enabled PCIF and PCI low time Measurement at 0.8V
12.27095 16.27995 ns
11.87095 16.07995 ns
12.27365 16.27665 ns
Spread Disabled PCIF and PCI high
time
Measurement at 2.V
TLOW
Spread Disabled PCIF and PCI low time Measurement at 0.8V
11.87365 16.07665 ns
TR / TF
TSKEW
TCCJ
PCIF/PCI Rising/Falling Slew Rate
Measured between 0.8V and 2.0V
1.0
–
4.0
1000
500
V/ns
ps
Any PCI clock to Any PCI clock Skew Measurement at 1.5V
PCIF and PCI Cycle to Cycle Jitter
PCIF/PCI Long Term Accuracy
Measurement at 1.5V
Measurement at 1.5V
–
ps
LACC
–
100
ppm
48_M at 3.3V
TDC
Duty Cycle
Measurement at 1.5V
Measurement at 1.5V
Measurement at 1.5V
Measurement at 2V
45
55
%
ns
20.83125 20.83542
20.48125 21.18542
8.216563 11.15198
7.816563 10.95198
TPERIOD
TPERIODAbs
THIGH
Period
Absolute Period
48_M High time
ns
ns
TLOW
48_M Low time
Measurement at 0.8V
Measured between 0.8V and 2.0V
Measurement at 1.5V
Measurement at 1.5V
ns
TR / TF
TCCJ
Rising and Falling Edge Rate
Cycle to Cycle Jitter
48M Long Term Accuracy
1.0
–
2.0
350
100
V/ns
ps
LACC
–
ppm
27M_NSS/27M_SS at 3.3V
TDC
Duty Cycle
Measurement at 1.5V
45
55
%
TPERIOD
Spread Disabled 27M Period
Spread Enabled 27M Period
Rising and Falling Edge Rate
Cycle to Cycle Jitter
Measurement at 1.5V
37.03594 37.03813 ns
37.01299 37.13172 ns
Measurement at 1.5V
TR / TF
TCCJ
Measured between 0.8V and 2.0V
Measurement at 1.5V
1.0
–
4.0
250
50
V/ns
ps
LACC
27_M Long Term Accuracy
Measured at crossing point VOX
–
ppm
REF
TDC
REF Duty Cycle
REF Period
Measurement at 1.5V
Measurement at 1.5V
Measurement at 1.5V
Measurement at 2V
Measurement at 0.8V
45
55
%
ns
ns
ns
ns
69.82033 69.86224
68.83429 70.84826
29.97543 38.46654
29.57543 38.26654
TPERIOD
TPERIODAbs
THIGH
TLOW
REF Absolute Period
REF High time
REF Low time
...................... DOC #: SP-AP-0063 (Rev. AA) Page 24 of 31
SL28541
AC Electrical Specifications (continued)
Parameter
TR / TF
TSKEW
TCCJ
Description
REF Rising and Falling Edge Rate
REF Clock to REF Clock
REF Cycle to Cycle Jitter
Long Term Accuracy
Condition
Measured between 0.8V and 2.0V
Measurement at 1.5V
Min.
1.0
–
Max.
4.0
Unit
V/ns
ps
500
1000
100
Measurement at 1.5V
–
ps
LACC
Measurement at 1.5V
–
ppm
ENABLE/DISABLE and SET-UP
TSTABLE Clock Stabilization from Power-up
TSS Stopclock Set-up Time
–
1.8
–
ms
ns
10.0
Test and Measurement Set-up
For PCI Single-ended Signals and Reference
The following diagram shows the test load configurations for
the single-ended PCI, USB, and REF output signals.
Measurement
Point
22
L1
L2
50
4 pF
4 pF
L1 = 0.5", L2 = 8"
22
PCI/USB
Measurement
Point
50
L2
L1
Figure 10. Single-ended PCI and USB Double Load Configuration
Measurement
15
L2
L1
Point
50
4 pF
Measurement
Point
4 pF
15
15
L1
L1
L2
REF
50
Measurement
Point
4 pF
L2
50
L1 = 0.5", L2 = 8"
Figure 11. Single-ended REF Triple Load Configuration
Figure 12. Single-ended Output Signals (for AC Parameters Measurement)
...................... DOC #: SP-AP-0063 (Rev. AA) Page 25 of 31
SL28541
For CPU, SRC, and DOT96 Signals and Reference
This diagram shows the test load configuration for the differential CPU and SRC outputs
M e asu rem e nt P oin t
L
O U T +
5 0 O h m
2p F
L= 8"
M e asure m e nt P o int
L
O U T -
5 0 O h m
2 p F
Figure 13. 0.7V Differential Load Configuration
Clock Period (Differential)
Positive Duty Cycle (Differential)
Negative Duty Cycle (Differential)
0.0V
0.0V
Clock-Clock#
Rise
Edge
Rate
Fall
Edge
Rate
VIH = +150mV
VIH = +150mV
0.0V
0.0V
VIL = -150mV
VIL = -150mV
Clock-Clock#
Figure 14. Differential Measurement for Differential Output Signals (for AC Parameters Measurement)
...................... DOC #: SP-AP-0063 (Rev. AA) Page 26 of 31
SL28541
VMAX = 1.15V
VMAX = 1.15V
CLK#
VcrossMAX = 550mV
VcrossMIN = 300mV
VcrossMAX = 550mV
VcrossMIN = 300mV
CLK
VMIN = 0.30V
VMIN = 0.30V
CLK#
Vcross delta = 140mV
Vcross delta = 140mV
CLK
CLK#
CLK#
Vcross median +75mV
Vcross median
Vcross median
Vcross median -75mV
CLK
CLK
Figure 15. Single-ended Measurement for Differential Output Signals (for AC Parameters Measurement)
Ordering Information
Part Number
Package Type
Product Flow
Lead-free
SL28541BZC
SL28541BZCT
SL28541BQCR
SL28541BQCRT
SL28541BZI
64-pin TSSOP
Commercial, 0 to 85C
Commercial, 0 to 85C
Commercial, 0 to 85C
Commercial, 0 to 85C
Industrial, -40 to 85C
Industrial, -40 to 85C
Industrial, -40 to 85C
Industrial, -40 to 85C
64-pin TSSOP–Tape and Reel
64-pin QFN
64-pin QFN–Tape and Reel
64-pin TSSOP
SL28541BZIT
SL28541BQIR
SL28541BQIRT
64-pin TSSOP–Tape and Reel
64-pin QFN
64-pin QFN–Tape and Reel
This device is Pb-free, Halogen-free and RoHS compliant.
...................... DOC #: SP-AP-0063 (Rev. AA) Page 27 of 31
SL28541
Package Diagrams
64-Lead Thin Shrunk Small Outline Package (6 mm x 17 mm)
...................... DOC #: SP-AP-0063 (Rev. AA) Page 28 of 31
SL28541
Package Diagrams (continued)
...................... DOC #: SP-AP-0063 (Rev. AA) Page 29 of 31
SL28541
Document History Page
Document Title: SL28541 Clock Generator for Intel®Mobile Chipset
DOC #: SP-AP-0063 (Rev. AA)
Issue
Date
Orig. of
Change
REV. ECR#
Description of Change
1.0
1.1
1.2
1.3
1/01/07
6/15/07
9/18/07
10/31/07
JMA
BEN
BEN
BEN
New data sheet
Change ordering number to SL28541BQC
VDDIO range change from 1.25V to 1.05V
1. Added 64 TSSOP pin definitions
2. Added 64 TSSOP package dimension
3. Byte1[2] is changed from 0 to 1 and Byte1[1] is changed from 1 to 0 by power up
default
4. Changed Byte 13 bit 5 spread percentage from -1% to -0.45%
5. Updated revision ID
1.4
1.5
1.6
12/15/07
1/23/08
7/8/08
SLI
JMA
JMA
1. Updated Pin Definition table
2. Updated Table 7. PLL3/SE Configuration Table
1. Changed Byte 13 Bit 5 to replace 0.45% spread to 1% spread.
2. Changed 27MHz period spec to be reflect down spread.
3. Changed 27MHz CCJ spec from 200ps to 250ps.
1. Changed maximum operating temperature range from 85C to 70C
2. Added note on Pb-free, Halogen-free, and RoHS compliant
3. Added note on extended temperature
4. Added Mitsui package
1.7
1.8
2/23/09
3/31/09
JMA
JMA
1. Added 64-TSSOP package on page 1.
2. Change operating temperature back to 85C
1. Updated QFN packge information
2. Udpated Slew rate measurement for 27MHz clocks
3. Updated Tperiod for CPU clock at 100MHz
4. Corrected Byte 7 Revision ID
5. Corrected Byte 8 Device ID
6. Added PWRDWN IDD Spec
1.9
2.0
4/27/09
9/10/09
JMA
1. Corrected Reserved bit in Byte18
2. Corrected Reserved bit in Byte 20
3. Corrected wording for PD to PWRDWN
4. Added “F” in pF in Figure 2
5. Removed Cypress package marking
JMA
JMA
1. Updated QFN package information
AA
1453 04/09’/10
1. Added CLKIN feature.
2. Updated Absolut spec
3. Move location of Output Drive Satus & PLL3/SE Configue tables
4. Combined commercial and industrial temperature grade
5. Updated VDD_IO voltage
...................... DOC #: SP-AP-0063 (Rev. AA) Page 30 of 31
SL28541
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Sil-
icon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the
use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or
parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, repre-
sentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-
quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per-
sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized appli-
cation, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
...................... DOC #: SP-AP-0063 (Rev. AA) Page 31 of 31
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