SL28545ALC-4_技术文档

SL28545-4

Clock Generator for next Gen Intel^®Mobile Platform

Features

• Programmable CLKREQ#s control individual SRC

clock

• Compliant to Intel^®CK505

• Integratedvoltageregulatorandinetrnalseriesresistor

for differential clocks

• 33-MHz PCI clocks

• Buffered Reference Clock 14.318 MHz

• Low-voltage frequency select inputs

• I²C support with readback capabilities

• 8-step drive strength control for single-eneded clocks

• Low power differential push-pull CPU clock pairs

• 100-MHz low power differential push-pull SRC clocks

• 96-MHz low power differential push-pull DOT clock

• 27-MHz Spread and Non-spread video clocks

• 48-MHz USB clock

• Support spread spectrum modulation for maximum

electromagnetic interference (EMI) reduction

• 3.3V power supply

• 68-pin QFN 8x8 package

Table 1. Output Confguration Table

CPU

SRC

PCI

x7

REF

x 1

DOT96

x 1

USB_48M

x 1

LCD

x1

27M

x2

x2/x3

x8/10

Block Diagram

Pin Configuration

VDD_REF

Xin

Xout

14.318MHz

Crystal

REF0

PLL Reference

VDD_CPU

CPU_STP#

PCI_STP#

CLKREQ#

FS[C:A]

CPUT[1:0]

CPUC[1:0]

CPU

SRC

VDD_CPU

CPU PLL1

SS

CPUT2_ITP/SRC10T

CPUC2_ITP/SRC10C

68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52

ITP_EN

PCIF1

CKPWRGD/PD#

VDD_48

48M/FSA

VSS_48

DOT96T / 27M_NSS

1

2

3

4

5

6

51 XIN

50 XOUT

49 VDD_REF

48 SDATA

47 SCLK

CKPWRGD/PD#

FCTSEL

VDD_SRC

PCI

SRCT [8:1]

SRCC [8:1]

46 VSS_CPU

VDD_PCI

DOT96C/ 27M_SS

FSB/TEST_MODE

*CLKREQ#_1

7

45 CPUT0

44 CPUC0

43 VDD_CPU

42 CPUT1

PCI[5:1], PCIF[1:0]

8

9

CY28545-4

VDD_SRC

PLL3

SS

LCD_100T/SRC0T

LCD_100C/SRC0C

SRCT_0 / LCD100MT 10

LCD_100

27M_SS

SRCC_0 / LCD100MC 11

VDD_SRC 12

SRCT_1 13

41 CPUC1

40 CLKREQ#7*

39 VSSA

SRCC_1 14

38 VDDA

SRCT_2 15

SRCC_2 16

VDD_SRC 17

37 CPUT2_ITP / SRCT_10

36 CPUC2_ITP / SRCC_10

35 VDD_SRC

DOT96T/27M_NSS

DOT96C/27M_SS

DOT96

PLL2

Fixed

27M_NSS

18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

VDD_48

USB_48

I2C

Logic

SDATA

SCLK

* internal Pull-up

** internal Pull-down

Confidential

Tel:(408) 855-0555 Fax:(408) 855-0550

Rev 1.1, March 10, 2008

2200 Laurelwood Road, Santa Clara, CA 95054

Page 1 of 29

www.SpectraLinear.com

SL28545-4

Pin Description

Pin No.

Name

Type

Description

1

2

PCIF1

O, SE 33-MHz free running clock output

CKPWRGD/PD#

I

3.3V LVTTL input. This pin is a level sensitive strobe. When asserted, it latches

data on the FSA, FSB, FSC, FCT_SEL and ITP_SEL pins. After assertion, it

becomes a real time input for controlling power down.

3

4

VDD_48

PWR 3.3V power supply for outputs.

48M/FSA

I/O

Fixed 48-MHz clock output/3.3V-tolerant input for CPU frequency selection

Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.

5

VSS_48

GND Ground for outputs.

6, 7

DOT96T/ 27M_NSS

DOT96C/ 27M_SS

O, DIF Fixed 96-MHz clock output or 27 Mhz Spread and Non-spread output Selected

via FCTSEL1 at CKPWRGD assertion.

8

FSB/TEST_MODE

I

3.3V-tolerant input for CPU frequency selection. Selects Ref/N or Tri-state when

in test mode

0 = Tri-state, 1 = Ref/N

Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.

9, 59, 20, 60, CLKREQ#[1, 3, 4, 5, 6, I, PU 3.3V LVTTL input for enabling assigned SRC clock (active LOW).

25, 40, 34

7, 8]

Internal pull-up resistor of 100K to 3.3V, use 10K resistor to pull it low externally

if needed

10, 11

SRC[T/C]0/

LCD100M[T/C]

O,DIF 100-MHz differential serial reference clock output/Differential LCD 100-MHz SS

clock for flat-panel display

Selected via FCT_SEL at CKPWRGD assertion.

12, 17, 28, 35 VDD_SRC

PWR 3.3V power supply for outputs.

13, 14, 15,

16, 18, 19,

21, 22, 23,

24, 26, 27,

29, 30, 32, 33

SRCT/C[1:8]

O, DIF 100-MHz Differential serial reference clocks.

31

VSS_SRC

GND Ground for outputs.

36, 37

CPUT2_ITP/SRCT10, O, DIF Selectable differential CPU or SRC clock output.

CPUC2_ITP/SRCC10

ITP_SEL = 0 @ CKPWRGD assertion = SRC10

ITP_SEL = 1 @ CKPWRGD assertion = CPU2_ITP

38

VDDA

PWR 3.3V power supply for PLL.

GND Ground for PLL.

39

VSSA

41, 42

43

CPUC1, CPUT1

VDD_CPU

CPUC0, CPUT0

VSS_CPU

SCLK

O, DIF Differential CPU clock output to MCH

PWR 3.3V power supply for outputs.

O, DIF Differential CPU clock output

GND Ground for outputs.

44, 45

46

47

I

SMBus-compatible SCLOCK.

48

SDATA

I/O, OD SMBus-compatible SDATA.

PWR 3.3V power supply for outputs.

O, SE 14.318-MHz crystal output.

49

VDD_REF

XOUT

50

51

XIN

I

14.318-MHz crystal input.

52

VSS_REF

GPU_STP#

GND Ground for outputs.

53

I, PU 3.3V LVTTL input for enableing DOT96 and 27MHz (spread and non-spread)

clocks. Internal pull-up resistor of 100K to 3.3V, use 10K resistor to pull it low

externally if needed

0 = DOT96/27MHz disable, 1 = DOT96/27MHz enable

54

REF0/FSC_TESTSEL

I/O

Fixed 14.318 clock output / 3.3V-tolerant input for CPU frequency

selection/Selects test mode if pulled to V_{IMFS_C}when CKPWRGD is asserted

High.

Refer to DC Electrical Specifications table for V_{ILFS_C},V_{IMFS_C},V_{IHFS_C}specifi-

cations.

Confidential

Rev 1.1,March 10, 2008

Page 2 of 29

SL28545-4

Pin Description (continued)

Pin No.

Name

CPU_STP#

Type

Description

55

56

I

3.3V LVTTL input for CPU_STP# active LOW

During direct clock off to M1 mode transition, a serial load of BSEL data is driven

on this pin and sampled on the rising edge of PCI_STP#. See Figure 14.for more

information.

PCI_STP#

I

3.3V LVTTL input for PCI_STP# active LOW

During direct clock off to M1 mode transition, a serial load of BSEL data is driven

on CPU_STP# and sampled on the rising edge of this pin. See Figure 14. for more

information.

57, 58, 63, 64 PCI[1,2,3,4]

O, SE 33-MHz clock output

PWR 3.3V power supply for outputs.

GND Ground for outputs.

61, 67

62, 66

65

VDD_PCI

VSS_PCI

PCI5/FCT_SEL

I/O,SE, 33-MHz clock output/3.3V LVTTL input for selecting SRC[T/C]0 or

PD LCD_100M[T/C] on pin 10, 11 and selecting DOT96[T/C] or 27M Spread and

Non-spread on pin 6 and 7(sampled on CKPWRGD assertion).

Internal pull-down resistor of 100K to GND, use 10K resistor to pull it high exter-

nally if needed

Pin 6

Pin 7

Pin 10

Pin 11

FCT_SEL

0 (default) DOT96T

1 27M_NSS

DOT96C

LCD_100_T LCD_100_C

27M_SS

SRCT0 SRCC0

68

PCIF0/ITP_SEL

I/O,SE, 33-MHz clock output / 3.3V LVTTL input for selecting SRC10 or CPU2_ITP on

PD pin 36,17. (sampled on CKPWRGD assertion).

Internal pull-down resistor of 100K to GND, use 10K resistor to pull it high exter-

nally if needed

0 = SRC10 (default), 1 = CPU2_ITP,

use of this interface is optional. Clock device register changes

Frequency Select Pins (FSA, FSB, and FSC)

are normally made upon system initialization, if any are

required. The interface cannot be used during system

operation for power management functions.

Host clock frequency selection is achieved by applying the

appropriate logic levels to FSA, FSB, FSC inputs prior to

CKPWRGD assertion (as seen by the clock synthesizer).

Upon CKPWRGD being sampled HIGH by the clock chip

(indicating processor CK_PWRGD voltage is stable), the clock

chip samples the FSA, FSB, and FSC input values. For all

logic levels of FSA, FSB, and FSC, CKPWRGD employs a

Data Protocol

The clock driver serial protocol accepts byte write, byte read,

block write, and block read operations from the controller. For

block write/read operation, the bytes must be accessed in

sequential order from lowest to highest byte (most significant

bit first) with the ability to stop after any complete byte has

been transferred. For byte write and byte read operations, the

system controller can access individually indexed bytes. The

offset of the indexed byte is encoded in the command code,

as described in Table 3.

one-shot functionality in that once

a valid HIGH on

CK_PWRGD has been sampled, all further CKPWRGD, FSA,

FSB, and FSC transitions will be ignored, except in test mode.

Serial Data Interface

To enhance the flexibility and function of the clock synthesizer,

a two-signal serial interface is provided. Through the Serial

Data Interface, various device functions, such as individual

clock output buffers, can be individually enabled or disabled.

The registers associated with the Serial Data Interface

initialize to their default setting upon power-up, and therefore

Table 2. Frequency Select Table FSA, FSB, and FSC

The block write and block read protocol is outlined in Table 4

while Table 5 outlines the corresponding byte write and byte

read protocol. The slave receiver address is 11010010 (D2h)

FSC FSB FSA

CPU

SRC

PCIF/PCI

27MHz

REF

DOT96

USB

0

1

0

1

0

1

0

1

0

1

266.66MHz

100.00 MHz 33.33 MHz 27.00 MHz

14.318 MHz

96.00 MHz 48.00 MHz

133.33 MHz 100.00 MHz 33.33 MHz 27.00 MHz

200.00 MHz 100.00 MHz 33.33 MHz 27.00 MHz

166.66 MHz 100.00 MHz 33.33 MHz 27.00 MHz

333.33 MHz 100.00 MHz 33.33 MHz 27.00 MHz

100.00 MHz 100.00 MHz 33.33 MHz 27.00 MHz

Confidential

Rev 1.1,March 10, 2008

Page 3 of 29

SL28545-4

Table 2. Frequency Select Table FSA, FSB, and FSC

FSC FSB FSA CPU SRC

400.00 MHz 100.00 MHz 33.33 MHz 27.00 MHz

Reserved Reserved Reserved Reserved

PCIF/PCI

27MHz

REF

DOT96

USB

1

0

1

14.318 MHz

Reserved

96.00 MHz 48.00 MHz

Reserved

Table 3. Command Code Definition

Bit

Description

7

0 = Block read or block write operation, 1 = Byte read or byte write operation

(6:0)

Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be

'0000000'

Table 4. Block Read and Block Write Protocol

Block Write Protocol

Block Read Protocol

Description

Bit

1

Description

Bit

1

Start

8:2

9

Slave address–7 bits

Write

8:2

9

Slave address–7 bits

Write

10

Acknowledge from slave

Command Code–8 bits

Acknowledge from slave

Byte Count–8 bits

10

Acknowledge from slave

Command Code–8 bits

Acknowledge from slave

Repeat start

18:11

19

18:11

19

27:20

28

20

Acknowledge from slave

Data byte 1–8 bits

27:21

28

Slave address–7 bits

Read = 1

36:29

37

Acknowledge from slave

Data byte 2–8 bits

29

Acknowledge from slave

Byte Count from slave–8 bits

Acknowledge

45:38

46

37:30

38

Acknowledge from slave

Data Byte/Slave Acknowledges

Data Byte N–8 bits

Acknowledge from slave

Stop

....

46:39

47

Data byte 1 from slave–8 bits

Acknowledge

....

55:48

56

Data byte 2 from slave–8 bits

Acknowledge

....

Data bytes from slave/Acknowledge

Data Byte N from slave–8 bits

NOT Acknowledge

Stop

....

Table 5. Byte Read and Byte Write Protocol

Byte Write Protocol

Byte Read Protocol

Description

Bit

1

Description

Bit

1

Start

8:2

9

Slave address–7 bits

Write

8:2

9

Slave address–7 bits

Write

10

Acknowledge from slave

Command Code–8 bits

Acknowledge from slave

Data byte–8 bits

10

Acknowledge from slave

Command Code–8 bits

Acknowledge from slave

Repeated start

18:11

19

18:11

19

27:20

28

20

Acknowledge from slave

Stop

27:21

28

Slave address–7 bits

Read

29

Acknowledge from slave

Confidential

Rev 1.1,March 10, 2008

Page 4 of 29

SL28545-4

Table 5. Byte Read and Byte Write Protocol

Byte Write Protocol

Byte Read Protocol

Description

Data from slave–8 bits

Bit

Description

Bit

37:30

38

NOT Acknowledge

Stop

39

Control Registers

Byte 0 Control Register 0

Bit

7

@Pup

Name

Description

0

RESEREVD

iAMT_EN

RESERVED

6

5

4

Set via SMBus or by combination of PD, CPU_STP and PCI_STP

0 = Legacy mode, 1 = iAMT enable

3

2

1

0

1

RESEREVD

PD_Restore

RESERVED

Save configuration in PD

0 = Configuration cleared, 1 = Configuration saved

Byte 1 Control Register 1

Bit

@Pup

Name

Description

7

1

SRC7_OE

SRC[T/C]7 Output Enable

0 = Disabled, 1 = Enabled

6

5

4

3

2

1

0

1

SRC6_OE

SRC5_OE

SRC4_OE

SRC3_OE

SRC2_OE

SRC1_OE

SRC[T/C]6 Output Enable

0 = Disabled, 1 = Enabled

SRC[T/C]5 Output Enable

0 = Disabled, 1 = Enabled

SRC[T/C]4 Output Enable

0 = Disabled, 1 = Enabled

SRC[T/C]3 Output Enable

0 = Disabled, 1 = Enabled

SRC[T/C]2 Output Enable

0 = Disabled, 1 = Enabled

SRC[T/C]1 Output Enable

0 = Disabled, 1 = Enabled

SRC0

/LCD_100M_OE

SRC[T/C]0/LCD_100M[T/C] Output Enable

0 = Disabled, 1 = Enabled

Byte 2 Control Register 2

Bit

@Pup

Name

Description

7

1

PCIF0_OE

PCIF0 Output Enable

0 = Disabled, 1 = Enabled

6

5

4

3

1

27M NSS/DOT_96_OE 27M Non-spread and DOT_96 MHz Output Enable

0 = Disable, 1 = Enabled

48M_OE

REF0_OE

RESERVED

48-MHz Output Enable

0 = Disabled, 1 = Enabled

REF0 Output Enable

0 = Disabled, 1 = Enabled

RESERVED

Confidential

Rev 1.1,March 10, 2008

Page 5 of 29

SL28545-4

Byte 2 Control Register 2 (continued)

Bit

@Pup

Name

Description

2

1

CPU1_OE

CPU[T/C]1 Output Enable

0 = Disabled, 1 = Enabled

1

0

1

0

CPU0_OE

CPU[T/C]0 Output Enable

0 = Disabled, 1 = Enabled

CPU, SRC, PCI, PCIF PLL1 (CPU PLL) Spread Spectrum Enable

Spread Enable

0 = Spread off, 1 = Spread on

Byte 3 Control Register 3

Bit

@Pup

Name

Description

7

1

PCI5_OE

PCI5 Output Enable

0 = Disabled, 1 = Enabled

6

5

4

3

1

PCI4_OE

PCI3_OE

PCI2_OE

PCI1_OE

PCI4 Output Enable

0 = Disabled, 1 = Enabled

PCI3 Output Enable

0 = Disabled, 1 = Enabled

PCI2 Output Enable

0 = Disabled, 1 = Enabled

PCI1 Output Enable

0 = Disabled, 1 = Enabled

2

1

RESERVED

CPU2/SRC10_OE

CPU[T/C]2/SRC[T/C]10 Output Enable

0 = Disabled, 1 = Enabled

0

1

PCIF1_OE

PCIF1 Output Enable

0 = Disabled, 1 = Enabled

Byte 4 Control Register 4

Bit

@Pup

Name

Description

7

0

SRC7_STP _CTRL

Allow control of SRC[T/C]7 with assertion of PCI_STP# or SW PCI_STP#

0 = Free running, 1 = Stopped with PCI_STP#

6

5

4

3

2

1

0

SRC6_STP _CTRL

SRC5_STP _CTRL

SRC4_STP _CTRL

SRC3_STP _CTRL

SRC2_STP _CTRL

SRC1_STP _CTRL

SRC0_STP _CTRL

Allow control of SRC[T/C]6 with assertion of PCI_STP# or SW PCI_STP#

0 = Free running, 1 = Stopped with PCI_STP#

Allow control of SRC[T/C]5 with assertion of PCI_STP# or SW PCI_STP#

0 = Free running, 1 = Stopped with PCI_STP#

Allow control of SRC[T/C]4 with assertion of PCI_STP# or SW PCI_STP#

0 = Free running, 1 = Stopped with PCI_STP#

Allow control of SRC[T/C]3 with assertion of PCI_STP# or SW PCI_STP#

0 = Free running, 1 = Stopped with PCI_STP#

Allow control of SRC[T/C]2 with assertion of PCI_STP# or SW PCI_STP#

0 = Free running, 1 = Stopped with PCI_STP#

Allow control of SRC[T/C]1 with assertion of PCI_STP# or SW PCI_STP#

0 = Free running, 1 = Stopped with PCI_STP#

Allow control of SRC[T/C]0 with assertion of PCI_STP# or SW PCI_STP#

0 = Free running, 1 = Stopped with PCI_STP#

Byte 5 Control Register 5

Bit

@Pup

Name

Description

7

0

LCD_PD_MODE

LCD PD# drive Mode

0 = Driven (L/L) when PD# asserted

1 = Tri-state (L/L) when PD# asserted

6

0

DOT96_PD_MODE

DOT96 PD# drive Mode

0 = Driven (L/L) when PD# asserted

1 = Tri-state (L/L) when PD# asserted

Confidential

Rev 1.1,March 10, 2008

Page 6 of 29

SL28545-4

Byte 5 Control Register 5 (continued)

Bit

@Pup

Name

Description

5

0

SRC_CLKREQ_MODE

SRC CLKREQ# drive Mode

0 = Driven (L/L) when CLKRQE# asserted

1 = Tri-state (L/L) when CLKREQ# asserted

4

3

2

1

0

1

PCIF1_STP_CTRL

PCIF0_STP_CTRL

CPU2_STP_CTRL

CPU1_STP_CTRL

CPU0_STP_CTRL

Allow control of PCIF1 with assertion of SW and HW PCI_STP#

0 = Free running, 1 = Stopped with PCI_STP#

Allow control of PCIF0 with assertion of SW and HW PCI_STP#

0 = Free running, 1 = Stopped with PCI_STP#

Allow control of CPU[T/C]2 with assertion of CPU_STP#

0 = Free running, 1 = Stopped with CPU_STP#

Allow control of CPU[T/C]1 with assertion of CPU_STP#

0 = Free running, 1 = Stopped with CPU_STP#

Allow control of CPU[T/C]0 with assertion of CPU_STP#

0 = Free running, 1 = Stopped with CPU_STP#

Byte 6 Control Register 6

Bit

@Pup

Name

Description

7

0

SRC_PCISTP_MODE

SRC[T/C] PCI_STP# Drive Mode

0 = Driven (H/L) when PCI_STP# asserted

1 = Tri-state (L/L) when PCI_STP# asserted

6

5

4

3

2

1

0

CPU2_CPUSTP_MODE CPU[T/C]2 CPU_STP# Drive Mode

0 = Driven (H/L) when CPU_STP# asserted

1 = Tri-state(L/L) when CPU_STP# asserted

CPU1_CPUSTP_MODE CPU[T/C]1 CPU_STP# Drive Mode

0 = Driven (H/L) when CPU_STP# asserted

1 = Tri-state (L/L) when CPU_STP# asserted

CPU0_CPUSTP_MODE CPU[T/C]0 CPU_STP# Drive Mode

0 = Driven (H/L) when CPU_STP# asserted

1 = Tri-state(L/L) when CPU_STP# asserted

SRC_PD_MODE

CPU2_PD_MODE

CPU1_PD_MODE

CPU0_PD_MODE

SRC PD# Drive Mode

0 = Driven (L/L) when PD# asserted

1 = Tri-state (L/L) when PD# asserted

CPU2 PD# Drive Mode

0 = Driven (L/L) when PD# asserted

1 = Tri-state (L/L) when PD# asserted

CPU1 PD# Drive Mode

0 = Driven (L/L) when PD# asserted

1 = Tri-state (L/L) when PD# asserted

CPU0 PD# Drive Mode

0 = Driven (L/L) when PD# asserted

1 = Tri-state (L/L) when PD# asserted

Byte 7 Control Register 7

Bit

@Pup

Name

Description

7

0

TEST_SEL

REF/N or Tri-state Select

0 = Tri-state, 1 = REF/N Clock

6

0

TEST_MODE

Test Clock Mode Entry Control

0 = Normal operation, 1 = REF/N or Tri-state mode,

5

4

0

RESERVED

REF0

RESERVED

REF0 Output Drive Strength

0 = Low, 1 = High

Confidential

Rev 1.1,March 10, 2008

Page 7 of 29

SL28545-4

Byte 7 Control Register 7 (continued)

Bit

@Pup

Name

Description

3

1

PCI, PCIF and SRC clock SW PCI_STP Function

outputs except those set to 0 = SW PCI_STP assert, 1= SW PCI_STP deassert

free running

When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will

be stopped in a synchronous manner with no short pulses.

When this bit is set to 1, all STOPPED PCI, PCIF and SRC outputs will

resume in a synchronous manner with no short pulses.

2

1

0

HW

FSC

FSB

FSA

FSC Reflects the value of the FSC pin sampled on power up

0 = FSC was low during CK_PWRGD assertion

FSB Reflects the value of the FSB pin sampled on power up

0 = FSB was low during CK_PWRGD assertion

FSA Reflects the value of the FSA pin sampled on power up

0 = FSA was low during CK_PWRGD assertion

Byte 8 Vendor ID

Bit

7

@Pup

Name

Description

Revision Code Bit 3

Revision Code Bit 2

Revision Code Bit 1

Revision Code Bit 0

Vendor ID Bit 3

0

1

0

Revision Code Bit 3

Revision Code Bit 2

Revision Code Bit 1

Revision Code Bit 0

Vendor ID Bit 3

6

5

4

3

2

Vendor ID Bit 2

1

Vendor ID Bit 1

0

Vendor ID Bit 0

Byte 9 Control Register 9

Bit

@Pup

Name

Description

7

0

CPU SS S1

CPU Spread percentage S1 bit

S1 S0

00=0.5%, 01=0.75%, 10=1%, 11=1.5%

6

5

0

CPU SS Control

CPU SS S0

CPU Spread Control

0 = down spread, 1 = center spread

CPU Spread percentage S2 bit

S1 S0

00=0.5%, 01=0.75%, 10=1%, 11=1.5%

4

3

2

0

1

RESERVED

48M

RESERVED

48-MHz Output Drive Strength

0 = Low, 1 = High

1

0

1

0

PCI1

PCI1 Output Drive Strength

0 = Low, 1 = High

PCIF0

PCIF0 Output Drive Strength

0 = Low, 1 = High

Byte 10 Control Register 10

Bit

7

@Pup

Name

Description

0

RESERVED

6

RESERVED

Confidential

Rev 1.1,March 10, 2008

Page 8 of 29

SL28545-4

Byte 10 Control Register 10 (continued)

Bit

5

@Pup

Name

S1

Description

0

27M_SS/LCD_100M SS Spread Spectrum Selection table:

S[1:0] SS%

‘00’ = –0.5%(Default value)

‘01’ = –1.0%

4

S0

‘10’ = –1.5%

‘11’ = –2.0%

3

2

1

RESERVED

27M_SS

RESERVED

27M Spread Output Enable

0 = Disabled, 1 = Enabled

1

0

1

0

27M_SS/LCD_100M

Spread Enable

27M_SS/LCD_100M Spread spectrum enable.

0 = Disabled, 1 = Enabled

PCIF1

PCIF1 Output Drive Strength

0 = Low, 1 = High

Byte 11 Control Register 11

Bit

7

@Pup

Name

Description

0

1

RESERVED

SRC8_OE

RESERVED

6

5

4

SRC[T/C]8 Output Enable

0 = Disable (Hi-Z), 1 = Enable

3

2

0

RESERVED

SRC10_STP_CTRL

Allow control of SRC[T/C]10 with assertion of SW PCI_STP#

0 = Free running, 1 = Stopped with PCI_STP#

1

0

RESERVED

SRC8_STP_CTRL

Allow control of SRC[T/C]8 with assertion of SW PCI_STP#

0 = Free running, 1 = Stopped with PCI_STP#

Byte 12 Control Register 12

Bit

7

@Pup

0

Name

RESERVED

Description

RESERVED, Set to 0

RESERVED

6

HW

1

RESERVED

5

RESERVED

4

RESERVED

3

27M_SS/27M_NSS

27-MHz (spread and non-spread) Output Drive Strength

0 = Low, 1 = High

2

1

0

HW

1

RESERVED

HW

Byte 13 Control Register 13

Bit

7

@Pup

Name

Description

0

RESERVED

CLKREQ#8

RESERVED

6

CLKREQ#8 Input Enable

0 = Disabled, 1 = Enabled

5

4

0

CLKREQ#7

CLKREQ#6

CLKREQ#7 Input Enable

0 = Disabled, 1 = Enabled

CLKREQ#6 Input Enable

0 = Disabled, 1 = Enabled

Confidential

Rev 1.1,March 10, 2008

Page 9 of 29

SL28545-4

Byte 13 Control Register 13 (continued)

Bit

@Pup

Name

Description

3

0

CLKREQ#5

CLKREQ#5 Input Enable

0 = Disabled, 1 = Enabled

2

1

0

CLKREQ#4

CLKREQ#3

RESERVED

CLKREQ#4 Input Enable

0 = Disabled, 1 = Enabled

CLKREQ#3 Input Enable

0 = Disabled, 1 = Enabled

RESERVED

Byte 14 Control Register 14

Bit

@Pup

Name

Description

7

0

CLKREQ#1

CLKREQ#1 Input Enable

0 = Disabled, 1 = Enabled

6

5

1

LCD_CLK Freq

LCD_CLK output frequency

0 = 96MHz, 1 = 100MHz

GPU_STP#_Control

Allow GPU_STP# control DOT96/27M_NSS

0 = DOT96/27M_NSS not stoppable by GPU_STP#

1 = DOT96/27M_NSS stoppable by GPU_STP#

4

1

GPU_STP#_Control

Allow GPU_STP# control 27M_SS

0 = 27M_SS not stoppable by GPU_STP#

1 = 27M_SS stoppable by GPU_STP#

3

2

1

0

PCI5

PCI4

PCI3

PCI2

PCI5 (Spread and Non-spread) Output Drive Strength

0 = Low, 1 = High

PCI4 (Spread and Non-spread) Output Drive Strength

0 = Low, 1 = High

PCI3 (Spread and Non-spread) Output Drive Strength

0 = Low, 1 = High

PCI2 (Spread and Non-spread) Output Drive Strength

0 = Low, 1 = High

Byte 15 Control Register 15

Bit

7

@Pup

Name

Description

RESERVED

1

0

1

0

1

RESERVED

IO_VOUT2

IO_VOUT1

IO_VOUT0

6

RESERVED

5

RESERVED

4

RESERVED

3

RESERVED

2

IO_VOUT[2,1,0]

000 = 0.3V

001 = 0.4V

1

0

010 = 0.5V

011 = 0.6V

100 = 0.7V

101 = 0.8V (Default)

110 = 0.9V

111 = Reserved

Byte 16 Control Register 16

Bit

@Pup

Name

Description

7

1

CLKREQ#8

SRC[T/C]8 Control

0 = SRC[T/C]8 not stoppable by CLKREQ#8

1 = SRC[T/C]8 stoppable by CLKREQ#8

Confidential

Rev 1.1,March 10, 2008

Page 10 of 29

SL28545-4

Bit

@Pup

Name

Description

6

5

4

3

2

1

0

CLKREQ#8

SRC[T/C]7 Control

0 = SRC[T/C]7 not stoppable by CLKREQ#8

1 = SRC[T/C]7 stoppable by CLKREQ#8

0

CLKREQ#8

SRC[T/C]6 Control

0 = SRC[T/C]6 not stoppable by CLKREQ#8

1 = SRC[T/C]6 stoppable by CLKREQ#8

SRC[T/C]5 Control

0 = SRC[T/C]5 not stoppable by CLKREQ#8

1 = SRC[T/C]5 stoppable by CLKREQ#8

SRC[T/C]4 Control

0 = SRC[T/C]4 not stoppable by CLKREQ#8

1 = SRC[T/C]4 stoppable by CLKREQ#8

SRC[T/C]3 Control

0 = SRC[T/C]3 not stoppable by CLKREQ#8

1 = SRC[T/C]3 stoppable by CLKREQ#8

SRC[T/C]2 Control

0 = SRC[T/C]2 not stoppable by CLKREQ#8

1 = SRC[T/C]2 stoppable by CLKREQ#8

SRC[T/C]1 Control

0 = SRC[T/C1 not stoppable by CLKREQ#8

1 = SRC[T/C]1 stoppable by CLKREQ#8

Byte 17 Control Register 17

Bit

@Pup

Name

Description

7

6

5

4

3

2

1

0

CLKREQ#5

SRC[T/C]8 Control

0 = SRC[T/C]8 not stoppable by CLKREQ#5

1 = SRC[T/C]8 stoppable by CLKREQ#5

0

1

0

CLKREQ#5

SRC[T/C]7 Control

0 = SRC[T/C]7 not stoppable by CLKREQ#5

1 = SRC[T/C]7 stoppable by CLKREQ#5

SRC[T/C]6 Control

0 = SRC[T/C]6 not stoppable by CLKREQ#5

1 = SRC[T/C]6 stoppable by CLKREQ#5

SRC[T/C]5 Control

0 = SRC[T/C]5 not stoppable by CLKREQ#5

1 = SRC[T/C]5 stoppable by CLKREQ#5

SRC[T/C]4 Control

0 = SRC[T/C]4 not stoppable by CLKREQ#5

1 = SRC[T/C]4 stoppable by CLKREQ#5

SRC[T/C]3 Control

0 = SRC[T/C]3 not stoppable by CLKREQ#5

1 = SRC[T/C]3 stoppable by CLKREQ#5

SRC[T/C]2 Control

0 = SRC[T/C]2 not stoppable by CLKREQ#5

1 = SRC[T/C]2 stoppable by CLKREQ#5

SRC[T/C]1 Control

0 = SRC[T/C]1 not stoppable by CLKREQ#5

1 = SRC[T/C]1 stoppable by CLKREQ#5

Byte 18 Control Register 18

Bit

@Pup

Name

Description

7

0

CLKREQ#4

SRC[T/C]8 Control

0 = SRC[T/C]8 not stoppable by CLKREQ#4

1 = SRC[T/C]8 stoppable by CLKREQ#4

Confidential

Rev 1.1,March 10, 2008

Page 11 of 29

SL28545-4

Bit

@Pup

Name

Description

6

5

4

3

2

1

0

CLKREQ#4

SRC[T/C]7 Control

0 = SRC[T/C]7 not stoppable by CLKREQ#4

1 = SRC[T/C]7 stoppable by CLKREQ#4

0

1

0

CLKREQ#4

SRC[T/C]6 Control

0 = SRC[T/C]6 not stoppable by CLKREQ#4

1 = SRC[T/C]6 stoppable by CLKREQ#4

SRC[T/C]5 Control

0 = SRC[T/C]5 not stoppable by CLKREQ#4

1 = SRC[T/C]5 stoppable by CLKREQ#4

SRC[T/C]4 Control

0 = SRC[T/C]4 not stoppable by CLKREQ#4

1 = SRC[T/C]4 stoppable by CLKREQ#4

SRC[T/C]3 Control

0 = SRC[T/C]3 not stoppable by CLKREQ#4

1 = SRC[T/C]3 stoppable by CLKREQ#4

SRC[T/C]2 Control

0 = SRC[T/C]2 not stoppable by CLKREQ#4

1 = SRC[T/C]2 stoppable by CLKREQ#4

SRC[T/C]1 Control

0 = SRC[T/C]1 not stoppable by CLKREQ#4

1 = SRC[T/C]1 stoppable by CLKREQ#4

Byte 19 Control Register 19

Bit

@Pup

Name

Description

7

6

5

4

3

2

1

0

CLKREQ#3

SRC[T/C]8 Control

0 = SRC[T/C]8 not stoppable by CLKREQ#3

1 = SRC[T/C]8 stoppable by CLKREQ#3

0

1

0

CLKREQ#3

SRC[T/C]7 Control

0 = SRC[T/C]7 not stoppable by CLKREQ#3

1 = SRC[T/C]7 stoppable by CLKREQ#3

SRC[T/C]6 Control

0 = SRC[T/C]6 not stoppable by CLKREQ#3

1 = SRC[T/C]6 stoppable by CLKREQ#3

SRC[T/C]5 Control

0 = SRC[T/C]5 not stoppable by CLKREQ#3

1 = SRC[T/C]5 stoppable by CLKREQ#3

SRC[T/C]4 Control

0 = SRC[T/C]4 not stoppable by CLKREQ#3

1 = SRC[T/C]4 stoppable by CLKREQ#3

SRC[T/C]3 Control

0 = SRC[T/C]3 not stoppable by CLKREQ#3

1 = SRC[T/C]3 stoppable by CLKREQ#3

SRC[T/C]2 Control

0 = SRC[T/C]2 not stoppable by CLKREQ#3

1 = SRC[T/C]2 stoppable by CLKREQ#3

SRC[T/C]1 Control

0 = SRC[T/C]1 not stoppable by CLKREQ#3

1 = SRC[T/C]1 stoppable by CLKREQ#3

Byte 20 Control Register 20

Bit

@Pup

Name

Description

7

0

CLKREQ#1

SRC[T/C]8 Control

0 = SRC[T/C]8 not stoppable by CLKREQ#1

1 = SRC[T/C]8 stoppable by CLKREQ#1

Confidential

Rev 1.1,March 10, 2008

Page 12 of 29

SL28545-4

Bit

@Pup

Name

Description

6

5

4

3

2

1

0

CLKREQ#1

SRC[T/C]7 Control

0 = SRC[T/C]7 not stoppable by CLKREQ#1

1 = SRC[T/C]7 stoppable by CLKREQ#1

0

1

CLKREQ#1

SRC[T/C]6 Control

0 = SRC[T/C]6 not stoppable by CLKREQ#1

1 = SRC[T/C]6 stoppable by CLKREQ#1

SRC[T/C]5 Control

0 = SRC[T/C]5 not stoppable by CLKREQ#1

1 = SRC[T/C]5 stoppable by CLKREQ#1

SRC[T/C]4 Control

0 = SRC[T/C]4 not stoppable by CLKREQ#1

1 = SRC[T/C]4 stoppable by CLKREQ#1

SRC[T/C]3 Control

0 = SRC[T/C]3 not stoppable by CLKREQ#1

1 = SRC[T/C]3 stoppable by CLKREQ#1

SRC[T/C]2 Control

0 = SRC[T/C]2 not stoppable by CLKREQ#1

1 = SRC[T/C]2 stoppable by CLKREQ#1

SRC[T/C]1 Control

0 = SRC[T/C]1 not stoppable by CLKREQ#1

1 = SRC[T/C]1 stoppable by CLKREQ#1

Byte 21 Control Register 21

Bit

@Pup

Name

Description

7

6

5

4

3

2

1

0

GPU_STP# Control

SRC7

Allow control of SRC7 by GPU_STP#

0 = SRC7 not stoppable by GPU_STP#

1 = SRC7 stoppable by GPU_STP#

0

GPU_STP# Control

SRC6

Allow control of SRC6 by GPU_STP#

0 = SRC6 not stoppable by GPU_STP#

1 = SRC6 stoppable by GPU_STP#

0

GPU_STP# Control

SRC5

Allow control of SRC5 by GPU_STP#

0 = SRC5 not stoppable by GPU_STP#

1 = SRC5 stoppable by GPU_STP#

0

GPU_STP# Control

SRC4

Allow control of SRC4 by GPU_STP#

0 = SRC4 not stoppable by GPU_STP#

1 = SRC4 stoppable by GPU_STP#

0

GPU_STP# Control

SRC3

Allow control of SRC3 by GPU_STP#

0 = SRC3 not stoppable by GPU_STP#

1 = SRC3 stoppable by GPU_STP#

GPU_STP# Control

SRC2

Allow control of SRC2 by GPU_STP#

0 = SRC2not stoppable by GPU_STP#

1 = SRC2 stoppable by GPU_STP#

FCT_SEL

GPU_STP# Control

SRC1

Allow control of SRC1 by GPU_STP#

0 = SRC1 not stoppable by GPU_STP#

1 = SRC1 stoppable by GPU_STP#

When FCT_SEL = 0, this bit is 0, FCT_SEL = 1, this bit is 1

0

FCT_SEL#

GPU_STP# Control

SRC0/LCD

Allow control of SRC0/LCD by GPU_STP#

0 = SRC0/LCD not stoppable by GPU_STP#

1 = SRC0/LCD stoppable by GPU_STP#

When FCT_SEL = 1, this bit is 0, FCT_SEL = 0, this bit is 1

Confidential

Rev 1.1,March 10, 2008

Page 13 of 29

SL28545-4

Byte 22 Control Register 22

Bit

7

@Pup

Name

Description

0

1

0

PCI range boost

PCI range select

USB range boost

USB range select

6

RangeBoost Drive Strength RangeSel

5

(Byte22)

(Byte 7,9,12,14) (Byte 22) Buffer Strength

4

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1x

1.25x

1.5x

2x

2.25x

2.5x

2.7x

3x

3

27M_SS/27M_NSS

range boost

REF, PCI default

27M, USB default

2

0

27M_SS/27M_NSS

range select

1

0

1

REF range boost

REF range select

Table 6. Crystal Recommendations

Frequency

Drive

(max.)

Shunt Cap Motional

Tolerance

(max.)

Stability

(max.)

Aging

(max.)

(Fund)

Cut

Loading Load Cap

(max.)

14.31818 MHz

AT

Parallel 20 pF

0.1 mW

5 pF

0.016 pF

35 ppm

30 ppm

5 ppm

The SL28545-4 requires a Parallel Resonance Crystal. Substi-

tuting a series resonance crystal will cause the SL28545-4 to

operate at the wrong frequency and violate the ppm specifi-

cation. For most applications there is a 300-ppm frequency

shift between series and parallel crystals due to incorrect

loading.

crystal. This means the total capacitance on each side of the

crystal must be twice the specified crystal load capacitance

(CL). While the capacitance on each side of the crystal is in

series with the crystal, trim capacitors (Ce1,Ce2) should be

calculated to provide equal capacitive loading on both sides.

Clock Chip

Crystal Loading

Crystal loading plays a critical role in achieving low ppm perfor-

mance. To realize low ppm performance, the total capacitance

the crystal will see must be considered to calculate the appro-

priate capacitive loading (CL).

Ci2

Ci1

3 to 6p

Figure 1 shows a typical crystal configuration using the two

trim capacitors. An important clarification for the following

discussion is that the trim capacitors are in series with the

crystal not parallel. It’s a common misconception that load

capacitors are in parallel with the crystal and should be

approximately equal to the load capacitance of the crystal.

This is not true.

X2

X1

Cs2

Cs1

Trace

2.8 pF

XTAL

Ce1

Ce2

Trim

33 pF

Figure 2. Crystal Loading Example

Use the following formulas to calculate the trim capacitor

values for Ce1 and Ce2.

Load Capacitance (each side)

Figure 1. Crystal Capacitive Clarification

Ce = 2 * CL – (Cs + Ci)

Calculating Load Capacitors

Total Capacitance (as seen by the crystal)

1

In addition to the standard external trim capacitors, trace

capacitance and pin capacitance must also be considered to

correctly calculate crystal loading. As mentioned previously,

the capacitance on each side of the crystal is in series with the

CLe

=

1

(

)

+

Ce2 + Cs2 + Ci2

Ce1 + Cs1 + Ci1

Confidential

Rev 1.1,March 10, 2008

Page 14 of 29

SL28545-4

CLKREQ#X

SRCT(free running)

SRCC(free running)

SRCT(stoppable)

Figure 3. CLKREQ# Deassertion/Assertion Waveform

CL ................................................... Crystal load capacitance

CLKREQ# Deassertion (CLKREQ# -> HIGH)

CLe .........................................Actual loading seen by crystal

using standard value trim capacitors

The impact of deasserting the CLKREQ# pins is that all SRC

outputs that are set in the control registers to stoppable via

deassertion of CLKREQ# are to be stopped after their next

transition. The final state of all stopped SRC clocks is

Low/Low.

Ce .....................................................External trim capacitors

Cs ............................................. Stray capacitance (terraced)

Ci .......................................................... Internal capacitance

(lead frame, bond wires etc.)

PD# (Power-down) Clarification

The CKPWRGD/PD# pin is a dual-function pin. During initial

power-up, the pin functions as CK_PWRGD. Once

CKPWRGD has been sampled HIGH by the clock chip, the pin

assumes PD# functionality. The PD# pin is an asynchronous

active LOW input used to shut off all clocks cleanly prior to

shutting off power to the device. This signal is synchronized

internal to the device prior to powering down the clock synthe-

sizer. PD# is also an asynchronous input for powering up the

system. When PD# is asserted LOW, all clocks need to be

driven to a LOW value and held prior to turning off the VCOs

and the crystal oscillator.

CLKREQ# Description

The CLKREQ# signals are active LOW inputs used for clean

enabling and disabling selected SRC outputs. The outputs

controlled by CLKREQ# are determined by the settings in

register byte 8. The CLKREQ# signal is a de-bounced signal

in that it’s state must remain unchanged during two consec-

utive rising edges of SRCC to be recognized as a valid

assertion or deassertion. (The assertion and deassertion of

this signal is absolutely asynchronous.)

CLKREQ# Assertion (CLKREQ# -> LOW)

PD# (Power-down) Assertion

All differential outputs that were stopped are to resume normal

operation in a glitch-free manner. The maximum latency from

the assertion to active outputs is between 2 and 6 SRC clock

periods (2 clocks are shown) with all SRC outputs resuming

simultaneously. All stopped SRC outputs must be driven HIGH

within 10 ns of CLKREQ# deassertion to a voltage greater than

200 mV.

When PD# is sampled LOW by two consecutive rising edges

of CPUC, all single-ended outputs will be held LOW on their

next HIGH-to-LOW transition and differential clocks must be

held Low on the next diff clock# HIGH-to-LOW transition within

4 clock periods. Note that Figure 4 shows CPUT = 133 MHz

and PD drive mode = ‘1’ for all differential outputs. This

diagram and description is applicable to valid CPU

frequencies. In the event that PD mode is desired as the initial

power-on state, PD must be asserted HIGH in less than 10 µs

after asserting CK_PWRGD..

P D #

C P U T , 133M H z

C P U C , 133M H z

S R C T 100M H z

S R C C 100M H z

U S B , 48M H z

D O T 96T

D O T 96C

P C I, 33 M H z

R E F

Figure 4. Power-down Assertion Timing Waveform

Confidential

Rev 1.1,March 10, 2008

Page 15 of 29

SL28545-4

PD# Deassertion

condition resulting from power down will be driven high in less

than 300 µs of PD deassertion to a voltage greater than

200 mV. After the clock chip’s internal PLL is powered up and

locked, all outputs will be enabled within a few clock cycles of

each other. Figure 5 is an example showing the relationship of

clocks coming up.

The power-up latency is less than 1.8 ms. This is the time from

the deassertion of the PD pin or the ramping of the power

supply until the time that stable clocks are output from the

clock chip. All differential outputs stopped in a three-state

Tstable

<1.8ms

PD#

CPUT, 133MHz

CPUC, 133MHz

SRCT 100MHz

SRCC 100MHz

USB, 48MHz

DOT96T

DOT96C

PCI, 33MHz

REF

Tdrive_PW RDN#

<300µS, >200mV

Figure 5. Power-down Deassertion Timing Waveform

set with the SMBus configuration to be stoppable via assertion

CPU_STP# Assertion

of CPU_STP# will be stopped within two–six CPU clock

periods after being sampled by two rising edges of the internal

CPUC clock. The final state of all stopped CPU clocks is

High/Low when driven, Low/Low when tri-stated.

The CPU_STP# signal is an active LOW input used for

synchronous stopping and starting the CPU output clocks

while the rest of the clock generator continues to function.

When the CPU_STP# pin is asserted, all CPU outputs that are

CPU_STP#

CPUT

CPUC

Figure 6. CPU_STP# Assertion Waveform

CPU_STP#

CPUT

CPUC

CPUT Internal

CPUC Internal

Tdrive_CPU_STP#,10 ns>200 mV

Figure 7. CPU_STP# Deassertion Waveform

Confidential

Rev 1.1,March 10, 2008

Page 16 of 29

SL28545-4

PCI_STP# Assertion

driven Low, SRC outputs are High/Low if set to driven and

Low/Low if set to tri-state.

The PCI_STP# signal is an active LOW input used for

synchronous stopping and starting the PCI outputs and SRC

outputs if they are set to be stoppable in SMbus while the rest

of the clock generator continues to function. The set-up time

for capturing PCI_STP# going LOW is 10 ns (t_SU). (See

Figure 9.) The PCIF clocks will not be affected by this pin if

their corresponding control bit in the SMBus register is set to

allow them to be free running. All stopped PCI outputs are

PCI_STP# Deassertion

The deassertion of the PCI_STP# signal will cause all PCI and

stoppable PCIF clocks to resume running in a synchronous

manner within two PCI clock periods after PCI_STP# transi-

tions to a HIGH level.

1.8mS

CPU_STOP#

PD

CPUT(Free Running)

CPUC(Free Running)

CPUT(Stoppable)

CPUC(Stoppable)

DOT96T

DOT96C

Figure 8. CPU_STP# = Tri-state, CPU_PD = Tri-state, DOT_PD = Tri-state

Tsu

PCI_STP#

PCI_F

PCI

SRC 100MHz

Figure 9. PC I_STP# Assertion Waveform

Figure 10. CPU_STP# = Driven, CPU_PD = Driven, DOT_PD = Driven

Confidential

Rev 1.1,March 10, 2008

Page 17 of 29

SL28545-4

Tdrive_SRC

Tsu

PCI_STP#

PCI_F

PCI

SRC 100MHz

Figure 11. PCI_STP# Deassertion Waveform

Figure 12. CKPWRGD Timing DIagram

Table 7. Output Driver Status during PCI-STP# and CPU_STP#

PCI_STP# Asserted

Driven Low

CPU_STP# Asserted

Running

SMBus OE Disabled

Single-ended Clocks Stoppable

Non Stoppable

Stoppable

Driven Low

Running

Differential Clocks

Clock Driven High

Clock# Driven Low

Clock Driven High

Clock# Driven Low

Driven Low or 20K

pulldown

Non Stoppable

Running

Table 8. Output Driver Status

All Single-ended Clocks

All Differential Clocks except CPU1

Clock Clock#

Low or 20K pulldown Low

CPU1

w/o Strap

Latches Open State Low

w/Strap

Clock

Clock#

Hi-Z

Low or 20K

pulldown

Low

Powerdown

M1

Low

Hi-Z

Low or 20K pulldown Low

Low or 20K

pulldown

Low

Running

Confidential

Rev 1.1,March 10, 2008

Page 18 of 29

SL28545-4

Figure 13. CY28545-4 State Diagram

Confidential

Rev 1.1,March 10, 2008

Page 19 of 29

SL28545-4

Absolute Maximum Conditions

Parameter

V_DD

Description

Core Supply Voltage

Condition

Min.

–0.5

–65

0

Max.

4.6

Unit

V

4.6

V_{DD_A}

V_IN

Analog Supply Voltage

Input Voltage

V

+ 0.5

Relative to V_SS

Non-functional

Functional

VDC

°C

DD

T_S

Temperature, Storage

150

85

150

20

60

–

T_A

Temperature, Operating Ambient

Temperature, Junction

°C

T_J

Functional

–

°C

Ø_JC

Dissipation, Junction to Case

Dissipation, Junction to Ambient

Mil-STD-883E Method 1012.1

JEDEC (JESD 51)

–

°C/W

V

Ø_JA

–

ESD_HBM

UL-94

MSL

ESD Protection (Human Body Model) MIL-STD-883, Method 3015

2000

Flammability Rating

At 1/8 in.

V–0

1

Moisture Sensitivity Level

Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.

DC Electrical Specifications

Parameter

All VDDs

V_ILI2C

V_IHI2C

V_{IL_FS}

V_{IH_FS}

V_{ILFS_C}

V_{IMFS_C}

V_{IHFS_C}

V_IL

Description

3.3V Operating Voltage

Input Low Voltage

Condition

Min.

3.135

–

Max. Unit

3.3 ± 5%

3.465

1.0

V

SDATA, SCLK

Input High Voltage

2.2

–

V

– 0.3

FS_[A,B] Input Low Voltage

FS_[A,B] Input High Voltage

FS_C Input Low Voltage

FS_C Input Middle Voltage

FS_C Input High Voltage

3.3V Input Low Voltage

3.3V Input High Voltage

Input Low Leakage Current

Input High Leakage Current

3.3V Output Low Voltage

3.3V Output High Voltage

High-impedance Output Current

Input Pin Capacitance

Output Pin Capacitance

Pin Inductance

0.35

V

SS

V

+ 0.5

0.7

– 0.3

V

DD

0.35

1.7

+ 0.5

V

SS

0.7

2.0

– 0.3

V

DD

V

0.8

+ 0.3

V

SS

V_IH

2.0

–5

–

V

DD

I_IL

Except internal pull-up resistors, 0 < V_IN< V_DD

Except internal pull-down resistors, 0 < V_IN< V_DD

I_OL= 1 mA

5

µA

V

I_IH

V_OL

–

0.4

–

V_OH

I_OH= –1 mA

2.4

–10

3

V

I_OZ

10

5

µA

pF

nH

V

C_IN

C_OUT

L_IN

3

6

–

7

V_XIH

Xin High Voltage

0.7V

0

V_DD

DD

V_XIL

Xin Low Voltage

0.3V

V

DD

I_DD3.3V

I_PD3.3V

Dynamic Supply Current

Power-down Supply Current

–

190¹

mA

–

1

1. Measured with CPU running at 266MHz under low drive condition

Confidential

Rev 1.1,March 10, 2008

Page 20 of 29

SL28545-4

AC Electrical Specifications

Parameter

Crystal

T_DC

Description

Condition

Min.

Max.

Unit

XIN Duty Cycle

The device will operate reliably with input duty

cycles up to 30/70 but the REF clock duty cycle

will not be within specification

47.5

52.5

%

T_PERIOD

XIN Period

When XIN is driven from an external clock

source

69.841

71.0

ns

T_R/T_F

XIN Rise and Fall Times

XIN Cycle to Cycle Jitter

Measured between 0.3V_DDand 0.7V_DD

–

10.0

500

ns

ps

T_CCJ

As an average over 1-µs duration

CPU at 0.8V

T_DC

CPUT and CPUC Duty Cycle

Measured at 0V differential @ 0.1s

45

55

%

T_PERIOD

100-MHz CPUT and CPUC Period

133-MHz CPUT and CPUC Period

166-MHz CPUT and CPUC Period

200-MHz CPUT and CPUC Period

266-MHz CPUT and CPUC Period

333-MHz CPUT and CPUC Period

400-MHz CPUT and CPUC Period

9.99700 10.0030 ns

7.497751 7.52251 ns

5.99820 6.00180 ns

4.99850 5.00150 ns

3.74963 3.75038 ns

2.99970 3.00030 ns

2.49975 2.50025 ns

9.99700 10.05327 ns

7.49775 7.53995 ns

5.99820 6.03196 ns

4.99850 5.02663 ns

3.74887 3.76997 ns

2.99910 3.01598 ns

2.49925 2.51331 ns

9.91200 10.0880 ns

T_PERIODSS100-MHz CPUT and CPUC Period, SSC Measured at differential 0V @ 0.1s

T_PERIODSS133-MHz CPUT and CPUC Period, SSC Measured at differential 0V @ 0.1s

T_PERIODSS166-MHz CPUT and CPUC Period, SSC Measured at differential 0V @ 0.1s

T_PERIODSS200-MHz CPUT and CPUC Period, SSC Measured at differential 0V @ 0.1s

T_PERIODSS266-MHz CPUT and CPUC Period, SSC Measured at 0V differential @ 0.1s

T_PERIODSS333-MHz CPUT and CPUC Period, SSC Measured at 0V differential @ 0.1s

T_PERIODSS400-MHz CPUT and CPUC Period, SSC Measured at 0V differential @ 0.1s

T_PERIODAbs100-MHz CPUT and CPUC Absolute

period

Measured at 0V differential @ 1 clock

T_PERIODAbs133-MHz CPUT and CPUC Absolute

period

7.41275 7.58725 ns

5.91320 6.08680 ns

4.91350 5.08650 ns

3.66387 3.83613 ns

2.91410 3.08590 ns

2.41425 2.58575 ns

9.91200 10.13827 ns

7.41275 7.62495 ns

5.91320 6.11696 ns

4.91350 5.11163 ns

3.66387 3.85497 ns

T_PERIODAbs166-MHz CPUT and CPUC Absolute

period

T_PERIODAbs200-MHz CPUT and CPUC Absolute

period

T_PERIODAbs266-MHz CPUT and CPUC Absolute

period

T_PERIODAbs333-MHz CPUT and CPUC Absolute

period

T_PERIODAbs400-MHz CPUT and CPUC Absolute

period

T_PERI-

100-MHz CPUT and CPUC Absolute

period, SSC

ODSSAbs

1. Measured with CPU running at 266MHz

T_PERI-

ODSSAbs

T_PERI-

ODSSAbs

T_PERI-

ODSSAbs

T_PERI-

133-MHz CPUT and CPUC Absolute

period, SSC

166-MHz CPUT and CPUC Absolute

period, SSC

200-MHz CPUT and CPUC Absolute

period, SSC

266-MHz CPUT and CPUC Absolute

period, SSC

ODSSAbs

Confidential

Rev 1.1,March 10, 2008

Page 21 of 29

SL28545-4

AC Electrical Specifications (continued)

Parameter

Description

Condition

Min.

Max.

Unit

T_PERI-

ODSSAbs

T_PERI-

ODSSAbs

T_CCJ

333-MHz CPUT and CPUC Absolute

period, SSC

Measured at 0V differential @ 1 clock

2.91410 3.10098 ns

400-MHz CPUT and CPUC Absolute

period, SSC

Measured at 0V differential @ 1 clock

2.41425 2.59831 ns

CPUT/C Cycle to Cycle Jitter

CPU2_ITP Cycle to Cycle Jitter

Long-term Accuracy

Measured at crossing point V_OX

–

85

ps

T_CCJ2

L_ACC

125

300

100

8.0

–

ppm

ps

T_SKEW

CPU1 to CPU0 Clock Skew

–

Slew_rise Rising slew rate

Slew_Fall Falling slew rate

Slew_var Slew rate matching

Measured differentially from +150mV to

-150mV

2.5

V/ns

Measured differentially from -150mV to

+150mV

2.5

8.0

V/ns

–

20

%

V

V_max

Max output voltage

Measurement taken from single eneded

waveform including overshoot

1.15

V_min

Min output Voltage

Measurement taken from single eneded

waveform including undershoot

–0.3

300

–

V

V_cross

Crossing Point Voltage at 0.7V Swing

550

mV

SRC at 0.8V

T_DC

SRCT and SRCC Duty Cycle

Measured at crossing point V_OX

45

55

%

ns

9.99700

10.0030

T_PERIOD

100-MHz SRCT and SRCC Period

9.99700 10.05327

9.87200 10.12800

T_PERIODSS100-MHz SRCT and SRCC Period, SSC Measured at crossing point V_OX

T_PERIODAbs100-MHz SRCT and SRCC Absolute

Period

Measured at crossing point V_OX

9.87200 10.17827

T_PERI-

ODSSAbs

T_SKEW

100-MHz SRCT and SRCC Absolute

Period, SSC

Measured at crossing point V_OX

ns

Any SRCT/C to SRCT/C Clock Skew

SRCT/C Cycle to Cycle Jitter

SRCT/C Long Term Accuracy

Measured at crossing point V_OX

–

250

125

300

8.0

ps

T_CCJ

L_ACC

–

ppm

V/ns

Slew_rise Rising slew rate

Slew_Fall Falling slew rate

Slew_var Slew rate matching

Measured differentially from +150mV to

-150mV

2.5

Measured differentially from -150mV to

+150mV

2.5

8.0

V/ns

–

20

%

V

V_max

Max output voltage

Measurement taken from single eneded

waveform including overshoot

1.15

V_min

Min output Voltage

Measurement taken from single eneded

waveform including undershoot

–0.3

–

V

V_cross

T_SKEW

T_CCJ

Crossing Point Voltage at 0.7V Swing

Any SRCT/C to SRCT/C Clock Skew

SRCT/C Cycle to Cycle Jitter

300

–

550

250

125

300

mV

ps

Measured at crossing point V_OX

–

ps

L_ACC

SRCT/C Long Term Accuracy

–

ppm

LCD_100M_SSC at 0.8V

T_DC

SSCT and SSCC Duty Cycle

100-MHz SSCT and SSCC Period

Measured at crossing point V_OX

45

55

%

ns

9.997001 10.00300

9.997001 10.05327

9.872001 10.12800

T_PERIOD

T_PERIODSS100-MHz SSCT and SSCC Period, SSC Measured at crossing point V_OX

T_PERIODAbs100-MHz SSCT and SSCC Absolute

Period

Measured at crossing point V_OX

Confidential

Rev 1.1,March 10, 2008

Page 22 of 29

SL28545-4

AC Electrical Specifications (continued)

Parameter

Description

Condition

Min.

Max.

Unit

9.872001 10.17827

T_PERI-

ODSSAbs

T_CCJ

100-MHz SRCT and SRCC Absolute

Period, SSC

Measured at crossing point V_OX

ns

SSCT/C Cycle to Cycle Jitter

SSCT/C Long Term Accuracy

Measured at crossing point V_OX

–

125

300

8.0

ps

L_ACC

ppm

V/ns

Slew_rise Rising slew rate

Slew_Fall Falling slew rate

Slew_var Slew rate matching

Measured differentially from +150mV to

-150mV

2.5

Measured differentially from -150mV to

+150mV

2.5

8.0

V/ns

–

20

%

V

V_max

Max output voltage

Measurement taken from single eneded

waveform including overshoot

1.15

V_min

Min output Voltage

Measurement taken from single eneded

waveform including undershoot

–0.3

300

–

V

V_cross

Crossing Point Voltage at 0.7V Swing

550

mV

DOT96 at 0.8V

45

55

T_DC

DOT96T and DOT96C Duty Cycle

DOT96T and DOT96C Period

Measured at crossing point V_OX

%

ns

10.41354 10.41979

10.16354 10.66979

T_PERIOD

T_PERIODAbsDOT96T and DOT96C Absolute Period Measured at crossing point V_OX

ns

T_CCJ

L_ACC

DOT96T/C Cycle to Cycle Jitter

DOT96T/C Long Term Accuracy

Measured at crossing point V_OX

–

250

300

8.0

ps

ppm

V/ns

Slew_rise Rising slew rate

Slew_Fall Falling slew rate

Slew_var Slew rate matching

Measured differentially from +150mV to

-150mV

2.5

Measured differentially from -150mV to

+150mV

2.5

8.0

V/ns

–

20

%

V

V_max

Max output voltage

Measurement taken from single eneded

waveform including overshoot

1.15

V_min

Min output Voltage

Measurement taken from single eneded

waveform including undershoot

–0.3

300

–

V

V_cross

Crossing Point Voltage at 0.7V Swing

550

mV

PCI/PCIF at 3.3V

45

55

T_DC

PCI Duty Cycle

Spread Disabled PCIF/PCI Period

Measurement at 1.5V

%

ns

29.99100 30.00900

29.9910 30.15980

29.49100 30.50900

29.49100 30.65980

T_PERIOD

T_PERIODSSSpread Enabled PCIF/PCI Period, SSC Measurement at 1.5V

T_PERIODAbsSpread Disabled PCIF/PCI Period Measurement at 1.5V

Spread Enabled PCIF/PCI Period, SSC Measurement at 1.5V

T_PERI-

ODSSAbs

T_HIGH

12.0

1.0

–

PCIF and PCI high time

Measurement at 2.4V

ns

T_LOW

T_R/T_F

T_SKEW

T_delay

Tdrive

PCIF and PCI low time

Measurement at 0.4V

PCIF/PCI rising and falling Edge Rate

Any PCI clock to Any PCI clock Skew

Intentional PCI-PCI delay

Measured between 0.8V and 2.0V

Measurement at 1.5V

4.0

1000

200

15

V/ns

ps

Measurement at 1.5V

pS

ns

PCI output enable after PCI_STP#

de-assertion

–

500

300

T_CCJ

L_ACC

PCIF and PCI Cycle to Cycle Jitter

PCIF/PCI Long Term Accuracy

Measurement at 1.5V

ps

Measured at crossing point V_OX

ppm

Confidential

Rev 1.1, March 10, 2008

Page 23 of 29

SL28545-4

AC Electrical Specifications (continued)

Parameter

Description

Condition

Min.

Max.

Unit

48_M at 3.3V

45

55

T_DC

Duty Cycle

Period

Measurement at 1.5V

%

ns

20.83125 20.83542

20.48125 21.18542

T_PERIOD

Measurement at 1.5V

T_PERIODAbsAbsolute Period

Measurement at 1.5V

ns

8.094

7.694

1.0

–

11.100

2.0

T_HIGH

T_LOW

T_R/T_F

T_CCJ

48_M High time

Measurement at 2.4V

ns

48_M Low time

Measurement at 0.4V

ns

Rising and Falling Edge Rate

Cycle to Cycle Jitter

48M Long Term Accuracy

Measured between 0.8V and 2.0V

Measurement at 1.5V

V/ns

ps

350

–

300

L_ACC

Measured at crossing point V_OX

ppm

27_M at 3.3V

T_DC

Duty Cycle

Measurement at 1.5V

45

55

%

ns

37.035

36.785

37.038

37.288

T_PERIOD

Spread Disabled 27M Period

T_PERI-

ODABS

T_HIGH

Spread Disabled 27M absolute Period

10.5

1.0

–

27_M High time

Measurement at 2.0V

Measurement at 0.8V

Measured between 0.8V and 2.0V

Measurement at 1.5V

1uS after trigger

ns

–

T_LOW

27_M Low time

4.0

350

700

T_R/T_F

Rising and Falling Edge Rate

Cycle to Cycle Jitter

Long Term Jitter

V/ns

ps

T_CCJ

T_LTJ

ps

REF at 3.3V

T_DC

45

55

REF Duty Cycle

REF Period

Measurement at 1.5V

Measured between 0.8V and 2.0V

Measurement at 1.5V

%

ns

69.8203

69.8622

T_PERIOD

68.82033 70.86224

T_PERIODAbsREF Absolute Period

ns

1.0

–

4.0

500

T_R/T_F

T_SKEW

T_CCJ

REF Rising and Falling Edge Rate

V/ns

ps

REF Clock to REF Clock

REF Cycle to Cycle Jitter

Long Term Accuracy

–

1000

300

ps

–

L_ACC

ppm

ENABLE/DISABLE and SET-UP

T_STABLEClock Stabilization from Power-up

T_SS

–

10.0

0

1.8

–

ms

ns

Stopclock Set-up Time

Stopclock Hold Time

T_SH

–

Confidential

Rev 1.1,March 10, 2008

Page 24 of 29

SL28545-4

Test and Measurement Set-up

For Single-ended Signals and Reference

The following diagram shows test load configurations for the

single-ended PCI, USB, and REF output signals.

Figure 14.Single-ended Load Configuration Low Drive Option

Figure 15. Single-ended Load Configuration High Drive Option

The following diagram shows the test load configuration for the

differential CPU and SRC outputs.

Figure 16. 0.8V Differential Load Configuration

Confidential

Rev 1.1,March 10, 2008

Page 25 of 29

SL28545-4

3 .3 V s ig n a ls

T _{D C}

-

3.3V

2.0V

1.5V

0.8V

0V

T _R

T _F

Figure 17. Single-ended Output Signals (for AC Parameters Measurement)

Ordering Information

Part Number

Lead-free

Package Type

Product Flow

SL28545ALC-4

SL28545ALC-4T

68-pin QFN

68-pin QFN Tape and Reel

Commercial, 0° to 85°C

SL28545ALC-4 is Pb free and RoHS compliant

Rev 1.1,March 10, 2008

Confidential

Page 26 of 29

SL28545-4

Package Diagrams

68-Lead QFN 8 x 8 mm (0.4-mm Pitch)

MIN/MAX

DIMENSIONS IN MM[INCHES]

REFERENCE JEDEC MO-220

PACKAGE WEIGHT: 0.17 grams

TOP VIEW

SIDE VIEW

BOTTOM VIEW

7.90[0.311]

A

0.18[0.007]

0.28[0.011]

8.10[0.319]

0.08

C

1.0[0.039] MAX

0.80[0.031] MAX

7.70[0.303]

7.80[0.307]

0.05[0.002] MAX

0.2[0.008] REF

6.30 REF

PIN1 ID

0.20 R.

N

1

2

3

1

2

3

0.80[0.031]

0.45[0.017]

DIA

6.30

REF

0.40[0.012]

0.50[0.020]

0°-12°

0.24[0.009]

0.60[0.023]

0.4 B.S.C.

C

SEATING

PLANE

0.25[0.009] MIN.

6.50[0.255] REF

51-85214-*A

Confidential

Rev 1.1,March 10, 2008

Page 27 of 29

SL28545-4

Package Diagrams (continued)

68-Lead QFN 8 x 8 mm (0.4-mm Pitch)

Confidential

Rev 1.1,March 10, 2008

Page 28 of 29

SL28545-4

Document History Page

Document Title: SL28545-4 Clock Generator for next Gen Intel^®Mobile Platform

Document Number:

Orig. of

REV.

1.0

Issue Date Change

Description of Change

11/20/07

3/10/08

SLI

New data sheet

1.1

Removed Preliminary status

Updated package diagram

Updated DC Electrical Specification table

Updated AC Electrical Specification table

While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the

use of any circuitry or for the infringement of any patents or other rights of third parties which would result from each use. This

product is intended for use in normal commercial applications and is not warranted nor is it intended for use in life support, criti-

cal medical instruments, or any other application requiring extended temperature range, high reliability, or any other extraordi-

nary environmental requirements unless pursuant to additional processing by Spectra Linear Inc., and expressed written

agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any circuitry or specification without notice.

Confidential

Rev 1.1,March 10, 2008

Page 29 of 29


型号：	SL28545ALC-4
厂家：	SILICON
描述：	Processor Specific Clock Generator, CMOS, 8 X 8 MM, 0.40 MM PITCH, ROHS COMPLIANT, MO-220, QFN-64 外围集成电路
文件：	总29页 (文件大小：332K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SL28545ALC-4 [SILICON]

相关型号：

SL28548ALC-2

SL28548ATC-2

SL28548ATC-2T

SL28555AQC

SL28610

SL28610BLC

SL28610BLI

SL28610BLIT

SL28640BLC

SL28640BLCT

SL28647CLC

SL28647CLCT